[U-Boot] U-Boot for MIPS AR7161
I am attempting to create a U-Boot image for a router, Buffalo WZR-HP-AG300H, details can be found here, http://wiki.openwrt.org/toh/buffalo/wzr-hp-ag300h.
I am having trouble compiling and/or finding a pre-compiled version of U-Boot for it.
I am attempting to recover a router that has its bootloader erased, I have an identical router that is functioning and have debug access through JTAG to both devices. I located one image on the internet 8Muboot_RAM_version.bin, and loaded it into ram and executed it, but I don't receive any serial output, but it does turn on one LED indicator on the board, indicating that the program did execute somewhat. This was built for the AR724x processor though, and might be why it is not functioning fully.
I have attempted to halt the running board in the bootup, copy the ram contents from one board to the other, and resume the processor, but it seems I am missing something. I am going to paste below the contents of the openocd file that I am using, along with the initial startup of the working board. I can also provide any other details that are helpful.
If I can build a working RAM startup image, that would be great, I can then use that to rewrite the onboard flash memory, or if I can directly access the flash memory through the JTAG, but so far, I have not been successful with that either.
I believe I have a working toolchain to build U-Boot, but keep running into odd errors when building possibly due to different toolchain versions. Any help or assistance would be greatly appreciated.
Thanks, Allan Drassal
ar71xx.cfg
# Atheros AR71xx MIPS 24Kc SoC. # tested on PB44 refererence board
adapter_nsrst_delay 100 jtag_ntrst_delay 100
reset_config trst_and_srst
set CHIPNAME ar71xx
jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
set TARGETNAME $CHIPNAME.cpu target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
$TARGETNAME configure -event reset-halt-post { #setup PLL to lowest common denominator 300/300/150 setting #mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0 #mww 0xb8050000 0x800f40a3 ;# send to PLL mww 0xb8050000 0x40140180 ;# reset val + CPU:3 DDR:3 AHB:0 mww 0xb8050000 0xc0140180 ;# send to PLL
#next command will reset for PLL changes to take effect mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC) }
$TARGETNAME configure -event reset-init { #complete pll initialization mww 0xb8050000 0x800f0080 ;# set sw_update bit mww 0xb8050008 0 ;# clear reset_switch bit mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass mww 0xb8050008 1 ;# set clock_switch bit sleep 1 ;# wait for lock
# Setup DDR config and flash mapping mww 0xb8000000 0x77b8884e ;# DDR cfg cdl val (rst: 0x5bfc8d0) mww 0xb8000004 0x812cd6a8 ;# DDR cfg2 cdl val (rst: 0x80d106a8) #mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0) #mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8)
mww 0xb8000010 8 ;# force precharge all banks mww 0xb8000010 1 ;# force EMRS update cycle mww 0xb800000c 0 ;# clr ext. mode register mww 0xb8000010 2 ;# force auto refresh all banks mww 0xb8000010 8 ;# force precharge all banks #mww 0xb8000008 0x31 ;# set DDR mode value CAS=3 mww 0xb8000008 0x33 ;# set DDR mode value CAS=3 mww 0xb8000010 1 ;# force EMRS update cycle #mww 0xb8000014 0x461b ;# DDR refresh value #mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff) mww 0xb8000014 0x44a6 ;# DDR refresh value mww 0xb8000018 0x00ff ;# DDR Read Data This Cycle value (16bit: 0xffff) mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7) mww 0xb8000020 7 mww 0xb8000024 7 mww 0xb8000028 7 }
# setup working area somewhere in RAM $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
# serial SPI capable flash # flash bank <driver> <base> <size> <chip_width> <bus_width>
commands used in openocd through a telnet connection to 127.0.0.1 4444: reset halt reset mww 0xb8060008 3 mww 0xb806000c 0x12c halt mww 0xb8050000 0x00090828 mww 0xb8050000 0x00050828 mww 0xb8050000 0x00040828 mww 0xb8050008 2 mww 0xb8050008 3 halt reset init load_image 8Muboot_RAM_version.bin 0x80000000 resume 0x80000000
startup sequence of working board:
BUFFALO U-BOOT Ver 1.01 == CPU:680MHz, DDR:340MHz, AHB:170MHz == AP96 (ar7100) U-boot 0.0.1 DRAM: 128 MB Top of RAM usable for U-Boot at: 84000000 Reserving 266k for U-Boot at: 83fbc000 Reserving 192k for malloc() at: 83f8c000 Reserving 44 Bytes for Board Info at: 83f8bfd4 Reserving 36 Bytes for Global Data at: 83f8bfb0 Reserving 128k for boot params() at: 83f6bfb0 Stack Pointer at: 83f6bf98 Now running in RAM - U-Boot at: 83fbc000 flash bank #0 found 16 MB flash [W25Q128BV, blk:0x10000, sectors:256] flash bank #1 found 16 MB flash [W25Q128BV, blk:0x10000, sectors:256] Flash: 32 MB In: serial Out: serial Err: serial Memory Test uboot use 83F6BFB0 - 84000000 Memory Test start(80000000) end(83F00000) size(03F00000) Pattern 00000000 Writing... Reading... Memory Test start(84000000) end(88000000) size(04000000) Pattern 00000000 Writing... Reading... Memory Test OK ### buf_ver=[1.01] U-Boot Ver.=[1.01] ### build_date(env)=[Jan 14 2011 - 05:47:09] build_date(bin)=[Jan 14 2011 - 05:] ag7100_enet_initialize... Reading MAC Address from ENV(0x83f8c2fd) Port 0, Neg Success Port 1, Neg Success Port 2, Neg Success Port 3, Neg Success eth0: Phy Specific Status=0010 eth0: Phy Specific Status=0010 eth0: Phy Specific Status=0010 eth0: Phy Specific Status=0010{leth0: 02:aa:bb:cc:dd:20 eth0 up Reading MAC Address from ENV(0x83f8c2fd) Port 4, Neg Success eth1: Phy Specific Status=0010 eth1: 02:aa:bb:cc:dd:21 eth1 up eth0 02:AA:BB:CC:DD:20 , eth1 02:AA:BB:CC:DD:21
eth0 link down
tftp server(receive) go, waiting:4[sec] eth0 link down Load address: 0x84000000
Abort no file was loaded. ar7100> ar7100> flinfo
Bank # 1: flash-id : EF401800 Size: 16384 KB in 256 Sectors Sector Start Addresses: BF000000 RO BF010000 RO BF020000 RO BF030000 RO BF040000 BF050000 RO BF060000 BF070000 BF080000 BF090000 BF0A0000 BF0B0000 BF0C0000 BF0D0000 BF0E0000 BF0F0000 BF100000 BF110000 BF120000 BF130000 BF140000 BF150000 BF160000 BF170000 BF180000 BF190000 BF1A0000 BF1B0000 BF1C0000 BF1D0000 BF1E0000 BF1F0000 BF200000 BF210000 BF220000 BF230000 BF240000 BF250000 BF260000 BF270000 BF280000 BF290000 BF2A0000 BF2B0000 BF2C0000 BF2D0000 BF2E0000 BF2F0000 BF300000 BF310000 BF320000 BF330000 BF340000 BF350000 BF360000 BF370000 BF380000 BF390000 BF3A0000 BF3B0000 BF3C0000 BF3D0000 BF3E0000 BF3F0000 BF400000 BF410000 BF420000 BF430000 BF440000 BF450000 BF460000 BF470000 BF480000 BF490000 BF4A0000 BF4B0000 BF4C0000 BF4D0000 BF4E0000 BF4F0000 BF500000 BF510000 BF520000 BF530000 BF540000 BF550000 BF560000 BF570000 BF580000 BF590000 BF5A0000 BF5B0000 BF5C0000 BF5D0000 BF5E0000 BF5F0000 BF600000 BF610000 BF620000 BF630000 BF640000 BF650000 BF660000 BF670000 BF680000 BF690000 BF6A0000 BF6B0000 BF6C0000 BF6D0000 BF6E0000 BF6F0000 BF700000 BF710000 BF720000 BF730000 BF740000 BF750000 BF760000 BF770000 BF780000 BF790000 BF7A0000 BF7B0000 BF7C0000 BF7D0000 BF7E0000 BF7F0000 BF800000 BF810000 BF820000 BF830000 BF840000 BF850000 BF860000 BF870000 BF880000 BF890000 BF8A0000 BF8B0000 BF8C0000 BF8D0000 BF8E0000 BF8F0000 BF900000 BF910000 BF920000 BF930000 BF940000 BF950000 BF960000 BF970000 BF980000 BF990000 BF9A0000 BF9B0000 BF9C0000 BF9D0000 BF9E0000 BF9F0000 BFA00000 BFA10000 BFA20000 BFA30000 BFA40000 BFA50000 BFA60000 BFA70000 BFA80000 BFA90000 BFAA0000 BFAB0000 BFAC0000 BFAD0000 BFAE0000 BFAF0000 BFB00000 BFB10000 BFB20000 BFB30000 BFB40000 BFB50000 BFB60000 BFB70000 BFB80000 BFB90000 BFBA0000 BFBB0000 BFBC0000 BFBD0000 BFBE0000 BFBF0000 BFC00000 BFC10000 BFC20000 BFC30000 BFC40000 BFC50000 BFC60000 BFC70000 BFC80000 BFC90000 BFCA0000 BFCB0000 BFCC0000 BFCD0000 BFCE0000 BFCF0000 BFD00000 BFD10000 BFD20000 BFD30000 BFD40000 BFD50000 BFD60000 BFD70000 BFD80000 BFD90000 BFDA0000 BFDB0000 BFDC0000 BFDD0000 BFDE0000 BFDF0000 BFE00000 BFE10000 BFE20000 BFE30000 BFE40000 BFE50000 BFE60000 BFE70000 BFE80000 BFE90000 BFEA0000 BFEB0000 BFEC0000 BFED0000 BFEE0000 BFEF0000 BFF00000 BFF10000 BFF20000 BFF30000 BFF40000 BFF50000 BFF60000 BFF70000 BFF80000 BFF90000 BFFA0000 BFFB0000 BFFC0000 BFFD0000 BFFE0000 BFFF0000
Bank # 2: flash-id : EF401800 Size: 16384 KB in 256 Sectors Sector Start Addresses: BE000000 BE010000 BE020000 BE030000 BE040000 BE050000 BE060000 BE070000 BE080000 BE090000 BE0A0000 BE0B0000 BE0C0000 BE0D0000 BE0E0000 BE0F0000 BE100000 BE110000 BE120000 BE130000 BE140000 BE150000 BE160000 BE170000 BE180000 BE190000 BE1A0000 BE1B0000 BE1C0000 BE1D0000 BE1E0000 BE1F0000 BE200000 BE210000 BE220000 BE230000 BE240000 BE250000 BE260000 BE270000 BE280000 BE290000 BE2A0000 BE2B0000 BE2C0000 BE2D0000 BE2E0000 BE2F0000 BE300000 BE310000 BE320000 BE330000 BE340000 BE350000 BE360000 BE370000 BE380000 BE390000 BE3A0000 BE3B0000 BE3C0000 BE3D0000 BE3E0000 BE3F0000 BE400000 BE410000 E BE420000 E BE430000 E BE440000 E BE450000 E BE460000 E BE470000 E BE480000 E BE490000 E BE4A0000 E BE4B0000 E BE4C0000 E BE4D0000 E BE4E0000 E BE4F0000 E BE500000 E BE510000 E BE520000 E BE530000 E BE540000 E BE550000 E BE560000 E BE570000 E BE580000 E BE590000 E BE5A0000 E BE5B0000 E BE5C0000 E BE5D0000 E BE5E0000 E BE5F0000 E BE600000 E BE610000 E BE620000 E BE630000 E BE640000 E BE650000 E BE660000 E BE670000 E BE680000 E BE690000 E BE6A0000 E BE6B0000 E BE6C0000 E BE6D0000 E BE6E0000 E BE6F0000 E BE700000 E BE710000 E BE720000 E BE730000 E BE740000 E BE750000 E BE760000 E BE770000 E BE780000 E BE790000 E BE7A0000 E BE7B0000 E BE7C0000 E BE7D0000 E BE7E0000 E
ar7100> imls Image at BF060000: Image Name: MIPS Linux Kernel Image Created: 2011-12-20 4:33:01 UTC Image Type: MIPS Linux Kernel Image (lzma compressed) Data Size: 958722 Bytes = 936.3 kB Load Address: 80002000 Entry Point: 801fb6d0 Verifying Checksum ... crc32_fw: bf060040 - bf14a141 (len:000ea102) calc... crc32_fw: range1 bf060040 - bf14a141 OK
Hi Allan,
2012/11/27 Drassal, Allan drasal@wsu.edu:
I am attempting to create a U-Boot image for a router, Buffalo WZR-HP-AG300H, details can be found here, http://wiki.openwrt.org/toh/buffalo/wzr-hp-ag300h.
I am having trouble compiling and/or finding a pre-compiled version of U-Boot for it.
I am attempting to recover a router that has its bootloader erased, I have an identical router that is functioning and have debug access through JTAG to both devices.
have you tried to dump the MTD partition of U-Boot on the working device?
I located one image on the internet 8Muboot_RAM_version.bin, and loaded it into ram and executed it, but I don't receive any serial output, but it does turn on one LED indicator on the board, indicating that the program did execute somewhat. This was built for the AR724x processor though, and might be why it is not functioning fully.
Do you know the original text base address of that binary? If you load the binary to the wrong address, function calls or relocation will not work.
I have attempted to halt the running board in the bootup, copy the ram contents from one board to the other, and resume the processor, but it seems I am missing something.
maybe there are cache coherency problems or the memory controller is not initialized correctly
I am going to paste below the contents of the openocd file that I am using, along with the initial startup of the working board. I can also provide any other details that are helpful.
If I can build a working RAM startup image, that would be great, I can then use that to rewrite the onboard flash memory, or if I can directly access the flash memory through the JTAG, but so far, I have not been successful with that either.
I believe I have a working toolchain to build U-Boot, but keep running into odd errors when building possibly due to different toolchain versions. Any help or assistance would be greatly appreciated.
Thanks, Allan Drassal
ar71xx.cfg
# Atheros AR71xx MIPS 24Kc SoC. # tested on PB44 refererence board
adapter_nsrst_delay 100 jtag_ntrst_delay 100
reset_config trst_and_srst
set CHIPNAME ar71xx
jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
set TARGETNAME $CHIPNAME.cpu target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
$TARGETNAME configure -event reset-halt-post { #setup PLL to lowest common denominator 300/300/150 setting #mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0 #mww 0xb8050000 0x800f40a3 ;# send to PLL mww 0xb8050000 0x40140180 ;# reset val + CPU:3 DDR:3 AHB:0 mww 0xb8050000 0xc0140180 ;# send to PLL
#next command will reset for PLL changes to take effect mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC)}
$TARGETNAME configure -event reset-init { #complete pll initialization mww 0xb8050000 0x800f0080 ;# set sw_update bit mww 0xb8050008 0 ;# clear reset_switch bit mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass mww 0xb8050008 1 ;# set clock_switch bit sleep 1 ;# wait for lock
# Setup DDR config and flash mapping mww 0xb8000000 0x77b8884e ;# DDR cfg cdl val (rst: 0x5bfc8d0) mww 0xb8000004 0x812cd6a8 ;# DDR cfg2 cdl val (rst: 0x80d106a8) #mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0) #mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8) mww 0xb8000010 8 ;# force precharge all banks mww 0xb8000010 1 ;# force EMRS update cycle mww 0xb800000c 0 ;# clr ext. mode register mww 0xb8000010 2 ;# force auto refresh all banks mww 0xb8000010 8 ;# force precharge all banks #mww 0xb8000008 0x31 ;# set DDR mode value CAS=3 mww 0xb8000008 0x33 ;# set DDR mode value CAS=3 mww 0xb8000010 1 ;# force EMRS update cycle #mww 0xb8000014 0x461b ;# DDR refresh value #mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff) mww 0xb8000014 0x44a6 ;# DDR refresh value mww 0xb8000018 0x00ff ;# DDR Read Data This Cycle value (16bit: 0xffff) mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7) mww 0xb8000020 7 mww 0xb8000024 7 mww 0xb8000028 7}
are there no registers for enabling/disabling the memory controller? Usually you need to disable a memory controller when changing its configuration and to enable it to start the initialization sequence for the DRAM device.
# setup working area somewhere in RAM $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
# serial SPI capable flash # flash bank <driver> <base> <size> <chip_width> <bus_width>
commands used in openocd through a telnet connection to 127.0.0.1 4444: reset halt reset mww 0xb8060008 3 mww 0xb806000c 0x12c halt mww 0xb8050000 0x00090828 mww 0xb8050000 0x00050828 mww 0xb8050000 0x00040828 mww 0xb8050008 2 mww 0xb8050008 3 halt reset init load_image 8Muboot_RAM_version.bin 0x80000000 resume 0x80000000
are you sure that 0x80000000 is the real text base address? The mainline U-Boot code uses 0x80000000 + CONFIG_SYS_INIT_SP_OFFSET as initial stack area before relocation.
-- Best regards, Daniel
-----Original Message----- From: Daniel Schwierzeck [mailto:daniel.schwierzeck@gmail.com] Sent: Wednesday, November 28, 2012 9:16 AM To: Drassal, Allan Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] U-Boot for MIPS AR7161
Hi Allan,
2012/11/27 Drassal, Allan drasal@wsu.edu:
I am attempting to create a U-Boot image for a router, Buffalo
WZR-HP-AG300H, details can be found here, http://wiki.openwrt.org/toh/buffalo/wzr-hp-ag300h.
I am having trouble compiling and/or finding a pre-compiled version of
U-Boot for it.
I am attempting to recover a router that has its bootloader erased, I
have an identical router that is functioning and have debug access through JTAG to both devices.
have you tried to dump the MTD partition of U-Boot on the working device?
I have dumped all the partitions from the working device from the linux console onto a USB memory stick.
I located one image on the internet 8Muboot_RAM_version.bin, and loaded
it into ram and executed it, but I don't receive any serial output, but it does turn on one LED indicator on the board, indicating that the program did execute somewhat. This was built for the AR724x processor though, and might be why it is not functioning fully.
Do you know the original text base address of that binary? If you load the binary to the wrong address, function calls or relocation will not work.
The original base address is mapped to flash memory, I believe it is 0xbfc03860. This is the first address the processor looks to upon startup I believe.
From my understanding, U-Boot itself contains a short bootstrap as well that configures the DRAM controller, and a few other necessary things, copies itself into DRAM, then transfers execution to the copy that resides in DRAM to continue the next step in U-Boot execution.
I have tried to copy the part in DRAM from the working device to the non working device, but I might not have something configured correctly. If I knew what I was looking for, it must be contained in the initial few bytes in the U-Boot loader, the DRAM configuration, etc. Technically I think I should be able to execute this directly in DRAM if I know what to copy over.
I have attempted to halt the running board in the bootup, copy the ram
contents from one board to the other, and resume the processor, but it seems I am missing something.
maybe there are cache coherency problems or the memory controller is not initialized correctly
I think this might be the case, but it executes one loader correctly (I think) because it turns on the DIAG LED on the device when loaded into DRAM and executed. But, that does not mean it is not getting stuck somewhere after the LED turns on...
I guess I need a deeper understanding of what is going on during the boot process... Generally I think the following happens, but I might be missing something, or over simplified something... 1. Processor starts up and looks to a predetermined address for initial instructions 2. The initial U-Boot bootstrap is loaded 3. This initializes some things such as the UART (for debug), DRAM controller, etc 4. U-Boot is copied to DRAM then executed from there 5. The main U-Boot is executed and initializes the remaining devices 6. Control is (usually) then transferred to a Linux kernel which is loaded into DRAM by U-Boot then executed
I am going to attempt to get my toolchain working for building U-Boot, maybe I just need to build a clean image, however, I can't find support for the AR7161 in the mainline, so I might have to piece together parts from various sources to get a complete working build.
In reality though, I would rather just use the existing working U-Boot on the working device to start up the non-working device to be able to rewrite the bootloader, however, I might need to compile a new U-Boot to get this far.
I have done work with ARM based (SheevaPlug, GuruPlug, DreamPlug) devices before, and they were easier to work with than this MIPS based device, for one I could access the flash directly through JTAG (with exception of the DreamPlug).
I can provide a copy of the working devices boot loader if this helps to figure out load addresses and such, I am not sure how the file is build, so looking at the instructions might not make much sense to me. I am assuming it is not compressed in any way since the processor has no way to decompress it until after loading it.
I am going to paste below the contents of the openocd file that I am using,
along with the initial startup of the working board. I can also provide any other details that are helpful.
If I can build a working RAM startup image, that would be great, I can
then use that to rewrite the onboard flash memory, or if I can directly access the flash memory through the JTAG, but so far, I have not been successful with that either.
I believe I have a working toolchain to build U-Boot, but keep running
into odd errors when building possibly due to different toolchain versions.
Any help or assistance would be greatly appreciated.
Thanks, Allan Drassal
ar71xx.cfg
# Atheros AR71xx MIPS 24Kc SoC. # tested on PB44 refererence board
adapter_nsrst_delay 100 jtag_ntrst_delay 100
reset_config trst_and_srst
set CHIPNAME ar71xx
jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f
-expected-id 1
set TARGETNAME $CHIPNAME.cpu target create $TARGETNAME mips_m4k -endian big -chain-position
$TARGETNAME
$TARGETNAME configure -event reset-halt-post { #setup PLL to lowest common denominator 300/300/150 setting #mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0 #mww 0xb8050000 0x800f40a3 ;# send to PLL mww 0xb8050000 0x40140180 ;# reset val + CPU:3 DDR:3 AHB:0 mww 0xb8050000 0xc0140180 ;# send to PLL
#next command will reset for PLL changes to take effect mww 0xb8050008 3 ;# set reset_switch andclock_switch (resets SoC)
}
$TARGETNAME configure -event reset-init { #complete pll initialization mww 0xb8050000 0x800f0080 ;# set sw_update bit mww 0xb8050008 0 ;# clear reset_switch bit mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass mww 0xb8050008 1 ;# set clock_switch bit sleep 1 ;# wait for lock
# Setup DDR config and flash mapping mww 0xb8000000 0x77b8884e ;# DDR cfg cdl val (rst:0x5bfc8d0)
mww 0xb8000004 0x812cd6a8 ;# DDR cfg2 cdl val (rst:0x80d106a8)
#mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst:0x5bfc8d0)
#mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst:0x80d106a8)
mww 0xb8000010 8 ;# force precharge all banks mww 0xb8000010 1 ;# force EMRS update cycle mww 0xb800000c 0 ;# clr ext. mode register mww 0xb8000010 2 ;# force auto refresh all banks mww 0xb8000010 8 ;# force precharge all banks #mww 0xb8000008 0x31 ;# set DDR mode value CAS=3 mww 0xb8000008 0x33 ;# set DDR mode value CAS=3 mww 0xb8000010 1 ;# force EMRS update cycle #mww 0xb8000014 0x461b ;# DDR refresh value #mww 0xb8000018 0xffff ;# DDR Read Data This Cyclevalue (16bit: 0xffff)
mww 0xb8000014 0x44a6 ;# DDR refresh value mww 0xb8000018 0x00ff ;# DDR Read Data This Cycle value(16bit: 0xffff)
mww 0xb800001c 0x7 ;# delay added to the DQS line(normal = 7)
mww 0xb8000020 7 mww 0xb8000024 7 mww 0xb8000028 7}
are there no registers for enabling/disabling the memory controller? Usually you need to disable a memory controller when changing its configuration and to enable it to start the initialization sequence for the DRAM device.
# setup working area somewhere in RAM $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size
0x20000
# serial SPI capable flash # flash bank <driver> <base> <size> <chip_width> <bus_width>
commands used in openocd through a telnet connection to 127.0.0.1 4444: reset halt reset mww 0xb8060008 3 mww 0xb806000c 0x12c halt mww 0xb8050000 0x00090828 mww 0xb8050000 0x00050828 mww 0xb8050000 0x00040828 mww 0xb8050008 2 mww 0xb8050008 3 halt reset init load_image 8Muboot_RAM_version.bin 0x80000000 resume 0x80000000
are you sure that 0x80000000 is the real text base address? The mainline U-Boot code uses 0x80000000 + CONFIG_SYS_INIT_SP_OFFSET as initial stack area before relocation.
-- Best regards, Daniel
Thanks, Allan
participants (2)
-
Daniel Schwierzeck -
Drassal, Allan