Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files. Minor update in socfpga_per_reset(). No functional change.

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 2 +- arch/arm/mach-socfpga/include/mach/reset_manager.h | 42 +------- .../mach-socfpga/include/mach/reset_manager_gen5.h | 47 +++++++++ arch/arm/mach-socfpga/reset_manager.c | 93 +---------------- arch/arm/mach-socfpga/reset_manager_gen5.c | 113 +++++++++++++++++++++ 5 files changed, 168 insertions(+), 129 deletions(-) create mode 100755 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h create mode 100755 arch/arm/mach-socfpga/reset_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index b76de4c..97819ac 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o

# QTS-generated config file wrappers obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ - clock_manager_gen5.o + clock_manager_gen5.o reset_manager_gen5.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 2f070f2..9e253bf 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,27 +8,12 @@ #define _RESET_MANAGER_H_

void reset_cpu(ulong addr); -void reset_deassert_peripherals_handoff(void);

void socfpga_bridges_reset(int enable);

void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void);

-struct socfpga_reset_manager { - u32 status; - u32 ctrl; - u32 counts; - u32 padding1; - u32 mpu_mod_reset; - u32 per_mod_reset; - u32 per2_mod_reset; - u32 brg_mod_reset; - u32 misc_mod_reset; - u32 padding2[12]; - u32 tstscratch; -}; - #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 #else @@ -55,28 +40,11 @@ struct socfpga_reset_manager { #define RSTMGR_BANK(_reset) \ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)

-/* - * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: - * 0 ... mpumodrst - * 1 ... permodrst - * 2 ... per2modrst - * 3 ... brgmodrst - * 4 ... miscmodrst - */ -#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) -#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) -#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) -#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) -#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) -#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) -#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) -#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) -#define RSTMGR_DMA RSTMGR_DEFINE(1, 28) -#define RSTMGR_SDR RSTMGR_DEFINE(1, 29) - /* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/reset_manager_gen5.h> +#endif + #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h new file mode 100755 index 0000000..028974a --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RESET_MANAGER_GEN5_H_ +#define _RESET_MANAGER_GEN5_H_ + +void reset_deassert_peripherals_handoff(void); + +struct socfpga_reset_manager { + u32 status; + u32 ctrl; + u32 counts; + u32 padding1; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; + u32 misc_mod_reset; + u32 padding2[12]; + u32 tstscratch; +}; + +/* + * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... permodrst + * 2 ... per2modrst + * 3 ... brgmodrst + * 4 ... miscmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) +#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 28) +#define RSTMGR_SDR RSTMGR_DEFINE(1, 29) + +#endif /* _RESET_MANAGER_GEN5_H_ */ diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2..29438ed 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -7,53 +7,12 @@

#include <common.h> #include <asm/io.h> -#include <asm/arch/fpga_manager.h> #include <asm/arch/reset_manager.h> -#include <asm/arch/system_manager.h>

DECLARE_GLOBAL_DATA_PTR;

static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - -/* Assert or de-assert SoCFPGA reset manager reset. */ -void socfpga_per_reset(u32 reset, int set) -{ - const void *reg; - - if (RSTMGR_BANK(reset) == 0) - reg = &reset_manager_base->mpu_mod_reset; - else if (RSTMGR_BANK(reset) == 1) - reg = &reset_manager_base->per_mod_reset; - else if (RSTMGR_BANK(reset) == 2) - reg = &reset_manager_base->per2_mod_reset; - else if (RSTMGR_BANK(reset) == 3) - reg = &reset_manager_base->brg_mod_reset; - else if (RSTMGR_BANK(reset) == 4) - reg = &reset_manager_base->misc_mod_reset; - else /* Invalid reset register, do nothing */ - return; - - if (set) - setbits_le32(reg, 1 << RSTMGR_RESET(reset)); - else - clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); -} - -/* - * Assert reset on every peripheral but L4WD0. - * Watchdog must be kept intact to prevent glitches - * and/or hangs. - */ -void socfpga_per_reset_all(void) -{ - const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); - - writel(~l4wd0, &reset_manager_base->per_mod_reset); - writel(0xffffffff, &reset_manager_base->per2_mod_reset); -}

/* * Write the reset manager register to cause reset @@ -61,8 +20,8 @@ void socfpga_per_reset_all(void) void reset_cpu(ulong addr) { /* request a warm reset */ - writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), - &reset_manager_base->ctrl); + writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, + &reset_manager_base->ctrl); /* * infinite loop here as watchdog will trigger and reset * the processor @@ -70,51 +29,3 @@ void reset_cpu(ulong addr) while (1) ; } - -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} - -#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -void socfpga_bridges_reset(int enable) -{ - /* For SoCFPGA-VT, this is NOP. */ -} -#else - -#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 -#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 -#define L3REGS_REMAP_OCRAM_MASK 0x01 - -void socfpga_bridges_reset(int enable) -{ - const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | - L3REGS_REMAP_HPS2FPGA_MASK | - L3REGS_REMAP_OCRAM_MASK; - - if (enable) { - /* brdmodrst */ - writel(0xffffffff, &reset_manager_base->brg_mod_reset); - } else { - writel(0, &sysmgr_regs->iswgrp_handoff[0]); - writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); - - /* Check signal from FPGA. */ - if (!fpgamgr_test_fpga_ready()) { - /* FPGA not ready, do nothing. */ - printf("%s: FPGA not ready, aborting.\n", __func__); - return; - } - - /* brdmodrst */ - writel(0, &reset_manager_base->brg_mod_reset); - - /* Remap the bridges into memory map */ - writel(l3mask, SOCFPGA_L3REGS_ADDRESS); - } -} -#endif diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c new file mode 100755 index 0000000..a170865 --- /dev/null +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/fpga_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* Assert or de-assert SoCFPGA reset manager reset. */ +void socfpga_per_reset(u32 reset, int set) +{ + const volatile u32 *reg; + u32 rstmgr_bank = RSTMGR_BANK(reset); + + switch (rstmgr_bank) { + case 0: + reg = &reset_manager_base->mpu_mod_reset; + break; + case 1: + reg = &reset_manager_base->per_mod_reset; + break; + case 2: + reg = &reset_manager_base->per2_mod_reset; + break; + case 3: + reg = &reset_manager_base->brg_mod_reset; + break; + case 4: + reg = &reset_manager_base->misc_mod_reset; + break; + + default: + return; + } + + if (set) + setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + else + clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); +} + +/* + * Assert reset on every peripheral but L4WD0. + * Watchdog must be kept intact to prevent glitches + * and/or hangs. + */ +void socfpga_per_reset_all(void) +{ + const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); + + writel(~l4wd0, &reset_manager_base->per_mod_reset); + writel(0xffffffff, &reset_manager_base->per2_mod_reset); +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +void socfpga_bridges_reset(int enable) +{ + /* For SoCFPGA-VT, this is NOP. */ +} +#else + +#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 +#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 +#define L3REGS_REMAP_OCRAM_MASK 0x01 + +void socfpga_bridges_reset(int enable) +{ + const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | + L3REGS_REMAP_HPS2FPGA_MASK | + L3REGS_REMAP_OCRAM_MASK; + + if (enable) { + /* brdmodrst */ + writel(0xffffffff, &reset_manager_base->brg_mod_reset); + } else { + writel(0, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + + /* Check signal from FPGA. */ + if (!fpgamgr_test_fpga_ready()) { + /* FPGA not ready, do nothing. */ + printf("%s: FPGA not ready, aborting.\n", __func__); + return; + } + + /* brdmodrst */ + writel(0, &reset_manager_base->brg_mod_reset); + + /* Remap the bridges into memory map */ + writel(l3mask, SOCFPGA_L3REGS_ADDRESS); + } +} +#endif

Restructure system manager in the preparation to support A10. No functional change.

Change uint32_t to u32.

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 4 +- .../arm/mach-socfpga/include/mach/system_manager.h | 125 ++------------------- .../include/mach/system_manager_gen5.h | 121 ++++++++++++++++++++ arch/arm/mach-socfpga/system_manager.c | 85 -------------- arch/arm/mach-socfpga/system_manager_gen5.c | 85 ++++++++++++++ 5 files changed, 215 insertions(+), 205 deletions(-) create mode 100755 arch/arm/mach-socfpga/include/mach/system_manager_gen5.h delete mode 100644 arch/arm/mach-socfpga/system_manager.c create mode 100644 arch/arm/mach-socfpga/system_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 5b09ea9..e83da2e 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -7,7 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ +obj-y += misc.o timer.o reset_manager.o clock_manager.o \ fpga_manager.o board.o

obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o @@ -15,7 +15,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ clock_manager_gen5.o reset_manager_gen5.o \ - misc_gen5.o + misc_gen5.o system_manager_gen5.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index c45edea..53ced81 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -1,120 +1,11 @@ /* - * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */

-#ifndef _SYSTEM_MANAGER_H_ -#define _SYSTEM_MANAGER_H_ - -#ifndef __ASSEMBLY__ - -void sysmgr_pinmux_init(void); -void sysmgr_config_warmrstcfgio(int enable); - -void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); -#endif - -struct socfpga_system_manager { - /* System Manager Module */ - u32 siliconid1; /* 0x00 */ - u32 siliconid2; - u32 _pad_0x8_0xf[2]; - u32 wddbg; /* 0x10 */ - u32 bootinfo; - u32 hpsinfo; - u32 parityinj; - /* FPGA Interface Group */ - u32 fpgaintfgrp_gbl; /* 0x20 */ - u32 fpgaintfgrp_indiv; - u32 fpgaintfgrp_module; - u32 _pad_0x2c_0x2f; - /* Scan Manager Group */ - u32 scanmgrgrp_ctrl; /* 0x30 */ - u32 _pad_0x34_0x3f[3]; - /* Freeze Control Group */ - u32 frzctrl_vioctrl; /* 0x40 */ - u32 _pad_0x44_0x4f[3]; - u32 frzctrl_hioctrl; /* 0x50 */ - u32 frzctrl_src; - u32 frzctrl_hwctrl; - u32 _pad_0x5c_0x5f; - /* EMAC Group */ - u32 emacgrp_ctrl; /* 0x60 */ - u32 emacgrp_l3master; - u32 _pad_0x68_0x6f[2]; - /* DMA Controller Group */ - u32 dmagrp_ctrl; /* 0x70 */ - u32 dmagrp_persecurity; - u32 _pad_0x78_0x7f[2]; - /* Preloader (initial software) Group */ - u32 iswgrp_handoff[8]; /* 0x80 */ - u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ - /* Boot ROM Code Register Group */ - u32 romcodegrp_ctrl; /* 0xc0 */ - u32 romcodegrp_cpu1startaddr; - u32 romcodegrp_initswstate; - u32 romcodegrp_initswlastld; - u32 romcodegrp_bootromswstate; /* 0xd0 */ - u32 __pad_0xd4_0xdf[3]; - /* Warm Boot from On-Chip RAM Group */ - u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ - u32 romcodegrp_warmramgrp_datastart; - u32 romcodegrp_warmramgrp_length; - u32 romcodegrp_warmramgrp_execution; - u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ - u32 __pad_0xf4_0xff[3]; - /* Boot ROM Hardware Register Group */ - u32 romhwgrp_ctrl; /* 0x100 */ - u32 _pad_0x104_0x107; - /* SDMMC Controller Group */ - u32 sdmmcgrp_ctrl; - u32 sdmmcgrp_l3master; - /* NAND Flash Controller Register Group */ - u32 nandgrp_bootstrap; /* 0x110 */ - u32 nandgrp_l3master; - /* USB Controller Group */ - u32 usbgrp_l3master; - u32 _pad_0x11c_0x13f[9]; - /* ECC Management Register Group */ - u32 eccgrp_l2; /* 0x140 */ - u32 eccgrp_ocram; - u32 eccgrp_usb0; - u32 eccgrp_usb1; - u32 eccgrp_emac0; /* 0x150 */ - u32 eccgrp_emac1; - u32 eccgrp_dma; - u32 eccgrp_can0; - u32 eccgrp_can1; /* 0x160 */ - u32 eccgrp_nand; - u32 eccgrp_qspi; - u32 eccgrp_sdmmc; - u32 _pad_0x170_0x3ff[164]; - /* Pin Mux Control Group */ - u32 emacio[20]; /* 0x400 */ - u32 flashio[12]; /* 0x450 */ - u32 generalio[28]; /* 0x480 */ - u32 _pad_0x4f0_0x4ff[4]; - u32 mixed1io[22]; /* 0x500 */ - u32 mixed2io[8]; /* 0x558 */ - u32 gplinmux[23]; /* 0x578 */ - u32 gplmux[71]; /* 0x5d4 */ - u32 nandusefpga; /* 0x6f0 */ - u32 _pad_0x6f4; - u32 rgmii1usefpga; /* 0x6f8 */ - u32 _pad_0x6fc_0x700[2]; - u32 i2c0usefpga; /* 0x704 */ - u32 sdmmcusefpga; /* 0x708 */ - u32 _pad_0x70c_0x710[2]; - u32 rgmii0usefpga; /* 0x714 */ - u32 _pad_0x718_0x720[3]; - u32 i2c3usefpga; /* 0x724 */ - u32 i2c2usefpga; /* 0x728 */ - u32 i2c1usefpga; /* 0x72c */ - u32 spim1usefpga; /* 0x730 */ - u32 _pad_0x734; - u32 spim0usefpga; /* 0x738 */ -}; +#ifndef _SYSTEM_MANAGER_H_ +#define _SYSTEM_MANAGER_H_

#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) @@ -129,12 +20,6 @@ struct socfpga_system_manager { #define SYSMGR_FPGAINTF_NAND (1 << 4) #define SYSMGR_FPGAINTF_SDMMC (1 << 5)

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 -#else -#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 -#endif - #define SYSMGR_SDMMC_DRVSEL_SHIFT 0

/* EMAC Group Bit definitions */ @@ -146,4 +31,8 @@ struct socfpga_system_manager { #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/system_manager_gen5.h> +#endif + #endif /* _SYSTEM_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h new file mode 100755 index 0000000..3ad4ca1 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYSTEM_MANAGER_GEN5_H_ +#define _SYSTEM_MANAGER_GEN5_H_ + +#ifndef __ASSEMBLY__ + +void sysmgr_pinmux_init(void); +void sysmgr_config_warmrstcfgio(int enable); + +void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); + +struct socfpga_system_manager { + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ + u32 siliconid2; + u32 _pad_0x8_0xf[2]; + u32 wddbg; /* 0x10 */ + u32 bootinfo; + u32 hpsinfo; + u32 parityinj; + /* FPGA Interface Group */ + u32 fpgaintfgrp_gbl; /* 0x20 */ + u32 fpgaintfgrp_indiv; + u32 fpgaintfgrp_module; + u32 _pad_0x2c_0x2f; + /* Scan Manager Group */ + u32 scanmgrgrp_ctrl; /* 0x30 */ + u32 _pad_0x34_0x3f[3]; + /* Freeze Control Group */ + u32 frzctrl_vioctrl; /* 0x40 */ + u32 _pad_0x44_0x4f[3]; + u32 frzctrl_hioctrl; /* 0x50 */ + u32 frzctrl_src; + u32 frzctrl_hwctrl; + u32 _pad_0x5c_0x5f; + /* EMAC Group */ + u32 emacgrp_ctrl; /* 0x60 */ + u32 emacgrp_l3master; + u32 _pad_0x68_0x6f[2]; + /* DMA Controller Group */ + u32 dmagrp_ctrl; /* 0x70 */ + u32 dmagrp_persecurity; + u32 _pad_0x78_0x7f[2]; + /* Preloader (initial software) Group */ + u32 iswgrp_handoff[8]; /* 0x80 */ + u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ + /* Boot ROM Code Register Group */ + u32 romcodegrp_ctrl; /* 0xc0 */ + u32 romcodegrp_cpu1startaddr; + u32 romcodegrp_initswstate; + u32 romcodegrp_initswlastld; + u32 romcodegrp_bootromswstate; /* 0xd0 */ + u32 __pad_0xd4_0xdf[3]; + /* Warm Boot from On-Chip RAM Group */ + u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ + u32 romcodegrp_warmramgrp_datastart; + u32 romcodegrp_warmramgrp_length; + u32 romcodegrp_warmramgrp_execution; + u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ + u32 __pad_0xf4_0xff[3]; + /* Boot ROM Hardware Register Group */ + u32 romhwgrp_ctrl; /* 0x100 */ + u32 _pad_0x104_0x107; + /* SDMMC Controller Group */ + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x110 */ + u32 nandgrp_l3master; + /* USB Controller Group */ + u32 usbgrp_l3master; + u32 _pad_0x11c_0x13f[9]; + /* ECC Management Register Group */ + u32 eccgrp_l2; /* 0x140 */ + u32 eccgrp_ocram; + u32 eccgrp_usb0; + u32 eccgrp_usb1; + u32 eccgrp_emac0; /* 0x150 */ + u32 eccgrp_emac1; + u32 eccgrp_dma; + u32 eccgrp_can0; + u32 eccgrp_can1; /* 0x160 */ + u32 eccgrp_nand; + u32 eccgrp_qspi; + u32 eccgrp_sdmmc; + u32 _pad_0x170_0x3ff[164]; + /* Pin Mux Control Group */ + u32 emacio[20]; /* 0x400 */ + u32 flashio[12]; /* 0x450 */ + u32 generalio[28]; /* 0x480 */ + u32 _pad_0x4f0_0x4ff[4]; + u32 mixed1io[22]; /* 0x500 */ + u32 mixed2io[8]; /* 0x558 */ + u32 gplinmux[23]; /* 0x578 */ + u32 gplmux[71]; /* 0x5d4 */ + u32 nandusefpga; /* 0x6f0 */ + u32 _pad_0x6f4; + u32 rgmii1usefpga; /* 0x6f8 */ + u32 _pad_0x6fc_0x700[2]; + u32 i2c0usefpga; /* 0x704 */ + u32 sdmmcusefpga; /* 0x708 */ + u32 _pad_0x70c_0x710[2]; + u32 rgmii0usefpga; /* 0x714 */ + u32 _pad_0x718_0x720[3]; + u32 i2c3usefpga; /* 0x724 */ + u32 i2c2usefpga; /* 0x728 */ + u32 i2c1usefpga; /* 0x72c */ + u32 spim1usefpga; /* 0x730 */ + u32 _pad_0x734; + u32 spim0usefpga; /* 0x738 */ +}; +#endif + +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 + +#endif /* _SYSTEM_MANAGER_GEN5_H_ */ diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c deleted file mode 100644 index 75a65f3..0000000 --- a/arch/arm/mach-socfpga/system_manager.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/system_manager.h> -#include <asm/arch/fpga_manager.h> - -DECLARE_GLOBAL_DATA_PTR; - -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - -/* - * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. - * The value is not wrote to SYSMGR.FPGAINTF.MODULE but - * CONFIG_SYSMGR_ISWGRP_HANDOFF. - */ -static void populate_sysmgr_fpgaintf_module(void) -{ - uint32_t handoff_val = 0; - - /* ISWGRP_HANDOFF_FPGAINTF */ - writel(0, &sysmgr_regs->iswgrp_handoff[2]); - - /* Enable the signal for those HPS peripherals that use FPGA. */ - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) - handoff_val |= SYSMGR_FPGAINTF_NAND; - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) - handoff_val |= SYSMGR_FPGAINTF_EMAC1; - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) - handoff_val |= SYSMGR_FPGAINTF_SDMMC; - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) - handoff_val |= SYSMGR_FPGAINTF_EMAC0; - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) - handoff_val |= SYSMGR_FPGAINTF_SPIM0; - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) - handoff_val |= SYSMGR_FPGAINTF_SPIM1; - - /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE - based on pinmux setting */ - setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val); - - handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]); - if (fpgamgr_test_fpga_ready()) { - /* Enable the required signals only */ - writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module); - } -} - -/* - * Configure all the pin muxes - */ -void sysmgr_pinmux_init(void) -{ - uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0]; - const u8 *sys_mgr_init_table; - unsigned int len; - int i; - - sysmgr_get_pinmux_table(&sys_mgr_init_table, &len); - - for (i = 0; i < len; i++) { - writel(sys_mgr_init_table[i], regs); - regs += sizeof(regs); - } - - populate_sysmgr_fpgaintf_module(); -} - -/* - * This bit allows the bootrom to configure the IOs after a warm reset. - */ -void sysmgr_config_warmrstcfgio(int enable) -{ - if (enable) - setbits_le32(&sysmgr_regs->romcodegrp_ctrl, - SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); - else - clrbits_le32(&sysmgr_regs->romcodegrp_ctrl, - SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); -} diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c new file mode 100644 index 0000000..3588a57 --- /dev/null +++ b/arch/arm/mach-socfpga/system_manager_gen5.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/fpga_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. + * The value is not wrote to SYSMGR.FPGAINTF.MODULE but + * CONFIG_SYSMGR_ISWGRP_HANDOFF. + */ +static void populate_sysmgr_fpgaintf_module(void) +{ + u32 handoff_val = 0; + + /* ISWGRP_HANDOFF_FPGAINTF */ + writel(0, &sysmgr_regs->iswgrp_handoff[2]); + + /* Enable the signal for those HPS peripherals that use FPGA. */ + if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_NAND; + if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC1; + if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SDMMC; + if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC0; + if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM0; + if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM1; + + /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE + based on pinmux setting */ + setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val); + + handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]); + if (fpgamgr_test_fpga_ready()) { + /* Enable the required signals only */ + writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module); + } +} + +/* + * Configure all the pin muxes + */ +void sysmgr_pinmux_init(void) +{ + u32 regs = (u32)&sysmgr_regs->emacio[0]; + const u8 *sys_mgr_init_table; + unsigned int len; + int i; + + sysmgr_get_pinmux_table(&sys_mgr_init_table, &len); + + for (i = 0; i < len; i++) { + writel(sys_mgr_init_table[i], regs); + regs += sizeof(regs); + } + + populate_sysmgr_fpgaintf_module(); +} + +/* + * This bit allows the bootrom to configure the IOs after a warm reset. + */ +void sysmgr_config_warmrstcfgio(int enable) +{ + if (enable) + setbits_le32(&sysmgr_regs->romcodegrp_ctrl, + SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); + else + clrbits_le32(&sysmgr_regs->romcodegrp_ctrl, + SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); +}

Add clock driver support for Arria 10 and update Gen5 clock driver.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 3 +- arch/arm/mach-socfpga/clock_manager.c | 36 +- arch/arm/mach-socfpga/clock_manager_arria10.c | 1104 ++++++++++++++++++++ arch/arm/mach-socfpga/clock_manager_gen5.c | 132 ++- arch/arm/mach-socfpga/include/mach/clock_manager.h | 8 +- .../include/mach/clock_manager_arria10.h | 231 ++++ 6 files changed, 1455 insertions(+), 59 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c mode change 100755 => 100644 arch/arm/mach-socfpga/clock_manager_gen5.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index d81f003..c494930 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -10,7 +10,8 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \ fpga_manager.o board.o

-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \ + reset_manager_arria10.o

obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index d675973..7f48193 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> +#include <fdtdec.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -18,7 +19,12 @@ void cm_wait_for_lock(u32 mask) register u32 inter_val; u32 retry = 0; do { +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + inter_val = readl(&clock_manager_base->stat) & mask; +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; +#endif + /* Wait for stable lock */ if (inter_val == mask) retry++; else @@ -31,22 +37,39 @@ void cm_wait_for_lock(u32 mask) /* function to poll in the fsm busy bit */ void cm_wait_for_fsm(void) { - while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) + while (readl(&clock_manager_base->stat) & + CLKMGR_CLKMGR_STAT_BUSY_SET_MSK) ; }

static void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); + printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("QSPI %8d kHz\n", + cm_get_qspi_controller_clk_hz() / 1000); + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + printf("EOSC1 %8d kHz\n", eosc1_hz / 1000); + printf("cb_intosc %8d kHz\n", cb_intosc_hz / 1000); + printf("f2s_free %8d kHz\n", f2s_free_hz / 1000); + printf("Main VCO %8d kHz\n", cm_get_main_vco_clk_hz()/1000); + printf("NOC %8d kHz\n", cm_get_noc_clk_hz()/1000); + printf("L4 Main %8d kHz\n", + cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB)/1000); + printf("L4 MP %8d kHz\n", + cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB)/1000); + printf("L4 SP %8d kHz\n", + cm_get_l4_sp_clk_hz()/1000); + printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz/1000); +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000); printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000); printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000); printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000); printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000); - printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); - printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); - printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); +#endif }

int set_cpu_clk_info(void) @@ -57,7 +80,12 @@ int set_cpu_clk_info(void)

gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0; + +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + gd->bd->bi_ddr_freq = 0; +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; +#endif

return 0; } diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c new file mode 100644 index 0000000..4fa841f --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -0,0 +1,1104 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> +#include <fdtdec.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 eosc1_hz; +u32 cb_intosc_hz; +u32 f2s_free_hz; +u32 cm_l4_main_clk_hz; +u32 cm_l4_sp_clk_hz; +u32 cm_l4_mp_clk_hz; +u32 cm_l4_sys_free_clk_hz; + +struct strtopu32 { + const char *str; + u32 *p; +}; + +struct mainpll_cfg { + u32 vco0_psrc; + u32 vco1_denom; + u32 vco1_numer; + u32 mpuclk; + u32 mpuclk_cnt; + u32 mpuclk_src; + u32 nocclk; + u32 nocclk_cnt; + u32 nocclk_src; + u32 cntr2clk_cnt; + u32 cntr3clk_cnt; + u32 cntr4clk_cnt; + u32 cntr5clk_cnt; + u32 cntr6clk_cnt; + u32 cntr7clk_cnt; + u32 cntr7clk_src; + u32 cntr8clk_cnt; + u32 cntr9clk_cnt; + u32 cntr9clk_src; + u32 cntr15clk_cnt; + u32 nocdiv_l4mainclk; + u32 nocdiv_l4mpclk; + u32 nocdiv_l4spclk; + u32 nocdiv_csatclk; + u32 nocdiv_cstraceclk; + u32 nocdiv_cspdbclk; +}; + +struct perpll_cfg { + u32 vco0_psrc; + u32 vco1_denom; + u32 vco1_numer; + u32 cntr2clk_cnt; + u32 cntr2clk_src; + u32 cntr3clk_cnt; + u32 cntr3clk_src; + u32 cntr4clk_cnt; + u32 cntr4clk_src; + u32 cntr5clk_cnt; + u32 cntr5clk_src; + u32 cntr6clk_cnt; + u32 cntr6clk_src; + u32 cntr7clk_cnt; + u32 cntr8clk_cnt; + u32 cntr8clk_src; + u32 cntr9clk_cnt; + u32 emacctl_emac0sel; + u32 emacctl_emac1sel; + u32 emacctl_emac2sel; + u32 gpiodiv_gpiodbclk; +}; + +struct alteragrp_cfg { + u32 nocclk; + u32 mpuclk; +}; + +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; + +static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg) +{ + if (fdtdec_get_int_array(blob, node, "altr,of_reg_value", + (u32 *)cfg, cfg_len)) { + /* could not find required property */ + return 100; + } + + return 0; +} + +static int of_get_input_clks(const void *blob, int node, void *cfg) +{ + if (fdtdec_get_int_array(blob, node, "clock-frequency", + (u32 *)cfg, 1)) { + /* could not find required property */ + return 100; + } + + return 0; +} + +static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + struct alteragrp_cfg *altrgrp_cfg) +{ + int node, child, len; + const char *node_name; + + node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK); + + if (node < 0) + return 1; + + child = fdt_first_subnode(blob, node); + + if (child < 0) + return 2; + + child = fdt_first_subnode(blob, child); + + if (child < 0) + return 3; + + node_name = fdt_get_name(blob, child, &len); + + while (node_name) { + if (!strcmp(node_name, "osc1")) { + if (of_get_input_clks(blob, child, &eosc1_hz)) + return 101; + } else if (!strcmp(node_name, "cb_intosc_ls_clk")) { + if (of_get_input_clks(blob, child, &cb_intosc_hz)) + return 102; + } else if (!strcmp(node_name, "f2s_free_clk")) { + if (of_get_input_clks(blob, child, &f2s_free_hz)) + return 103; + } else if (!strcmp(node_name, "main_pll")) { + if (of_to_struct(blob, child, + sizeof(*main_cfg)/sizeof(u32), + main_cfg)) + return 104; + } else if (!strcmp(node_name, "periph_pll")) { + if (of_to_struct(blob, child, + sizeof(*per_cfg)/sizeof(u32), + per_cfg)) + return 105; + } else if (!strcmp(node_name, "altera")) { + if (of_to_struct(blob, child, + sizeof(*altrgrp_cfg)/sizeof(u32), + altrgrp_cfg)) + return 106; + + main_cfg->mpuclk = altrgrp_cfg->mpuclk; + main_cfg->nocclk = altrgrp_cfg->nocclk; + } + child = fdt_next_subnode(blob, child); + + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, &len); + } + + return 0; +} + +/* calculate the intended main VCO frequency based on handoff */ +static unsigned int cm_calc_handoff_main_vco_clk_hz + (struct mainpll_cfg *main_cfg) +{ + unsigned int clk_hz; + + /* Check main VCO clock source: eosc, intosc or f2s? */ + switch (main_cfg->vco0_psrc) { + case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + /* calculate the VCO frequency */ + clk_hz /= (1 + main_cfg->vco1_denom); + clk_hz *= (1 + main_cfg->vco1_numer); + + return clk_hz; +} + +/* calculate the intended periph VCO frequency based on handoff */ +static unsigned int cm_calc_handoff_periph_vco_clk_hz + (struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) +{ + unsigned int clk_hz; + + /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ + switch (per_cfg->vco0_psrc) { + case CLKMGR_PERPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_MAIN: + clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= main_cfg->cntr15clk_cnt; + break; + default: + return 0; + } + + /* calculate the VCO frequency */ + clk_hz /= (1 + per_cfg->vco1_denom); + clk_hz *= (1 + per_cfg->vco1_numer); + + return clk_hz; +} + +/* calculate the intended MPU clock frequency based on handoff */ +static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg) +{ + unsigned int clk_hz; + + /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ + switch (main_cfg->mpuclk_src) { + case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: + clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= ((main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + + 1); + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: + clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); + clk_hz /= (((main_cfg->mpuclk >> + CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1); + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + clk_hz /= (main_cfg->mpuclk_cnt + 1); + return clk_hz; +} + +/* calculate the intended NOC clock frequency based on handoff */ +static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg) +{ + unsigned int clk_hz; + + /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ + switch (main_cfg->nocclk_src) { + case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: + clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= ((main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + + 1); + break; + case CLKMGR_MAINPLL_NOCCLK_SRC_PERI: + clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); + clk_hz /= (((main_cfg->nocclk >> + CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1); + break; + case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + clk_hz /= (main_cfg->nocclk_cnt + 1); + return clk_hz; +} + +/* return 1 if PLL ramp is required */ +static int cm_is_pll_ramp_required(int main0periph1, + struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg) +{ + /* Check for main PLL */ + if (main0periph1 == 0) { + /* + * PLL ramp is not required if both MPU clock and NOC clock are + * not sourced from main PLL + */ + if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && + main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) + return 0; + + /* + * PLL ramp is required if MPU clock is sourced from main PLL + * and MPU clock is over 900MHz (as advised by HW team) + */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && + (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > + CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) + return 1; + + /* + * PLL ramp is required if NOC clock is sourced from main PLL + * and NOC clock is over 300MHz (as advised by HW team) + */ + if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && + (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > + CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) + return 2; + + } else if (main0periph1 == 1) { + /* + * PLL ramp is not required if both MPU clock and NOC clock are + * not sourced from periph PLL + */ + if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI && + main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI) + return 0; + + /* + * PLL ramp is required if MPU clock are source from periph PLL + * and MPU clock is over 900MHz (as advised by HW team) + */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI && + (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > + CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) + return 1; + + /* + * PLL ramp is required if NOC clock are source from periph PLL + * and NOC clock is over 300MHz (as advised by HW team) + */ + if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI && + (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > + CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) + return 2; + } + return 0; +} + +/* + * Calculate the new PLL numerator which is based on existing DTS hand off and + * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the + * numerator while maintaining denominator as denominator will influence the + * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final + * value for numerator is minus with 1 to cater our register value + * representation. + */ +static unsigned int cm_calc_safe_pll_numer(int main0periph1, + struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + unsigned int safe_hz) +{ + unsigned int clk_hz = 0; + + /* Check for main PLL */ + if (main0periph1 == 0) { + /* Check main VCO clock source: eosc, intosc or f2s? */ + switch (main_cfg->vco0_psrc) { + case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + /* Applicable if MPU clock is from main PLL */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { + /* calculate the safe numer value */ + clk_hz = (safe_hz / clk_hz) * + (main_cfg->mpuclk_cnt + 1) * + ((main_cfg->mpuclk & + CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) * + (1 + main_cfg->vco1_denom) - 1; + } + /* Reach here if MPU clk not from main PLL but NOC clk is */ + else if (main_cfg->nocclk_src == + CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { + /* calculate the safe numer value */ + clk_hz = (safe_hz / clk_hz) * + (main_cfg->nocclk_cnt + 1) * + ((main_cfg->nocclk & + CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) * + (1 + main_cfg->vco1_denom) - 1; + } else + clk_hz = 0; + + } else if (main0periph1 == 1) { + /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ + switch (per_cfg->vco0_psrc) { + case CLKMGR_PERPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_MAIN: + clk_hz = cm_calc_handoff_main_vco_clk_hz( + main_cfg); + clk_hz /= main_cfg->cntr15clk_cnt; + break; + default: + return 0; + } + /* Applicable if MPU clock is from periph PLL */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { + /* calculate the safe numer value */ + clk_hz = (safe_hz / clk_hz) * + (main_cfg->mpuclk_cnt + 1) * + (((main_cfg->mpuclk >> + CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) * + (1 + per_cfg->vco1_denom) - 1; + } + /* Reach here if MPU clk not from periph PLL but NOC clk is */ + else if (main_cfg->nocclk_src == + CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { + /* calculate the safe numer value */ + clk_hz = (safe_hz / clk_hz) * + (main_cfg->nocclk_cnt + 1) * + (((main_cfg->nocclk >> + CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) * + (1 + per_cfg->vco1_denom) - 1; + } else + clk_hz = 0; + } + return clk_hz; +} + +/* ramping the main PLL to final value */ +static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + unsigned int pll_ramp_main_hz) +{ + unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; + + /* find out the increment value */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { + clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; + clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); + } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { + clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; + clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); + } + /* execute the ramping here */ + for (clk_hz = pll_ramp_main_hz + clk_incr_hz; + clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { + writel((main_cfg->vco1_denom << + CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), + &clock_manager_base->main_pll.vco1); + udelay(1000); + cm_wait_for_lock(LOCKED_MASK); + } + writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + main_cfg->vco1_numer, + &clock_manager_base->main_pll.vco1); + udelay(1000); + cm_wait_for_lock(LOCKED_MASK); +} + +/* ramping the periph PLL to final value */ +static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + unsigned int pll_ramp_periph_hz) +{ + unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; + + /* find out the increment value */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { + clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; + clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); + } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { + clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; + clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); + } + /* execute the ramping here */ + for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; + clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { + writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), + &clock_manager_base->per_pll.vco1); + udelay(1000); + cm_wait_for_lock(LOCKED_MASK); + } + writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + per_cfg->vco1_numer, + &clock_manager_base->per_pll.vco1); + udelay(1000); + cm_wait_for_lock(LOCKED_MASK); +} + +/* + * Setup clocks while making no assumptions of the + * previous state of the clocks. + * + * Start by being paranoid and gate all sw managed clocks + * + * Put all plls in bypass + * + * Put all plls VCO registers back to reset value (bgpwr dwn). + * + * Put peripheral and main pll src to reset value to avoid glitch. + * + * Delay 5 us. + * + * Deassert bg pwr dn and set numerator and denominator + * + * Start 7 us timer. + * + * set internal dividers + * + * Wait for 7 us timer. + * + * Enable plls + * + * Set external dividers while plls are locking + * + * Wait for pll lock + * + * Assert/deassert outreset all. + * + * Take all pll's out of bypass + * + * Clear safe mode + * + * set source main and peripheral clocks + * + * Ungate clocks + */ + +static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) +{ + unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0, + ramp_required; + + /* gate off all mainpll clock excpet HW managed clock */ + writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | + CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, + &clock_manager_base->main_pll.enr); + + /* now we can gate off the rest of the peripheral clocks */ + writel(0, &clock_manager_base->per_pll.en); + + /* Put all plls in external bypass */ + writel(CLKMGR_MAINPLL_BYPASS_RESET, + &clock_manager_base->main_pll.bypasss); + writel(CLKMGR_PERPLL_BYPASS_RESET, + &clock_manager_base->per_pll.bypasss); + + /* + * Put all plls VCO registers back to reset value. + * Some code might have messed with them. At same time set the + * desired clock source + */ + writel(CLKMGR_MAINPLL_VCO0_RESET | + CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | + (main_cfg->vco0_psrc << + CLKMGR_MAINPLL_VCO0_PSRC_LSB), + &clock_manager_base->main_pll.vco0); + + writel(CLKMGR_PERPLL_VCO0_RESET | + CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | + (per_cfg->vco0_psrc << + CLKMGR_PERPLL_VCO0_PSRC_LSB), + &clock_manager_base->per_pll.vco0); + + writel(CLKMGR_MAINPLL_VCO1_RESET, + &clock_manager_base->main_pll.vco1); + writel(CLKMGR_PERPLL_VCO1_RESET, + &clock_manager_base->per_pll.vco1); + + /* clear the interrupt register status register */ + writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, + &clock_manager_base->intr); + + /* Program VCO Numerator and Denominator for main PLL */ + ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); + if (ramp_required) { + /* set main PLL to safe starting threshold frequency */ + if (ramp_required == 1) + pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; + else if (ramp_required == 2) + pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; + + writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(0, main_cfg, per_cfg, + pll_ramp_main_hz), + &clock_manager_base->main_pll.vco1); + } else + writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + main_cfg->vco1_numer, + &clock_manager_base->main_pll.vco1); + + /* Program VCO Numerator and Denominator for periph PLL */ + ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); + if (ramp_required) { + /* set periph PLL to safe starting threshold frequency */ + if (ramp_required == 1) + pll_ramp_periph_hz = + CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; + else if (ramp_required == 2) + pll_ramp_periph_hz = + CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; + + writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(1, main_cfg, per_cfg, + pll_ramp_periph_hz), + &clock_manager_base->per_pll.vco1); + } else + writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + per_cfg->vco1_numer, + &clock_manager_base->per_pll.vco1); + + /* Wait for at least 5 us */ + udelay(5); + + /* Now deassert BGPWRDN and PWRDN */ + clrbits_le32(&clock_manager_base->main_pll.vco0, + CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | + CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); + clrbits_le32(&clock_manager_base->per_pll.vco0, + CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | + CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); + + /* Wait for at least 7 us */ + udelay(7); + + /* enable the VCO and disable the external regulator to PLL */ + writel((readl(&clock_manager_base->main_pll.vco0) & + ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | + CLKMGR_MAINPLL_VCO0_EN_SET_MSK, + &clock_manager_base->main_pll.vco0); + writel((readl(&clock_manager_base->per_pll.vco0) & + ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | + CLKMGR_PERPLL_VCO0_EN_SET_MSK, + &clock_manager_base->per_pll.vco0); + + /* setup all the main PLL counter and clock source */ + writel(main_cfg->nocclk, + SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET); + writel(main_cfg->mpuclk, + SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); + + /* main_emaca_clk divider */ + writel(main_cfg->cntr2clk_cnt, + &clock_manager_base->main_pll.cntr2clk); + /* main_emacb_clk divider */ + writel(main_cfg->cntr3clk_cnt, + &clock_manager_base->main_pll.cntr3clk); + /* main_emac_ptp_clk divider */ + writel(main_cfg->cntr4clk_cnt, + &clock_manager_base->main_pll.cntr4clk); + /* main_gpio_db_clk divider */ + writel(main_cfg->cntr5clk_cnt, + &clock_manager_base->main_pll.cntr5clk); + /* main_sdmmc_clk divider */ + writel(main_cfg->cntr6clk_cnt, + &clock_manager_base->main_pll.cntr6clk); + /* main_s2f_user0_clk divider */ + writel(main_cfg->cntr7clk_cnt | + (main_cfg->cntr7clk_src << + CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), + &clock_manager_base->main_pll.cntr7clk); + /* main_s2f_user1_clk divider */ + writel(main_cfg->cntr8clk_cnt, + &clock_manager_base->main_pll.cntr8clk); + /* main_hmc_pll_clk divider */ + writel(main_cfg->cntr9clk_cnt | + (main_cfg->cntr9clk_src << + CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), + &clock_manager_base->main_pll.cntr9clk); + /* main_periph_ref_clk divider */ + writel(main_cfg->cntr15clk_cnt, + &clock_manager_base->main_pll.cntr15clk); + + /* setup all the peripheral PLL counter and clock source */ + /* peri_emaca_clk divider */ + writel(per_cfg->cntr2clk_cnt | + (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr2clk); + /* peri_emacb_clk divider */ + writel(per_cfg->cntr3clk_cnt | + (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr3clk); + /* peri_emac_ptp_clk divider */ + writel(per_cfg->cntr4clk_cnt | + (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr4clk); + /* peri_gpio_db_clk divider */ + writel(per_cfg->cntr5clk_cnt | + (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr5clk); + /* peri_sdmmc_clk divider */ + writel(per_cfg->cntr6clk_cnt | + (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr6clk); + /* peri_s2f_user0_clk divider */ + writel(per_cfg->cntr7clk_cnt, + &clock_manager_base->per_pll.cntr7clk); + /* peri_s2f_user1_clk divider */ + writel(per_cfg->cntr8clk_cnt | + (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr8clk); + /* peri_hmc_pll_clk divider */ + writel(per_cfg->cntr9clk_cnt, + &clock_manager_base->per_pll.cntr9clk); + + /* setup all the external PLL counter */ + /* mpu wrapper / external divider */ + writel(main_cfg->mpuclk_cnt | + (main_cfg->mpuclk_src << + CLKMGR_MAINPLL_MPUCLK_SRC_LSB), + &clock_manager_base->main_pll.mpuclk); + /* NOC wrapper / external divider */ + writel(main_cfg->nocclk_cnt | + (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), + &clock_manager_base->main_pll.nocclk); + /* NOC subclock divider such as l4 */ + writel(main_cfg->nocdiv_l4mainclk | + (main_cfg->nocdiv_l4mpclk << + CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | + (main_cfg->nocdiv_l4spclk << + CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | + (main_cfg->nocdiv_csatclk << + CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | + (main_cfg->nocdiv_cstraceclk << + CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | + (main_cfg->nocdiv_cspdbclk << + CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), + &clock_manager_base->main_pll.nocdiv); + /* gpio_db external divider */ + writel(per_cfg->gpiodiv_gpiodbclk, + &clock_manager_base->per_pll.gpiodiv); + + /* setup the EMAC clock mux select */ + writel((per_cfg->emacctl_emac0sel << + CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | + (per_cfg->emacctl_emac1sel << + CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | + (per_cfg->emacctl_emac2sel << + CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), + &clock_manager_base->per_pll.emacctl); + + /* at this stage, check for PLL lock status */ + cm_wait_for_lock(LOCKED_MASK); + + /* + * after locking, but before taking out of bypass, + * assert/deassert outresetall + */ + /* assert mainpll outresetall */ + setbits_le32(&clock_manager_base->main_pll.vco0, + CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); + /* assert perpll outresetall */ + setbits_le32(&clock_manager_base->per_pll.vco0, + CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); + /* de-assert mainpll outresetall */ + clrbits_le32(&clock_manager_base->main_pll.vco0, + CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); + /* de-assert perpll outresetall */ + clrbits_le32(&clock_manager_base->per_pll.vco0, + CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); + + /* Take all PLLs out of bypass when boot mode is cleared. */ + /* release mainpll from bypass */ + writel(CLKMGR_MAINPLL_BYPASS_RESET, + &clock_manager_base->main_pll.bypassr); + /* wait till Clock Manager is not busy */ + cm_wait_for_fsm(); + + /* release perpll from bypass */ + writel(CLKMGR_PERPLL_BYPASS_RESET, + &clock_manager_base->per_pll.bypassr); + /* wait till Clock Manager is not busy */ + cm_wait_for_fsm(); + + /* clear boot mode */ + clrbits_le32(&clock_manager_base->ctrl, + CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); + /* wait till Clock Manager is not busy */ + cm_wait_for_fsm(); + + /* At here, we need to ramp to final value if needed */ + if (pll_ramp_main_hz != 0) + cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); + if (pll_ramp_periph_hz != 0) + cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); + + /* Now ungate non-hw-managed clocks */ + writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | + CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, + &clock_manager_base->main_pll.ens); + writel(CLKMGR_PERPLL_EN_RESET, + &clock_manager_base->per_pll.ens); + + /* Clear the loss lock and slip bits as they might set during + clock reconfiguration */ + writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, + &clock_manager_base->intr); + + return 0; +} + +void cm_use_intosc(void) +{ + setbits_le32(&clock_manager_base->ctrl, + CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); +} + +unsigned int cm_get_noc_clk_hz(void) +{ + unsigned int clk_src, dividor, nocclk, src_hz; + + nocclk = readl(&clock_manager_base->main_pll.nocclk); + clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) & + CLKMGR_MAINPLL_NOCCLK_SRC_MSK; + + dividor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK); + + if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) { + src_hz = cm_get_main_vco_clk_hz(); + src_hz /= 1 + + (readl(SOCFPGA_CLKMGR_ADDRESS+CLKMGR_MAINPLL_NOC_CLK_OFFSET)& + CLKMGR_MAINPLL_NOCCLK_CNT_MSK); + } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) { + src_hz = cm_get_per_vco_clk_hz(); + src_hz /= 1 + + ((readl(SOCFPGA_CLKMGR_ADDRESS+CLKMGR_MAINPLL_NOC_CLK_OFFSET)>> + CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB)& + CLKMGR_MAINPLL_NOCCLK_CNT_MSK); + } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) { + src_hz = eosc1_hz; + } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) { + src_hz = cb_intosc_hz; + } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) { + src_hz = f2s_free_hz; + } else { + src_hz = 0; + } + return src_hz/dividor; +} + +unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift) +{ + unsigned int dividor2 = 1 << + ((readl(&clock_manager_base->main_pll.nocdiv) >> + nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK); + + return cm_get_noc_clk_hz()/dividor2; +} + +int cm_basic_init(const void *blob) +{ + struct mainpll_cfg main_cfg; + struct perpll_cfg per_cfg; + struct alteragrp_cfg altrgrp_cfg; + int rval; + + /* initialize to zero for use case of optional node */ + memset(&main_cfg, 0, sizeof(main_cfg)); + memset(&per_cfg, 0, sizeof(per_cfg)); + memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg)); + + if (of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg)) + return 1; + + rval = cm_full_cfg(&main_cfg, &per_cfg); + + cm_l4_main_clk_hz = + cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); + + cm_l4_mp_clk_hz = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); + + cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz(); + + cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz()/4; + + return rval; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + u32 reg, clk_hz; + u32 clk_src, mainmpuclk_reg; + + mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk); + + clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) & + CLKMGR_MAINPLL_MPUCLK_SRC_MSK; + + reg = readl(&clock_manager_base->altera.mpuclk); + /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ + switch (clk_src) { + case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: + clk_hz = cm_get_main_vco_clk_hz(); + clk_hz /= ((reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + + 1); + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: + clk_hz = cm_get_per_vco_clk_hz(); + clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1); + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + default: + printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src); + return 0; + } + + clk_hz /= ((mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1); + + return clk_hz; +} + +unsigned int cm_get_per_vco_clk_hz(void) +{ + u32 src_hz = 0; + u32 clk_src = 0; + u32 numer = 0; + u32 denom = 0; + u32 vco = 0; + + clk_src = readl(&clock_manager_base->per_pll.vco0); + + clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) & + CLKMGR_PERPLL_VCO0_PSRC_MSK; + + if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) { + src_hz = eosc1_hz; + } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) { + src_hz = cb_intosc_hz; + } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) { + src_hz = f2s_free_hz; + } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) { + src_hz = cm_get_main_vco_clk_hz(); + src_hz /= (readl + (&clock_manager_base->main_pll.cntr15clk) & + CLKMGR_MAINPLL_CNTRCLK_MSK) + 1; + } else { + printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src); + return 0; + } + + vco = readl(&clock_manager_base->per_pll.vco1); + + numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK; + + denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) & + CLKMGR_PERPLL_VCO1_DENOM_MSK; + + vco = src_hz; + vco /= (1 + denom); + vco *= (1 + numer); + + return vco; +} + +unsigned int cm_get_main_vco_clk_hz(void) +{ + u32 src_hz, numer, denom, vco; + + u32 clk_src = readl(&clock_manager_base->main_pll.vco0); + + clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) & + CLKMGR_MAINPLL_VCO0_PSRC_MSK; + + if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) { + src_hz = eosc1_hz; + } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) { + src_hz = cb_intosc_hz; + } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) { + src_hz = f2s_free_hz; + } else { + printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src); + return 0; + } + + vco = readl(&clock_manager_base->main_pll.vco1); + + numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK; + + denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) & + CLKMGR_MAINPLL_VCO1_DENOM_MSK; + + vco = src_hz; + vco /= (1 + denom); + vco *= (1 + numer); + + return vco; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB); +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + u32 clk_hz = 0; + u32 clk_input = 0; + + clk_input = readl(&clock_manager_base->per_pll.cntr6clk); + clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) & + CLKMGR_PERPLLGRP_SRC_MSK; + + switch (clk_input) { + case CLKMGR_PERPLLGRP_SRC_MAIN: + clk_hz = cm_get_main_vco_clk_hz(); + clk_hz /= 1 + + (readl + (&clock_manager_base->main_pll.cntr6clk) & + CLKMGR_MAINPLL_CNTRCLK_MSK); + break; + + case CLKMGR_PERPLLGRP_SRC_PERI: + clk_hz = cm_get_per_vco_clk_hz(); + clk_hz /= 1 + (readl + (&clock_manager_base->per_pll.cntr6clk) & + CLKMGR_PERPLL_CNTRCLK_MSK); + break; + + case CLKMGR_PERPLLGRP_SRC_OSC1: + clk_hz = eosc1_hz; + break; + + case CLKMGR_PERPLLGRP_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + + case CLKMGR_PERPLLGRP_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + } + + return clk_hz/4; +} + +unsigned int cm_get_spi_controller_clk_hz(void) +{ + return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); +} + +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); +} diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c old mode 100755 new mode 100644 index 1df2ed4..5632843 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -1,7 +1,7 @@ /* - * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * Copyright (C) 2016-2017 Intel Corporation * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 */

#include <common.h> @@ -65,7 +65,6 @@ static void cm_write_with_phase(u32 value, * set source main and peripheral clocks * Ungate clocks */ - void cm_basic_init(const struct cm_config * const cfg) { unsigned long end; @@ -304,58 +303,75 @@ void cm_basic_init(const struct cm_config * const cfg) &clock_manager_base->inter); }

-static unsigned int cm_get_main_vco_clk_hz(void) +unsigned int cm_get_main_vco_clk_hz(void) { - u32 reg, clock; + u32 src_hz, numer, denom, vco;

/* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); - clock = cm_get_osc_clk_hz(1); - clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> - CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; - clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> - CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1; + vco = readl(&clock_manager_base->main_pll.vco);

- return clock; + numer = ((vco & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET); + denom = ((vco & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET); + + src_hz = cm_get_osc_clk_hz(1); + + vco = src_hz; + vco /= (1 + denom); + vco *= (1 + numer); + + return vco; }

-static unsigned int cm_get_per_vco_clk_hz(void) +unsigned int cm_get_per_vco_clk_hz(void) { - u32 reg, clock = 0; + u32 src_hz = 0; + u32 clk_src = 0; + u32 numer = 0; + u32 denom = 0; + u32 vco = 0;

/* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); - reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> + clk_src = readl(&clock_manager_base->per_pll.vco); + clk_src = (clk_src & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = cm_get_osc_clk_hz(1); - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = cm_get_osc_clk_hz(2); - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = cm_get_f2s_per_ref_clk_hz(); + if (clk_src == CLKMGR_VCO_SSRC_EOSC1) + src_hz = cm_get_osc_clk_hz(1); + else if (clk_src == CLKMGR_VCO_SSRC_EOSC2) + src_hz = cm_get_osc_clk_hz(2); + else if (clk_src == CLKMGR_VCO_SSRC_F2S) + src_hz = cm_get_f2s_per_ref_clk_hz();

/* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); - clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> - CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; - clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> - CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1; + vco = readl(&clock_manager_base->per_pll.vco);

- return clock; + numer = (vco & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET; + + denom = (vco & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET; + + vco = src_hz; + vco /= (1 + denom); + vco *= (1 + numer); + + return vco; }

unsigned long cm_get_mpu_clk_hz(void) { - u32 reg, clock; + u32 reg, clk_hz;

- clock = cm_get_main_vco_clk_hz(); + clk_hz = cm_get_main_vco_clk_hz();

/* get the MPU clock */ reg = readl(&clock_manager_base->altera.mpuclk); - clock /= (reg + 1); + clk_hz /= (reg + 1); reg = readl(&clock_manager_base->main_pll.mpuclk); - clock /= (reg + 1); - return clock; + clk_hz /= (reg + 1); + + return clk_hz; }

unsigned long cm_get_sdram_clk_hz(void) @@ -391,7 +407,8 @@ unsigned long cm_get_sdram_clk_hz(void)

unsigned int cm_get_l4_sp_clk_hz(void) { - u32 reg, clock = 0; + u32 clock = 0; + u32 reg;

/* identify the source of L4 SP clock */ reg = readl(&clock_manager_base->main_pll.l4src); @@ -425,37 +442,45 @@ unsigned int cm_get_l4_sp_clk_hz(void)

unsigned int cm_get_mmc_controller_clk_hz(void) { - u32 reg, clock = 0; + u32 clk_hz = 0; + u32 clk_input = 0;

- /* identify the source of MMC clock */ - reg = readl(&clock_manager_base->per_pll.src); - reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> + clk_input = readl(&clock_manager_base->per_pll.src); + clk_input = (clk_input & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;

- if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { - clock = cm_get_f2s_per_ref_clk_hz(); - } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { - clock = cm_get_main_vco_clk_hz(); + switch (clk_input) { + case CLKMGR_SDMMC_CLK_SRC_F2S: + clk_hz = cm_get_f2s_per_ref_clk_hz(); + break; + + case CLKMGR_SDMMC_CLK_SRC_MAIN: + clk_hz = cm_get_main_vco_clk_hz();

/* get the SDMMC clock */ - reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); - clock /= (reg + 1); - } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { - clock = cm_get_per_vco_clk_hz(); + clk_input = + readl(&clock_manager_base->main_pll.mainnandsdmmcclk); + clk_hz /= (clk_input + 1); + break; + + case CLKMGR_SDMMC_CLK_SRC_PER: + clk_hz = cm_get_per_vco_clk_hz();

/* get the SDMMC clock */ - reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); - clock /= (reg + 1); + clk_input = + readl(&clock_manager_base->per_pll.pernandsdmmcclk); + clk_hz /= (clk_input + 1); + break; }

- /* further divide by 4 as we have fixed divider at wrapper */ - clock /= 4; - return clock; + return clk_hz / 4; }

+ unsigned int cm_get_qspi_controller_clk_hz(void) { - u32 reg, clock = 0; + u32 clock = 0; + u32 reg;

/* identify the source of QSPI clock */ reg = readl(&clock_manager_base->per_pll.src); @@ -483,7 +508,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void)

unsigned int cm_get_spi_controller_clk_hz(void) { - u32 reg, clock = 0; + u32 clock = 0; + u32 reg;

clock = cm_get_per_vco_clk_hz();

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 123f6e2..0b099ba 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -12,7 +12,13 @@ void cm_wait_for_lock(u32 mask); void cm_wait_for_fsm(void); #endif

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +/* Common mask */ +#define CLKMGR_CLKMGR_STAT_BUSY_SET_MSK 0x00000001 + +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/clock_manager_arria10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <asm/arch/clock_manager_gen5.h> #endif + #endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h new file mode 100644 index 0000000..fc0bfe7 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef CLOCK_MANAGER_ARRIA10 +#define CLOCK_MANAGER_ARRIA10 + +#ifndef __ASSEMBLER__ + +struct socfpga_clock_manager_main_pll { + u32 vco0; + u32 vco1; + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 mpuclk; + u32 nocclk; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 pad_0x48_0x5b[5]; + u32 cntr15clk; + u32 outrst; + u32 outrststat; + u32 nocdiv; + u32 pad_0x6c_0x80[5]; +}; + +struct socfpga_clock_manager_per_pll { + u32 vco0; + u32 vco1; + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 pad_0x20_0x27[2]; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 pad_0x48_0x5f[6]; + u32 outrst; + u32 outrststat; + u32 emacctl; + u32 gpiodiv; + u32 pad_0x70_0x80[4]; +}; + +struct socfpga_clock_manager_altera { + u32 mpuclk; + u32 nocclk; + u32 mainmisc0; + u32 mainmisc1; + u32 perimisc0; + u32 perimisc1; +}; + +struct socfpga_clock_manager { + /* clkmgr */ + u32 ctrl; + u32 intr; + u32 intrs; + u32 intrr; + u32 intren; + u32 intrens; + u32 intrenr; + u32 stat; + u32 testioctrl; + u32 _pad_0x24_0x40[7]; + /* mainpllgrp */ + struct socfpga_clock_manager_main_pll main_pll; + /* perpllgrp */ + struct socfpga_clock_manager_per_pll per_pll; + struct socfpga_clock_manager_altera altera; +}; + +void cm_use_intosc(void); +unsigned int cm_get_noc_clk_hz(void); +unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift); +int cm_basic_init(const void *blob); + +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_main_vco_clk_hz(void); +unsigned int cm_get_per_vco_clk_hz(void); +unsigned long cm_get_mpu_clk_hz(void); + +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); + +extern u32 cm_l4_main_clk_hz; +extern u32 cm_l4_sp_clk_hz; +extern u32 cm_l4_mp_clk_hz; +extern u32 cm_l4_sys_free_clk_hz; +extern u32 eosc1_hz; +extern u32 cb_intosc_hz; +extern u32 f2s_free_hz; + +#endif /* __ASSEMBLER__ */ + +#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140 +#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144 +#define LOCKED_MASK \ + (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \ + CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK) + +/* value */ +#define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f +#define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff +#define CLKMGR_MAINPLL_VCO0_RESET 0x00010053 +#define CLKMGR_MAINPLL_VCO1_RESET 0x00010001 +#define CLKMGR_PERPLL_VCO0_RESET 0x00010053 +#define CLKMGR_PERPLL_VCO1_RESET 0x00010001 +#define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0 +#define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1 +#define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2 +#define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0 +#define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1 +#define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2 +#define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3 + +/* mask */ +#define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK 0x00000040 +#define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK 0x00000080 +#define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK 0x00000100 +#define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK 0x00000200 +#define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK 0x00020000 +#define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001 +#define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002 +#define CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004 +#define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008 +#define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010 +#define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK 0x00000001 +#define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK 0x00000002 +#define CLKMGR_PERPLL_VCO0_EN_SET_MSK 0x00000004 +#define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008 +#define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010 +#define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK 0x00000800 +#define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK 0x00000400 +#define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK 0x00000200 +#define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK 0x00000100 +#define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK 0x00000008 +#define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK 0x00000004 +#define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK 0x00000001 +#define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK 0x00000002 +#define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK 0x00000001 +#define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300 +#define CLKMGR_PERPLL_EN_RESET 0x00000f7f +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020 +#define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003 +#define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff +#define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f +#define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff +#define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003 +#define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff +#define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f +#define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff +#define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007 +#define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff +#define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0 +#define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1 +#define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2 +#define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3 +#define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4 +#define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003 +#define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff +#define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007 +#define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0 +#define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1 +#define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2 +#define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3 +#define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4 + +#define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007 +#define CLKMGR_PERPLLGRP_SRC_MAIN 0 +#define CLKMGR_PERPLLGRP_SRC_PERI 1 +#define CLKMGR_PERPLLGRP_SRC_OSC1 2 +#define CLKMGR_PERPLLGRP_SRC_INTOSC 3 +#define CLKMGR_PERPLLGRP_SRC_FPGA 4 + +/* bit shifting macro */ +#define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8 +#define CLKMGR_PERPLL_VCO0_PSRC_LSB 8 +#define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16 +#define CLKMGR_PERPLL_VCO1_DENOM_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0 +#define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8 +#define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16 +#define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24 +#define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26 +#define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28 +#define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26 +#define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27 +#define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28 + +/* PLL ramping work around */ +#define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000 +#define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000 +#define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000 +#define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000 + +#endif /* CLOCK_MANAGER_ARRIA10 */

Add system manager support for Arria 10.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- .../arm/mach-socfpga/include/mach/system_manager.h | 54 ++++++++++++++- .../include/mach/system_manager_arria10.h | 81 ++++++++++++++++++++++ .../include/mach/system_manager_gen5.h | 1 + 3 files changed, 135 insertions(+), 1 deletion(-) create mode 100755 arch/arm/mach-socfpga/include/mach/system_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 53ced81..324d13f 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -31,7 +31,59 @@ #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +/* For dedicated IO configuration */ +/* Voltage select enums */ +#define VOLTAGE_SEL_3V 0x0 +#define VOLTAGE_SEL_1P8V 0x1 +#define VOLTAGE_SEL_2P5V 0x2 + +/* Input buffer enable */ +#define INPUT_BUF_DISABLE 0 +#define INPUT_BUF_1P8V 1 +#define INPUT_BUF_2P5V3V 2 + +/* Weak pull up enable */ +#define WK_PU_DISABLE 0 +#define WK_PU_ENABLE 1 + +/* Pull up slew rate control */ +#define PU_SLW_RT_SLOW 0 +#define PU_SLW_RT_FAST 1 +#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW + +/* Pull down slew rate control */ +#define PD_SLW_RT_SLOW 0 +#define PD_SLW_RT_FAST 1 +#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW + +/* Drive strength control */ +#define PU_DRV_STRG_DEFAULT 0x10 +#define PD_DRV_STRG_DEFAULT 0x10 + +/* bit position */ +#define PD_DRV_STRG_LSB 0 +#define PD_SLW_RT_LSB 5 +#define PU_DRV_STRG_LSB 8 +#define PU_SLW_RT_LSB 13 +#define WK_PU_LSB 16 +#define INPUT_BUF_LSB 17 +#define BIAS_TRIM_LSB 19 +#define VOLTAGE_SEL_LSB 0 + +#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x00000001 +#define ALT_SYSMGR_NOC_LWH2F_SET_MSK 0x00000010 +#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x00000100 +#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK 0x00010000 +#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK 0x00100000 +#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK 0x01000000 +#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x00000001 + +#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x00000002 +#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x00000002 + +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/system_manager_arria10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <asm/arch/system_manager_gen5.h> #endif

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h new file mode 100755 index 0000000..78432ec --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYSTEM_MANAGER_ARRIA10_H_ +#define _SYSTEM_MANAGER_ARRIA10_H_ + +struct socfpga_system_manager { + u32 siliconid1; + u32 siliconid2; + u32 wddbg; + u32 bootinfo; + u32 mpu_ctrl_l2_ecc; + u32 _pad_0x14_0x1f[3]; + u32 dma; + u32 dma_periph; + u32 sdmmcgrp_ctrl; + u32 sdmmc_l3master; + u32 nand_bootstrap; + u32 nand_l3master; + u32 usb0_l3master; + u32 usb1_l3master; + u32 emac_global; + u32 emac[3]; + u32 _pad_0x50_0x5f[4]; + u32 fpgaintf_en_global; + u32 fpgaintf_en_0; + u32 fpgaintf_en_1; + u32 fpgaintf_en_2; + u32 fpgaintf_en_3; + u32 _pad_0x74_0x7f[3]; + u32 noc_addr_remap_value; + u32 noc_addr_remap_set; + u32 noc_addr_remap_clear; + u32 _pad_0x8c_0x8f; + u32 ecc_intmask_value; + u32 ecc_intmask_set; + u32 ecc_intmask_clr; + u32 ecc_intstatus_serr; + u32 ecc_intstatus_derr; + u32 mpu_status_l2_ecc; + u32 mpu_clear_l2_ecc; + u32 mpu_status_l1_parity; + u32 mpu_clear_l1_parity; + u32 mpu_set_l1_parity; + u32 _pad_0xb8_0xbf[2]; + u32 noc_timeout; + u32 noc_idlereq_set; + u32 noc_idlereq_clr; + u32 noc_idlereq_value; + u32 noc_idleack; + u32 noc_idlestatus; + u32 fpga2soc_ctrl; + u32 _pad_0xdc_0xff[9]; + u32 tsmc_tsel_0; + u32 tsmc_tsel_1; + u32 tsmc_tsel_2; + u32 tsmc_tsel_3; + u32 _pad_0x110_0x200[60]; + u32 romhw_ctrl; + u32 romcode_ctrl; + u32 romcode_cpu1startaddr; + u32 romcode_initswstate; + u32 romcode_initswlastld; + u32 _pad_0x214_0x217; + u32 warmram_enable; + u32 warmram_datastart; + u32 warmram_length; + u32 warmram_execution; + u32 warmram_crc; + u32 _pad_0x22c_0x22f; + u32 isw_handoff[8]; + u32 romcode_bootromswstate[8]; +}; + +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 12 + +#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h index 3ad4ca1..285c1a2 100755 --- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h @@ -117,5 +117,6 @@ struct socfpga_system_manager { #endif

#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 0

#endif /* _SYSTEM_MANAGER_GEN5_H_ */

Add misc support for Arria 10 and minor fix on misc Gen5.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/misc.h | 6 + arch/arm/mach-socfpga/misc_arria10.c | 262 ++++++++++++++++++++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 3 +- 4 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-socfpga/misc_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index c494930..9c4617f 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -11,6 +11,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \ fpga_manager.o board.o

obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \ + misc_arria10.o \ reset_manager_arria10.o

obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 64f9b86..446ee0f 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -23,4 +23,10 @@ void socfpga_fpga_add(void); inline void socfpga_fpga_add(void) {} #endif

+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +unsigned int dedicated_uart_com_port(const void *blob); +unsigned int shared_uart_com_port(const void *blob); +unsigned int uart_com_port(const void *blob); +#endif + #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c new file mode 100644 index 0000000..2e89067 --- /dev/null +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <altera.h> +#include <miiphy.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/sdram_arria10.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/nic301.h> +#include <asm/pl310.h> +#include <fdtdec.h> +#include <ns16550.h> + +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 + +DECLARE_GLOBAL_DATA_PTR; + +static int find_peripheral_uart(const void *blob, + int child, const char *node_name); +static int is_peripheral_uart_true(const void *blob, + int node, const char *child_name); + +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) +{ + u32 reset; + + if (of_reset_id == EMAC0_RESET) { + reset = SOCFPGA_RESET(EMAC0); + } else if (of_reset_id == EMAC1_RESET) { + reset = SOCFPGA_RESET(EMAC1); + } else if (of_reset_id == EMAC2_RESET) { + reset = SOCFPGA_RESET(EMAC2); + } else { + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); + return; + } + + clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + phymode); + + /* Release the EMAC controller from reset */ + socfpga_per_reset(reset, 0); +} +#endif + +/* ++ * This function initializes security policies to be consistent across ++ * all logic units in the Arria 10. ++ * ++ * The idea is to set all security policies to be normal, nonsecure ++ * for all units. ++ */ +static void initialize_security_policies(void) +{ + /* Put OCRAM in non-secure */ + writel(0x003f0000, &noc_fw_ocram_base->region0); + writel(0x1, &noc_fw_ocram_base->enable); + + /* Put DDR in non-secure */ + writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr); + writel(0x1, &noc_fw_ddr_l3_base->enable); +} + +int arch_early_init_r(void) +{ + initialize_security_policies(); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, &pl310->pl310_addr_filter_start); + + /* assert reset to all except L4WD0 and L4TIMER0 */ + socfpga_per_reset_all(); + + /* configuring the clock based on handoff */ + /* TODO: Add call to cm_basic_init() */ + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + return 0; +} + +/* + * This function looking the 1st encounter UART peripheral, + * and then return its offset of the dedicated/shared IO pin + * mux. offset value (zero and above). + */ +static int find_peripheral_uart(const void *blob, + int child, const char *node_name) +{ + int len; + fdt_addr_t base_addr = 0; + fdt_size_t size; + const u32 *cell; + u32 value, offset = 0; + + base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); + if (base_addr != FDT_ADDR_T_NONE) { + cell = fdt_getprop(blob, child, "pinctrl-single,pins", + &len); + if (cell != NULL) { + for (; len > 0; len -= (2 * sizeof(u32))) { + offset = fdt32_to_cpu(*cell++); + value = fdt32_to_cpu(*cell++); + /* Found UART peripheral */ + if (0x0D == value) + return offset; + } + } + } + return -1; +} + +/* + * This function looking the 1st encounter UART peripheral, + * and then return its offset of the dedicated/shared IO pin + * mux. UART peripheral is found if the offset is not in negative + * value. + */ +static int is_peripheral_uart_true(const void *blob, + int node, const char *child_name) +{ + int child, len; + const char *node_name; + + child = fdt_first_subnode(blob, node); + + if (child < 0) + return -1; + + node_name = fdt_get_name(blob, child, &len); + + while (node_name) { + if (!strcmp(child_name, node_name)) + return find_peripheral_uart(blob, child, node_name); + + child = fdt_next_subnode(blob, child); + + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, &len); + } + + return -1; +} + +/* + * This function looking the 1st encounter UART dedicated IO peripheral, + * and then return based address of the 1st encounter UART dedicated + * IO peripheral. + */ +unsigned int dedicated_uart_com_port(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return 0; + + if (0 <= is_peripheral_uart_true(blob, node, "dedicated")) + return SOCFPGA_UART1_ADDRESS; + else + return 0; +} + +/* + * This function looking the 1st encounter UART shared IO peripheral, and then + * return based address of the 1st encounter UART shared IO peripheral. + */ +unsigned int shared_uart_com_port(const void *blob) +{ + int node, ret; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return 0; + + ret = is_peripheral_uart_true(blob, node, "shared"); + + if (PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 == ret || + PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 == ret || + PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 == ret) + return SOCFPGA_UART0_ADDRESS; + else if (PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 == ret || + PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 == ret || + PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 == ret) + return SOCFPGA_UART1_ADDRESS; + else + return 0; +} + +/* + * This function looking the 1st encounter UART peripheral, and then return + * base address of the 1st encounter UART peripheral. + */ +unsigned int uart_com_port(const void *blob) +{ + unsigned int ret; + + ret = dedicated_uart_com_port(blob); + + if (ret) + return ret; + + return shared_uart_com_port(blob); +} + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; + + puts("CPU: Altera SoCFPGA Arria 10\n"); + + printf("BOOT: %s\n", bsel_str[bsel].name); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index f870e1f..3b8ce11 100755 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -200,7 +200,8 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; + const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;

puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1);

Add pinmux support for Arria 10.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/pinmux.h | 15 +++++ arch/arm/mach-socfpga/pinmux_arria10.c | 98 +++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h create mode 100644 arch/arm/mach-socfpga/pinmux_arria10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 9c4617f..68d55e4 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -12,6 +12,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \

obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \ misc_arria10.o \ + pinmux_arria10.o \ reset_manager_arria10.o

obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h b/arch/arm/mach-socfpga/include/mach/pinmux.h new file mode 100644 index 0000000..c5d5dd6 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _PINMUX_H_ +#define _PINMUX_H_ + +#ifndef __ASSEMBLY__ +int config_dedicated_pins(const void *blob); +int config_pins(const void *blob, const char *pin_grp); +#endif + +#endif /* _PINMUX_H_ */ diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c b/arch/arm/mach-socfpga/pinmux_arria10.c new file mode 100644 index 0000000..04acaa2 --- /dev/null +++ b/arch/arm/mach-socfpga/pinmux_arria10.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <fdtdec.h> +#include <asm/arch/pinmux.h> + +static int do_pinctr_pin(const void *blob, int child, const char *node_name) +{ + int len; + fdt_addr_t base_addr; + fdt_size_t size; + const u32 *cell; + u32 offset, value; + + base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); + if (base_addr != FDT_ADDR_T_NONE) { + cell = fdt_getprop(blob, child, "pinctrl-single,pins", + &len); + if (cell != NULL) { + debug("%p %d\n", cell, len); + for (; len > 0; len -= (2*sizeof(u32))) { + offset = fdt32_to_cpu(*cell++); + value = fdt32_to_cpu(*cell++); + debug("<0x%x 0x%x>\n", offset, value); + writel(value, base_addr + offset); + } + return 0; + } + } + return -EFAULT; +} + +static int do_pinctrl_pins(const void *blob, int node, const char *child_name) +{ + int child, len; + const char *node_name; + + child = fdt_first_subnode(blob, node); + + if (child < 0) + return -EINVAL; + + node_name = fdt_get_name(blob, child, &len); + + while (node_name) { + if (!strcmp(child_name, node_name)) + return do_pinctr_pin(blob, child, node_name); + + child = fdt_next_subnode(blob, child); + + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, &len); + } + + return -EFAULT; +} + +int config_dedicated_pins(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return -EINVAL; + + if (do_pinctrl_pins(blob, node, "dedicated_cfg")) + return -EFAULT; + + if (do_pinctrl_pins(blob, node, "dedicated")) + return -EFAULT; + + return 0; +} + +int config_pins(const void *blob, const char *pin_grp) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return -EINVAL; + + if (do_pinctrl_pins(blob, node, pin_grp)) + return -EFAULT; + + return 0; +}

Device tree files for Arria 10

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria10.dtsi | 859 +++++++++++++++++++++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 30 + .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 479 ++++++++++++ 4 files changed, 1369 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index eb68c20..25e08eb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -139,6 +139,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb

dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_arria10_socdk_sdmmc.dtb \ socfpga_arria5_socdk.dtb \ socfpga_cyclone5_is1.dtb \ socfpga_cyclone5_mcvevk.dtb \ diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi new file mode 100644 index 0000000..52ab7fe --- /dev/null +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -0,0 +1,859 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 X11 + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/altr,rst-mgr-a10.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + spi0 = &spi0; + spi1 = &spi1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@ffffd000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xffffd000 0x1000>, + <0xffffc100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffda1000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda1000 0x1000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, + <0 84 IRQ_TYPE_LEVEL_HIGH>, + <0 85 IRQ_TYPE_LEVEL_HIGH>, + <0 86 IRQ_TYPE_LEVEL_HIGH>, + <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>, + <0 89 IRQ_TYPE_LEVEL_HIGH>, + <0 90 IRQ_TYPE_LEVEL_HIGH>, + <0 91 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + reg-names = "soc_clock_manager_OCP_SLV"; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb_intosc_ls_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s_free_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>; + reg = <0x40>; + + main_mpu_base_clk: main_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x140 0 11>; + }; + + main_noc_base_clk: main_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x144 0 11>; + }; + + main_emaca_clk: main_emaca_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x68>; + }; + + main_emacb_clk: main_emacb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x6C>; + }; + + main_emac_ptp_clk: main_emac_ptp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x70>; + }; + + main_gpio_db_clk: main_gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x74>; + }; + + main_sdmmc_clk: main_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x78>; + }; + + main_s2f_usr0_clk: main_s2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x7C>; + }; + + main_s2f_usr1_clk: main_s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x80>; + }; + + main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x84>; + }; + + main_periph_ref_clk: main_periph_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x9C>; + }; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>, <&main_periph_ref_clk>; + reg = <0xC0>; + + peri_mpu_base_clk: peri_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x140 16 11>; + }; + + peri_noc_base_clk: peri_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x144 16 11>; + }; + + peri_emaca_clk: peri_emaca_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xE8>; + }; + + peri_emacb_clk: peri_emacb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xEC>; + }; + + peri_emac_ptp_clk: peri_emac_ptp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF0>; + }; + + peri_gpio_db_clk: peri_gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF4>; + }; + + peri_sdmmc_clk: peri_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF8>; + }; + + peri_s2f_usr0_clk: peri_s2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xFC>; + }; + + peri_s2f_usr1_clk: peri_s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x100>; + }; + + peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x104>; + }; + }; + + mpu_free_clk: mpu_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x60>; + }; + + noc_free_clk: noc_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x64>; + }; + + s2f_user1_free_clk: s2f_user1_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x104>; + }; + + sdmmc_free_clk: sdmmc_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + fixed-divider = <4>; + reg = <0xF8>; + }; + + l4_sys_free_clk: l4_sys_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&noc_free_clk>; + fixed-divider = <4>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 0 2>; + clk-gate = <0x48 1>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 8 2>; + clk-gate = <0x48 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 16 2>; + clk-gate = <0x48 3>; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&mpu_free_clk>; + fixed-divider = <4>; + clk-gate = <0x48 0>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&sdmmc_free_clk>; + clk-gate = <0xC8 5>; + clk-phase = <0 135>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 11>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 10>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 9>; + }; + + usb_clk: usb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 8>; + }; + + s2f_usr1_clk: s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&peri_s2f_usr1_clk>; + clk-gate = <0xC8 6>; + }; + }; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + reg = <0xff800000 0x2000>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + reg = <0xff802000 0x2000>; + interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x4C 0>; + reg = <0xff804000 0x2000>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gpio0: gpio@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02900 0x100>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02a00 0x100>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio2: gpio@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02b00 0x100>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + fpga_mgr: fpga-mgr@ffd03000 { + compatible = "altr,socfpga-a10-fpga-mgr"; + reg = <0xffd03000 0x100 + 0xffcfe400 0x20>; + clocks = <&l4_mp_clk>; + resets = <&rst FPGAMGR_RESET>; + reset-names = "fpgamgr"; + }; + + i2c0: i2c@ffc02200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02200 0x100>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + i2c1: i2c@ffc02300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02300 0x100>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + i2c2: i2c@ffc02400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02400 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + i2c3: i2c@ffc02500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02500 0x100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + i2c4: i2c@ffc02600 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02600 0x100>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + sdr: sdr@0xffcfb100 { + compatible = "syscon"; + reg = <0xffcfb100 0x80>; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x100>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + num-chipselect = <4>; + bus-num = <0>; + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + num-chipselect = <4>; + bus-num = <0>; + tx-dma-channel = <&pdma 20>; + rx-dma-channel = <&pdma 21>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + + L2: l2-cache@fffff000 { + compatible = "arm,pl310-cache"; + reg = <0xfffff000 0x1000>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + }; + + mmc: dwmmc0@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + fifo-depth = <0x400>; + bus-width = <4>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x40000>; + }; + + eccmgr: eccmgr@ffd06000 { + compatible = "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac { + compatible = "altr,sdram-edac-a10"; + altr,sdr-syscon = <&sdr>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <49 IRQ_TYPE_LEVEL_HIGH>; + }; + + l2-ecc@ffd06010 { + compatible = "altr,socfpga-a10-l2-ecc"; + reg = <0xffd06010 0x4>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <32 IRQ_TYPE_LEVEL_HIGH>; + }; + + ocram-ecc@ff8c3000 { + compatible = "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8c3000 0x400>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, + <33 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-rx-ecc@ff8c0800 { + compatible = "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0800 0x400>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, + <36 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-tx-ecc@ff8c0c00 { + compatible = "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0c00 0x400>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, + <37 IRQ_TYPE_LEVEL_HIGH>; + }; + + dma-ecc@ff8c8000 { + compatible = "altr,socfpga-dma-ecc"; + reg = <0xff8c8000 0x400>; + altr,ecc-parent = <&pdma>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <42 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb0-ecc@ff8c8800 { + compatible = "altr,socfpga-usb-ecc"; + reg = <0xff8c8800 0x400>; + altr,ecc-parent = <&usb0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <34 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qspi: qspi@ff809000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cadence,qspi"; + reg = <0xff809000 0x100>, + <0xffa00000 0x100000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_main_clk>; + ext-decoder = <0>; /* external decoder */ + num-chipselect = <4>; + fifo-depth = <128>; + sram-size = <512>; + bus-num = <2>; + status = "disabled"; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x100>; + altr,modrst-offset = <0x20>; + }; + + scu: snoop-control-unit@ffffc000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xffffc000 0x100>; + }; + + sysmgr: sysmgr@ffd06000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd06000 0x300>; + cpu1-start-addr = <0xffd06230>; + }; + + /* Local timer */ + timer@ffffc600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xffffc600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc02700 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffc02700 0x100>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer1: timer1@ffc02800 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffc02800 0x100>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffd00000 0x100>; + clocks = <&l4_sys_free_clk>; + clock-names = "timer"; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffd01000 0x100>; + clocks = <&l4_sys_free_clk>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + uart1: serial1@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb_clk>; + clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb_clk>; + clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sys_free_clk>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sys_free_clk>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts new file mode 100644 index 0000000..a4215ee --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 X11 + */ + +/dts-v1/; +#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200"; + }; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&mmc { + u-boot,dm-pre-reloc; + status = "okay"; + num-slots = <1>; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; + altr,dw-mshc-ciu-div = <3>; + altr,dw-mshc-sdr-timing = <0 3>; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi new file mode 100644 index 0000000..e530f80 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi @@ -0,0 +1,479 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 X11 + * + *<auto-generated> + * This code was generated by a tool based on + * handoffs from both Qsys and Quartus. + * + * Changes to this file may be lost if + * the code is regenerated. + *</auto-generated> + */ + +#include "socfpga_arria10.dtsi" + +/ { + model = "Altera SOCFPGA Arria 10"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + chosen { + /* Bootloader setting: uboot.rbf_filename */ + cff-file = "ghrd_10as066n2.periph.rbf"; + early-release-fpga-config; + }; + + soc { + u-boot,dm-pre-reloc; + clkmgr@ffd04000 { + u-boot,dm-pre-reloc; + clocks { + u-boot,dm-pre-reloc; + osc1 { + u-boot,dm-pre-reloc; + clock-frequency = <25000000>; + clock-output-names = "altera_arria10_hps_eosc1-clk"; + }; + + cb_intosc_ls_clk { + u-boot,dm-pre-reloc; + clock-frequency = <60000000>; + clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; + }; + + f2s_free_clk { + u-boot,dm-pre-reloc; + clock-frequency = <200000000>; + clock-output-names = "altera_arria10_hps_f2h_free-clk"; + }; + + main_pll { + u-boot,dm-pre-reloc; + /* + * Address Block: soc_clock_manager_OCP_SLV. + * i_clk_mgr_mainpllgrp + */ + altr,of_reg_value = < + 0 /* Field: vco0.psrc */ + 1 /* Field: vco1.denom */ + 191 /* Field: vco1.numer */ + 0 /* Field: mpuclk */ + 0 /* Field: mpuclk.cnt */ + 0 /* Field: mpuclk.src */ + 0 /* Field: nocclk */ + 0 /* Field: nocclk.cnt */ + 0 /* Field: nocclk.src */ + 900 /* Field: cntr2clk.cnt */ + 900 /* Field: cntr3clk.cnt */ + 900 /* Field: cntr4clk.cnt */ + 900 /* Field: cntr5clk.cnt */ + 900 /* Field: cntr6clk.cnt */ + 900 /* Field: cntr7clk.cnt */ + 0 /* Field: cntr7clk.src */ + 900 /* Field: cntr8clk.cnt */ + 900 /* Field: cntr9clk.cnt */ + 0 /* Field: cntr9clk.src */ + 900 /* Field: cntr15clk.cnt */ + 0 /* Field: nocdiv.l4mainclk */ + 0 /* Field: nocdiv.l4mpclk */ + 2 /* Field: nocdiv.l4spclk */ + 0 /* Field: nocdiv.csatclk */ + 1 /* Field: nocdiv.cstraceclk */ + 1 /* Field: nocdiv.cspdbgclk */ + >; + }; + + periph_pll { + u-boot,dm-pre-reloc; + /* + * Address Block: soc_clock_manager_OCP_SLV. + * i_clk_mgr_perpllgrp + */ + altr,of_reg_value = < + 0 /* Field: vco0.psrc */ + 1 /* Field: vco1.denom */ + 159 /* Field: vco1.numer */ + 7 /* Field: cntr2clk.cnt */ + 1 /* Field: cntr2clk.src */ + 900 /* Field: cntr3clk.cnt */ + 1 /* Field: cntr3clk.src */ + 19 /* Field: cntr4clk.cnt */ + 1 /* Field: cntr4clk.src */ + 499 /* Field: cntr5clk.cnt */ + 1 /* Field: cntr5clk.src */ + 9 /* Field: cntr6clk.cnt */ + 1 /* Field: cntr6clk.src */ + 900 /* Field: cntr7clk.cnt */ + 900 /* Field: cntr8clk.cnt */ + 0 /* Field: cntr8clk.src */ + 900 /* Field: cntr9clk.cnt */ + 0 /* Field: emacctl.emac0sel */ + 0 /* Field: emacctl.emac1sel */ + 0 /* Field: emacctl.emac2sel */ + 32000 /* Field: gpiodiv.gpiodbclk */ + >; + }; + + altera { + u-boot,dm-pre-reloc; + /* + * Address Block: soc_clock_manager_OCP_SLV. + * i_clk_mgr_alteragrp + */ + altr,of_reg_value = < + 0x0384000b /* Register: nocclk */ + 0x03840001 /* Register: mpuclk */ + >; + }; + }; + }; + + /* + * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver + * Binding: pinmux + */ + i_io48_pin_mux: pinmux@0xffd07000 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "pinctrl-single"; + reg = <0xffd07000 0x00000800>; + reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; + + /* + * Address Block: soc_3v_io48_pin_mux_OCP_SLV. + * i_io48_pin_mux_shared_3v_io_grp + */ + shared { + u-boot,dm-pre-reloc; + reg = <0xffd07000 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Reg: pinmux_shared_io_q1_1 */ + <0x00000000 0x00000008>, + /* Reg: pinmux_shared_io_q1_2 */ + <0x00000004 0x00000008>, + /* Reg: pinmux_shared_io_q1_3 */ + <0x00000008 0x00000008>, + /* Reg: pinmux_shared_io_q1_4 */ + <0x0000000c 0x00000008>, + /* Reg: pinmux_shared_io_q1_5 */ + <0x00000010 0x00000008>, + /* Reg: pinmux_shared_io_q1_6 */ + <0x00000014 0x00000008>, + /* Reg: pinmux_shared_io_q1_7 */ + <0x00000018 0x00000008>, + /* Reg: pinmux_shared_io_q1_8 */ + <0x0000001c 0x00000008>, + /* Reg: pinmux_shared_io_q1_9 */ + <0x00000020 0x00000008>, + /* Reg: pinmux_shared_io_q1_10 */ + <0x00000024 0x00000008>, + /* Reg: pinmux_shared_io_q1_11 */ + <0x00000028 0x00000008>, + /* Reg: pinmux_shared_io_q1_12 */ + <0x0000002c 0x00000008>, + /* Reg: pinmux_shared_io_q2_1 */ + <0x00000030 0x00000004>, + /* Reg: pinmux_shared_io_q2_2 */ + <0x00000034 0x00000004>, + /* Reg: pinmux_shared_io_q2_3 */ + <0x00000038 0x00000004>, + /* Reg: pinmux_shared_io_q2_4 */ + <0x0000003c 0x00000004>, + /* Reg: pinmux_shared_io_q2_5 */ + <0x00000040 0x00000004>, + /* Reg: pinmux_shared_io_q2_6 */ + <0x00000044 0x00000004>, + /* Reg: pinmux_shared_io_q2_7 */ + <0x00000048 0x00000004>, + /* Reg: pinmux_shared_io_q2_8 */ + <0x0000004c 0x00000004>, + /* Reg: pinmux_shared_io_q2_9 */ + <0x00000050 0x00000004>, + /* Reg: pinmux_shared_io_q2_10 */ + <0x00000054 0x00000004>, + /* Reg: pinmux_shared_io_q2_11 */ + <0x00000058 0x00000004>, + /* Reg: pinmux_shared_io_q2_12 */ + <0x0000005c 0x00000004>, + /* Reg: pinmux_shared_io_q3_1 */ + <0x00000060 0x00000003>, + /* Reg: pinmux_shared_io_q3_2 */ + <0x00000064 0x00000003>, + /* Reg: pinmux_shared_io_q3_3 */ + <0x00000068 0x00000003>, + /* Reg: pinmux_shared_io_q3_4 */ + <0x0000006c 0x00000003>, + /* Reg: pinmux_shared_io_q3_5 */ + <0x00000070 0x00000003>, + /* Reg: pinmux_shared_io_q3_6 */ + <0x00000074 0x0000000f>, + /* Reg: pinmux_shared_io_q3_7 */ + <0x00000078 0x0000000a>, + /* Reg: pinmux_shared_io_q3_8 */ + <0x0000007c 0x0000000a>, + /* Reg: pinmux_shared_io_q3_9 */ + <0x00000080 0x0000000a>, + /* Reg: pinmux_shared_io_q3_10 */ + <0x00000084 0x0000000a>, + /* Reg: pinmux_shared_io_q3_11 */ + <0x00000088 0x00000001>, + /* Reg: pinmux_shared_io_q3_12 */ + <0x0000008c 0x00000001>, + /* Reg: pinmux_shared_io_q4_1 */ + <0x00000090 0x00000000>, + /* Reg: pinmux_shared_io_q4_2 */ + <0x00000094 0x00000000>, + /* Reg: pinmux_shared_io_q4_3 */ + <0x00000098 0x0000000f>, + /* Reg: pinmux_shared_io_q4_4 */ + <0x0000009c 0x0000000c>, + /* Reg: pinmux_shared_io_q4_5 */ + <0x000000a0 0x0000000f>, + /* Reg: pinmux_shared_io_q4_6 */ + <0x000000a4 0x0000000f>, + /* Reg: pinmux_shared_io_q4_7 */ + <0x000000a8 0x0000000a>, + /* Reg: pinmux_shared_io_q4_8 */ + <0x000000ac 0x0000000a>, + /* Reg: pinmux_shared_io_q4_9 */ + <0x000000b0 0x0000000c>, + /* Reg: pinmux_shared_io_q4_10 */ + <0x000000b4 0x0000000c>, + /* Reg: pinmux_shared_io_q4_11 */ + <0x000000b8 0x0000000c>, + /* Reg: pinmux_shared_io_q4_12 */ + <0x000000bc 0x0000000c>; + }; + + /* + * Address Block: soc_3v_io48_pin_mux_OCP_SLV. + * i_io48_pin_mux_dedicated_io_grp + */ + dedicated { + u-boot,dm-pre-reloc; + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Reg: pinmux_dedicated_io_4 */ + <0x0000000c 0x00000008>, + /* Reg: pinmux_dedicated_io_5 */ + <0x00000010 0x00000008>, + /* Reg: pinmux_dedicated_io_6 */ + <0x00000014 0x00000008>, + /* Regi: pinmux_dedicated_io_7 */ + <0x00000018 0x00000008>, + /* Reg: pinmux_dedicated_io_8 */ + <0x0000001c 0x00000008>, + /* Reg: pinmux_dedicated_io_9 */ + <0x00000020 0x00000008>, + /* Reg: pinmux_dedicated_io_10 */ + <0x00000024 0x0000000a>, + /* Reg: pinmux_dedicated_io_11 */ + <0x00000028 0x0000000a>, + /* Reg: pinmux_dedicated_io_12 */ + <0x0000002c 0x00000008>, + /* Reg: pinmux_dedicated_io_13 */ + <0x00000030 0x00000008>, + /* Reg: pinmux_dedicated_io_14 */ + <0x00000034 0x00000008>, + /* Reg: pinmux_dedicated_io_15 */ + <0x00000038 0x00000008>, + /* Reg: pinmux_dedicated_io_16 */ + <0x0000003c 0x0000000d>, + /* Reg: pinmux_dedicated_io_17 */ + <0x00000040 0x0000000d>; + }; + + /* + * Address Block: soc_3v_io48_pin_mux_OCP_SLV. + * i_io48_pin_mux_dedicated_io_grp + */ + dedicated_cfg { + u-boot,dm-pre-reloc; + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x003f3f3f>; + pinctrl-single,pins = + /* Reg: cfg_dedicated_io_bank */ + <0x00000100 0x00000101>, + /* Reg: cfg_dedicated_io_1 */ + <0x00000104 0x000b080a>, + /* Reg: cfg_dedicated_io_2 */ + <0x00000108 0x000b080a>, + /* Reg: cfg_dedicated_io_3 */ + <0x0000010c 0x000b080a>, + /* Reg: cfg_dedicated_io_4 */ + <0x00000110 0x000a282a>, + /* Reg: cfg_dedicated_io_5 */ + <0x00000114 0x000a282a>, + /* Reg: cfg_dedicated_io_6 */ + <0x00000118 0x0008282a>, + /* Reg: cfg_dedicated_io_7 */ + <0x0000011c 0x000a282a>, + /* Reg: cfg_dedicated_io_8 */ + <0x00000120 0x000a282a>, + /* Reg: cfg_dedicated_io_9 */ + <0x00000124 0x000a282a>, + /* Reg: cfg_dedicated_io_10 */ + <0x00000128 0x00090000>, + /* Reg: cfg_dedicated_io_11 */ + <0x0000012c 0x00090000>, + /* Reg: cfg_dedicated_io_12 */ + <0x00000130 0x000b282a>, + /* Reg: cfg_dedicated_io_13 */ + <0x00000134 0x000b282a>, + /* Reg: cfg_dedicated_io_14 */ + <0x00000138 0x000b282a>, + /* Reg: cfg_dedicated_io_15 */ + <0x0000013c 0x000b282a>, + /* Reg: cfg_dedicated_io_16 */ + <0x00000140 0x0008282a>, + /* Reg: cfg_dedicated_io_17 */ + <0x00000144 0x000a282a>; + }; + + /* + * Address Block: soc_3v_io48_pin_mux_OCP_SLV. + * i_io48_pin_mux_fpga_interface_grp + */ + fpga { + u-boot,dm-pre-reloc; + reg = <0xffd07400 0x00000100>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000001>; + pinctrl-single,pins = + /* Reg: pinmux_emac0_usefpga */ + <0x00000000 0x00000000>, + /* Reg: pinmux_emac1_usefpga */ + <0x00000004 0x00000000>, + /* Reg: pinmux_emac2_usefpga */ + <0x00000008 0x00000000>, + /* Reg: pinmux_i2c0_usefpga */ + <0x0000000c 0x00000000>, + /* Reg: pinmux_i2c1_usefpga */ + <0x00000010 0x00000000>, + /* Reg: pinmux_i2c_emac0_usefpga */ + <0x00000014 0x00000000>, + /* Reg: pinmux_i2c_emac1_usefpga */ + <0x00000018 0x00000000>, + /* Reg: pinmux_i2c_emac2_usefpga */ + <0x0000001c 0x00000000>, + /* Reg: pinmux_nand_usefpga */ + <0x00000020 0x00000000>, + /* Reg: pinmux_qspi_usefpga */ + <0x00000024 0x00000000>, + /* Reg: pinmux_sdmmc_usefpga */ + <0x00000028 0x00000000>, + /* Reg: pinmux_spim0_usefpga */ + <0x0000002c 0x00000000>, + /* Reg: pinmux_spim1_usefpga */ + <0x00000030 0x00000000>, + /* Reg: pinmux_spis0_usefpga */ + <0x00000034 0x00000000>, + /* Reg: pinmux_spis1_usefpga */ + <0x00000038 0x00000000>, + /* Reg: pinmux_uart0_usefpga */ + <0x0000003c 0x00000000>, + /* Reg: pinmux_uart1_usefpga */ + <0x00000040 0x00000000>; + }; + }; + + i_noc: noc@0xffd10000 { + compatible = "altr,socfpga-a10-noc"; + reg = <0xffd10000 0x00008000>; + reg-names = "mpu_m0"; + + firewall { + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * mpuregion0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * mpuregion0addr.limit + */ + altr,mpu0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr. + * hpsregion0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr. + * hpsregion0addr.limit + */ + altr,l3-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.limit + */ + altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.limit + */ + altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.limit + */ + altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>; + }; + }; + + hps_fpgabridge0: fpgabridge@0 { + compatible = "altr,socfpga-hps2fpga-bridge"; + altr,init-val = <1>; + }; + + hps_fpgabridge1: fpgabridge@1 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + altr,init-val = <1>; + }; + + hps_fpgabridge2: fpgabridge@2 { + compatible = "altr,socfpga-fpga2hps-bridge"; + altr,init-val = <1>; + }; + + hps_fpgabridge3: fpgabridge@3 { + compatible = "altr,socfpga-fpga2sdram0-bridge"; + altr,init-val = <1>; + }; + + hps_fpgabridge4: fpgabridge@4 { + compatible = "altr,socfpga-fpga2sdram1-bridge"; + altr,init-val = <0>; + }; + + hps_fpgabridge5: fpgabridge@5 { + compatible = "altr,socfpga-fpga2sdram2-bridge"; + altr,init-val = <1>; + }; + }; +};

Convert Altera ddr driver to use Kconfig method. Enable ALTERA_SDRAM by default it is on Gen5 target. Arria 10 will have different driver.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- drivers/Kconfig | 2 ++ drivers/ddr/Kconfig | 1 + drivers/ddr/altera/Kconfig | 6 ++++++ include/configs/socfpga_common.h | 5 ----- 4 files changed, 9 insertions(+), 5 deletions(-) create mode 100644 drivers/ddr/Kconfig create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig index 0e5d97d..3e6bbac 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"

source "drivers/crypto/Kconfig"

+source "drivers/ddr/Kconfig" + source "drivers/demo/Kconfig"

source "drivers/ddr/fsl/Kconfig" diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig new file mode 100644 index 0000000..b764add --- /dev/null +++ b/drivers/ddr/Kconfig @@ -0,0 +1 @@ +source "drivers/ddr/altera/Kconfig" diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig new file mode 100644 index 0000000..9554da7 --- /dev/null +++ b/drivers/ddr/altera/Kconfig @@ -0,0 +1,6 @@ +config ALTERA_SDRAM + bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices" + default y if TARGET_SOCFPGA_GEN5 + help + This is for building the SDRAM controller for the Arria5/Cyclone5 + devices. diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 55e0bf9..bc92a2c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -77,11 +77,6 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS

/* - * SDRAM controller - */ -#define CONFIG_ALTERA_SDRAM - -/* * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI

Add support for the Arria10 SoCDK.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- board/altera/arria10-socdk/Kconfig | 18 ++++++++++++++++++ board/altera/arria10-socdk/Makefile | 7 +++++++ board/altera/arria10-socdk/socfpga.c | 7 +++++++ 3 files changed, 32 insertions(+) create mode 100644 board/altera/arria10-socdk/Kconfig create mode 100644 board/altera/arria10-socdk/Makefile create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig new file mode 100644 index 0000000..b80cc6d --- /dev/null +++ b/board/altera/arria10-socdk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SOCFPGA_ARRIA10 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "socfpga_arria10" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga_arria10" + +config SYS_CONFIG_NAME + default "socfpga_arria10" + +endif diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile new file mode 100644 index 0000000..1d885ce --- /dev/null +++ b/board/altera/arria10-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c new file mode 100644 index 0000000..8516633 --- /dev/null +++ b/board/altera/arria10-socdk/socfpga.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2015 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h>