SDRAM setup alike to ORIGEN Dev board.

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - no changes

include/configs/trats.h | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/include/configs/trats.h b/include/configs/trats.h index 185cb68..f391227 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -170,12 +170,17 @@ /* Stack sizes */ #define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */

-/* TRATS has 2 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */ +/* TRATS has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE

#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */

SDRAM setup alike to ORIGEN Dev board.

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - no changes Changes for v3: - no changes

include/configs/trats.h | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/include/configs/trats.h b/include/configs/trats.h index 185cb68..f391227 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -170,12 +170,17 @@ /* Stack sizes */ #define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */

-/* TRATS has 2 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */ +/* TRATS has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE

#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */

Full 1GiB is visible

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - no changes Changes for v3: - no changes Changes for v4: - no changes --- board/samsung/trats/trats.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index e11a892..7b981fa 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -93,7 +93,9 @@ void i2c_init_board(void) int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);

return 0; } @@ -104,6 +106,10 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; }

static unsigned int get_hw_revision(void)

Hi Piotr,

I commented at the previously patch. But I didn't find the any modification.

pinmux.c: In function 'exynos_pinmux_config': pinmux.c:296:20: warning: 'bank_ext' may be used uninitialized in this function [-Wuninitialized] pinmux.c:272:31: note: 'bank_ext' was declared here pinmux.c:290:19: warning: 'bank' may be used uninitialized in this function [-Wuninitialized] pinmux.c:272:24: note: 'bank' was declared here

Could you remove the warning message?

Best Regards, Jaehoon Chung

On 09/20/2012 07:19 PM, Piotr Wilczek wrote:

This patch add pinmux settings for Exynos4 for mmc0 and mmc2

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com

---

Changes for v2:

• mmc initialisation code moved to pinmux instead of creating a new common code file

Changes for v3:

• no changes

Changes for v4:

• eliminated warning for uninitialized bank, bank_ext

---

arch/arm/cpu/armv7/exynos/pinmux.c | 58 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 1 + 2 files changed, 59 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 7776add..5796d56 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -265,10 +265,68 @@ static int exynos5_pinmux_config(int peripheral, int flags) return 0; }

+static int exynos4_mmc_config(int peripheral, int flags) +{

• struct exynos4_gpio_part2 *gpio2 =

• (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  

• struct s5p_gpio_bank *bank, *bank_ext;
• int i;
• switch (peripheral) {
• case PERIPH_ID_SDMMC0:

• bank = &gpio2->k0;
  

• bank_ext = &gpio2->k1;
  

• break;
  

• case PERIPH_ID_SDMMC2:

• bank = &gpio2->k2;
  

• bank_ext = &gpio2->k3;
  

• break;
  

• default:

• return -1;
  

• }
• for (i = 0; i < 7; i++) {

• if (i == 2)
  

• 	continue;
  

• s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
  

• s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
  

• s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
  

• }
• if (flags & PINMUX_FLAG_8BIT_MODE) {

• for (i = 3; i < 7; i++) {
  

• 	s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
  

• 	s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
  

• 	s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
  

• }
  

• }
• return 0;

+}

+static int exynos4_pinmux_config(int peripheral, int flags) +{

• switch (peripheral) {
• case PERIPH_ID_SDMMC0:
• case PERIPH_ID_SDMMC2:

• return exynos4_mmc_config(peripheral, flags);
  

• case PERIPH_ID_SDMMC1:
• case PERIPH_ID_SDMMC3:
• case PERIPH_ID_SDMMC4:

• printf("SDMMC device %d not implemented\n", peripheral);
  

• return -1;
  

• default:

• debug("%s: invalid peripheral %d", __func__, peripheral);
  

• return -1;
  

• }
• return 0;

+}

int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) return exynos5_pinmux_config(peripheral, flags);

• else if (cpu_is_exynos4())

• return exynos4_pinmux_config(peripheral, flags);
  

  else { debug("pinmux functionality not supported\n"); return -1;

diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index b861d7d..082611c 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -42,6 +42,7 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3,

• PERIPH_ID_SDMMC4, PERIPH_ID_SROMC, PERIPH_ID_UART0, PERIPH_ID_UART1,

This patch use the pinmux for mmc configuration for Trats

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com Acked-by: Jaehoon Chung jh80.chung@samsung.com --- Changes for v2: - mmc iniatialisation using pinmux Changes for v3: - init SD card also when eMMC init failed Changes for v4: - no changes --- board/samsung/trats/trats.c | 68 +++++++----------------------------------- 1 files changed, 12 insertions(+), 56 deletions(-)

diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 7b981fa..57400ce 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -29,6 +29,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> #include <asm/arch/clock.h> #include <asm/arch/clk.h> #include <asm/arch/mipi_dsim.h> @@ -157,54 +158,22 @@ int board_mmc_init(bd_t *bis) { struct exynos4_gpio_part2 *gpio = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int i, err; + int err;

/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ s5p_gpio_direction_output(&gpio->k0, 2, 1); s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);

/* - * eMMC GPIO: - * SDR 8-bit@48MHz at MMC0 - * GPK0[0] SD_0_CLK(2) - * GPK0[1] SD_0_CMD(2) - * GPK0[2] SD_0_CDn -> Not used - * GPK0[3:6] SD_0_DATA[0:3](2) - * GPK1[3:6] SD_0_DATA[0:3](3) - * - * DDR 4-bit@26MHz at MMC4 - * GPK0[0] SD_4_CLK(3) - * GPK0[1] SD_4_CMD(3) - * GPK0[2] SD_4_CDn -> Not used - * GPK0[3:6] SD_4_DATA[0:3](3) - * GPK1[3:6] SD_4_DATA[4:7](4) - */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPK0[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio->k0, i, 0x2); - /* GPK0[0:6] pull disable */ - s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE); - /* GPK0[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X); - } - - for (i = 3; i < 7; i++) { - /* GPK1[3:6] special function 3 */ - s5p_gpio_cfg_pin(&gpio->k1, i, 0x3); - /* GPK1[3:6] pull disable */ - s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE); - /* GPK1[3:6] drv 4x */ - s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X); - } - - /* * MMC device init * mmc0 : eMMC (8-bit buswidth) * mmc2 : SD card (4-bit buswidth) */ - err = s5p_mmc_init(0, 8); + err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); + if (err) + debug("SDMMC0 not configured\n"); + else + err = s5p_mmc_init(0, 8);

/* T-flash detect */ s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); @@ -215,24 +184,11 @@ int board_mmc_init(bd_t *bis) * GPX3[4] T-flash detect pin */ if (!s5p_gpio_get_value(&gpio->x3, 4)) { - /* - * SD card GPIO: - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn -> Not used - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio->k2, i, 0x2); - /* GPK2[0:6] pull disable */ - s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE); - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X); - } - err = s5p_mmc_init(2, 4); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) + debug("SDMMC2 not configured\n"); + else + err = s5p_mmc_init(2, 4); }

return err;

Low level initialisation is done by another bootloader

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - no changes Changes for v3: - no changes Changes for v4: - no changes --- board/samsung/universal_c210/Makefile | 1 - board/samsung/universal_c210/lowlevel_init.S | 395 -------------------------- board/samsung/universal_c210/universal.c | 8 + include/configs/s5pc210_universal.h | 2 + 4 files changed, 10 insertions(+), 396 deletions(-) delete mode 100644 board/samsung/universal_c210/lowlevel_init.S

diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile index bfec08f..587cc1b 100644 --- a/board/samsung/universal_c210/Makefile +++ b/board/samsung/universal_c210/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o

COBJS-y := universal.o onenand.o -SOBJS := lowlevel_init.o

SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S deleted file mode 100644 index dc7f69e..0000000 --- a/board/samsung/universal_c210/lowlevel_init.S +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Lowlevel setup for universal board based on EXYNOS4210 - * - * Copyright (C) 2010 Samsung Electronics - * Kyungmin Park kyungmin.park@samsung.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clock.h> - -/* - * Register usages: - * - * r5 has zero always - * r7 has GPIO part1 base 0x11400000 - * r6 has GPIO part2 base 0x11000000 - */ - - .globl lowlevel_init -lowlevel_init: - mov r11, lr - - /* r5 has always zero */ - mov r5, #0 - - ldr r7, =EXYNOS4_GPIO_PART1_BASE - ldr r6, =EXYNOS4_GPIO_PART2_BASE - - /* System Timer */ - ldr r0, =EXYNOS4_SYSTIMER_BASE - ldr r1, =0x5000 - str r1, [r0, #0x0] - ldr r1, =0xffffffff - str r1, [r0, #0x8] - ldr r1, =0x49 - str r1, [r0, #0x4] - - /* PMIC manual reset */ - /* nPOWER: XEINT_23: GPX2[7] */ - add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET - ldr r1, [r0, #0x0] - bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit - orr r1, r1, #(0x1 << 28) @ Output - str r1, [r0, #0x0] - - ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit - str r1, [r0, #0x4] - - /* init system clock */ - bl system_clock_init - - /* Disable Watchdog */ - ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000 - str r5, [r0] - - /* UART */ - bl uart_asm_init - - /* PMU init */ - bl system_power_init - - bl tzpc_init - - mov lr, r11 - mov pc, lr - nop - nop - nop - -/* - * uart_asm_init: Initialize UART's pins - */ -uart_asm_init: - /* - * setup UART0-UART4 GPIOs (part1) - * GPA1CON[3] = I2C_3_SCL (3) - * GPA1CON[2] = I2C_3_SDA (3) - */ - mov r0, r7 - ldr r1, =0x22222222 - str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET - ldr r1, =0x00223322 - str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET - - /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ - add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET - ldr r1, [r0, #0x0] - bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit - orr r1, r1, #(0x1 << 28) - str r1, [r0, #0x0] - - ldr r1, [r0, #0x8] - bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit - orr r1, r1, #(0x3 << 14) @ Pull-up enabled - str r1, [r0, #0x8] - - ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit - str r1, [r0, #0x4] - - mov pc, lr - nop - nop - nop - -system_clock_init: - ldr r0, =EXYNOS4_CLOCK_BASE - - /* APLL(1), MPLL(1), CORE(0), HPM(0) */ - ldr r1, =0x0101 - ldr r2, =0x14200 @ CLK_SRC_CPU - str r1, [r0, r2] - - /* wait ?us */ - mov r1, #0x10000 -1: subs r1, r1, #1 - bne 1b - - /* - * CLK_SRC_TOP0 - * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166 - * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL - * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL - */ - ldr r1, =0x10000110 - ldr r2, =0x0C210 @ CLK_SRC_TOP - str r1, [r0, r2] - - /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ - ldr r1, =0x0066666 - ldr r2, =0x0C240 @ CLK_SRC_FSYS - str r1, [r0, r2] - /* UART[0:5], PWM: SCLKMPLL(6) */ - ldr r1, =0x6666666 - ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET - str r1, [r0, r2] - - /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */ - ldr r1, =0x0133730 - ldr r2, =0x14500 @ CLK_DIV_CPU0 - str r1, [r0, r2] - /* CPU1: COPY, HPM */ - ldr r1, =0x03 - ldr r2, =0x14504 @ CLK_DIV_CPU1 - str r1, [r0, r2] - /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */ - ldr r1, =0x13111113 - ldr r2, =0x10500 @ CLK_DIV_DMC0 - str r1, [r0, r2] - /* DMC1: PWI, DVSEM, DPM */ - ldr r1, =0x01010100 - ldr r2, =0x10504 @ CLK_DIV_DMC1 - str r1, [r0, r2] - /* LEFTBUS: GDL, GPL */ - ldr r1, =0x13 - ldr r2, =0x04500 @ CLK_DIV_LEFTBUS - str r1, [r0, r2] - /* RIGHHTBUS: GDR, GPR */ - ldr r1, =0x13 - ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS - str r1, [r0, r2] - /* - * CLK_DIV_TOP - * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1) - * ACLK_200, ACLK_100, ACLK_160, ACLK_133, - */ - ldr r1, =0x00005473 - ldr r2, =0x0C510 @ CLK_DIV_TOP - str r1, [r0, r2] - /* MMC[0:1] */ - ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C544 @ CLK_DIV_FSYS1 - str r1, [r0, r2] - /* MMC[2:3] */ - ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C548 @ CLK_DIV_FSYS2 - str r1, [r0, r2] - /* MMC4 */ - ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C54C @ CLK_DIV_FSYS3 - str r1, [r0, r2] - /* UART[0:5] */ - ldr r1, =0x774777 - ldr r2, =0x0C550 @ CLK_DIV_PERIL0 - str r1, [r0, r2] - /* SLIMBUS: ???, PWM */ - ldr r1, =0x8 - ldr r2, =0x0C55C @ CLK_DIV_PERIL3 - str r1, [r0, r2] - - /* PLL Setting */ - ldr r1, =0x1C20 - ldr r2, =0x14000 @ APLL_LOCK - str r1, [r0, r2] - ldr r2, =0x14008 @ MPLL_LOCK - str r1, [r0, r2] - ldr r2, =0x0C010 @ EPLL_LOCK - str r1, [r0, r2] - ldr r2, =0x0C020 @ VPLL_LOCK - str r1, [r0, r2] - - /* APLL */ - ldr r1, =0x8000001c - ldr r2, =0x14104 @ APLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80c80601 @ 800MHz - ldr r2, =0x14100 @ APLL_CON0 - str r1, [r0, r2] - /* MPLL */ - ldr r1, =0x8000001C - ldr r2, =0x1410C @ MPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80c80601 @ 800MHz - ldr r2, =0x14108 @ MPLL_CON0 - str r1, [r0, r2] - /* EPLL */ - ldr r1, =0x0 - ldr r2, =0x0C114 @ EPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80300302 @ 96MHz - ldr r2, =0x0C110 @ EPLL_CON0 - str r1, [r0, r2] - /* VPLL */ - ldr r1, =0x11000400 - ldr r2, =0x0C124 @ VPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80350302 @ 108MHz - ldr r2, =0x0C120 @ VPLL_CON0 - str r1, [r0, r2] - - /* - * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001 - * Turn off all - */ - ldr r1, =0xFFF80000 - ldr r2, =0x0C920 @ CLK_GATE_IP_CAM - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFC0 - ldr r2, =0x0C924 @ CLK_GATE_IP_VP - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFE0 - ldr r2, =0x0C928 @ CLK_GATE_IP_MFC - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFFC - ldr r2, =0x0C92C @ CLK_GATE_IP_G3D - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFC00 - ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE - str r1, [r0, r2] - - /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */ - ldr r1, =0xFFFFFFF1 - ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0 - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFC0 - ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1 - str r1, [r0, r2] - - /* - * SMMUPCIE[18], NFCON[16] : 1111 1010 - * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000 - * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011 - */ - ldr r1, =0xFFFAB8A3 - ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFFC - ldr r2, =0x0C94C @ CLK_GATE_IP_GPS - str r1, [r0, r2] - - /* - * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001 - * I2C2[8] : 1111 1110 - */ - ldr r1, =0xF1FFFEFF - ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL - str r1, [r0, r2] - - /* - * KEYIF[16] : 1111 1110 - */ - ldr r1, =0xFFFEFFFF - ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR - str r1, [r0, r2] - - /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */ - ldr r1, =0xFFFFFFD1 - ldr r2, =0x0C970 @ CLK_GATE_BLOCK - str r1, [r0, r2] - mov pc, lr - nop - nop - nop - -system_power_init: - ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000 - - ldr r2, =0x330C @ PS_HOLD_CONTROL - ldr r1, [r0, r2] - orr r1, r1, #(0x3 << 8) @ Data High, Output En - str r1, [r0, r2] - - /* Power Down */ - add r2, r0, #0x3000 - str r5, [r2, #0xC20] @ TV_CONFIGURATION - str r5, [r2, #0xC40] @ MFC_CONFIGURATION - str r5, [r2, #0xC60] @ G3D_CONFIGURATION - str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION - str r5, [r2, #0xCE0] @ GPS_CONFIGURATION - - mov pc, lr - nop - nop - nop - -tzpc_init: - ldr r0, =0x10110000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10120000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10130000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10140000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10150000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - mov pc, lr diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 7a4941c..ded97ca 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -32,6 +32,7 @@ #include <usb/s3c_udc.h> #include <asm/arch/cpu.h> #include <max8998_pmic.h> +#include <asm/arch/watchdog.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -276,3 +277,10 @@ struct s3c_plat_otg_data s5pc210_otg_data = { .usb_flags = PHY0_SLEEP, }; #endif + +int board_early_init_f(void) +{ + wdt_stop(); + + return 0; +} diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 7727624..46f2663 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -56,6 +56,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG #define CONFIG_CMDLINE_EDITING +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F

/* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))

Full 1GiB is visible

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - no chages Changes for v3: - no changes

board/samsung/trats/trats.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index a8b2b11..f5df56c 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -76,7 +76,9 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);

return 0; } @@ -87,6 +89,10 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; }

static unsigned int get_hw_revision(void)

Hi Piotr,

On 08/29/2012 04:56 PM, Piotr Wilczek wrote:

This patch add pinmux settings for Exynos4 for mmc0 and mmc2

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com

---

Changes for v2:

• mmc initialisation code moved to pinmux instead of creating a new common code file

Changes for v3:

• no changes

arch/arm/cpu/armv7/exynos/pinmux.c | 56 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 1 + 2 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d2b7d2c..84ee05c 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -209,10 +209,66 @@ static int exynos5_pinmux_config(int peripheral, int flags) return 0; }

+static int exynos4_mmc_config(int peripheral, int flags) +{

• struct exynos4_gpio_part2 *gpio2 =

• (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  

• struct s5p_gpio_bank *bank, *bank_ext;

bank, bank_ext is uninitialized.

• int i;
• switch (peripheral) {
• case PERIPH_ID_SDMMC0:

• bank = &gpio2->k0;
  

• bank_ext = &gpio2->k1;
  

• break;
  

• case PERIPH_ID_SDMMC2:

• bank = &gpio2->k2;
  

• bank_ext = &gpio2->k3;
  

• break;
  

• }
• for (i = 0; i < 7; i++) {

• if (i == 2)
  

• 	continue;
  

• s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
  

• s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
  

• s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
  

• }
• if (flags & PINMUX_FLAG_8BIT_MODE) {

• for (i = 3; i < 7; i++) {
  

• 	s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
  

• 	s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
  

• 	s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
  

• }
  

• }
• return 0;

+}

+static int exynos4_pinmux_config(int peripheral, int flags) +{

• switch (peripheral) {
• case PERIPH_ID_SDMMC0:
• case PERIPH_ID_SDMMC2:

• return exynos4_mmc_config(peripheral, flags);
  

• case PERIPH_ID_SDMMC1:
• case PERIPH_ID_SDMMC3:
• case PERIPH_ID_SDMMC4:

• printf("SDMMC device %d not implemented\n", peripheral);
  

• return -1;
  

• default:

• debug("%s: invalid peripheral %d", __func__, peripheral);
  

• return -1;
  

• }
• return 0;

+}

int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) return exynos5_pinmux_config(peripheral, flags);

• else if (cpu_is_exynos4())

• return exynos4_pinmux_config(peripheral, flags);
  

  else { debug("pinmux functionality not supported\n"); return -1;

diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 5db25aa..4e1da82 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -34,6 +34,7 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3,

• PERIPH_ID_SDMMC4, PERIPH_ID_SROMC, PERIPH_ID_UART0, PERIPH_ID_UART1,

Acked-by: Jaehoon Chung jh80.chung@samsung.com

On 08/29/2012 04:56 PM, Piotr Wilczek wrote:

This patch use the pinmux for mmc configuration for Trats

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com

---

Changes for v2:

• mmc initialisation using pinmux

Changes for v3:

• init SD card also when eMMC init failed

board/samsung/trats/trats.c | 68 +++++++----------------------------------- 1 files changed, 12 insertions(+), 56 deletions(-)

diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index f5df56c..84b7430 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -29,6 +29,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> #include <asm/arch/clock.h> #include <asm/arch/clk.h> #include <asm/arch/mipi_dsim.h> @@ -140,54 +141,22 @@ int board_mmc_init(bd_t *bis) { struct exynos4_gpio_part2 *gpio = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();

• int i, err;

• int err;

  /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ s5p_gpio_direction_output(&gpio->k0, 2, 1); s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);

  /*

• * eMMC GPIO:
  

• * SDR 8-bit@48MHz at MMC0
  

• * GPK0[0]	SD_0_CLK(2)
  

• * GPK0[1]	SD_0_CMD(2)
  

• * GPK0[2]	SD_0_CDn	-> Not used
  

• * GPK0[3:6]	SD_0_DATA[0:3](2)
  

• * GPK1[3:6]	SD_0_DATA[0:3](3)
  

• *
  

• * DDR 4-bit@26MHz at MMC4
  

• * GPK0[0]	SD_4_CLK(3)
  

• * GPK0[1]	SD_4_CMD(3)
  

• * GPK0[2]	SD_4_CDn	-> Not used
  

• * GPK0[3:6]	SD_4_DATA[0:3](3)
  

• * GPK1[3:6]	SD_4_DATA[4:7](4)
  

• */
  

• for (i = 0; i < 7; i++) {

• if (i == 2)
  

• 	continue;
  

• /* GPK0[0:6] special function 2 */
  

• s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
  

• /* GPK0[0:6] pull disable */
  

• s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
  

• /* GPK0[0:6] drv 4x */
  

• s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
  

• }
• for (i = 3; i < 7; i++) {

• /* GPK1[3:6] special function 3 */
  

• s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
  

• /* GPK1[3:6] pull disable */
  

• s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
  

• /* GPK1[3:6] drv 4x */
  

• s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
  

• }
• /*
  • MMC device init
  • mmc0 : eMMC (8-bit buswidth)
  • mmc2 : SD card (4-bit buswidth)
  */
• err = s5p_mmc_init(0, 8);

• err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);

• if (err)

• debug("SDMMC0 not configured\n");
  

• else

• err = s5p_mmc_init(0, 8);
  
  

  /* T-flash detect */ s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);

@@ -198,24 +167,11 @@ int board_mmc_init(bd_t *bis) * GPX3[4] T-flash detect pin */ if (!s5p_gpio_get_value(&gpio->x3, 4)) {

• /*
  

•  * SD card GPIO:
  

•  * GPK2[0]	SD_2_CLK(2)
  

•  * GPK2[1]	SD_2_CMD(2)
  

•  * GPK2[2]	SD_2_CDn	-> Not used
  

•  * GPK2[3:6]	SD_2_DATA[0:3](2)
  

•  */
  

• for (i = 0; i < 7; i++) {
  

• 	if (i == 2)
  

• 		continue;
  

• 	/* GPK2[0:6] special function 2 */
  

• 	s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
  

• 	/* GPK2[0:6] pull disable */
  

• 	s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
  

• 	/* GPK2[0:6] drv 4x */
  

• 	s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
  

• }
  

• err = s5p_mmc_init(2, 4);
  

• err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
  

• if (err)
  

• 	debug("SDMMC2 not configured\n");
  

• else
  

• 	err = s5p_mmc_init(2, 4);
  

  }

  return err;

Low level initialisation is done by another bootloader

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - no changes Changes for v3: - no changes

board/samsung/universal_c210/Makefile | 1 - board/samsung/universal_c210/lowlevel_init.S | 395 -------------------------- board/samsung/universal_c210/universal.c | 8 + include/configs/s5pc210_universal.h | 2 + 4 files changed, 10 insertions(+), 396 deletions(-) delete mode 100644 board/samsung/universal_c210/lowlevel_init.S

diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile index bfec08f..587cc1b 100644 --- a/board/samsung/universal_c210/Makefile +++ b/board/samsung/universal_c210/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o

COBJS-y := universal.o onenand.o -SOBJS := lowlevel_init.o

SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S deleted file mode 100644 index dc7f69e..0000000 --- a/board/samsung/universal_c210/lowlevel_init.S +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Lowlevel setup for universal board based on EXYNOS4210 - * - * Copyright (C) 2010 Samsung Electronics - * Kyungmin Park kyungmin.park@samsung.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clock.h> - -/* - * Register usages: - * - * r5 has zero always - * r7 has GPIO part1 base 0x11400000 - * r6 has GPIO part2 base 0x11000000 - */ - - .globl lowlevel_init -lowlevel_init: - mov r11, lr - - /* r5 has always zero */ - mov r5, #0 - - ldr r7, =EXYNOS4_GPIO_PART1_BASE - ldr r6, =EXYNOS4_GPIO_PART2_BASE - - /* System Timer */ - ldr r0, =EXYNOS4_SYSTIMER_BASE - ldr r1, =0x5000 - str r1, [r0, #0x0] - ldr r1, =0xffffffff - str r1, [r0, #0x8] - ldr r1, =0x49 - str r1, [r0, #0x4] - - /* PMIC manual reset */ - /* nPOWER: XEINT_23: GPX2[7] */ - add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET - ldr r1, [r0, #0x0] - bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit - orr r1, r1, #(0x1 << 28) @ Output - str r1, [r0, #0x0] - - ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit - str r1, [r0, #0x4] - - /* init system clock */ - bl system_clock_init - - /* Disable Watchdog */ - ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000 - str r5, [r0] - - /* UART */ - bl uart_asm_init - - /* PMU init */ - bl system_power_init - - bl tzpc_init - - mov lr, r11 - mov pc, lr - nop - nop - nop - -/* - * uart_asm_init: Initialize UART's pins - */ -uart_asm_init: - /* - * setup UART0-UART4 GPIOs (part1) - * GPA1CON[3] = I2C_3_SCL (3) - * GPA1CON[2] = I2C_3_SDA (3) - */ - mov r0, r7 - ldr r1, =0x22222222 - str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET - ldr r1, =0x00223322 - str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET - - /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ - add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET - ldr r1, [r0, #0x0] - bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit - orr r1, r1, #(0x1 << 28) - str r1, [r0, #0x0] - - ldr r1, [r0, #0x8] - bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit - orr r1, r1, #(0x3 << 14) @ Pull-up enabled - str r1, [r0, #0x8] - - ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit - str r1, [r0, #0x4] - - mov pc, lr - nop - nop - nop - -system_clock_init: - ldr r0, =EXYNOS4_CLOCK_BASE - - /* APLL(1), MPLL(1), CORE(0), HPM(0) */ - ldr r1, =0x0101 - ldr r2, =0x14200 @ CLK_SRC_CPU - str r1, [r0, r2] - - /* wait ?us */ - mov r1, #0x10000 -1: subs r1, r1, #1 - bne 1b - - /* - * CLK_SRC_TOP0 - * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166 - * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL - * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL - */ - ldr r1, =0x10000110 - ldr r2, =0x0C210 @ CLK_SRC_TOP - str r1, [r0, r2] - - /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ - ldr r1, =0x0066666 - ldr r2, =0x0C240 @ CLK_SRC_FSYS - str r1, [r0, r2] - /* UART[0:5], PWM: SCLKMPLL(6) */ - ldr r1, =0x6666666 - ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET - str r1, [r0, r2] - - /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */ - ldr r1, =0x0133730 - ldr r2, =0x14500 @ CLK_DIV_CPU0 - str r1, [r0, r2] - /* CPU1: COPY, HPM */ - ldr r1, =0x03 - ldr r2, =0x14504 @ CLK_DIV_CPU1 - str r1, [r0, r2] - /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */ - ldr r1, =0x13111113 - ldr r2, =0x10500 @ CLK_DIV_DMC0 - str r1, [r0, r2] - /* DMC1: PWI, DVSEM, DPM */ - ldr r1, =0x01010100 - ldr r2, =0x10504 @ CLK_DIV_DMC1 - str r1, [r0, r2] - /* LEFTBUS: GDL, GPL */ - ldr r1, =0x13 - ldr r2, =0x04500 @ CLK_DIV_LEFTBUS - str r1, [r0, r2] - /* RIGHHTBUS: GDR, GPR */ - ldr r1, =0x13 - ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS - str r1, [r0, r2] - /* - * CLK_DIV_TOP - * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1) - * ACLK_200, ACLK_100, ACLK_160, ACLK_133, - */ - ldr r1, =0x00005473 - ldr r2, =0x0C510 @ CLK_DIV_TOP - str r1, [r0, r2] - /* MMC[0:1] */ - ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C544 @ CLK_DIV_FSYS1 - str r1, [r0, r2] - /* MMC[2:3] */ - ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C548 @ CLK_DIV_FSYS2 - str r1, [r0, r2] - /* MMC4 */ - ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */ - ldr r2, =0x0C54C @ CLK_DIV_FSYS3 - str r1, [r0, r2] - /* UART[0:5] */ - ldr r1, =0x774777 - ldr r2, =0x0C550 @ CLK_DIV_PERIL0 - str r1, [r0, r2] - /* SLIMBUS: ???, PWM */ - ldr r1, =0x8 - ldr r2, =0x0C55C @ CLK_DIV_PERIL3 - str r1, [r0, r2] - - /* PLL Setting */ - ldr r1, =0x1C20 - ldr r2, =0x14000 @ APLL_LOCK - str r1, [r0, r2] - ldr r2, =0x14008 @ MPLL_LOCK - str r1, [r0, r2] - ldr r2, =0x0C010 @ EPLL_LOCK - str r1, [r0, r2] - ldr r2, =0x0C020 @ VPLL_LOCK - str r1, [r0, r2] - - /* APLL */ - ldr r1, =0x8000001c - ldr r2, =0x14104 @ APLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80c80601 @ 800MHz - ldr r2, =0x14100 @ APLL_CON0 - str r1, [r0, r2] - /* MPLL */ - ldr r1, =0x8000001C - ldr r2, =0x1410C @ MPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80c80601 @ 800MHz - ldr r2, =0x14108 @ MPLL_CON0 - str r1, [r0, r2] - /* EPLL */ - ldr r1, =0x0 - ldr r2, =0x0C114 @ EPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80300302 @ 96MHz - ldr r2, =0x0C110 @ EPLL_CON0 - str r1, [r0, r2] - /* VPLL */ - ldr r1, =0x11000400 - ldr r2, =0x0C124 @ VPLL_CON1 - str r1, [r0, r2] - ldr r1, =0x80350302 @ 108MHz - ldr r2, =0x0C120 @ VPLL_CON0 - str r1, [r0, r2] - - /* - * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001 - * Turn off all - */ - ldr r1, =0xFFF80000 - ldr r2, =0x0C920 @ CLK_GATE_IP_CAM - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFC0 - ldr r2, =0x0C924 @ CLK_GATE_IP_VP - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFE0 - ldr r2, =0x0C928 @ CLK_GATE_IP_MFC - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFFC - ldr r2, =0x0C92C @ CLK_GATE_IP_G3D - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFC00 - ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE - str r1, [r0, r2] - - /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */ - ldr r1, =0xFFFFFFF1 - ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0 - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFC0 - ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1 - str r1, [r0, r2] - - /* - * SMMUPCIE[18], NFCON[16] : 1111 1010 - * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000 - * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011 - */ - ldr r1, =0xFFFAB8A3 - ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS - str r1, [r0, r2] - - /* Turn off all */ - ldr r1, =0xFFFFFFFC - ldr r2, =0x0C94C @ CLK_GATE_IP_GPS - str r1, [r0, r2] - - /* - * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001 - * I2C2[8] : 1111 1110 - */ - ldr r1, =0xF1FFFEFF - ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL - str r1, [r0, r2] - - /* - * KEYIF[16] : 1111 1110 - */ - ldr r1, =0xFFFEFFFF - ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR - str r1, [r0, r2] - - /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */ - ldr r1, =0xFFFFFFD1 - ldr r2, =0x0C970 @ CLK_GATE_BLOCK - str r1, [r0, r2] - mov pc, lr - nop - nop - nop - -system_power_init: - ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000 - - ldr r2, =0x330C @ PS_HOLD_CONTROL - ldr r1, [r0, r2] - orr r1, r1, #(0x3 << 8) @ Data High, Output En - str r1, [r0, r2] - - /* Power Down */ - add r2, r0, #0x3000 - str r5, [r2, #0xC20] @ TV_CONFIGURATION - str r5, [r2, #0xC40] @ MFC_CONFIGURATION - str r5, [r2, #0xC60] @ G3D_CONFIGURATION - str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION - str r5, [r2, #0xCE0] @ GPS_CONFIGURATION - - mov pc, lr - nop - nop - nop - -tzpc_init: - ldr r0, =0x10110000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10120000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10130000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10140000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - ldr r0, =0x10150000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x0804] - str r1, [r0, #0x0810] - str r1, [r0, #0x081C] - str r1, [r0, #0x0828] - - mov pc, lr diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 4ef8eae..e41c322 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -32,6 +32,7 @@ #include <usb/s3c_udc.h> #include <asm/arch/cpu.h> #include <max8998_pmic.h> +#include <asm/arch/watchdog.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -277,3 +278,10 @@ struct s3c_plat_otg_data s5pc210_otg_data = { .usb_flags = PHY0_SLEEP, }; #endif + +int board_early_init_f(void) +{ + wdt_stop(); + + return 0; +} diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index a332f28..7978317 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -56,6 +56,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG #define CONFIG_CMDLINE_EDITING +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F

/* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))

This patch add pinmux settings for Exynos4 for mmc0 and mmc2

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - mmc initialisation code moved to pinmux instead of creating a new common code file

arch/arm/cpu/armv7/exynos/pinmux.c | 56 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 1 + 2 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d2b7d2c..84ee05c 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -209,10 +209,66 @@ static int exynos5_pinmux_config(int peripheral, int flags) return 0; }

+static int exynos4_mmc_config(int peripheral, int flags) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); + struct s5p_gpio_bank *bank, *bank_ext; + int i; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio2->k0; + bank_ext = &gpio2->k1; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio2->k2; + bank_ext = &gpio2->k3; + break; + } + for (i = 0; i < 7; i++) { + if (i == 2) + continue; + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = 3; i < 7; i++) { + s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + + return 0; +} + +static int exynos4_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC2: + return exynos4_mmc_config(peripheral, flags); + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC3: + case PERIPH_ID_SDMMC4: + printf("SDMMC device %d not implemented\n", peripheral); + return -1; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) return exynos5_pinmux_config(peripheral, flags); + else if (cpu_is_exynos4()) + return exynos4_pinmux_config(peripheral, flags); else { debug("pinmux functionality not supported\n"); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 5db25aa..4e1da82 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -34,6 +34,7 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, + PERIPH_ID_SDMMC4, PERIPH_ID_SROMC, PERIPH_ID_UART0, PERIPH_ID_UART1,

On 08/23/2012 09:01 PM, Piotr Wilczek wrote:

This patch use the pinmux for mmc configuration for Trats

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com

---

Chaneges for v2:

• mmc iniatialisation using pinmux

board/samsung/trats/trats.c | 62 +++++++----------------------------------- 1 files changed, 11 insertions(+), 51 deletions(-)

diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index f5df56c..0fab2e0 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -29,6 +29,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> #include <asm/arch/clock.h> #include <asm/arch/clk.h> #include <asm/arch/mipi_dsim.h> @@ -140,46 +141,16 @@ int board_mmc_init(bd_t *bis) { struct exynos4_gpio_part2 *gpio = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();

• int i, err;

• int err;

  /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ s5p_gpio_direction_output(&gpio->k0, 2, 1); s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);

• /*

• * eMMC GPIO:
  

• * SDR 8-bit@48MHz at MMC0
  

• * GPK0[0]	SD_0_CLK(2)
  

• * GPK0[1]	SD_0_CMD(2)
  

• * GPK0[2]	SD_0_CDn	-> Not used
  

• * GPK0[3:6]	SD_0_DATA[0:3](2)
  

• * GPK1[3:6]	SD_0_DATA[0:3](3)
  

• *
  

• * DDR 4-bit@26MHz at MMC4
  

• * GPK0[0]	SD_4_CLK(3)
  

• * GPK0[1]	SD_4_CMD(3)
  

• * GPK0[2]	SD_4_CDn	-> Not used
  

• * GPK0[3:6]	SD_4_DATA[0:3](3)
  

• * GPK1[3:6]	SD_4_DATA[4:7](4)
  

• */
  

• for (i = 0; i < 7; i++) {

• if (i == 2)
  

• 	continue;
  

• /* GPK0[0:6] special function 2 */
  

• s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
  

• /* GPK0[0:6] pull disable */
  

• s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
  

• /* GPK0[0:6] drv 4x */
  

• s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
  

• }
• for (i = 3; i < 7; i++) {

• /* GPK1[3:6] special function 3 */
  

• s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
  

• /* GPK1[3:6] pull disable */
  

• s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
  

• /* GPK1[3:6] drv 4x */
  

• s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
  

• err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
• if (err) {

• debug("SDMMC0 not configured\n");
  

• return err;
  

  }

if err, return? then how can sd-card init? SD/eMMC card didn't have the dependency.

Best Regards, Jaehoon Chung

/* @@ -198,23 +169,12 @@ int board_mmc_init(bd_t *bis) * GPX3[4] T-flash detect pin */ if (!s5p_gpio_get_value(&gpio->x3, 4)) {

• /*
  

•  * SD card GPIO:
  

•  * GPK2[0]	SD_2_CLK(2)
  

•  * GPK2[1]	SD_2_CMD(2)
  

•  * GPK2[2]	SD_2_CDn	-> Not used
  

•  * GPK2[3:6]	SD_2_DATA[0:3](2)
  

•  */
  

• for (i = 0; i < 7; i++) {
  

• 	if (i == 2)
  

• 		continue;
  

• 	/* GPK2[0:6] special function 2 */
  

• 	s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
  

• 	/* GPK2[0:6] pull disable */
  

• 	s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
  

• 	/* GPK2[0:6] drv 4x */
  

• 	s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
  

• err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
  

• if (err) {
  

• 	debug("SDMMC2 not configured\n");
  

• 	return err;
  

  }
• err = s5p_mmc_init(2, 4); }

Hi Piotr,

...

...

• for (i = 0; i < 7; i++) {

• if (i == 2)
  

• 	continue;
  

• /* GPK0[0:6] special function 2 */
  

• s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
  

• /* GPK0[0:6] pull disable */
  

• s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
  

• /* GPK0[0:6] drv 4x */
  

• s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
  

• }
• for (i = 3; i < 7; i++) {

• /* GPK1[3:6] special function 3 */
  

• s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
  

• /* GPK1[3:6] pull disable */
  

• s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
  

• /* GPK1[3:6] drv 4x */
  

• s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
  

• err = exynos_pinmux_config(PERIPH_ID_SDMMC0,

PINMUX_FLAG_8BIT_MODE);

...

• if (err) {

• debug("SDMMC0 not configured\n");
  

• return err;
  

  }

if err, return? then how can sd-card init? SD/eMMC card didn't have the dependency.

exynos_pinmux_config() returns err only if given peripheral and/or mode (or cpu) are not supported. Then gpio pins are not configured and MMC cannot be initiated. Err is returned to indicate this situation and it is essential to init MMC0 correctly. The dependency didn't exist in trats nor universal but exists when pinmux is used ex: smdk5250 board.

You're Right. it returned error, as you mentioned. But if eMMC init is failed, could you ensure that sd init is also failed? I didn't think so. Although eMMC card init is failed, i think that sd-card init should be succeed. 1) eMMC init failed -> return error. : this is your code. 2) eMMC init failed -> if SD card detect, then try to init SD-card. : this is my opinion.

If my thinking is wrong, plz let me know.

Best Regards, Jaehoon Chung

Best regards Piotr Wilczek

...

Best Regards, Jaehoon Chung

...

/* @@ -198,23 +169,12 @@ int board_mmc_init(bd_t *bis) * GPX3[4] T-flash detect pin */ if (!s5p_gpio_get_value(&gpio->x3, 4)) {

• /*
  

•  * SD card GPIO:
  

•  * GPK2[0]	SD_2_CLK(2)
  

•  * GPK2[1]	SD_2_CMD(2)
  

•  * GPK2[2]	SD_2_CDn	-> Not used
  

•  * GPK2[3:6]	SD_2_DATA[0:3](2)
  

•  */
  

• for (i = 0; i < 7; i++) {
  

• 	if (i == 2)
  

• 		continue;
  

• 	/* GPK2[0:6] special function 2 */
  

• 	s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
  

• 	/* GPK2[0:6] pull disable */
  

• 	s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
  

• 	/* GPK2[0:6] drv 4x */
  

• 	s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
  

• err = exynos_pinmux_config(PERIPH_ID_SDMMC2,
  

PINMUX_FLAG_NONE);

...

• if (err) {
  

• 	debug("SDMMC2 not configured\n");
  

• 	return err;
  

  }
• err = s5p_mmc_init(2, 4); }

---

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

This patch use the pinmux for mmc configuration for Universal C210

Signed-off-by: Piotr Wilczek p.wilczek@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - mmc initialisation using pinmux

board/samsung/universal_c210/universal.c | 70 ++++++----------------------- 1 files changed, 15 insertions(+), 55 deletions(-)

diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 90fff5c..f6bc51d 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -27,6 +27,7 @@ #include <asm/arch/adc.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> #include <pmic.h> #include <usb/s3c_udc.h> #include <asm/arch/cpu.h> @@ -177,7 +178,7 @@ int checkboard(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - int i, err; + int err;

switch (get_hwrev()) { case 0: @@ -199,46 +200,12 @@ int board_mmc_init(bd_t *bis) break; }

- /* - * eMMC GPIO: - * SDR 8-bit@48MHz at MMC0 - * GPK0[0] SD_0_CLK(2) - * GPK0[1] SD_0_CMD(2) - * GPK0[2] SD_0_CDn -> Not used - * GPK0[3:6] SD_0_DATA[0:3](2) - * GPK1[3:6] SD_0_DATA[0:3](3) - * - * DDR 4-bit@26MHz at MMC4 - * GPK0[0] SD_4_CLK(3) - * GPK0[1] SD_4_CMD(3) - * GPK0[2] SD_4_CDn -> Not used - * GPK0[3:6] SD_4_DATA[0:3](3) - * GPK1[3:6] SD_4_DATA[4:7](4) - */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPK0[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2); - /* GPK0[0:6] pull disable */ - s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); - /* GPK0[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); - } - - for (i = 3; i < 7; i++) { - /* GPK1[3:6] special function 3 */ - s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3); - /* GPK1[3:6] pull disable */ - s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); - /* GPK1[3:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); + err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); + if (err) { + debug("SDMMC0 not configured\n"); + return err; }

- /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); - /* * MMC device init * mmc0 : eMMC (8-bit buswidth) @@ -246,28 +213,21 @@ int board_mmc_init(bd_t *bis) */ err = s5p_mmc_init(0, 8);

+ /* T-flash detect */ + s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); + s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); + /* * Check the T-flash detect pin * GPX3[4] T-flash detect pin */ if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - /* - * SD card GPIO: - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn -> Not used - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2); - /* GPK2[0:6] pull disable */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) { + debug("SDMMC2 not configured\n"); + return err; } + err = s5p_mmc_init(2, 4); }