[U-Boot] [PATCH 1/2] ARM: socfpga: Pull PL310 clearing into common code
Pull the PL310 clearing code into common code, so it can be reused by Arria10.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 54 +++++++++++++++++++++++ arch/arm/mach-socfpga/spl_gen5.c | 54 ----------------------- 3 files changed, 55 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 86d5d2b62b..876b850be2 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); #endif
void do_bridge_reset(int enable); +void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e045..14337ff2d9 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -46,6 +46,60 @@ int dram_init(void) return 0; }
+void socfpga_pl310_clear(void) +{ + u32 mask = 0xff, ena = 0; + + icache_enable(); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x0, &pl310->pl310_tag_latency_ctrl); + writel(0x10, &pl310->pl310_data_latency_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + ena = readl(&pl310->pl310_ctrl); + ena |= L2X0_CTRL_EN; + + /* + * Invalidate the PL310 L2 cache. Keep the invalidation code + * entirely in L1 I-cache to avoid any bus traffic through + * the L2. + */ + asm volatile( + ".align 5 \n" + " b 3f \n" + "1: str %1, [%4] \n" + " dsb \n" + " isb \n" + " str %0, [%2] \n" + " dsb \n" + " isb \n" + "2: ldr %0, [%2] \n" + " cmp %0, #0 \n" + " bne 2b \n" + " str %0, [%3] \n" + " dsb \n" + " isb \n" + " b 4f \n" + "3: b 1b \n" + "4: nop \n" + : "+r"(mask), "+r"(ena) + : "r"(&pl310->pl310_inv_way), + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) + : "memory", "cc"); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + void enable_caches(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 142b60f887..3e2b9365ec 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -66,60 +66,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif
-static void socfpga_pl310_clear(void) -{ - u32 mask = 0xff, ena = 0; - - icache_enable(); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x0, &pl310->pl310_tag_latency_ctrl); - writel(0x10, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); - - /* Enable the L2 cache */ - ena = readl(&pl310->pl310_ctrl); - ena |= L2X0_CTRL_EN; - - /* - * Invalidate the PL310 L2 cache. Keep the invalidation code - * entirely in L1 I-cache to avoid any bus traffic through - * the L2. - */ - asm volatile( - ".align 5 \n" - " b 3f \n" - "1: str %1, [%4] \n" - " dsb \n" - " isb \n" - " str %0, [%2] \n" - " dsb \n" - " isb \n" - "2: ldr %0, [%2] \n" - " cmp %0, #0 \n" - " bne 2b \n" - " str %0, [%3] \n" - " dsb \n" - " isb \n" - " b 4f \n" - "3: b 1b \n" - "4: nop \n" - : "+r"(mask), "+r"(ena) - : "r"(&pl310->pl310_inv_way), - "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) - : "memory", "cc"); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config();
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC.
The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller.
This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again.
The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org --- arch/arm/mach-socfpga/spl_a10.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c8e73d47c0..8eb856f3d8 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -81,6 +81,7 @@ void board_init_f(ulong dummy)
socfpga_init_security_policies(); socfpga_sdram_remap_zero(); + socfpga_pl310_clear();
/* Assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all();
On 3/22/19 9:30 AM, Marek Vasut wrote:
Pull the PL310 clearing code into common code, so it can be reused by Arria10.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org
arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 54 +++++++++++++++++++++++ arch/arm/mach-socfpga/spl_gen5.c | 54 ----------------------- 3 files changed, 55 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 86d5d2b62b..876b850be2 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); #endif
void do_bridge_reset(int enable); +void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e045..14337ff2d9 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -46,6 +46,60 @@ int dram_init(void) return 0; }
+void socfpga_pl310_clear(void) +{
- u32 mask = 0xff, ena = 0;
- icache_enable();
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
- writel(0x0, &pl310->pl310_tag_latency_ctrl);
- writel(0x10, &pl310->pl310_data_latency_ctrl);
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |L310_AUX_CTRL_INST_PREFETCH_MASK |L310_SHARED_ATT_OVERRIDE_ENABLE);
Do we need to enable these bits here? They get enabled again in v7_outer_cache_enable().
Otherwise, feel free to add:
Reviewed-by: Dinh Nguyen dinguyen@kernel.org
Dinh
On 3/25/19 2:51 PM, Dinh Nguyen wrote:
On 3/22/19 9:30 AM, Marek Vasut wrote:
Pull the PL310 clearing code into common code, so it can be reused by Arria10.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org
arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 54 +++++++++++++++++++++++ arch/arm/mach-socfpga/spl_gen5.c | 54 ----------------------- 3 files changed, 55 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 86d5d2b62b..876b850be2 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); #endif
void do_bridge_reset(int enable); +void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e045..14337ff2d9 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -46,6 +46,60 @@ int dram_init(void) return 0; }
+void socfpga_pl310_clear(void) +{
- u32 mask = 0xff, ena = 0;
- icache_enable();
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
- writel(0x0, &pl310->pl310_tag_latency_ctrl);
- writel(0x10, &pl310->pl310_data_latency_ctrl);
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |L310_AUX_CTRL_INST_PREFETCH_MASK |L310_SHARED_ATT_OVERRIDE_ENABLE);Do we need to enable these bits here? They get enabled again in v7_outer_cache_enable().
I think you want to configure the controller correctly right from the start , no ?
Otherwise, feel free to add:
Reviewed-by: Dinh Nguyen dinguyen@kernel.org
Dinh
participants (2)
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Dinh Nguyen -
Marek Vasut