[U-Boot] [PATCHv2 0/3] Odroid n2 using eMMC would fail to boot up
Here are some small changes to fix booting of Odroid N2 using eMMC. Fixed the clk tunnig during mmc initialization.
Build and tested on top of below patches [0] https://patchwork.ozlabs.org/patch/1213648/ [1] https://patchwork.ozlabs.org/patch/1213650/
Tested on below eMMC module on Odroid N2 and C2 new orange - eMMC AJNB4R 14.6 GiB MMC 5.1 old back - eMMC CGND3R 58.2 GiB MMC 5.0
Prevoius changes: [3] https://patchwork.ozlabs.org/cover/1201206/
-Anand
Anand Moon (3): mmc: meson-gx: Fix clk phase tuning for MMC configs: meson64: enable GIC support for G12A/G12B board: amlogic: select PWRSEQ for all amlogic platform
arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++-------- arch/arm/mach-meson/Kconfig | 1 + drivers/mmc/meson_gx_mmc.c | 9 +++++---- include/configs/meson64.h | 2 +- 4 files changed, 13 insertions(+), 13 deletions(-)
As per mainline line kernel fix the clk tunnig phase for mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
Signed-off-by: Anand Moon linux.amoon@gmail.com --- Changes from previous use the mainline kernel tuning for clk tuning. Fixed the commmit messages. Patch v1: https://patchwork.ozlabs.org/patch/1201208/
Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards --- arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++-------- drivers/mmc/meson_gx_mmc.c | 9 +++++---- 2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..d70fe4f03e 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__
#include <mmc.h> +#include <linux/bitops.h>
#define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,11 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) + +#define CLK_CORE_PHASE_MASK GENMASK(9, 8) +#define CLK_TX_PHASE_MASK GENMASK(11, 10) +#define CLK_RX_PHASE_MASK GENMASK(13, 12) + #define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..402981c3bb 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc) clk_div = DIV_ROUND_UP(clk, mmc->clock);
/* 180 phase core clock */ - meson_mmc_clk |= CLK_CO_PHASE_180; - - /* 180 phase tx clock */ - meson_mmc_clk |= CLK_TX_PHASE_000; + meson_mmc_clk |= CLK_CORE_PHASE_MASK; + /* 000 phase rx clock */ + meson_mmc_clk |= CLK_RX_PHASE_MASK; + /* 000 phase tx clock */ + meson_mmc_clk |= CLK_TX_PHASE_MASK;
/* clock settings */ meson_mmc_clk |= clk_src;
On Tue 24 Dec 2019 at 14:25, Anand Moon linux.amoon@gmail.com wrote:
As per mainline line kernel fix the clk tunnig phase for mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
Signed-off-by: Anand Moon linux.amoon@gmail.com
Changes from previous use the mainline kernel tuning for clk tuning. Fixed the commmit messages. Patch v1: https://patchwork.ozlabs.org/patch/1201208/
Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++-------- drivers/mmc/meson_gx_mmc.c | 9 +++++---- 2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..d70fe4f03e 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__
#include <mmc.h> +#include <linux/bitops.h>
#define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,11 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10)
+#define CLK_CORE_PHASE_MASK GENMASK(9, 8) +#define CLK_TX_PHASE_MASK GENMASK(11, 10) +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..402981c3bb 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc) clk_div = DIV_ROUND_UP(clk, mmc->clock);
/* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
- /* 180 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_000;
- meson_mmc_clk |= CLK_CORE_PHASE_MASK;
- /* 000 phase rx clock */
- meson_mmc_clk |= CLK_RX_PHASE_MASK;
- /* 000 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_MASK;
I'm not sure how this acheive what is descibed in the commit description.
It looks more that it would set a 270 degree phase on all clocks, which is not desirable.
/* clock settings */ meson_mmc_clk |= clk_src;
Hi Jerome,
On Thu, 26 Dec 2019 at 14:40, Jerome Brunet jbrunet@baylibre.com wrote:
On Tue 24 Dec 2019 at 14:25, Anand Moon linux.amoon@gmail.com wrote:
As per mainline line kernel fix the clk tunnig phase for mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
Signed-off-by: Anand Moon linux.amoon@gmail.com
Changes from previous use the mainline kernel tuning for clk tuning. Fixed the commmit messages. Patch v1: https://patchwork.ozlabs.org/patch/1201208/
Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++-------- drivers/mmc/meson_gx_mmc.c | 9 +++++---- 2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..d70fe4f03e 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__
#include <mmc.h> +#include <linux/bitops.h>
#define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,11 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10)
+#define CLK_CORE_PHASE_MASK GENMASK(9, 8) +#define CLK_TX_PHASE_MASK GENMASK(11, 10) +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..402981c3bb 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc) clk_div = DIV_ROUND_UP(clk, mmc->clock);
/* 180 phase core clock */
meson_mmc_clk |= CLK_CO_PHASE_180;/* 180 phase tx clock */meson_mmc_clk |= CLK_TX_PHASE_000;
meson_mmc_clk |= CLK_CORE_PHASE_MASK;/* 000 phase rx clock */meson_mmc_clk |= CLK_RX_PHASE_MASK;/* 000 phase tx clock */meson_mmc_clk |= CLK_TX_PHASE_MASK;I'm not sure how this acheive what is descibed in the commit description.
It looks more that it would set a 270 degree phase on all clocks, which is not desirable.
Oops thanks for spotting my mistake, you are correct, it should be as below.
clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); I will resend with correct configuration.
-Anand
Enable GIC support for G12A/G12B platform.
Signed-off-by: Anand Moon linux.amoon@gmail.com Reviewed-by: Neil Armstrong narmstrong@baylibre.com --- no changes --- include/configs/meson64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 736081277d..50707a3197 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -8,7 +8,7 @@ #define __MESON64_CONFIG_H
/* Generic Interrupt Controller Definitions */ -#if defined(CONFIG_MESON_AXG) +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A)) #define GICD_BASE 0xffc01000 #define GICC_BASE 0xffc02000 #else /* MESON GXL and GXBB */
commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc") introduce CONFIG_PWESEQ for power sequence for eMMC module on amlogic platform, so enable this to all amlogic boards.
Signed-off-by: Anand Moon linux.amoon@gmail.com Reviewed-by: Neil Armstrong narmstrong@baylibre.com --- no changes --- arch/arm/mach-meson/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index e29e4c0acc..513a33dae2 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -8,6 +8,7 @@ config MESON64_COMMON select DM_SERIAL select SYSCON select REGMAP + select PWRSEQ select BOARD_LATE_INIT imply CMD_DM
participants (2)
-
Anand Moon -
Jerome Brunet