[U-Boot] [PATCH 00/18] Introduce cm-fx6 board
This patch series introduces the mx6 based cm-fx6 board. cm-fx6 comes with either single, dual, or quad core mx6 soc, and various dram configurations.
First 11 patches are preparatory steps which include: - Cleanups and bug fixes for the mx6 dram config code - New functions and macros for enabling clocks, i2c setup, and querying the status of sata port - Support for M25PE16 and M25PX16 spi flashes - sf probe command fix
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com
Nikita Kiryanov (18): spl: improve spi configuration mx6: add clock enabling functions sf: fix sf probe mtd: spi: add support for M25PE16 and M25PX16 compulab: eeprom: add support for defining eeprom i2c bus sata: dwc_ahsata: implement sata_port_status i2c: imx: add macros to setup pads for multiple SoC types arm: mx6: ddr: cleanup arm: mx6: ddr: do not write into reserved bit arm: mx6: ddr: configure MMDC for slow_pd arm: mx6: ddr: fix cs0_end calculation arm: mx6: add support for Compulab cm-fx6 CoM arm: mx6: cm_fx6: add nand support arm: mx6: cm_fx6: add ethernet support arm: mx6: cm_fx6: add usb support arm: mx6: cm_fx6: add i2c support arm: mx6: cm_fx6: use eeprom arm: mx6: cm_fx6: add sata support
README | 7 + arch/arm/cpu/armv7/mx6/clock.c | 99 ++++++ arch/arm/cpu/armv7/mx6/ddr.c | 272 +++++++-------- arch/arm/include/asm/arch-mx6/clock.h | 5 + arch/arm/include/asm/imx-common/mxc_i2c.h | 33 ++ board/boundary/nitrogen6x/nitrogen6x.c | 5 + board/compulab/cm_fx6/Makefile | 12 + board/compulab/cm_fx6/cm_fx6.c | 477 ++++++++++++++++++++++++++ board/compulab/cm_fx6/common.c | 83 +++++ board/compulab/cm_fx6/common.h | 53 +++ board/compulab/cm_fx6/imximage.cfg | 8 + board/compulab/cm_fx6/spl.c | 409 ++++++++++++++++++++++ board/compulab/common/eeprom.c | 10 +- board/embest/mx6boards/mx6boards.c | 5 + board/freescale/mx6qsabreauto/mx6qsabreauto.c | 7 + board/freescale/mx6sabresd/mx6sabresd.c | 7 + board/freescale/mx6slevk/mx6slevk.c | 5 + board/gateworks/gw_ventana/gw_ventana.c | 7 +- board/genesi/mx51_efikamx/efikamx.c | 5 + board/ttcontrol/vision2/vision2.c | 5 + boards.cfg | 2 + drivers/block/dwc_ahsata.c | 17 + drivers/mtd/spi/sf_params.c | 2 + drivers/mtd/spi/spi_spl_load.c | 15 +- drivers/spi/mxc_spi.c | 48 +-- include/configs/cm_fx6.h | 310 +++++++++++++++++ include/configs/cm_t335.h | 1 + include/configs/cm_t35.h | 1 + include/configs/cm_t54.h | 1 + include/configs/embestmx6boards.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/mx51_efikamx.h | 4 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/vision2.h | 4 +- include/sata.h | 1 + 37 files changed, 1756 insertions(+), 174 deletions(-) create mode 100644 board/compulab/cm_fx6/Makefile create mode 100644 board/compulab/cm_fx6/cm_fx6.c create mode 100644 board/compulab/cm_fx6/common.c create mode 100644 board/compulab/cm_fx6/common.h create mode 100644 board/compulab/cm_fx6/imximage.cfg create mode 100644 board/compulab/cm_fx6/spl.c create mode 100644 include/configs/cm_fx6.h
Currently we can define CONFIG_SPL_SPI_<any parameter except SPI MODE>. Define CONFIG_SPL_SPI_MODE option, and provide a default value for backwards compatibility. Default values are also provided for the rest of the spi_flash_probe parameters (like we do in cmd_sf), to help with config file brevity.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- README | 7 +++++++ drivers/mtd/spi/spi_spl_load.c | 15 ++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/README b/README index f704eb3..d7c55f8 100644 --- a/README +++ b/README @@ -2910,6 +2910,13 @@ CBFS (Coreboot Filesystem) support CONFIG_SF_DEFAULT_MODE (see include/spi.h) CONFIG_SF_DEFAULT_SPEED in Hz
+ The following defaults may be provided by the platform to + override SPL defaults for SPI. + + CONFIG_SPL_SPI_MODE SPI mode Default SPI_MODE3 + CONFIG_SPL_SPI_CS Chip-select Default 0 + CONFIG_SPL_SPI_BUS Bus identifier Default 0 + CONFIG_CMD_SF_TEST
Define this option to include a destructive SPI flash diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c index 1954b7e..b270b82 100644 --- a/drivers/mtd/spi/spi_spl_load.c +++ b/drivers/mtd/spi/spi_spl_load.c @@ -13,6 +13,19 @@ #include <spi_flash.h> #include <spl.h>
+#ifndef CONFIG_SF_DEFAULT_SPEED +# define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SPL_SPI_MODE +# define CONFIG_SPL_SPI_MODE SPI_MODE_3 +#endif +#ifndef CONFIG_SPL_SPI_CS +# define CONFIG_SPL_SPI_CS 0 +#endif +#ifndef CONFIG_SPL_SPI_BUS +# define CONFIG_SPL_SPI_BUS 0 +#endif + #ifdef CONFIG_SPL_OS_BOOT /* * Load the kernel, check for a valid header we can parse, and if found load @@ -57,7 +70,7 @@ void spl_spi_load_image(void) */
flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS, - CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3); + CONFIG_SF_DEFAULT_SPEED, CONFIG_SPL_SPI_MODE); if (!flash) { puts("SPI probe failed.\n"); hang();
On Sunday, August 03, 2014 at 09:34:31 AM, Nikita Kiryanov wrote:
Currently we can define CONFIG_SPL_SPI_<any parameter except SPI MODE>. Define CONFIG_SPL_SPI_MODE option, and provide a default value for backwards compatibility. Default values are also provided for the rest of the spi_flash_probe parameters (like we do in cmd_sf), to help with config file brevity.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
You might actually be even more bold and check if you cannot fall back to the CONFIG_DEFAULT_SPI_MODE etc. What do you think ?
Best regards, Marek Vasut
On 03/08/14 16:44, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:31 AM, Nikita Kiryanov wrote:
Currently we can define CONFIG_SPL_SPI_<any parameter except SPI MODE>. Define CONFIG_SPL_SPI_MODE option, and provide a default value for backwards compatibility. Default values are also provided for the rest of the spi_flash_probe parameters (like we do in cmd_sf), to help with config file brevity.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
You might actually be even more bold and check if you cannot fall back to the CONFIG_DEFAULT_SPI_MODE etc. What do you think ?
Not a fan of the idea. It will: - Complicate the #ifdefs - Complicate the relationship between CONFIG_DEFAULT_SPI_* and CONFIG_SPL_SPI_* #defines - Not get much use: most boards do not #define CONFIG_DEFAULT_SPI_* values in the config files, and of the ones that do, only two (dra7xx_evm and cm_fx6) use SPI in SPL.
Best regards, Marek Vasut
On Tuesday, August 05, 2014 at 03:28:04 PM, Nikita Kiryanov wrote:
On 03/08/14 16:44, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:31 AM, Nikita Kiryanov wrote:
Currently we can define CONFIG_SPL_SPI_<any parameter except SPI MODE>. Define CONFIG_SPL_SPI_MODE option, and provide a default value for backwards compatibility. Default values are also provided for the rest of the spi_flash_probe parameters (like we do in cmd_sf), to help with config file brevity.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
You might actually be even more bold and check if you cannot fall back to the CONFIG_DEFAULT_SPI_MODE etc. What do you think ?
Not a fan of the idea. It will:
- Complicate the #ifdefs
- Complicate the relationship between CONFIG_DEFAULT_SPI_* and CONFIG_SPL_SPI_* #defines
- Not get much use: most boards do not #define CONFIG_DEFAULT_SPI_* values in the config files, and of the ones that do, only two (dra7xx_evm and cm_fx6) use SPI in SPL.
On the other hand, it's now only a matter of time until we get CONFIG_TPL_SPI_* m which gives us _another_ set of defines. So the question is -- what is your proposition to keep the amount of new ad-hoc defines low and cater for this case?
Best regards, Marek Vasut
On 05/08/14 17:11, Marek Vasut wrote:
On Tuesday, August 05, 2014 at 03:28:04 PM, Nikita Kiryanov wrote:
On 03/08/14 16:44, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:31 AM, Nikita Kiryanov wrote:
Currently we can define CONFIG_SPL_SPI_<any parameter except SPI MODE>. Define CONFIG_SPL_SPI_MODE option, and provide a default value for backwards compatibility. Default values are also provided for the rest of the spi_flash_probe parameters (like we do in cmd_sf), to help with config file brevity.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
You might actually be even more bold and check if you cannot fall back to the CONFIG_DEFAULT_SPI_MODE etc. What do you think ?
Not a fan of the idea. It will:
- Complicate the #ifdefs
- Complicate the relationship between CONFIG_DEFAULT_SPI_* and CONFIG_SPL_SPI_* #defines
- Not get much use: most boards do not #define CONFIG_DEFAULT_SPI_* values in the config files, and of the ones that do, only two (dra7xx_evm and cm_fx6) use SPI in SPL.
On the other hand, it's now only a matter of time until we get CONFIG_TPL_SPI_* m which gives us _another_ set of defines. So the question is -- what is your proposition to keep the amount of new ad-hoc defines low and cater for this case?
OK I think I may have misunderstood your suggestion. You wanted to replace CONFIG_SPL_SPI_* #defines with CONFIG_DEFAULT_SPI_* #defines, not use both, right? Based on cursory grepping, this seems possible, though I think CONFIG_SF_DEFAULT_* is a better candidate.
I'll prepare a patch..
Best regards, Marek Vasut
On Wednesday, August 06, 2014 at 12:53:19 PM, Nikita Kiryanov wrote:
On 05/08/14 17:11, Marek Vasut wrote:
On Tuesday, August 05, 2014 at 03:28:04 PM, Nikita Kiryanov wrote:
On 03/08/14 16:44, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:31 AM, Nikita Kiryanov wrote:
Currently we can define CONFIG_SPL_SPI_<any parameter except SPI MODE>. Define CONFIG_SPL_SPI_MODE option, and provide a default value for backwards compatibility. Default values are also provided for the rest of the spi_flash_probe parameters (like we do in cmd_sf), to help with config file brevity.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
You might actually be even more bold and check if you cannot fall back to the CONFIG_DEFAULT_SPI_MODE etc. What do you think ?
Not a fan of the idea. It will:
Complicate the #ifdefs
Complicate the relationship between CONFIG_DEFAULT_SPI_* and
CONFIG_SPL_SPI_* #defines
Not get much use: most boards do not #define CONFIG_DEFAULT_SPI_*
values in the config files, and of the ones that do, only two (dra7xx_evm and cm_fx6) use SPI in SPL.
On the other hand, it's now only a matter of time until we get CONFIG_TPL_SPI_* m which gives us _another_ set of defines. So the question is -- what is your proposition to keep the amount of new ad-hoc defines low and cater for this case?
OK I think I may have misunderstood your suggestion. You wanted to replace CONFIG_SPL_SPI_* #defines with CONFIG_DEFAULT_SPI_* #defines, not use both, right? Based on cursory grepping, this seems possible, though I think CONFIG_SF_DEFAULT_* is a better candidate.
I'll prepare a patch..
Yep, thank you!
Best regards, Marek Vasut
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- arch/arm/cpu/armv7/mx6/clock.c | 99 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 5 ++ 2 files changed, 104 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 7dd83ec..696dc98 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable) } #endif
+#ifdef CONFIG_NAND_MXS +void setup_gpmi_io_clk(u32 cfg) +{ + /* Disable clocks per ERR007177 from MX6 errata */ + clrbits_le32(&imx_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + clrsetbits_le32(&imx_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + cfg); + + setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + setbits_le32(&imx_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); +} +#endif + void enable_usboh3_clk(unsigned char enable) { u32 reg; @@ -49,6 +78,76 @@ void enable_usboh3_clk(unsigned char enable)
}
+#ifdef CONFIG_FEC_MXC +void enable_enet_clk(unsigned char enable) +{ + u32 reg; + + reg = __raw_readl(&imx_ccm->CCGR1); + if (enable) + reg |= MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK; + else + reg &= ~(MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK); + __raw_writel(reg, &imx_ccm->CCGR1); +} +#endif + +#ifdef CONFIG_MXC_UART +void enable_uart_clk(unsigned char enable) +{ + u32 reg, mask; + + reg = __raw_readl(&imx_ccm->CCGR5); + mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; + if (enable) + reg |= mask; + else + reg &= ~mask; + __raw_writel(reg, &imx_ccm->CCGR5); +} +#endif + +#ifdef CONFIG_SPI +/* spi_num can be from 0 - 4 */ +int enable_cspi_clock(unsigned char enable, unsigned spi_num) +{ + u32 reg, mask; + + if (spi_num > 4) + return -EINVAL; + + mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2); + reg = readl(&imx_ccm->CCGR1); + if (enable) + reg |= mask; + else + reg &= ~mask; + + __raw_writel(reg, &imx_ccm->CCGR1); + return 0; +} +#endif + +#ifdef CONFIG_MMC +int enable_usdhc_clk(unsigned char enable, unsigned bus_num) +{ + u32 reg, mask; + + if (bus_num > 3) + return -EINVAL; + + mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2); + reg = readl(&imx_ccm->CCGR6); + if (enable) + reg |= mask; + else + reg &= ~mask; + + __raw_writel(reg, &imx_ccm->CCGR6); + return 0; +} +#endif + #ifdef CONFIG_SYS_I2C_MXC /* i2c_num can be from 0 - 2 */ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 1b4ded7..f0b728b 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -52,11 +52,16 @@ enum enet_freq { u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +void setup_gpmi_io_clk(u32 cfg); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); +void enable_uart_clk(unsigned char enable); +int enable_cspi_clock(unsigned char enable, unsigned spi_num); +int enable_usdhc_clk(unsigned char enable, unsigned bus_num); int enable_sata_clock(void); int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); +void enable_enet_clk(unsigned char enable); #endif /* __ASM_ARCH_CLOCK_H */
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/boundary/nitrogen6x/nitrogen6x.c | 5 +++ board/embest/mx6boards/mx6boards.c | 5 +++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 7 ++++ board/freescale/mx6sabresd/mx6sabresd.c | 7 ++++ board/freescale/mx6slevk/mx6slevk.c | 5 +++ board/gateworks/gw_ventana/gw_ventana.c | 7 +++- board/genesi/mx51_efikamx/efikamx.c | 5 +++ board/ttcontrol/vision2/vision2.c | 5 +++ drivers/spi/mxc_spi.c | 48 ++++++++++++++------------- include/configs/embestmx6boards.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/mx51_efikamx.h | 4 +-- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/vision2.h | 4 +-- 16 files changed, 79 insertions(+), 33 deletions(-)
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 84294db..aadddb9 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -328,6 +328,11 @@ int board_mmc_init(bd_t *bis) #endif
#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; +} + iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index d06b57d..e8a11c2 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -284,6 +284,11 @@ iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), };
+int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; +} + static void setup_spi(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 928dadf..836d722 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -259,6 +259,13 @@ int board_init(void) return 0; }
+#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index d7c4b4f..c5f10f7 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -513,6 +513,13 @@ static int pfuze_init(void) return 0; }
+#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index d2b64cc..ec63d9e 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -82,6 +82,11 @@ static iomux_v3_cfg_t ecspi1_pads[] = { MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), };
+int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1; +} + static void setup_spi(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 9d2651f..054f904 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -353,9 +353,14 @@ iomux_v3_cfg_t const ecspi1_pads[] = { IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), };
+int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; +} + static void setup_spi(void) { - gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + gpio_direction_output(IMX_GPIO_NR(3, 19), 1); SETUP_IOMUX_PADS(ecspi1_pads); } #endif diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 16769e5..137e4ed 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -152,6 +152,11 @@ static iomux_v3_cfg_t const efikamx_spi_pads[] = { * PMIC configuration */ #ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 1) ? 121 : -1; +} + static void power_init(void) { unsigned int val; diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index b4d3994..b5249e7 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -144,6 +144,11 @@ static void setup_uart(void) }
#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 1) ? 121 : -1; +} + void spi_io_init(void) { static const iomux_v3_cfg_t spi_pads[] = { diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index f3f029d..9583ef0 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -25,6 +25,11 @@ static unsigned long spi_bases[] = { MXC_SPI_BASE_ADDRESSES };
+__weak int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return -1; +} + #define OUT MXC_GPIO_DIRECTION_OUT
#define reg_read readl @@ -358,31 +363,30 @@ void spi_init(void) { }
-static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) +/* + * Some SPI devices require active chip-select over multiple + * transactions, we achieve this using a GPIO. Still, the SPI + * controller has to be configured to use one of its own chipselects. + * To use this feature you have to implement board_spi_cs_gpio() to assign + * a gpio value for each cs (-1 if cs doesn't need to use gpio). + * You must use some unused on this SPI controller cs between 0 and 3. + */ +static int setup_cs_gpio(struct mxc_spi_slave *mxcs, + unsigned int bus, unsigned int cs) { int ret;
- /* - * Some SPI devices require active chip-select over multiple - * transactions, we achieve this using a GPIO. Still, the SPI - * controller has to be configured to use one of its own chipselects. - * To use this feature you have to call spi_setup_slave() with - * cs = internal_cs | (gpio << 8), and you have to use some unused - * on this SPI controller cs between 0 and 3. - */ - if (cs > 3) { - mxcs->gpio = cs >> 8; - cs &= 3; - ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); - if (ret) { - printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); - return -EINVAL; - } - } else { - mxcs->gpio = -1; + mxcs->gpio = board_spi_cs_gpio(bus, cs); + if (mxcs->gpio == -1) + return 0; + + ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); + if (ret) { + printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); + return -EINVAL; }
- return cs; + return 0; }
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, @@ -402,14 +406,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
- ret = decode_cs(mxcs, cs); + ret = setup_cs_gpio(mxcs, bus, cs); if (ret < 0) { free(mxcs); return NULL; }
- cs = ret; - mxcs->base = spi_bases[bus];
ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index f1000f3..bcd5ea4 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -100,7 +100,7 @@ #define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(2, 30) << 8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 8197a72..97398a8 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -61,7 +61,7 @@ #define CONFIG_SPI_FLASH_BAR #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_BUS 0 - #define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) + #define CONFIG_SF_DEFAULT_CS 0 /* GPIO 3-19 (21248) */ #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h index 0f2a4ef..fce7ead 100644 --- a/include/configs/mx51_efikamx.h +++ b/include/configs/mx51_efikamx.h @@ -96,11 +96,11 @@
#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SST -#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8) +#define CONFIG_SF_DEFAULT_CS 1 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_ENV_SPI_CS (1 | 121 << 8) +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_MAX_HZ 25000000 #define CONFIG_ENV_SPI_MODE (SPI_MODE_0) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index e59a3b4..2d93d6c 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -74,7 +74,7 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 9) << 8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3d05a64..5b8309b 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -203,7 +203,7 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 11) << 8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index b2b17ce..d266f7d 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -53,7 +53,7 @@ #define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 25000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #endif diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 6891bf8..3f35076 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -57,11 +57,11 @@ * Use gpio 4 pin 25 as chip select for SPI flash * This corresponds to gpio 121 */ -#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8)) +#define CONFIG_SF_DEFAULT_CS 1 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_ENV_SPI_CS (1 | (121 << 8)) +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_MAX_HZ 25000000 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote:
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
[...] Best regards, Marek Vasut
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote:
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
I agree that the subject line should be made a bit more specific to mxc_spi though...
[...] Best regards, Marek Vasut
On Monday, August 04, 2014 at 02:48:54 PM, Nikita Kiryanov wrote:
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote:
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
Why not ?
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
You mean sf probe 0:15872 , right ? But then, you can use CONFIG_DEFAULT_SPI_CS to specify the default CS, no ?
I agree that the subject line should be made a bit more specific to mxc_spi though...
[...] Best regards, Marek Vasut
Best regards, Marek Vasut
On 04/08/14 16:10, Marek Vasut wrote:
On Monday, August 04, 2014 at 02:48:54 PM, Nikita Kiryanov wrote:
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote:
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
Why not ?
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
You mean sf probe 0:15872 , right ?
It's the same thing: sf probe [[bus:]cs] [hz] [mode]
The point is that cs 0 has to be represented as "15872", instead of "0".
But then, you can use CONFIG_DEFAULT_SPI_CS to specify the default CS, no ?
This only works if you have just one SPI device that requires GPIO use. Otherwise, chances are the user will have no idea how to access devices on other chip selects without looking at the code.
I agree that the subject line should be made a bit more specific to mxc_spi though...
[...] Best regards, Marek Vasut
Best regards, Marek Vasut
On Monday, August 04, 2014 at 03:45:57 PM, Nikita Kiryanov wrote:
On 04/08/14 16:10, Marek Vasut wrote:
On Monday, August 04, 2014 at 02:48:54 PM, Nikita Kiryanov wrote:
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote:
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
Why not ?
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
You mean sf probe 0:15872 , right ?
It's the same thing: sf probe [[bus:]cs] [hz] [mode]
The point is that cs 0 has to be represented as "15872", instead of "0".
That's expected, yep.
But then, you can use CONFIG_DEFAULT_SPI_CS to specify the default CS, no ?
This only works if you have just one SPI device that requires GPIO use. Otherwise, chances are the user will have no idea how to access devices on other chip selects without looking at the code.
Oh, so you're confused by those crazy chipselect numbers ?
Best regards, Marek Vasut
On 04/08/14 16:51, Marek Vasut wrote:
On Monday, August 04, 2014 at 03:45:57 PM, Nikita Kiryanov wrote:
On 04/08/14 16:10, Marek Vasut wrote:
On Monday, August 04, 2014 at 02:48:54 PM, Nikita Kiryanov wrote:
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote:
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
Why not ?
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
You mean sf probe 0:15872 , right ?
It's the same thing: sf probe [[bus:]cs] [hz] [mode]
The point is that cs 0 has to be represented as "15872", instead of "0".
That's expected, yep.
By whom?
But then, you can use CONFIG_DEFAULT_SPI_CS to specify the default CS, no ?
This only works if you have just one SPI device that requires GPIO use. Otherwise, chances are the user will have no idea how to access devices on other chip selects without looking at the code.
Oh, so you're confused by those crazy chipselect numbers ?
Are you suggesting that they make sense?
Best regards, Marek Vasut
On Monday, August 04, 2014 at 04:11:57 PM, Nikita Kiryanov wrote:
On 04/08/14 16:51, Marek Vasut wrote:
On Monday, August 04, 2014 at 03:45:57 PM, Nikita Kiryanov wrote:
On 04/08/14 16:10, Marek Vasut wrote:
On Monday, August 04, 2014 at 02:48:54 PM, Nikita Kiryanov wrote:
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote: > MXC SPI driver has a feature whereas a GPIO line can be used as a CS > signal. This is set up by joining the CS and GPIO values into a > single value using (cs | gpio << 8), and passing it off as a CS > value. This breaks the sf probe command, because it is no longer > possible to invoke it as sf probe <cs>. Instead, the user must use > sf probe <cs | gpio << 8>. > > Fix this by introducing a new board function: board_spi_cs_gpio(). > When called, board_spi_cs_gpio() will return the gpio number for the > cs value it is given. > > Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com > Cc: Eric Nelson eric.nelson@boundarydevices.com > Cc: Eric Benard eric@eukrea.com > Cc: Fabio Estevam fabio.estevam@freescale.com > Cc: Tim Harvey tharvey@gateworks.com > Cc: Stefano Babic sbabic@denx.de > Cc: Tom Rini trini@ti.com > Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
Why not ?
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
You mean sf probe 0:15872 , right ?
It's the same thing: sf probe [[bus:]cs] [hz] [mode]
The point is that cs 0 has to be represented as "15872", instead of "0".
That's expected, yep.
By whom?
By the interface. But anyway, let's proceed discussing this stuff in the other thread. This would only turn into pointless bickering here ;-)
[...]
On Mon, Aug 04, 2014 at 04:45:57PM +0300, Nikita Kiryanov wrote:
On 04/08/14 16:10, Marek Vasut wrote:
On Monday, August 04, 2014 at 02:48:54 PM, Nikita Kiryanov wrote:
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote:
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
Why not ?
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
You mean sf probe 0:15872 , right ?
It's the same thing: sf probe [[bus:]cs] [hz] [mode]
The point is that cs 0 has to be represented as "15872", instead of "0".
Eeep. That seems very likely to be gotten incorrect by users.
Can we do something like: mxc_spi.c: __weak int board_map_spi_cs_value(int desired_cs) { return -EINVAL; }
fooboard.c: board_map_spi_cs_value(int desired_cs) { if (desired_cs == 0) return IMX_GPIO_NR(2, 30); else return -EINVAL; }
I think it'll be very bad if the user has to type 'sf probe 0:15872' or 'sf probe 15872' since that's a programming detail rather than saying bank 2, gpio 30 (which I assume is what IMX_GPIO_NR means).
On Monday, August 04, 2014 at 04:02:42 PM, Tom Rini wrote: [...]
Eeep. That seems very likely to be gotten incorrect by users.
Can we do something like: mxc_spi.c: __weak int board_map_spi_cs_value(int desired_cs) { return -EINVAL; }
fooboard.c: board_map_spi_cs_value(int desired_cs) { if (desired_cs == 0) return IMX_GPIO_NR(2, 30); else return -EINVAL; }
I think it'll be very bad if the user has to type 'sf probe 0:15872' or 'sf probe 15872' since that's a programming detail rather than saying bank 2, gpio 30 (which I assume is what IMX_GPIO_NR means).
I'm worried about the user scripts which depend on this original behavior. Do we care about compatibility there ?
Best regards, Marek Vasut
On 04/08/14 17:02, Tom Rini wrote:
On Mon, Aug 04, 2014 at 04:45:57PM +0300, Nikita Kiryanov wrote:
On 04/08/14 16:10, Marek Vasut wrote:
On Monday, August 04, 2014 at 02:48:54 PM, Nikita Kiryanov wrote:
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote:
MXC SPI driver has a feature whereas a GPIO line can be used as a CS signal. This is set up by joining the CS and GPIO values into a single value using (cs | gpio << 8), and passing it off as a CS value. This breaks the sf probe command, because it is no longer possible to invoke it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << 8>.
Fix this by introducing a new board function: board_spi_cs_gpio(). When called, board_spi_cs_gpio() will return the gpio number for the cs value it is given.
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Eric Benard eric@eukrea.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
Why not ?
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
You mean sf probe 0:15872 , right ?
It's the same thing: sf probe [[bus:]cs] [hz] [mode]
The point is that cs 0 has to be represented as "15872", instead of "0".
Eeep. That seems very likely to be gotten incorrect by users.
Can we do something like: mxc_spi.c: __weak int board_map_spi_cs_value(int desired_cs) { return -EINVAL; }
fooboard.c: board_map_spi_cs_value(int desired_cs) { if (desired_cs == 0) return IMX_GPIO_NR(2, 30); else return -EINVAL; }
That's pretty much what the patch does.
I think it'll be very bad if the user has to type 'sf probe 0:15872' or 'sf probe 15872' since that's a programming detail rather than saying bank 2, gpio 30 (which I assume is what IMX_GPIO_NR means).
Agreed.
On Mon, Aug 04, 2014 at 05:19:28PM +0300, Nikita Kiryanov wrote:
On 04/08/14 17:02, Tom Rini wrote:
On Mon, Aug 04, 2014 at 04:45:57PM +0300, Nikita Kiryanov wrote:
On 04/08/14 16:10, Marek Vasut wrote:
On Monday, August 04, 2014 at 02:48:54 PM, Nikita Kiryanov wrote:
Hi Marek,
On 03/08/14 16:46, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:33 AM, Nikita Kiryanov wrote: >MXC SPI driver has a feature whereas a GPIO line can be used as a CS >signal. This is set up by joining the CS and GPIO values into a single >value using (cs | gpio << 8), and passing it off as a CS value. This >breaks the sf probe command, because it is no longer possible to invoke >it as sf probe <cs>. Instead, the user must use sf probe <cs | gpio << >8>. > >Fix this by introducing a new board function: board_spi_cs_gpio(). >When called, board_spi_cs_gpio() will return the gpio number for the >cs value it is given. > >Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com >Cc: Eric Nelson eric.nelson@boundarydevices.com >Cc: Eric Benard eric@eukrea.com >Cc: Fabio Estevam fabio.estevam@freescale.com >Cc: Tim Harvey tharvey@gateworks.com >Cc: Stefano Babic sbabic@denx.de >Cc: Tom Rini trini@ti.com >Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Just curious, but is this fixing generic SF code or MXC SPI driver ? I'd think the later, but it's not obvious from neither the description nor the subject. I don't quite understand the problem that you're trying to fix either, what happened, did the user command interface change ?
The U-Boot shell command "sf probe" can accept a chip select value, but if the SPI device on the other end requires an active chip-select over multiple transactions (achieved in the MXC SPI driver using a GPIO), simply typing something like "sf probe 0" will not work.
Why not ?
This is because whatever the user passes as chip select is propagated to the driver, and the driver expects this value to have GPIO information. So for example, if IMX_GPIO_NR(2, 30) is used to force active chip select 0, then instead of "sf probe 0" the user will have to type "sf probe 15872".
You mean sf probe 0:15872 , right ?
It's the same thing: sf probe [[bus:]cs] [hz] [mode]
The point is that cs 0 has to be represented as "15872", instead of "0".
Eeep. That seems very likely to be gotten incorrect by users.
Can we do something like: mxc_spi.c: __weak int board_map_spi_cs_value(int desired_cs) { return -EINVAL; }
fooboard.c: board_map_spi_cs_value(int desired_cs) { if (desired_cs == 0) return IMX_GPIO_NR(2, 30); else return -EINVAL; }
That's pretty much what the patch does.
I think it'll be very bad if the user has to type 'sf probe 0:15872' or 'sf probe 15872' since that's a programming detail rather than saying bank 2, gpio 30 (which I assume is what IMX_GPIO_NR means).
Agreed.
OK, it's just not clear from the commit messages then that 'sf probe 0' is still the correct thing to do for the boards and that behind the scenes we correct things to '15872'
Add support for M25PE16 and M25PX16
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- drivers/mtd/spi/sf_params.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index ac886fd..3a4beb0 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -68,6 +68,8 @@ const struct spi_flash_params spi_flash_params_table[] = { {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0}, {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0}, {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0}, + {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0, 0}, + {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0}, {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0}, {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0}, {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
On Sunday, August 03, 2014 at 09:34:34 AM, Nikita Kiryanov wrote:
Add support for M25PE16 and M25PX16
Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
Acked-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Dmitry Lifshitz lifshitz@compulab.co.il Cc: Tom Rini trini@ti.com Acked-by: Igor Grinberg grinberg@compulab.co.il Acked-by: Dmitry Lifshitz lifshitz@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/common/eeprom.c | 10 +++++++++- include/configs/cm_t335.h | 1 + include/configs/cm_t35.h | 1 + include/configs/cm_t54.h | 1 + 4 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index 20fe3e1..b5c1c2a 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -31,8 +31,16 @@ static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
static int cl_eeprom_read(uint offset, uchar *buf, int len) { - return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, + int res; + unsigned int current_i2c_bus = i2c_get_bus_num(); + + i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); + res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); + + i2c_set_bus_num(current_i2c_bus); + + return res; }
static int cl_eeprom_setup_layout(void) diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index a3e6452..767ef3a 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -107,6 +107,7 @@ /* I2C Configuration */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0
/* SPL */ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index d8d71a9..b5702e3 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -136,6 +136,7 @@ #define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 #define CONFIG_I2C_MULTI_BUS
/* diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index db04095..aa97823 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -27,6 +27,7 @@ #define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0
/* Enable SD/MMC CD and WP GPIOs */ #define OMAP_HSMMC_USE_GPIO
On Sunday, August 03, 2014 at 09:34:35 AM, Nikita Kiryanov wrote:
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Dmitry Lifshitz lifshitz@compulab.co.il Cc: Tom Rini trini@ti.com Acked-by: Igor Grinberg grinberg@compulab.co.il Acked-by: Dmitry Lifshitz lifshitz@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
board/compulab/common/eeprom.c | 10 +++++++++- include/configs/cm_t335.h | 1 + include/configs/cm_t35.h | 1 + include/configs/cm_t54.h | 1 + 4 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index 20fe3e1..b5c1c2a 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -31,8 +31,16 @@ static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
static int cl_eeprom_read(uint offset, uchar *buf, int len) {
- return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
- int res;
- unsigned int current_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
Please handle the return value of this function too. [...] BR,MV
On 03/08/14 16:48, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:35 AM, Nikita Kiryanov wrote:
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Dmitry Lifshitz lifshitz@compulab.co.il Cc: Tom Rini trini@ti.com Acked-by: Igor Grinberg grinberg@compulab.co.il Acked-by: Dmitry Lifshitz lifshitz@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
board/compulab/common/eeprom.c | 10 +++++++++- include/configs/cm_t335.h | 1 + include/configs/cm_t35.h | 1 + include/configs/cm_t54.h | 1 + 4 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index 20fe3e1..b5c1c2a 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -31,8 +31,16 @@ static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
static int cl_eeprom_read(uint offset, uchar *buf, int len) {
- return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
- int res;
- unsigned int current_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
Please handle the return value of this function too.
Will do..
[...] BR,MV
Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata.
Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- drivers/block/dwc_ahsata.c | 17 +++++++++++++++++ include/sata.h | 1 + 2 files changed, 18 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index 15d65d7..e122ed9 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -864,6 +864,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, return blkcnt; }
+int sata_port_status(int dev, int port) +{ + struct sata_port_regs *port_mmio; + struct ahci_probe_ent *probe_ent = NULL; + + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) + return -1; + + if (sata_dev_desc[dev].priv == NULL) + return -1; + + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio; + + return readl(&(port_mmio->ssts)) && SATA_PORT_SSTS_DET_MASK; +} + /* * SATA interface between low level driver and command layer */ diff --git a/include/sata.h b/include/sata.h index c95dc56..38f4b4a 100644 --- a/include/sata.h +++ b/include/sata.h @@ -9,6 +9,7 @@ ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
int sata_initialize(void); int __sata_initialize(void); +int sata_port_status(int dev, int port);
extern block_dev_desc_t sata_dev_desc[];
On Sunday, August 03, 2014 at 09:34:36 AM, Nikita Kiryanov wrote:
Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata.
Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
drivers/block/dwc_ahsata.c | 17 +++++++++++++++++ include/sata.h | 1 + 2 files changed, 18 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index 15d65d7..e122ed9 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -864,6 +864,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, return blkcnt; }
+int sata_port_status(int dev, int port) +{
- struct sata_port_regs *port_mmio;
- struct ahci_probe_ent *probe_ent = NULL;
- if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
return -1;
Please lets use values from errno.h here , let's set a good example and just do that please. [...] Best regards, Marek Vasut
On 03/08/14 16:49, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:36 AM, Nikita Kiryanov wrote:
Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata.
Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
drivers/block/dwc_ahsata.c | 17 +++++++++++++++++ include/sata.h | 1 + 2 files changed, 18 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index 15d65d7..e122ed9 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -864,6 +864,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, return blkcnt; }
+int sata_port_status(int dev, int port) +{
- struct sata_port_regs *port_mmio;
- struct ahci_probe_ent *probe_ent = NULL;
- if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
return -1;Please lets use values from errno.h here , let's set a good example and just do that please.
Will do...
[...] Best regards, Marek Vasut
On Monday, August 04, 2014 at 02:49:45 PM, Nikita Kiryanov wrote:
On 03/08/14 16:49, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:36 AM, Nikita Kiryanov wrote:
Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata.
Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
drivers/block/dwc_ahsata.c | 17 +++++++++++++++++ include/sata.h | 1 + 2 files changed, 18 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index 15d65d7..e122ed9 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -864,6 +864,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, return blkcnt;
}
+int sata_port_status(int dev, int port) +{
- struct sata_port_regs *port_mmio;
- struct ahci_probe_ent *probe_ent = NULL;
- if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
return -1;Please lets use values from errno.h here , let's set a good example and just do that please.
Will do...
Thanks!
Best regards, Marek Vasut
Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types.
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- arch/arm/include/asm/imx-common/mxc_i2c.h | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h index 47a9edc..182c2f3 100644 --- a/arch/arm/include/asm/imx-common/mxc_i2c.h +++ b/arch/arm/include/asm/imx-common/mxc_i2c.h @@ -19,6 +19,39 @@ struct i2c_pads_info { struct i2c_pin_ctrl sda; };
+#if defined(CONFIG_MX6QDL) +#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \ + struct i2c_pads_info mx6q_##name = { \ + .scl = { \ + .i2c_mode = MX6Q_##scl_i2c, \ + .gpio_mode = MX6Q_##scl_gpio, \ + .gp = scl_gp, \ + }, \ + .sda = { \ + .i2c_mode = MX6Q_##sda_i2c, \ + .gpio_mode = MX6Q_##sda_gpio, \ + .gp = sda_gp, \ + } \ + }; \ + struct i2c_pads_info mx6s_##name = { \ + .scl = { \ + .i2c_mode = MX6DL_##scl_i2c, \ + .gpio_mode = MX6DL_##scl_gpio, \ + .gp = scl_gp, \ + }, \ + .sda = { \ + .i2c_mode = MX6DL_##sda_i2c, \ + .gpio_mode = MX6DL_##sda_gpio, \ + .gp = sda_gp, \ + } \ + }; + + +#define I2C_PADS_INFO(name) \ + (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \ + &mx6q_##name : &mx6s_##name +#endif + void setup_i2c(unsigned i2c_index, int speed, int slave_addr, struct i2c_pads_info *p); void bus_i2c_init(void *base, int speed, int slave_addr,
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types.
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/include/asm/imx-common/mxc_i2c.h | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h index 47a9edc..182c2f3 100644 --- a/arch/arm/include/asm/imx-common/mxc_i2c.h +++ b/arch/arm/include/asm/imx-common/mxc_i2c.h @@ -19,6 +19,39 @@ struct i2c_pads_info { struct i2c_pin_ctrl sda; };
+#if defined(CONFIG_MX6QDL) +#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
struct i2c_pads_info mx6q_##name = { \.scl = { \.i2c_mode = MX6Q_##scl_i2c, \.gpio_mode = MX6Q_##scl_gpio, \.gp = scl_gp, \}, \.sda = { \.i2c_mode = MX6Q_##sda_i2c, \.gpio_mode = MX6Q_##sda_gpio, \.gp = sda_gp, \} \}; \struct i2c_pads_info mx6s_##name = { \.scl = { \.i2c_mode = MX6DL_##scl_i2c, \.gpio_mode = MX6DL_##scl_gpio, \.gp = scl_gp, \}, \.sda = { \.i2c_mode = MX6DL_##sda_i2c, \.gpio_mode = MX6DL_##sda_gpio, \.gp = sda_gp, \} \};+#define I2C_PADS_INFO(name) \
(is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \&mx6q_##name : &mx6s_##name+#endif
void setup_i2c(unsigned i2c_index, int speed, int slave_addr, struct i2c_pads_info *p); void bus_i2c_init(void *base, int speed, int slave_addr, -- 1.9.1
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi Nikita,
Very nice cleanup!
Acked-by: Tim Harvey tharvey@gateworks.com
Tim
No functional changes.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- arch/arm/cpu/armv7/mx6/ddr.c | 272 +++++++++++++++++++++---------------------- 1 file changed, 134 insertions(+), 138 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 0434211..af91314 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width, */ #define MR(val, ba, cmd, cs1) \ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) -void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, - const struct mx6_mmdc_calibration *c, - const struct mx6_ddr3_cfg *m) +void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, + const struct mx6_mmdc_calibration *calib, + const struct mx6_ddr3_cfg *ddr3_cfg) { volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1; - u32 reg; + u32 val; u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; - u16 CS0_END; + u16 cs0_end; u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ int clkper; /* clock period in picoseconds */ int clock; /* clock freq in mHz */ @@ -214,13 +214,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, clock = 400; tcwl = 3; } - clkper = (1000*1000)/clock; /* ps */ + clkper = (1000 * 1000) / clock; /* pico seconds */ todtlon = tcwl; taxpd = tcwl; tanpd = tcwl; - tcwl = tcwl;
- switch (m->density) { + switch (ddr3_cfg->density) { case 1: /* 1Gb per chip */ trfc = DIV_ROUND_UP(110000, clkper) - 1; txs = DIV_ROUND_UP(120000, clkper) - 1; @@ -239,80 +238,84 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, break; default: /* invalid density */ - printf("invalid chip density\n"); + puts("invalid chip density\n"); hang(); break; } txpr = txs;
- switch (m->mem_speed) { + switch (ddr3_cfg->mem_speed) { case 800: - txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; - tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; - if (m->pagesz == 1) { + txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1; + if (ddr3_cfg->pagesz == 1) { tfaw = DIV_ROUND_UP(40000, clkper) - 1; - trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1; } else { tfaw = DIV_ROUND_UP(50000, clkper) - 1; - trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1; } break; case 1066: - txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; - tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; - if (m->pagesz == 1) { + txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1; + if (ddr3_cfg->pagesz == 1) { tfaw = DIV_ROUND_UP(37500, clkper) - 1; - trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1; } else { tfaw = DIV_ROUND_UP(50000, clkper) - 1; - trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1; } break; case 1333: - txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; - tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; - if (m->pagesz == 1) { + txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1; + if (ddr3_cfg->pagesz == 1) { tfaw = DIV_ROUND_UP(30000, clkper) - 1; - trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1; } else { tfaw = DIV_ROUND_UP(45000, clkper) - 1; - trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1; } break; case 1600: - txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; - tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1; - if (m->pagesz == 1) { + txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1; + if (ddr3_cfg->pagesz == 1) { tfaw = DIV_ROUND_UP(30000, clkper) - 1; - trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1; } else { tfaw = DIV_ROUND_UP(40000, clkper) - 1; - trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1; } break; default: - printf("invalid memory speed\n"); + puts("invalid memory speed\n"); hang(); break; } - txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1; - tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3; - tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper); - tcksrx = tcksre; + txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1; + tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper); taonpd = DIV_ROUND_UP(2000, clkper) - 1; + tcksrx = tcksre; taofpd = taonpd; - trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1; + twr = DIV_ROUND_UP(15000, clkper) - 1; + tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1; + trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1; + tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1; + tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3; + trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1; + twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1; trcd = trp; - trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1; - tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1; - twr = DIV_ROUND_UP(15000, clkper) - 1; - tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1; - twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1; trtp = twtr; - CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127; - debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density); + cs0_end = (4 * sysinfo->cs_density <= 120) ? + 4 * sysinfo->cs_density + 7 : + 127; + + debug("density:%d Gb (%d Gb per chip)\n", + sysinfo->cs_density, ddr3_cfg->density); debug("clock: %dMHz (%d ps)\n", clock, clkper); - debug("memspd:%d\n", m->mem_speed); + debug("memspd:%d\n", ddr3_cfg->mem_speed); debug("tcke=%d\n", tcke); debug("tcksrx=%d\n", tcksrx); debug("tcksre=%d\n", tcksre); @@ -339,11 +342,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, debug("twtr=%d\n", twtr); debug("trrd=%d\n", trrd); debug("txpr=%d\n", txpr); - debug("CS0_END=%d\n", CS0_END); - debug("ncs=%d\n", i->ncs); - debug("Rtt_wr=%d\n", i->rtt_wr); - debug("Rtt_nom=%d\n", i->rtt_nom); - debug("SRT=%d\n", m->SRT); + debug("cs0_end=%d\n", cs0_end); + debug("ncs=%d\n", sysinfo->ncs); + debug("Rtt_wr=%d\n", sysinfo->rtt_wr); + debug("Rtt_nom=%d\n", sysinfo->rtt_nom); + debug("SRT=%d\n", ddr3_cfg->SRT); debug("tcl=%d\n", tcl); debug("twr=%d\n", twr);
@@ -353,137 +356,130 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, * see: * appnote, ddr3 spreadsheet */ - mmdc0->mpwldectrl0 = c->p0_mpwldectrl0; - mmdc0->mpwldectrl1 = c->p0_mpwldectrl1; - mmdc0->mpdgctrl0 = c->p0_mpdgctrl0; - mmdc0->mpdgctrl1 = c->p0_mpdgctrl1; - mmdc0->mprddlctl = c->p0_mprddlctl; - mmdc0->mpwrdlctl = c->p0_mpwrdlctl; - if (i->dsize > 1) { - mmdc1->mpwldectrl0 = c->p1_mpwldectrl0; - mmdc1->mpwldectrl1 = c->p1_mpwldectrl1; - mmdc1->mpdgctrl0 = c->p1_mpdgctrl0; - mmdc1->mpdgctrl1 = c->p1_mpdgctrl1; - mmdc1->mprddlctl = c->p1_mprddlctl; - mmdc1->mpwrdlctl = c->p1_mpwrdlctl; + mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; + mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1; + mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0; + mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; + mmdc0->mprddlctl = calib->p0_mprddlctl; + mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; + if (sysinfo->dsize > 1) { + mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0; + mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1; + mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0; + mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1; + mmdc1->mprddlctl = calib->p1_mprddlctl; + mmdc1->mpwrdlctl = calib->p1_mpwrdlctl; }
/* Read data DQ Byte0-3 delay */ - mmdc0->mprddqby0dl = (u32)0x33333333; - mmdc0->mprddqby1dl = (u32)0x33333333; - if (i->dsize > 0) { - mmdc0->mprddqby2dl = (u32)0x33333333; - mmdc0->mprddqby3dl = (u32)0x33333333; + mmdc0->mprddqby0dl = 0x33333333; + mmdc0->mprddqby1dl = 0x33333333; + if (sysinfo->dsize > 0) { + mmdc0->mprddqby2dl = 0x33333333; + mmdc0->mprddqby3dl = 0x33333333; } - if (i->dsize > 1) { - mmdc1->mprddqby0dl = (u32)0x33333333; - mmdc1->mprddqby1dl = (u32)0x33333333; - mmdc1->mprddqby2dl = (u32)0x33333333; - mmdc1->mprddqby3dl = (u32)0x33333333; + + if (sysinfo->dsize > 1) { + mmdc1->mprddqby0dl = 0x33333333; + mmdc1->mprddqby1dl = 0x33333333; + mmdc1->mprddqby2dl = 0x33333333; + mmdc1->mprddqby3dl = 0x33333333; }
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ - reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227; - mmdc0->mpodtctrl = reg; - if (i->dsize > 1) - mmdc1->mpodtctrl = reg; + val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227; + mmdc0->mpodtctrl = val; + if (sysinfo->dsize > 1) + mmdc1->mpodtctrl = val;
/* complete calibration */ - reg = (1 << 11); /* Force measurement on delay-lines */ - mmdc0->mpmur0 = reg; - if (i->dsize > 1) - mmdc1->mpmur0 = reg; + val = (1 << 11); /* Force measurement on delay-lines */ + mmdc0->mpmur0 = val; + if (sysinfo->dsize > 1) + mmdc1->mpmur0 = val;
/* Step 1: configuration request */ mmdc0->mdscr = (u32)(1 << 15); /* config request */
/* Step 2: Timing configuration */ - reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) | - (tfaw << 4) | tcl; - mmdc0->mdcfg0 = reg; - reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) | - (1 << 15) | /* trpa */ - (twr << 9) | (tmrd << 5) | tcwl; - mmdc0->mdcfg1 = reg; - reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; - mmdc0->mdcfg2 = reg; - reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) | - (todtlon << 12) | (todt_idle_off << 4); - mmdc0->mdotc = reg; - mmdc0->mdasp = CS0_END; /* CS addressing */ + mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) | + (txpdll << 9) | (tfaw << 4) | tcl; + mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) | + (tras << 16) | (1 << 15) /* trpa */ | + (twr << 9) | (tmrd << 5) | tcwl; + mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; + mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | + (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4); + mmdc0->mdasp = cs0_end; /* CS addressing */
/* Step 3: Configure DDR type */ - reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) | - (i->mif3_mode << 9) | (i->ralat << 6); - mmdc0->mdmisc = reg; + mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) | + (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) | + (sysinfo->ralat << 6);
/* Step 4: Configure delay while leaving reset */ - reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0); - mmdc0->mdor = reg; + mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) | + (sysinfo->rst_to_cke << 0);
/* Step 5: Configure DDR physical parameters (density and burst len) */ - reg = (m->rowaddr - 11) << 24 | /* ROW */ - (m->coladdr - 9) << 20 | /* COL */ - (1 << 19) | /* Burst Length = 8 for DDR3 */ - (i->dsize << 16); /* DDR data bus size */ - mmdc0->mdctl = reg; + mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */ + (ddr3_cfg->coladdr - 9) << 20 | /* COL */ + (1 << 19) | /* Burst Length = 8 for DDR3 */ + (sysinfo->dsize << 16); /* DDR data bus size */
/* Step 6: Perform ZQ calibration */ - reg = (u32)0xa1390001; /* one-time HW ZQ calib */ - mmdc0->mpzqhwctrl = reg; - if (i->dsize > 1) - mmdc1->mpzqhwctrl = reg; + val = 0xa1390001; /* one-time HW ZQ calib */ + mmdc0->mpzqhwctrl = val; + if (sysinfo->dsize > 1) + mmdc1->mpzqhwctrl = val;
/* Step 7: Enable MMDC with desired chip select */ - reg = mmdc0->mdctl | - (1 << 31) | /* SDE_0 for CS0 */ - ((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ - mmdc0->mdctl = reg; + mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ + ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
/* Step 8: Write Mode Registers to Init DDR3 devices */ - for (cs = 0; cs < i->ncs; cs++) { + for (cs = 0; cs < sysinfo->ncs; cs++) { /* MR2 */ - reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 | + val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 | ((tcwl - 3) & 3) << 3; - mmdc0->mdscr = (u32)MR(reg, 2, 3, cs); + mmdc0->mdscr = MR(val, 2, 3, cs); /* MR3 */ - mmdc0->mdscr = (u32)MR(0, 3, 3, cs); + mmdc0->mdscr = MR(0, 3, 3, cs); /* MR1 */ - reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 | - ((i->rtt_nom & 2) ? 1 : 0) << 6; - mmdc0->mdscr = (u32)MR(reg, 1, 3, cs); - reg = ((tcl - 1) << 4) | /* CAS */ + val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 | + ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6; + mmdc0->mdscr = MR(val, 1, 3, cs); + /* MR0 */ + val = ((tcl - 1) << 4) | /* CAS */ (1 << 8) | /* DLL Reset */ ((twr - 3) << 9); /* Write Recovery */ - /* MR0 */ - mmdc0->mdscr = (u32)MR(reg, 0, 3, cs); + mmdc0->mdscr = MR(val, 0, 3, cs); /* ZQ calibration */ - reg = (1 << 10); - mmdc0->mdscr = (u32)MR(reg, 0, 4, cs); + val = (1 << 10); + mmdc0->mdscr = MR(val, 0, 4, cs); }
/* Step 10: Power down control and self-refresh */ - reg = (tcke & 0x7) << 16 | - 5 << 12 | /* PWDT_1: 256 cycles */ - 5 << 8 | /* PWDT_0: 256 cycles */ - 1 << 6 | /* BOTH_CS_PD */ - (tcksrx & 0x7) << 3 | - (tcksre & 0x7); - mmdc0->mdpdc = reg; - mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */ + mmdc0->mdpdc = (tcke & 0x7) << 16 | + 5 << 12 | /* PWDT_1: 256 cycles */ + 5 << 8 | /* PWDT_0: 256 cycles */ + 1 << 6 | /* BOTH_CS_PD */ + (tcksrx & 0x7) << 3 | + (tcksre & 0x7); + mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ - mmdc0->mpzqhwctrl = (u32)0xa1390003; - if (i->dsize > 1) - mmdc1->mpzqhwctrl = (u32)0xa1390003; + val = 0xa1390003; + mmdc0->mpzqhwctrl = val; + if (sysinfo->dsize > 1) + mmdc1->mpzqhwctrl = val;
/* Step 12: Configure and activate periodic refresh */ - reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */ - (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ - mmdc0->mdref = reg; + mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ + (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
/* Step 13: Deassert config request - init complete */ - mmdc0->mdscr = (u32)0x00000000; + mmdc0->mdscr = 0x00000000;
/* wait for auto-ZQ calibration to complete */ mdelay(1);
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
No functional changes.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 272 +++++++++++++++++++++---------------------- 1 file changed, 134 insertions(+), 138 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 0434211..af91314 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width, */ #define MR(val, ba, cmd, cs1) \ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) -void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
const struct mx6_mmdc_calibration *c,const struct mx6_ddr3_cfg *m)+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,const struct mx6_ddr3_cfg *ddr3_cfg){ volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1;
u32 reg;
u32 val; u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
u16 CS0_END;
u16 cs0_end; u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ int clkper; /* clock period in picoseconds */ int clock; /* clock freq in mHz */@@ -214,13 +214,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, clock = 400; tcwl = 3; }
clkper = (1000*1000)/clock; /* ps */
clkper = (1000 * 1000) / clock; /* pico seconds */ todtlon = tcwl; taxpd = tcwl; tanpd = tcwl;
tcwl = tcwl;switch (m->density) {
switch (ddr3_cfg->density) { case 1: /* 1Gb per chip */ trfc = DIV_ROUND_UP(110000, clkper) - 1; txs = DIV_ROUND_UP(120000, clkper) - 1;@@ -239,80 +238,84 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, break; default: /* invalid density */
printf("invalid chip density\n");
puts("invalid chip density\n"); hang(); break; } txpr = txs;
switch (m->mem_speed) {
switch (ddr3_cfg->mem_speed) { case 800:
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;if (m->pagesz == 1) {
txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;if (ddr3_cfg->pagesz == 1) { tfaw = DIV_ROUND_UP(40000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1; } else { tfaw = DIV_ROUND_UP(50000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1; } break; case 1066:
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;if (m->pagesz == 1) {
txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;if (ddr3_cfg->pagesz == 1) { tfaw = DIV_ROUND_UP(37500, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1; } else { tfaw = DIV_ROUND_UP(50000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1; } break; case 1333:
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;if (m->pagesz == 1) {
txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;if (ddr3_cfg->pagesz == 1) { tfaw = DIV_ROUND_UP(30000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1; } else { tfaw = DIV_ROUND_UP(45000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1; } break; case 1600:
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;if (m->pagesz == 1) {
txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;if (ddr3_cfg->pagesz == 1) { tfaw = DIV_ROUND_UP(30000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1; } else { tfaw = DIV_ROUND_UP(40000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1; } break; default:
printf("invalid memory speed\n");
puts("invalid memory speed\n"); hang(); break; }
txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);tcksrx = tcksre;
txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper); taonpd = DIV_ROUND_UP(2000, clkper) - 1;tcksrx = tcksre; taofpd = taonpd;
trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
twr = DIV_ROUND_UP(15000, clkper) - 1;tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1; trcd = trp;
trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;twr = DIV_ROUND_UP(15000, clkper) - 1;tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1; trtp = twtr;CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
cs0_end = (4 * sysinfo->cs_density <= 120) ?4 * sysinfo->cs_density + 7 :127;debug("density:%d Gb (%d Gb per chip)\n",sysinfo->cs_density, ddr3_cfg->density); debug("clock: %dMHz (%d ps)\n", clock, clkper);
debug("memspd:%d\n", m->mem_speed);
debug("memspd:%d\n", ddr3_cfg->mem_speed); debug("tcke=%d\n", tcke); debug("tcksrx=%d\n", tcksrx); debug("tcksre=%d\n", tcksre);@@ -339,11 +342,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, debug("twtr=%d\n", twtr); debug("trrd=%d\n", trrd); debug("txpr=%d\n", txpr);
debug("CS0_END=%d\n", CS0_END);debug("ncs=%d\n", i->ncs);debug("Rtt_wr=%d\n", i->rtt_wr);debug("Rtt_nom=%d\n", i->rtt_nom);debug("SRT=%d\n", m->SRT);
debug("cs0_end=%d\n", cs0_end);debug("ncs=%d\n", sysinfo->ncs);debug("Rtt_wr=%d\n", sysinfo->rtt_wr);debug("Rtt_nom=%d\n", sysinfo->rtt_nom);debug("SRT=%d\n", ddr3_cfg->SRT); debug("tcl=%d\n", tcl); debug("twr=%d\n", twr);@@ -353,137 +356,130 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, * see: * appnote, ddr3 spreadsheet */
mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;mmdc0->mprddlctl = c->p0_mprddlctl;mmdc0->mpwrdlctl = c->p0_mpwrdlctl;if (i->dsize > 1) {mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;mmdc1->mprddlctl = c->p1_mprddlctl;mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;mmdc0->mprddlctl = calib->p0_mprddlctl;mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;if (sysinfo->dsize > 1) {mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;mmdc1->mprddlctl = calib->p1_mprddlctl;mmdc1->mpwrdlctl = calib->p1_mpwrdlctl; } /* Read data DQ Byte0-3 delay */
mmdc0->mprddqby0dl = (u32)0x33333333;mmdc0->mprddqby1dl = (u32)0x33333333;if (i->dsize > 0) {mmdc0->mprddqby2dl = (u32)0x33333333;mmdc0->mprddqby3dl = (u32)0x33333333;
mmdc0->mprddqby0dl = 0x33333333;mmdc0->mprddqby1dl = 0x33333333;if (sysinfo->dsize > 0) {mmdc0->mprddqby2dl = 0x33333333;mmdc0->mprddqby3dl = 0x33333333; }
if (i->dsize > 1) {mmdc1->mprddqby0dl = (u32)0x33333333;mmdc1->mprddqby1dl = (u32)0x33333333;mmdc1->mprddqby2dl = (u32)0x33333333;mmdc1->mprddqby3dl = (u32)0x33333333;
if (sysinfo->dsize > 1) {mmdc1->mprddqby0dl = 0x33333333;mmdc1->mprddqby1dl = 0x33333333;mmdc1->mprddqby2dl = 0x33333333;mmdc1->mprddqby3dl = 0x33333333; } /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;mmdc0->mpodtctrl = reg;if (i->dsize > 1)mmdc1->mpodtctrl = reg;
val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;mmdc0->mpodtctrl = val;if (sysinfo->dsize > 1)mmdc1->mpodtctrl = val; /* complete calibration */
reg = (1 << 11); /* Force measurement on delay-lines */mmdc0->mpmur0 = reg;if (i->dsize > 1)mmdc1->mpmur0 = reg;
val = (1 << 11); /* Force measurement on delay-lines */mmdc0->mpmur0 = val;if (sysinfo->dsize > 1)mmdc1->mpmur0 = val; /* Step 1: configuration request */ mmdc0->mdscr = (u32)(1 << 15); /* config request */ /* Step 2: Timing configuration */
reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |(tfaw << 4) | tcl;mmdc0->mdcfg0 = reg;reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |(1 << 15) | /* trpa */(twr << 9) | (tmrd << 5) | tcwl;mmdc0->mdcfg1 = reg;reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;mmdc0->mdcfg2 = reg;reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |(todtlon << 12) | (todt_idle_off << 4);mmdc0->mdotc = reg;mmdc0->mdasp = CS0_END; /* CS addressing */
mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |(txpdll << 9) | (tfaw << 4) | tcl;mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |(tras << 16) | (1 << 15) /* trpa */ |(twr << 9) | (tmrd << 5) | tcwl;mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |(taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);mmdc0->mdasp = cs0_end; /* CS addressing */ /* Step 3: Configure DDR type */
reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |(i->mif3_mode << 9) | (i->ralat << 6);mmdc0->mdmisc = reg;
mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |(sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |(sysinfo->ralat << 6); /* Step 4: Configure delay while leaving reset */
reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);mmdc0->mdor = reg;
mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |(sysinfo->rst_to_cke << 0); /* Step 5: Configure DDR physical parameters (density and burst len) */
reg = (m->rowaddr - 11) << 24 | /* ROW */(m->coladdr - 9) << 20 | /* COL */(1 << 19) | /* Burst Length = 8 for DDR3 */(i->dsize << 16); /* DDR data bus size */mmdc0->mdctl = reg;
mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */(ddr3_cfg->coladdr - 9) << 20 | /* COL */(1 << 19) | /* Burst Length = 8 for DDR3 */(sysinfo->dsize << 16); /* DDR data bus size */ /* Step 6: Perform ZQ calibration */
reg = (u32)0xa1390001; /* one-time HW ZQ calib */mmdc0->mpzqhwctrl = reg;if (i->dsize > 1)mmdc1->mpzqhwctrl = reg;
val = 0xa1390001; /* one-time HW ZQ calib */mmdc0->mpzqhwctrl = val;if (sysinfo->dsize > 1)mmdc1->mpzqhwctrl = val; /* Step 7: Enable MMDC with desired chip select */
reg = mmdc0->mdctl |(1 << 31) | /* SDE_0 for CS0 */((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */mmdc0->mdctl = reg;
mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ /* Step 8: Write Mode Registers to Init DDR3 devices */
for (cs = 0; cs < i->ncs; cs++) {
for (cs = 0; cs < sysinfo->ncs; cs++) { /* MR2 */
reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 | ((tcwl - 3) & 3) << 3;
mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
mmdc0->mdscr = MR(val, 2, 3, cs); /* MR3 */
mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
mmdc0->mdscr = MR(0, 3, 3, cs); /* MR1 */
reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |((i->rtt_nom & 2) ? 1 : 0) << 6;mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);reg = ((tcl - 1) << 4) | /* CAS */
val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;mmdc0->mdscr = MR(val, 1, 3, cs);/* MR0 */val = ((tcl - 1) << 4) | /* CAS */ (1 << 8) | /* DLL Reset */ ((twr - 3) << 9); /* Write Recovery */
/* MR0 */mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
mmdc0->mdscr = MR(val, 0, 3, cs); /* ZQ calibration */
reg = (1 << 10);mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
val = (1 << 10);mmdc0->mdscr = MR(val, 0, 4, cs); } /* Step 10: Power down control and self-refresh */
reg = (tcke & 0x7) << 16 |5 << 12 | /* PWDT_1: 256 cycles */5 << 8 | /* PWDT_0: 256 cycles */1 << 6 | /* BOTH_CS_PD */(tcksrx & 0x7) << 3 |(tcksre & 0x7);mmdc0->mdpdc = reg;mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
mmdc0->mdpdc = (tcke & 0x7) << 16 |5 << 12 | /* PWDT_1: 256 cycles */5 << 8 | /* PWDT_0: 256 cycles */1 << 6 | /* BOTH_CS_PD */(tcksrx & 0x7) << 3 |(tcksre & 0x7);mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
mmdc0->mpzqhwctrl = (u32)0xa1390003;if (i->dsize > 1)mmdc1->mpzqhwctrl = (u32)0xa1390003;
val = 0xa1390003;mmdc0->mpzqhwctrl = val;if (sysinfo->dsize > 1)mmdc1->mpzqhwctrl = val; /* Step 12: Configure and activate periodic refresh */
reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */(7 << 11); /* REFR: Refresh Rate - 8 refreshes */mmdc0->mdref = reg;
mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */(7 << 11); /* REFR: Refresh Rate - 8 refreshes */ /* Step 13: Deassert config request - init complete */
mmdc0->mdscr = (u32)0x00000000;
mmdc0->mdscr = 0x00000000; /* wait for auto-ZQ calibration to complete */ mdelay(1);-- 1.9.1
Acked-by: Tim Harvey tharvey@gateworks.com
Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- arch/arm/cpu/armv7/mx6/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index af91314..70ce38f 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7); - mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */ + mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ val = 0xa1390003;
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index af91314..70ce38f 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7);
mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ val = 0xa1390003;-- 1.9.1
Nikita,
This makes sense per the reference manual, but does not agree with the i.Mx6DQSDL DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917). I'm curious if you found any other explanation of this or anything else that makes you feel the spreadsheet is in error (vs the RM's). I've asked our Freescale FAE to clarify.
Regards,
Tim
Hi Tim,
On 04/08/14 08:43, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index af91314..70ce38f 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7);
mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ val = 0xa1390003;-- 1.9.1
Nikita,
This makes sense per the reference manual, but does not agree with the i.Mx6DQSDL DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917). I'm curious if you found any other explanation of this or anything else that makes you feel the spreadsheet is in error (vs the RM's).
Nothing specific, I just don't like to use undocumented features. It's probably benign, but still...
I've asked our Freescale FAE to clarify.
Looking forward to that...
Regards, Nikita Kiryanov
On Mon, Aug 4, 2014 at 5:49 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Hi Tim,
On 04/08/14 08:43, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index af91314..70ce38f 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7);
mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms*/ val = 0xa1390003; -- 1.9.1
Nikita,
This makes sense per the reference manual, but does not agree with the i.Mx6DQSDL DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917). I'm curious if you found any other explanation of this or anything else that makes you feel the spreadsheet is in error (vs the RM's).
Nothing specific, I just don't like to use undocumented features. It's probably benign, but still...
I've asked our Freescale FAE to clarify.
Looking forward to that...
Regards, Nikita Kiryanov
Nikita,
Freescale confirmed its an error in their spreadsheet (https://community.freescale.com/docs/DOC-94917#comment-12921), so:
Acked-by: Tim Harvey tharvey@gateworks.com
Tim
Hi Tim, hi Nikita,
On 06/08/2014 10:18, Tim Harvey wrote:
I've asked our Freescale FAE to clarify.
Looking forward to that...
Regards, Nikita Kiryanov
Nikita,
Freescale confirmed its an error in their spreadsheet (https://community.freescale.com/docs/DOC-94917#comment-12921), so:
Acked-by: Tim Harvey tharvey@gateworks.com
Thanks both to have clarified this issue, patch is ready to be merged.
Best regards, Stefano Babic
According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd, and the DRAM for slow pd.
Configure MMDC for slow pd.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- arch/arm/cpu/armv7/mx6/ddr.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 70ce38f..c0fb749 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -463,6 +463,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mdpdc = (tcke & 0x7) << 16 | 5 << 12 | /* PWDT_1: 256 cycles */ 5 << 8 | /* PWDT_0: 256 cycles */ + 1 << 7 | /* SLOW_PD */ 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7);
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd, and the DRAM for slow pd.
Nikita,
I'm inclined to agree with you. A glance at some of the existing non-spl board config's show this same discrepancy which probably comes form an error in the IMX DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917).
I would at least add to the description the fact that the precharge pd is MR0 bit12 for DRAM and the current value of 0 indicates 'Slow exit (DLL off)'. I've asked our Freescale FAE for clarification to see if the spreadsheet is in error.
Regards,
Tim
Configure MMDC for slow pd.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 70ce38f..c0fb749 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -463,6 +463,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mdpdc = (tcke & 0x7) << 16 | 5 << 12 | /* PWDT_1: 256 cycles */ 5 << 8 | /* PWDT_0: 256 cycles */
1 << 7 | /* SLOW_PD */ 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7);-- 1.9.1
On 04/08/14 08:42, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd, and the DRAM for slow pd.
Nikita,
I'm inclined to agree with you. A glance at some of the existing non-spl board config's show this same discrepancy which probably comes form an error in the IMX DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917).
I would at least add to the description the fact that the precharge pd is MR0 bit12 for DRAM and the current value of 0 indicates 'Slow exit (DLL off)'. I've asked our Freescale FAE for clarification to see if the spreadsheet is in error.
OK, I'll add it once the FAE confirms the error.
Regards,
Tim
Current way of calculation CS0_END field for MMDCx_MDASP register is problematic because in most cases the user is forced to define cs_density in an unnatural way: as value - 2, instead of value.
This breaks the abstraction provided by struct mx6_ddr_sysinfo because the user is forced to be aware of the way the calculation is performed.
Refactor the calculation.
Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- arch/arm/cpu/armv7/mx6/ddr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index c0fb749..d3891dc 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -308,9 +308,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1; trcd = trp; trtp = twtr; - cs0_end = (4 * sysinfo->cs_density <= 120) ? - 4 * sysinfo->cs_density + 7 : - 127; + cs0_end = 4 * sysinfo->cs_density - 1;
debug("density:%d Gb (%d Gb per chip)\n", sysinfo->cs_density, ddr3_cfg->density);
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- arch/arm/cpu/armv7/mx6/ddr.c | 1 - board/compulab/cm_fx6/Makefile | 12 ++ board/compulab/cm_fx6/cm_fx6.c | 108 ++++++++++ board/compulab/cm_fx6/common.c | 83 ++++++++ board/compulab/cm_fx6/common.h | 36 ++++ board/compulab/cm_fx6/imximage.cfg | 8 + board/compulab/cm_fx6/spl.c | 400 +++++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/cm_fx6.h | 227 +++++++++++++++++++++ 9 files changed, 876 insertions(+), 1 deletion(-) create mode 100644 board/compulab/cm_fx6/Makefile create mode 100644 board/compulab/cm_fx6/cm_fx6.c create mode 100644 board/compulab/cm_fx6/common.c create mode 100644 board/compulab/cm_fx6/common.h create mode 100644 board/compulab/cm_fx6/imximage.cfg create mode 100644 board/compulab/cm_fx6/spl.c create mode 100644 include/configs/cm_fx6.h
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index d3891dc..219263a 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -4,7 +4,6 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> #include <linux/types.h> #include <asm/arch/mx6-ddr.h> diff --git a/board/compulab/cm_fx6/Makefile b/board/compulab/cm_fx6/Makefile new file mode 100644 index 0000000..3e5c903 --- /dev/null +++ b/board/compulab/cm_fx6/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> +# +# Authors: Nikita Kiryanov nikita@compulab.co.il +# +# SPDX-License-Identifier: GPL-2.0+ +# +ifdef CONFIG_SPL_BUILD +obj-y = common.o spl.o +else +obj-y = common.o cm_fx6.o +endif diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c new file mode 100644 index 0000000..b55b99e --- /dev/null +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -0,0 +1,108 @@ +/* + * Board functions for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov nikita@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bis) +{ + int i; + + cm_fx6_set_usdhc_iomux(); + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]); + usdhc_cfg[i].max_bus_width = 4; + fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + enable_usdhc_clk(1, i); + } + + return 0; +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + return 0; +} + +int checkboard(void) +{ + puts("Board: CM-FX6\n"); + return 0; +} + +static ulong bank1_size; +static ulong bank2_size; + +#define MMDC1_MDCTL 0x21B0000 +static int probe_mmdc_config(void) +{ + u32 val = readl(0x21B0000); + switch (val) { + case 0x83180000: /* DDR_16BIT_256MB */ + gd->ram_size = 0x10000000; + bank1_size = 0x10000000; + bank2_size = 0; + break; + case 0x83190000: /* DDR_32BIT_512MB */ + gd->ram_size = 0x20000000; + bank1_size = 0x20000000; + bank2_size = 0; + break; + case 0xC3190000: /* DDR_32BIT_1GB */ + gd->ram_size = 0x40000000; + bank1_size = 0x20000000; + bank2_size = 0x20000000; + break; + case 0x831A0000: /* DDR_64BIT_1GB */ + gd->ram_size = 0x40000000; + bank1_size = 0x40000000; + bank2_size = 0; + break; + case 0xC31A0000: /* DDR_64BIT_2GB */ + gd->ram_size = 0x80000000; + bank1_size = 0x40000000; + bank2_size = 0x40000000; + break; + case 0xC41A0000: /* DDR_64BIT_4GB */ + gd->ram_size = 0xEFF00000; + bank1_size = 0x70000000; + bank2_size = 0x7FF00000; + break; + default: + printf("!!!ERROR!!! Unsupported DRAM configuration: 0x%x\n", + val); + return -1; + } + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = bank1_size; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = bank2_size; +} + +int dram_init(void) +{ + return probe_mmdc_config(); +} + +u32 get_board_rev(void) +{ + return 100; +} diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c new file mode 100644 index 0000000..a2d9ca4 --- /dev/null +++ b/board/compulab/cm_fx6/common.c @@ -0,0 +1,83 @@ +/* + * Code used by both U-Boot and SPL for Compulab CM-FX6 + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov nikita@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FSL_ESDHC +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +void cm_fx6_set_usdhc_iomux(void) +{ + SETUP_IOMUX_PADS(usdhc_pads); +} + +/* CINS bit doesn't work, so always try to access the MMC card */ +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} +#endif + +#ifdef CONFIG_MXC_SPI +#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +static iomux_v3_cfg_t const ecspi_pads[] = { + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), +}; + +void cm_fx6_set_ecspi_iomux(void) +{ + SETUP_IOMUX_PADS(ecspi_pads); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1; +} +#endif diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h new file mode 100644 index 0000000..05eab34 --- /dev/null +++ b/board/compulab/cm_fx6/common.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov nikita@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/mx6-pins.h> +#include <asm/arch/clock.h> + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30) +#define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31) + +#if defined(CONFIG_FSL_ESDHC) +#include <fsl_esdhc.h> + +static __maybe_unused struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, +}; + +static __maybe_unused enum mxc_clock usdhc_clk[3] = { + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, +}; +#endif + +void cm_fx6_set_usdhc_iomux(void); +void cm_fx6_set_ecspi_iomux(void); diff --git a/board/compulab/cm_fx6/imximage.cfg b/board/compulab/cm_fx6/imximage.cfg new file mode 100644 index 0000000..8e7ec91 --- /dev/null +++ b/board/compulab/cm_fx6/imximage.cfg @@ -0,0 +1,8 @@ +# +# Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +IMAGE_VERSION 2 +BOOT_FROM sd diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c new file mode 100644 index 0000000..9f9e5f8 --- /dev/null +++ b/board/compulab/cm_fx6/spl.c @@ -0,0 +1,400 @@ +/* + * SPL specific code for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov nikita@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/iomux-v3.h> +#include <fsl_esdhc.h> +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum ddr_config { + DDR_16BIT_256MB, + DDR_32BIT_512MB, + DDR_32BIT_1GB, + DDR_64BIT_1GB, + DDR_64BIT_2GB, + DDR_64BIT_4GB, + DDR_UNKNOWN, +}; + +static void spl_mx6s_dram_setup_iomux(void) +{ + struct mx6sdl_iomux_ddr_regs ddr_iomux; + struct mx6sdl_iomux_grp_regs grp_iomux; + + ddr_iomux.dram_sdqs0 = 0x00000038; + ddr_iomux.dram_sdqs1 = 0x00000038; + ddr_iomux.dram_sdqs2 = 0x00000038; + ddr_iomux.dram_sdqs3 = 0x00000038; + ddr_iomux.dram_sdqs4 = 0x00000038; + ddr_iomux.dram_sdqs5 = 0x00000038; + ddr_iomux.dram_sdqs6 = 0x00000038; + ddr_iomux.dram_sdqs7 = 0x00000038; + ddr_iomux.dram_dqm0 = 0x00000038; + ddr_iomux.dram_dqm1 = 0x00000038; + ddr_iomux.dram_dqm2 = 0x00000038; + ddr_iomux.dram_dqm3 = 0x00000038; + ddr_iomux.dram_dqm4 = 0x00000038; + ddr_iomux.dram_dqm5 = 0x00000038; + ddr_iomux.dram_dqm6 = 0x00000038; + ddr_iomux.dram_dqm7 = 0x00000038; + ddr_iomux.dram_cas = 0x00000038; + ddr_iomux.dram_ras = 0x00000038; + ddr_iomux.dram_sdclk_0 = 0x00000038; + ddr_iomux.dram_sdclk_1 = 0x00000038; + ddr_iomux.dram_sdcke0 = 0x00003000; + ddr_iomux.dram_sdcke1 = 0x00003000; + /* + * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to + * Freescale QRM, but this is exactly the value used by the automatic + * calibration script and it works also in all our tests, so we leave + * it as is at this point. + */ + ddr_iomux.dram_reset = 0x00000038; + ddr_iomux.dram_sdba2 = 0x00000000; + ddr_iomux.dram_sdodt0 = 0x00000038; + ddr_iomux.dram_sdodt1 = 0x00000038; + grp_iomux.grp_b0ds = 0x00000038; + grp_iomux.grp_b1ds = 0x00000038; + grp_iomux.grp_b2ds = 0x00000038; + grp_iomux.grp_b3ds = 0x00000038; + grp_iomux.grp_b4ds = 0x00000038; + grp_iomux.grp_b5ds = 0x00000038; + grp_iomux.grp_b6ds = 0x00000038; + grp_iomux.grp_b7ds = 0x00000038; + grp_iomux.grp_addds = 0x00000038; + grp_iomux.grp_ddrmode_ctl = 0x00020000; + grp_iomux.grp_ddrpke = 0x00000000; + grp_iomux.grp_ddrmode = 0x00020000; + grp_iomux.grp_ctlds = 0x00000038; + grp_iomux.grp_ddr_type = 0x000C0000; + mx6sdl_dram_iocfg(64, &ddr_iomux, &grp_iomux); +} + +static void spl_mx6q_dram_setup_iomux(void) +{ + struct mx6dq_iomux_ddr_regs ddr_iomux; + struct mx6dq_iomux_grp_regs grp_iomux; + + ddr_iomux.dram_sdqs0 = 0x00000038; + ddr_iomux.dram_sdqs1 = 0x00000038; + ddr_iomux.dram_sdqs2 = 0x00000038; + ddr_iomux.dram_sdqs3 = 0x00000038; + ddr_iomux.dram_sdqs4 = 0x00000038; + ddr_iomux.dram_sdqs5 = 0x00000038; + ddr_iomux.dram_sdqs6 = 0x00000038; + ddr_iomux.dram_sdqs7 = 0x00000038; + ddr_iomux.dram_dqm0 = 0x00000038; + ddr_iomux.dram_dqm1 = 0x00000038; + ddr_iomux.dram_dqm2 = 0x00000038; + ddr_iomux.dram_dqm3 = 0x00000038; + ddr_iomux.dram_dqm4 = 0x00000038; + ddr_iomux.dram_dqm5 = 0x00000038; + ddr_iomux.dram_dqm6 = 0x00000038; + ddr_iomux.dram_dqm7 = 0x00000038; + ddr_iomux.dram_cas = 0x00000038; + ddr_iomux.dram_ras = 0x00000038; + ddr_iomux.dram_sdclk_0 = 0x00000038; + ddr_iomux.dram_sdclk_1 = 0x00000038; + ddr_iomux.dram_sdcke0 = 0x00003000; + ddr_iomux.dram_sdcke1 = 0x00003000; + /* + * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to + * Freescale QRM, but this is exactly the value used by the automatic + * calibration script and it works also in all our tests, so we leave + * it as is at this point. + */ + ddr_iomux.dram_reset = 0x00000038; + ddr_iomux.dram_sdba2 = 0x00000000; + ddr_iomux.dram_sdodt0 = 0x00000038; + ddr_iomux.dram_sdodt1 = 0x00000038; + grp_iomux.grp_b0ds = 0x00000038; + grp_iomux.grp_b1ds = 0x00000038; + grp_iomux.grp_b2ds = 0x00000038; + grp_iomux.grp_b3ds = 0x00000038; + grp_iomux.grp_b4ds = 0x00000038; + grp_iomux.grp_b5ds = 0x00000038; + grp_iomux.grp_b6ds = 0x00000038; + grp_iomux.grp_b7ds = 0x00000038; + grp_iomux.grp_addds = 0x00000038; + grp_iomux.grp_ddrmode_ctl = 0x00020000; + grp_iomux.grp_ddrpke = 0x00000000; + grp_iomux.grp_ddrmode = 0x00020000; + grp_iomux.grp_ctlds = 0x00000038; + grp_iomux.grp_ddr_type = 0x000C0000; + mx6dq_dram_iocfg(64, &ddr_iomux, &grp_iomux); +} + +static void spl_mx6s_dram_init(enum ddr_config dram_config, int reset) +{ + struct mx6_mmdc_calibration calib; + struct mx6_ddr_sysinfo sysinfo; + struct mx6_ddr3_cfg ddr3_cfg; + + if (reset) + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; + + calib.p0_mpwldectrl0 = 0x005B0061; + calib.p0_mpwldectrl1 = 0x004F0055; + calib.p0_mpdgctrl0 = 0x0314030C; + calib.p0_mpdgctrl1 = 0x025C0268; + calib.p0_mprddlctl = 0x42464646; + calib.p0_mpwrdlctl = 0x36322C34; + ddr3_cfg.mem_speed = 800; + ddr3_cfg.density = 4; + ddr3_cfg.rowaddr = 14; + ddr3_cfg.coladdr = 10; + ddr3_cfg.pagesz = 2; + ddr3_cfg.trcd = 1800; + ddr3_cfg.trcmin = 5200; + ddr3_cfg.trasmin = 3600; + ddr3_cfg.SRT = 0; + sysinfo.cs1_mirror = 1; + sysinfo.cs_density = 16; + sysinfo.bi_on = 1; + sysinfo.rtt_nom = 1; + sysinfo.rtt_wr = 0; + sysinfo.ralat = 5; + sysinfo.walat = 1; + sysinfo.mif3_mode = 3; + sysinfo.rst_to_cke = 0x23; + sysinfo.sde_to_rst = 0x10; + switch (dram_config) { + case DDR_16BIT_256MB: + sysinfo.dsize = 0; + sysinfo.ncs = 1; + break; + case DDR_32BIT_512MB: + sysinfo.dsize = 1; + sysinfo.ncs = 1; + break; + case DDR_32BIT_1GB: + sysinfo.dsize = 1; + sysinfo.ncs = 2; + break; + default: + puts("Tried to setup invalid DDR configuration\n"); + hang(); + } + + mx6_dram_cfg(&sysinfo, &calib, &ddr3_cfg); + udelay(100); +} + +static void spl_mx6q_dram_init(enum ddr_config dram_config, int reset) +{ + struct mx6_mmdc_calibration calib; + struct mx6_ddr_sysinfo sysinfo; + struct mx6_ddr3_cfg ddr3_cfg; + + if (reset) + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; + + calib.p0_mpwldectrl0 = 0x00630068; + calib.p0_mpwldectrl1 = 0x0068005D; + calib.p0_mpdgctrl0 = 0x04140428; + calib.p0_mpdgctrl1 = 0x037C037C; + calib.p0_mprddlctl = 0x3C30303A; + calib.p0_mpwrdlctl = 0x3A344038; + calib.p1_mpwldectrl0 = 0x0035004C; + calib.p1_mpwldectrl1 = 0x00170026; + calib.p1_mpdgctrl0 = 0x0374037C; + calib.p1_mpdgctrl1 = 0x0350032C; + calib.p1_mprddlctl = 0x30322A3C; + calib.p1_mpwrdlctl = 0x48304A3E; + ddr3_cfg.mem_speed = 1066; + ddr3_cfg.density = 4; + ddr3_cfg.rowaddr = 14; + ddr3_cfg.coladdr = 10; + ddr3_cfg.pagesz = 2; + ddr3_cfg.trcd = 1324; + ddr3_cfg.trcmin = 59500; + ddr3_cfg.trasmin = 9750; + ddr3_cfg.SRT = 0; + sysinfo.cs_density = 16; + sysinfo.cs1_mirror = 1; + sysinfo.bi_on = 1; + sysinfo.rtt_nom = 1; + sysinfo.rtt_wr = 0; + sysinfo.ralat = 5; + sysinfo.walat = 1; + sysinfo.mif3_mode = 3; + sysinfo.rst_to_cke = 0x23; + sysinfo.sde_to_rst = 0x10; + switch (dram_config) { + case DDR_16BIT_256MB: + sysinfo.dsize = 0; + sysinfo.ncs = 1; + break; + case DDR_32BIT_512MB: + sysinfo.dsize = 1; + sysinfo.ncs = 1; + break; + case DDR_64BIT_1GB: + sysinfo.dsize = 2; + sysinfo.ncs = 1; + break; + case DDR_64BIT_2GB: + sysinfo.dsize = 2; + sysinfo.ncs = 2; + break; + case DDR_64BIT_4GB: + sysinfo.dsize = 2; + sysinfo.ncs = 2; + ddr3_cfg.rowaddr = 15; + break; + default: + puts("Tried to setup invalid DDR configuration\n"); + hang(); + } + + mx6_dram_cfg(&sysinfo, &calib, &ddr3_cfg); + udelay(100); +} + +static int cm_fx6_spl_dram_init(void) +{ + u32 cpurev, imxtype; + unsigned long bank1_size, bank2_size; + + cpurev = get_cpu_rev(); + imxtype = (cpurev & 0xFF000) >> 12; + + switch (imxtype) { + case MXC_CPU_MX6SOLO: + spl_mx6s_dram_setup_iomux(); + + spl_mx6s_dram_init(DDR_32BIT_1GB, 0); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x40000000) + return 0; + + if (bank1_size == 0x20000000) { + spl_mx6s_dram_init(DDR_32BIT_512MB, 1); + return 0; + } + + spl_mx6s_dram_init(DDR_16BIT_256MB, 1); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x10000000) + return 0; + + break; + case MXC_CPU_MX6D: + case MXC_CPU_MX6Q: + spl_mx6q_dram_setup_iomux(); + + spl_mx6q_dram_init(DDR_64BIT_4GB, 0); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x80000000) + return 0; + + if (bank1_size == 0x40000000) { + bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, + 0x80000000); + if (bank2_size == 0x40000000) { + /* Don't do a full reset here */ + spl_mx6q_dram_init(DDR_64BIT_2GB, 0); + } else { + spl_mx6q_dram_init(DDR_64BIT_1GB, 1); + } + + return 0; + } + + spl_mx6q_dram_init(DDR_32BIT_512MB, 1); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x20000000) + return 0; + + spl_mx6q_dram_init(DDR_16BIT_256MB, 1); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x10000000) + return 0; + + break; + } + + return -1; +} + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void cm_fx6_setup_uart(void) +{ + SETUP_IOMUX_PADS(uart4_pads); + enable_uart_clk(1); +} + +#ifdef CONFIG_SPL_SPI_SUPPORT +static void cm_fx6_setup_ecspi(void) +{ + enable_cspi_clock(1, 0); + cm_fx6_set_ecspi_iomux(); +} +#else +static void cm_fx6_setup_ecspi(void) { } +#endif + +void board_init_f(ulong dummy) +{ + gd = &gdata; + enable_usdhc_clk(1, 2); + arch_cpu_init(); + timer_init(); + cm_fx6_setup_ecspi(); + cm_fx6_setup_uart(); + get_clocks(); + preloader_console_init(); + gpio_direction_output(CM_FX6_GREEN_LED, 1); + if (cm_fx6_spl_dram_init()) { + puts("!!!ERROR!!! DRAM detection failed!!!\n"); + hang(); + } + + memset(__bss_start, 0, __bss_end - __bss_start); + board_init_r(NULL, 0); +} + +void spl_board_init(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + + if (bt_mem_ctl == 0x3 && !bt_mem_type) + puts("Booting from SPI flash\n"); + else if (bt_mem_ctl == 0x4 || bt_mem_ctl == 0x5) + puts("Booting from MMC\n"); + else + puts("Unknown boot device\n"); +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +int board_mmc_init(bd_t *bis) +{ + cm_fx6_set_usdhc_iomux(); + + usdhc_cfg[2].sdhc_clk = mxc_get_clock(usdhc_clk[2]); + usdhc_cfg[2].max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg[2]); +} +#endif diff --git a/boards.cfg b/boards.cfg index e3a0726..308b94e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -334,6 +334,8 @@ Active arm armv7 mx6 freescale mx6sabresd Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam fabio.estevam@freescale.com Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey tharvey@gateworks.com Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton jon.nettleton@gmail.com +Active arm armv7 mx6 compulab cm_fx6 cm_fx6 +- Nikita Kiryanov nikita@compulab.co.il Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman sakoman@gmail.com Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas notasas@gmail.com Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat raph@8d.com diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h new file mode 100644 index 0000000..285af33 --- /dev/null +++ b/include/configs/cm_fx6.h @@ -0,0 +1,227 @@ +/* + * Config file for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov nikita@compulab.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_CM_FX6_H +#define __CONFIG_CM_FX6_H + +#include <asm/arch/imx-regs.h> +#include <config_distro_defaults.h> + +#define CONFIG_SYS_L2CACHE_OFF +#include "mx6_common.h" + +/* Machine config */ +#define CONFIG_MX6 +#define CONFIG_MX6QDL +#define CONFIG_CM_FX6 +#define CONFIG_SYS_LITTLE_ENDIAN +#define CONFIG_MACH_TYPE 4273 +#define CONFIG_SYS_HZ 1000 + +/* Display information on boot */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_TIMESTAMP + +/* CMD */ +#include <config_cmd_default.h> +#define CONFIG_CMD_GREPENV +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* RAM */ +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Serial console */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Shell */ +#define CONFIG_SYS_PROMPT "CM-FX6 # " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024) + +/* SPI flash */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + +/* Environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (768 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel=uImage-cm-fx6\0" \ + "autoload=no\0" \ + "loadaddr=0x10800000\0" \ + "fdtaddr=0x11000000\0" \ + "console=ttymxc3,115200\0" \ + "ethprime=FEC0\0" \ + "bootscr=boot.scr\0" \ + "bootm_low=18000000\0" \ + "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ + "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ + "fdtfile=cm-fx6.dtb\0" \ + "doboot=bootm ${loadaddr}\0" \ + "loadfdt=false\0" \ + "setboottypez=setenv kernel zImage-cm-fx6;" \ + "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ + "setenv loadfdt true;\0" \ + "setboottypem=setenv kernel uImage-cm-fx6;" \ + "setenv doboot bootm ${loadaddr};" \ + "setenv loadfdt false;\0"\ + "run_eboot=echo Starting EBOOT ...; "\ + "mmc dev ${mmcdev} && " \ + "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ + "mmcdev=2\0" \ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "loadmmcbootscript=fatload mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \ + "mmcbootscript=echo Running bootscript from mmc ...; "\ + "source ${loadaddr}\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} " \ + "${video}\0" \ + "mmcloadkernel=fatload mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ + "mmcloadfdt=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "run doboot\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=ubifs\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} " \ + "${video}\0" \ + "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 0 780000; " \ + "if ${loadfdt}; then " \ + "run nandloadfdt;" \ + "fi; " \ + "run doboot\0" \ + "boot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "if run loadmmcbootscript; then " \ + "run mmcbootscript;" \ + "else " \ + "if run mmcloadkernel; then " \ + "if ${loadfdt}; then " \ + "run mmcloadfdt;" \ + "fi;" \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + "fi;" + +#define CONFIG_BOOTCOMMAND \ + "run setboottypem; run boot" + +/* SPI */ +#define CONFIG_SPI +#define CONFIG_MXC_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_WINBOND + +/* GPIO */ +#define CONFIG_MXC_GPIO + +/* Boot */ +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_TEXT_BASE 0x10800000 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* misc */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_STACKSIZE (128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ + +/* SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_STACK 0x0091FFB8 +#define CONFIG_SPL_TEXT_BASE 0x00908000 +#define CONFIG_SPL_BSS_START_ADDR 0x18200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x03200000 +#define CONFIG_SPL_MAX_SIZE (62 * 1024) +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_SPL_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_SPL_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) +#define CONFIG_SPL_SPI_LOAD + +#endif /* __CONFIG_CM_FX6_H */
On Sunday, August 03, 2014 at 09:34:42 AM, Nikita Kiryanov wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 1 - board/compulab/cm_fx6/Makefile | 12 ++ board/compulab/cm_fx6/cm_fx6.c | 108 ++++++++++ board/compulab/cm_fx6/common.c | 83 ++++++++ board/compulab/cm_fx6/common.h | 36 ++++ board/compulab/cm_fx6/imximage.cfg | 8 + board/compulab/cm_fx6/spl.c | 400 +++++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/cm_fx6.h | 227 +++++++++++++++++++++ 9 files changed, 876 insertions(+), 1 deletion(-) create mode 100644 board/compulab/cm_fx6/Makefile create mode 100644 board/compulab/cm_fx6/cm_fx6.c create mode 100644 board/compulab/cm_fx6/common.c create mode 100644 board/compulab/cm_fx6/common.h create mode 100644 board/compulab/cm_fx6/imximage.cfg create mode 100644 board/compulab/cm_fx6/spl.c create mode 100644 include/configs/cm_fx6.h
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index d3891dc..219263a 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -4,7 +4,6 @@
- SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h> #include <linux/types.h> #include <asm/arch/mx6-ddr.h>
Drop this piece ;-)
[...]
+++ b/board/compulab/cm_fx6/cm_fx6.c
[...]
+static ulong bank1_size; +static ulong bank2_size;
+#define MMDC1_MDCTL 0x21B0000 +static int probe_mmdc_config(void) +{
- u32 val = readl(0x21B0000);
- switch (val) {
- case 0x83180000: /* DDR_16BIT_256MB */
gd->ram_size = 0x10000000;bank1_size = 0x10000000;bank2_size = 0;break;- case 0x83190000: /* DDR_32BIT_512MB */
gd->ram_size = 0x20000000;bank1_size = 0x20000000;bank2_size = 0;break;
imx_ddr_size() won't cut it here ?
[...]
On 03/08/14 17:09, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:42 AM, Nikita Kiryanov wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 1 - board/compulab/cm_fx6/Makefile | 12 ++ board/compulab/cm_fx6/cm_fx6.c | 108 ++++++++++ board/compulab/cm_fx6/common.c | 83 ++++++++ board/compulab/cm_fx6/common.h | 36 ++++ board/compulab/cm_fx6/imximage.cfg | 8 + board/compulab/cm_fx6/spl.c | 400 +++++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/cm_fx6.h | 227 +++++++++++++++++++++ 9 files changed, 876 insertions(+), 1 deletion(-) create mode 100644 board/compulab/cm_fx6/Makefile create mode 100644 board/compulab/cm_fx6/cm_fx6.c create mode 100644 board/compulab/cm_fx6/common.c create mode 100644 board/compulab/cm_fx6/common.h create mode 100644 board/compulab/cm_fx6/imximage.cfg create mode 100644 board/compulab/cm_fx6/spl.c create mode 100644 include/configs/cm_fx6.h
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index d3891dc..219263a 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -4,7 +4,6 @@
- SPDX-License-Identifier: GPL-2.0+
*/
- #include <common.h> #include <linux/types.h> #include <asm/arch/mx6-ddr.h>
Drop this piece ;-)
Yep...
[...]
+++ b/board/compulab/cm_fx6/cm_fx6.c
[...]
+static ulong bank1_size; +static ulong bank2_size;
+#define MMDC1_MDCTL 0x21B0000 +static int probe_mmdc_config(void) +{
- u32 val = readl(0x21B0000);
- switch (val) {
- case 0x83180000: /* DDR_16BIT_256MB */
gd->ram_size = 0x10000000;bank1_size = 0x10000000;bank2_size = 0;break;- case 0x83190000: /* DDR_32BIT_512MB */
gd->ram_size = 0x20000000;bank1_size = 0x20000000;bank2_size = 0;break;imx_ddr_size() won't cut it here ?
It doesn't handle 4GB correctly (returns 0). I suppose I can make a patch which caps the return value of imx_ddr_size() for MX6 socs to 3840MB. What do you think?
[...]
On Monday, August 04, 2014 at 04:41:03 PM, Nikita Kiryanov wrote:
On 03/08/14 17:09, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:42 AM, Nikita Kiryanov wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 1 - board/compulab/cm_fx6/Makefile | 12 ++ board/compulab/cm_fx6/cm_fx6.c | 108 ++++++++++ board/compulab/cm_fx6/common.c | 83 ++++++++ board/compulab/cm_fx6/common.h | 36 ++++ board/compulab/cm_fx6/imximage.cfg | 8 + board/compulab/cm_fx6/spl.c | 400
+++++++++++++++++++++++++++++++++++++ boards.cfg |
2 +
include/configs/cm_fx6.h | 227 +++++++++++++++++++++ 9 files changed, 876 insertions(+), 1 deletion(-) create mode 100644 board/compulab/cm_fx6/Makefile create mode 100644 board/compulab/cm_fx6/cm_fx6.c create mode 100644 board/compulab/cm_fx6/common.c create mode 100644 board/compulab/cm_fx6/common.h create mode 100644 board/compulab/cm_fx6/imximage.cfg create mode 100644 board/compulab/cm_fx6/spl.c create mode 100644 include/configs/cm_fx6.h
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index d3891dc..219263a 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -4,7 +4,6 @@
- SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h> #include <linux/types.h> #include <asm/arch/mx6-ddr.h>
Drop this piece ;-)
Yep...
[...]
+++ b/board/compulab/cm_fx6/cm_fx6.c
[...]
+static ulong bank1_size; +static ulong bank2_size;
+#define MMDC1_MDCTL 0x21B0000 +static int probe_mmdc_config(void) +{
- u32 val = readl(0x21B0000);
- switch (val) {
- case 0x83180000: /* DDR_16BIT_256MB */
gd->ram_size = 0x10000000;bank1_size = 0x10000000;bank2_size = 0;break;- case 0x83190000: /* DDR_32BIT_512MB */
gd->ram_size = 0x20000000;bank1_size = 0x20000000;bank2_size = 0;break;imx_ddr_size() won't cut it here ?
It doesn't handle 4GB correctly (returns 0). I suppose I can make a patch which caps the return value of imx_ddr_size() for MX6 socs to 3840MB. What do you think?
That you should check the U-Boot ML, since that's what I did yesterday ;-) But still, this is rather sad practice -- instead of fixing a bug in code which you do know about, you implement such a workaround :-(
On 04/08/14 18:12, Marek Vasut wrote:
On Monday, August 04, 2014 at 04:41:03 PM, Nikita Kiryanov wrote:
On 03/08/14 17:09, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:42 AM, Nikita Kiryanov wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
arch/arm/cpu/armv7/mx6/ddr.c | 1 - board/compulab/cm_fx6/Makefile | 12 ++ board/compulab/cm_fx6/cm_fx6.c | 108 ++++++++++ board/compulab/cm_fx6/common.c | 83 ++++++++ board/compulab/cm_fx6/common.h | 36 ++++ board/compulab/cm_fx6/imximage.cfg | 8 + board/compulab/cm_fx6/spl.c | 400
+++++++++++++++++++++++++++++++++++++ boards.cfg |
2 +include/configs/cm_fx6.h | 227 +++++++++++++++++++++ 9 files changed, 876 insertions(+), 1 deletion(-) create mode 100644 board/compulab/cm_fx6/Makefile create mode 100644 board/compulab/cm_fx6/cm_fx6.c create mode 100644 board/compulab/cm_fx6/common.c create mode 100644 board/compulab/cm_fx6/common.h create mode 100644 board/compulab/cm_fx6/imximage.cfg create mode 100644 board/compulab/cm_fx6/spl.c create mode 100644 include/configs/cm_fx6.h
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index d3891dc..219263a 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -4,7 +4,6 @@
* * SPDX-License-Identifier: GPL-2.0+ */
#include <common.h> #include <linux/types.h> #include <asm/arch/mx6-ddr.h>
Drop this piece ;-)
Yep...
[...]
+++ b/board/compulab/cm_fx6/cm_fx6.c
[...]
+static ulong bank1_size; +static ulong bank2_size;
+#define MMDC1_MDCTL 0x21B0000 +static int probe_mmdc_config(void) +{
- u32 val = readl(0x21B0000);
- switch (val) {
- case 0x83180000: /* DDR_16BIT_256MB */
gd->ram_size = 0x10000000;bank1_size = 0x10000000;bank2_size = 0;break;- case 0x83190000: /* DDR_32BIT_512MB */
gd->ram_size = 0x20000000;bank1_size = 0x20000000;bank2_size = 0;break;imx_ddr_size() won't cut it here ?
It doesn't handle 4GB correctly (returns 0). I suppose I can make a patch which caps the return value of imx_ddr_size() for MX6 socs to 3840MB. What do you think?
That you should check the U-Boot ML, since that's what I did yesterday ;-) But still, this is rather sad practice -- instead of fixing a bug in code which you do know about, you implement such a workaround :-(
Actually, I only learned of this bug yesterday after you asked about imx_ddr_size(). Glad to hear you already fixed it; I'll look at it for the v2.
On Tuesday, August 05, 2014 at 09:36:27 AM, Nikita Kiryanov wrote:
[...]
imx_ddr_size() won't cut it here ?
It doesn't handle 4GB correctly (returns 0). I suppose I can make a patch which caps the return value of imx_ddr_size() for MX6 socs to 3840MB. What do you think?
That you should check the U-Boot ML, since that's what I did yesterday ;-) But still, this is rather sad practice -- instead of fixing a bug in code which you do know about, you implement such a workaround :-(
Actually, I only learned of this bug yesterday after you asked about imx_ddr_size(). Glad to hear you already fixed it; I'll look at it for the v2.
I did the capping, yep. HTH :)
Best regards, Marek Vasut
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
<snip>
+static void spl_mx6s_dram_init(enum ddr_config dram_config, int reset) +{
struct mx6_mmdc_calibration calib;struct mx6_ddr_sysinfo sysinfo;struct mx6_ddr3_cfg ddr3_cfg;if (reset)((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;calib.p0_mpwldectrl0 = 0x005B0061;calib.p0_mpwldectrl1 = 0x004F0055;calib.p0_mpdgctrl0 = 0x0314030C;calib.p0_mpdgctrl1 = 0x025C0268;calib.p0_mprddlctl = 0x42464646;calib.p0_mpwrdlctl = 0x36322C34;ddr3_cfg.mem_speed = 800;ddr3_cfg.density = 4;ddr3_cfg.rowaddr = 14;ddr3_cfg.coladdr = 10;ddr3_cfg.pagesz = 2;ddr3_cfg.trcd = 1800;ddr3_cfg.trcmin = 5200;ddr3_cfg.trasmin = 3600;ddr3_cfg.SRT = 0;sysinfo.cs1_mirror = 1;sysinfo.cs_density = 16;sysinfo.bi_on = 1;sysinfo.rtt_nom = 1;sysinfo.rtt_wr = 0;sysinfo.ralat = 5;sysinfo.walat = 1;sysinfo.mif3_mode = 3;sysinfo.rst_to_cke = 0x23;sysinfo.sde_to_rst = 0x10;switch (dram_config) {case DDR_16BIT_256MB:sysinfo.dsize = 0;sysinfo.ncs = 1;break;case DDR_32BIT_512MB:sysinfo.dsize = 1;sysinfo.ncs = 1;break;case DDR_32BIT_1GB:sysinfo.dsize = 1;sysinfo.ncs = 2;break;default:puts("Tried to setup invalid DDR configuration\n");hang();}mx6_dram_cfg(&sysinfo, &calib, &ddr3_cfg);udelay(100);+}
Nikita,
I'm curious why you add an extra udelay(100) here? There is an mdelay(1) before the return of mx6_dram_cfg() to wait for auto-ZQ calibration to complete (I never found a way to determine when it was complete via registers).
Regards,
Tim
On 04/08/14 07:45, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
<snip> > + > +static void spl_mx6s_dram_init(enum ddr_config dram_config, int reset) > +{ > + struct mx6_mmdc_calibration calib; > + struct mx6_ddr_sysinfo sysinfo; > + struct mx6_ddr3_cfg ddr3_cfg; > + > + if (reset) > + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; > + > + calib.p0_mpwldectrl0 = 0x005B0061; > + calib.p0_mpwldectrl1 = 0x004F0055; > + calib.p0_mpdgctrl0 = 0x0314030C; > + calib.p0_mpdgctrl1 = 0x025C0268; > + calib.p0_mprddlctl = 0x42464646; > + calib.p0_mpwrdlctl = 0x36322C34; > + ddr3_cfg.mem_speed = 800; > + ddr3_cfg.density = 4; > + ddr3_cfg.rowaddr = 14; > + ddr3_cfg.coladdr = 10; > + ddr3_cfg.pagesz = 2; > + ddr3_cfg.trcd = 1800; > + ddr3_cfg.trcmin = 5200; > + ddr3_cfg.trasmin = 3600; > + ddr3_cfg.SRT = 0; > + sysinfo.cs1_mirror = 1; > + sysinfo.cs_density = 16; > + sysinfo.bi_on = 1; > + sysinfo.rtt_nom = 1; > + sysinfo.rtt_wr = 0; > + sysinfo.ralat = 5; > + sysinfo.walat = 1; > + sysinfo.mif3_mode = 3; > + sysinfo.rst_to_cke = 0x23; > + sysinfo.sde_to_rst = 0x10; > + switch (dram_config) { > + case DDR_16BIT_256MB: > + sysinfo.dsize = 0; > + sysinfo.ncs = 1; > + break; > + case DDR_32BIT_512MB: > + sysinfo.dsize = 1; > + sysinfo.ncs = 1; > + break; > + case DDR_32BIT_1GB: > + sysinfo.dsize = 1; > + sysinfo.ncs = 2; > + break; > + default: > + puts("Tried to setup invalid DDR configuration\n"); > + hang(); > + } > + > + mx6_dram_cfg(&sysinfo, &calib, &ddr3_cfg); > + udelay(100); > +}
Nikita,
I'm curious why you add an extra udelay(100) here? There is an mdelay(1) before the return of mx6_dram_cfg() to wait for auto-ZQ calibration to complete (I never found a way to determine when it was complete via registers).
Yes you're right. This udelay can probably be removed (unless I catch the board misbehaving during multiple resets).
Regards,
Tim
On 04/08/14 16:36, Nikita Kiryanov wrote:
On 04/08/14 07:45, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
<snip> > + > +static void spl_mx6s_dram_init(enum ddr_config dram_config, int reset) > +{ > + struct mx6_mmdc_calibration calib; > + struct mx6_ddr_sysinfo sysinfo; > + struct mx6_ddr3_cfg ddr3_cfg; > + > + if (reset) > + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; > + > + calib.p0_mpwldectrl0 = 0x005B0061; > + calib.p0_mpwldectrl1 = 0x004F0055; > + calib.p0_mpdgctrl0 = 0x0314030C; > + calib.p0_mpdgctrl1 = 0x025C0268; > + calib.p0_mprddlctl = 0x42464646; > + calib.p0_mpwrdlctl = 0x36322C34; > + ddr3_cfg.mem_speed = 800; > + ddr3_cfg.density = 4; > + ddr3_cfg.rowaddr = 14; > + ddr3_cfg.coladdr = 10; > + ddr3_cfg.pagesz = 2; > + ddr3_cfg.trcd = 1800; > + ddr3_cfg.trcmin = 5200; > + ddr3_cfg.trasmin = 3600; > + ddr3_cfg.SRT = 0; > + sysinfo.cs1_mirror = 1; > + sysinfo.cs_density = 16; > + sysinfo.bi_on = 1; > + sysinfo.rtt_nom = 1; > + sysinfo.rtt_wr = 0; > + sysinfo.ralat = 5; > + sysinfo.walat = 1; > + sysinfo.mif3_mode = 3; > + sysinfo.rst_to_cke = 0x23; > + sysinfo.sde_to_rst = 0x10; > + switch (dram_config) { > + case DDR_16BIT_256MB: > + sysinfo.dsize = 0; > + sysinfo.ncs = 1; > + break; > + case DDR_32BIT_512MB: > + sysinfo.dsize = 1; > + sysinfo.ncs = 1; > + break; > + case DDR_32BIT_1GB: > + sysinfo.dsize = 1; > + sysinfo.ncs = 2; > + break; > + default: > + puts("Tried to setup invalid DDR configuration\n"); > + hang(); > + } > + > + mx6_dram_cfg(&sysinfo, &calib, &ddr3_cfg); > + udelay(100); > +}
Nikita,
I'm curious why you add an extra udelay(100) here? There is an mdelay(1) before the return of mx6_dram_cfg() to wait for auto-ZQ calibration to complete (I never found a way to determine when it was complete via registers).
Yes you're right. This udelay can probably be removed (unless I catch the board misbehaving during multiple resets).
Caught the DRAM config failing during multiple resets when udelay(100) is removed, so I guess they stay..
Regards,
Tim
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Wed, Aug 6, 2014 at 10:29 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
On 04/08/14 16:36, Nikita Kiryanov wrote:
On 04/08/14 07:45, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
<snip> > > + > +static void spl_mx6s_dram_init(enum ddr_config dram_config, int reset) > +{ > + struct mx6_mmdc_calibration calib; > + struct mx6_ddr_sysinfo sysinfo; > + struct mx6_ddr3_cfg ddr3_cfg; > + > + if (reset) > + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; > + > + calib.p0_mpwldectrl0 = 0x005B0061; > + calib.p0_mpwldectrl1 = 0x004F0055; > + calib.p0_mpdgctrl0 = 0x0314030C; > + calib.p0_mpdgctrl1 = 0x025C0268; > + calib.p0_mprddlctl = 0x42464646; > + calib.p0_mpwrdlctl = 0x36322C34; > + ddr3_cfg.mem_speed = 800; > + ddr3_cfg.density = 4; > + ddr3_cfg.rowaddr = 14; > + ddr3_cfg.coladdr = 10; > + ddr3_cfg.pagesz = 2; > + ddr3_cfg.trcd = 1800; > + ddr3_cfg.trcmin = 5200; > + ddr3_cfg.trasmin = 3600; > + ddr3_cfg.SRT = 0; > + sysinfo.cs1_mirror = 1; > + sysinfo.cs_density = 16; > + sysinfo.bi_on = 1; > + sysinfo.rtt_nom = 1; > + sysinfo.rtt_wr = 0; > + sysinfo.ralat = 5; > + sysinfo.walat = 1; > + sysinfo.mif3_mode = 3; > + sysinfo.rst_to_cke = 0x23; > + sysinfo.sde_to_rst = 0x10; > + switch (dram_config) { > + case DDR_16BIT_256MB: > + sysinfo.dsize = 0; > + sysinfo.ncs = 1; > + break; > + case DDR_32BIT_512MB: > + sysinfo.dsize = 1; > + sysinfo.ncs = 1; > + break; > + case DDR_32BIT_1GB: > + sysinfo.dsize = 1; > + sysinfo.ncs = 2; > + break; > + default: > + puts("Tried to setup invalid DDR configuration\n"); > + hang(); > + } > + > + mx6_dram_cfg(&sysinfo, &calib, &ddr3_cfg); > + udelay(100); > +}
Nikita,
I'm curious why you add an extra udelay(100) here? There is an mdelay(1) before the return of mx6_dram_cfg() to wait for auto-ZQ calibration to complete (I never found a way to determine when it was complete via registers).
Yes you're right. This udelay can probably be removed (unless I catch the board misbehaving during multiple resets).
Caught the DRAM config failing during multiple resets when udelay(100) is removed, so I guess they stay..
Nikita,
What exactly was failing? Was the subsequent to get_ram_size() failing? If the extra delay is really needed we should add it to the mx6_dram_cfg() function. The issue I ran into before I added the mdelay(1) there to wait for auto-ZQ calib to complete was that SDRAM operations immediately following the call to mx6_dram_cfg() would be un-reliable, specifically a memset to 0 would fail to clear memory where GD was which caused some interesting failures down the line.
Maybe I'll open up an issue with Freescale and ask them if there is a way to know when auto-ZQ calibration is complete because it isn't clear to me how to do that. The 1ms delay was because the 0 value we set to MPZQHWCTRL ZQ_HW_PER configures it for a 1ms ZQ calibration cycle.... maybe we simply need a little more headroom.
Tim
On 08/08/14 10:19, Tim Harvey wrote:
On Wed, Aug 6, 2014 at 10:29 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
On 04/08/14 16:36, Nikita Kiryanov wrote:
On 04/08/14 07:45, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
<snip> > > + > +static void spl_mx6s_dram_init(enum ddr_config dram_config, int reset) > +{ > + struct mx6_mmdc_calibration calib; > + struct mx6_ddr_sysinfo sysinfo; > + struct mx6_ddr3_cfg ddr3_cfg; > + > + if (reset) > + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; > + > + calib.p0_mpwldectrl0 = 0x005B0061; > + calib.p0_mpwldectrl1 = 0x004F0055; > + calib.p0_mpdgctrl0 = 0x0314030C; > + calib.p0_mpdgctrl1 = 0x025C0268; > + calib.p0_mprddlctl = 0x42464646; > + calib.p0_mpwrdlctl = 0x36322C34; > + ddr3_cfg.mem_speed = 800; > + ddr3_cfg.density = 4; > + ddr3_cfg.rowaddr = 14; > + ddr3_cfg.coladdr = 10; > + ddr3_cfg.pagesz = 2; > + ddr3_cfg.trcd = 1800; > + ddr3_cfg.trcmin = 5200; > + ddr3_cfg.trasmin = 3600; > + ddr3_cfg.SRT = 0; > + sysinfo.cs1_mirror = 1; > + sysinfo.cs_density = 16; > + sysinfo.bi_on = 1; > + sysinfo.rtt_nom = 1; > + sysinfo.rtt_wr = 0; > + sysinfo.ralat = 5; > + sysinfo.walat = 1; > + sysinfo.mif3_mode = 3; > + sysinfo.rst_to_cke = 0x23; > + sysinfo.sde_to_rst = 0x10; > + switch (dram_config) { > + case DDR_16BIT_256MB: > + sysinfo.dsize = 0; > + sysinfo.ncs = 1; > + break; > + case DDR_32BIT_512MB: > + sysinfo.dsize = 1; > + sysinfo.ncs = 1; > + break; > + case DDR_32BIT_1GB: > + sysinfo.dsize = 1; > + sysinfo.ncs = 2; > + break; > + default: > + puts("Tried to setup invalid DDR configuration\n"); > + hang(); > + } > + > + mx6_dram_cfg(&sysinfo, &calib, &ddr3_cfg); > + udelay(100); > +}
Nikita,
I'm curious why you add an extra udelay(100) here? There is an mdelay(1) before the return of mx6_dram_cfg() to wait for auto-ZQ calibration to complete (I never found a way to determine when it was complete via registers).
Yes you're right. This udelay can probably be removed (unless I catch the board misbehaving during multiple resets).
Caught the DRAM config failing during multiple resets when udelay(100) is removed, so I guess they stay..
Nikita,
What exactly was failing? Was the subsequent to get_ram_size() failing?
Yes.
If the extra delay is really needed we should add it to the mx6_dram_cfg() function. The issue I ran into before I added the mdelay(1) there to wait for auto-ZQ calib to complete was that SDRAM operations immediately following the call to mx6_dram_cfg() would be un-reliable, specifically a memset to 0 would fail to clear memory where GD was which caused some interesting failures down the line.
In my case the failures appeared after the board had been operational long enough for the soc to heat up. I'm curious to hear what kind of temperatures you tested your board under. If a warm temperature that is within reasonable limits can cause failures on your board as well, that would be a clear indication that the 1 msec delay is a borderline value and needs to be increased.
Maybe I'll open up an issue with Freescale and ask them if there is a way to know when auto-ZQ calibration is complete because it isn't clear to me how to do that. The 1ms delay was because the 0 value we set to MPZQHWCTRL ZQ_HW_PER configures it for a 1ms ZQ calibration cycle.... maybe we simply need a little more headroom.
Maybe. If a Freescale representative can provide an analytical reason like the one you're proposing, that would be great. The question is what to do if a good explanation is not given. We can simply increase the mdelay tentatively in mx6_dram_cfg(), or we can keep the udelay() for cm_fx6 and wait to see if someone else complains. I'm fine with both options.
Tim
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
<snip>
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h new file mode 100644 index 0000000..285af33 --- /dev/null +++ b/include/configs/cm_fx6.h @@ -0,0 +1,227 @@ +/*
- Config file for Compulab CM-FX6 board
- Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
- Author: Nikita Kiryanov nikita@compulab.co.il
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_CM_FX6_H +#define __CONFIG_CM_FX6_H
+#include <asm/arch/imx-regs.h> +#include <config_distro_defaults.h>
+#define CONFIG_SYS_L2CACHE_OFF +#include "mx6_common.h"
+/* Machine config */ +#define CONFIG_MX6 +#define CONFIG_MX6QDL +#define CONFIG_CM_FX6 +#define CONFIG_SYS_LITTLE_ENDIAN +#define CONFIG_MACH_TYPE 4273 +#define CONFIG_SYS_HZ 1000
+/* Display information on boot */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_TIMESTAMP
+/* CMD */ +#include <config_cmd_default.h> +#define CONFIG_CMD_GREPENV +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS
+/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+/* RAM */ +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)+#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)+/* Serial console */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+/* Shell */ +#define CONFIG_SYS_PROMPT "CM-FX6 # " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
+/* SPI flash */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+/* Environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (768 * 1024)
+#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel=uImage-cm-fx6\0" \"autoload=no\0" \"loadaddr=0x10800000\0" \"fdtaddr=0x11000000\0" \"console=ttymxc3,115200\0" \"ethprime=FEC0\0" \"bootscr=boot.scr\0" \"bootm_low=18000000\0" \"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \"fdtfile=cm-fx6.dtb\0" \"doboot=bootm ${loadaddr}\0" \"loadfdt=false\0" \"setboottypez=setenv kernel zImage-cm-fx6;" \"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \"setenv loadfdt true;\0" \"setboottypem=setenv kernel uImage-cm-fx6;" \"setenv doboot bootm ${loadaddr};" \"setenv loadfdt false;\0"\"run_eboot=echo Starting EBOOT ...; "\"mmc dev ${mmcdev} && " \"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \"mmcdev=2\0" \"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \"loadmmcbootscript=fatload mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \"mmcbootscript=echo Running bootscript from mmc ...; "\"source ${loadaddr}\0" \"mmcargs=setenv bootargs console=${console} " \"root=${mmcroot} " \"${video}\0" \"mmcloadkernel=fatload mmc ${mmcdev} ${loadaddr} ${kernel}\0" \"mmcloadfdt=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \"mmcboot=echo Booting from mmc ...; " \"run mmcargs; " \"run doboot\0" \"nandroot=/dev/mtdblock4 rw\0" \"nandrootfstype=ubifs\0" \"nandargs=setenv bootargs console=${console} " \"root=${nandroot} " \"rootfstype=${nandrootfstype} " \"${video}\0" \"nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \"nandboot=echo Booting from nand ...; " \"run nandargs; " \"nand read ${loadaddr} 0 780000; " \"if ${loadfdt}; then " \"run nandloadfdt;" \"fi; " \"run doboot\0" \"boot=mmc dev ${mmcdev}; " \"if mmc rescan; then " \"if run loadmmcbootscript; then " \"run mmcbootscript;" \"else " \"if run mmcloadkernel; then " \"if ${loadfdt}; then " \"run mmcloadfdt;" \"fi;" \"run mmcboot;" \"fi;" \"fi;" \"fi;"+#define CONFIG_BOOTCOMMAND \
"run setboottypem; run boot"+/* SPI */ +#define CONFIG_SPI +#define CONFIG_MXC_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_WINBOND
+/* GPIO */ +#define CONFIG_MXC_GPIO
+/* Boot */ +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_TEXT_BASE 0x10800000 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG
+/* misc */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_STACKSIZE (128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
+/* SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_STACK 0x0091FFB8 +#define CONFIG_SPL_TEXT_BASE 0x00908000 +#define CONFIG_SPL_BSS_START_ADDR 0x18200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x03200000 +#define CONFIG_SPL_MAX_SIZE (62 * 1024) +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_SPL_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_SPL_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) +#define CONFIG_SPL_SPI_LOAD
Nikita,
Are the values in include/configs/imx6_spl.h too inflexible to use? If so, I can submit a patch in the future to remove that file and pull them all in my board config files as I'm the only user of it.
Regards,
Tim
On 04/08/14 09:02, Tim Harvey wrote:
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov nikita@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
<snip> > diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h > new file mode 100644 > index 0000000..285af33 > --- /dev/null > +++ b/include/configs/cm_fx6.h > @@ -0,0 +1,227 @@ > +/* > + * Config file for Compulab CM-FX6 board > + * > + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ > + * > + * Author: Nikita Kiryanov <nikita@compulab.co.il> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIG_CM_FX6_H > +#define __CONFIG_CM_FX6_H > + > +#include <asm/arch/imx-regs.h> > +#include <config_distro_defaults.h> > + > +#define CONFIG_SYS_L2CACHE_OFF > +#include "mx6_common.h" > + > +/* Machine config */ > +#define CONFIG_MX6 > +#define CONFIG_MX6QDL > +#define CONFIG_CM_FX6 > +#define CONFIG_SYS_LITTLE_ENDIAN > +#define CONFIG_MACH_TYPE 4273 > +#define CONFIG_SYS_HZ 1000 > + > +/* Display information on boot */ > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > +#define CONFIG_TIMESTAMP > + > +/* CMD */ > +#include <config_cmd_default.h> > +#define CONFIG_CMD_GREPENV > +#undef CONFIG_CMD_FLASH > +#undef CONFIG_CMD_LOADB > +#undef CONFIG_CMD_LOADS > +#undef CONFIG_CMD_XIMG > +#undef CONFIG_CMD_FPGA > +#undef CONFIG_CMD_IMLS > +#undef CONFIG_CMD_NET > +#undef CONFIG_CMD_NFS > + > +/* MMC */ > +#define CONFIG_MMC > +#define CONFIG_CMD_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_FSL_ESDHC > +#define CONFIG_FSL_USDHC > +#define CONFIG_SYS_FSL_USDHC_NUM 3 > +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR > + > +/* RAM */ > +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR > +#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 > +#define CONFIG_NR_DRAM_BANKS 2 > +#define CONFIG_SYS_MEMTEST_START 0x10000000 > +#define CONFIG_SYS_MEMTEST_END 0x10010000 > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +/* Serial console */ > +#define CONFIG_MXC_UART > +#define CONFIG_MXC_UART_BASE UART4_BASE > +#define CONFIG_BAUDRATE 115200 > +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} > + > +/* Shell */ > +#define CONFIG_SYS_PROMPT "CM-FX6 # " > +#define CONFIG_SYS_CBSIZE 1024 > +#define CONFIG_SYS_MAXARGS 16 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > + sizeof(CONFIG_SYS_PROMPT) + 16) > +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024) > + > +/* SPI flash */ > +#define CONFIG_SYS_NO_FLASH > +#define CONFIG_CMD_SF > +#define CONFIG_SF_DEFAULT_BUS 0 > +#define CONFIG_SF_DEFAULT_CS 0 > +#define CONFIG_SF_DEFAULT_SPEED 25000000 > +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) > + > +/* Environment */ > +#define CONFIG_ENV_OVERWRITE > +#define CONFIG_ENV_IS_IN_SPI_FLASH > +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED > +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE > +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS > +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS > +#define CONFIG_ENV_SECT_SIZE (64 * 1024) > +#define CONFIG_ENV_SIZE (8 * 1024) > +#define CONFIG_ENV_OFFSET (768 * 1024) > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "kernel=uImage-cm-fx6\0" \ > + "autoload=no\0" \ > + "loadaddr=0x10800000\0" \ > + "fdtaddr=0x11000000\0" \ > + "console=ttymxc3,115200\0" \ > + "ethprime=FEC0\0" \ > + "bootscr=boot.scr\0" \ > + "bootm_low=18000000\0" \ > + "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ > + "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ > + "fdtfile=cm-fx6.dtb\0" \ > + "doboot=bootm ${loadaddr}\0" \ > + "loadfdt=false\0" \ > + "setboottypez=setenv kernel zImage-cm-fx6;" \ > + "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ > + "setenv loadfdt true;\0" \ > + "setboottypem=setenv kernel uImage-cm-fx6;" \ > + "setenv doboot bootm ${loadaddr};" \ > + "setenv loadfdt false;\0"\ > + "run_eboot=echo Starting EBOOT ...; "\ > + "mmc dev ${mmcdev} && " \ > + "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ > + "mmcdev=2\0" \ > + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ > + "loadmmcbootscript=fatload mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \ > + "mmcbootscript=echo Running bootscript from mmc ...; "\ > + "source ${loadaddr}\0" \ > + "mmcargs=setenv bootargs console=${console} " \ > + "root=${mmcroot} " \ > + "${video}\0" \ > + "mmcloadkernel=fatload mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ > + "mmcloadfdt=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ > + "mmcboot=echo Booting from mmc ...; " \ > + "run mmcargs; " \ > + "run doboot\0" \ > + "nandroot=/dev/mtdblock4 rw\0" \ > + "nandrootfstype=ubifs\0" \ > + "nandargs=setenv bootargs console=${console} " \ > + "root=${nandroot} " \ > + "rootfstype=${nandrootfstype} " \ > + "${video}\0" \ > + "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ > + "nandboot=echo Booting from nand ...; " \ > + "run nandargs; " \ > + "nand read ${loadaddr} 0 780000; " \ > + "if ${loadfdt}; then " \ > + "run nandloadfdt;" \ > + "fi; " \ > + "run doboot\0" \ > + "boot=mmc dev ${mmcdev}; " \ > + "if mmc rescan; then " \ > + "if run loadmmcbootscript; then " \ > + "run mmcbootscript;" \ > + "else " \ > + "if run mmcloadkernel; then " \ > + "if ${loadfdt}; then " \ > + "run mmcloadfdt;" \ > + "fi;" \ > + "run mmcboot;" \ > + "fi;" \ > + "fi;" \ > + "fi;" > + > +#define CONFIG_BOOTCOMMAND \ > + "run setboottypem; run boot" > + > +/* SPI */ > +#define CONFIG_SPI > +#define CONFIG_MXC_SPI > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_ATMEL > +#define CONFIG_SPI_FLASH_EON > +#define CONFIG_SPI_FLASH_GIGADEVICE > +#define CONFIG_SPI_FLASH_MACRONIX > +#define CONFIG_SPI_FLASH_SPANSION > +#define CONFIG_SPI_FLASH_STMICRO > +#define CONFIG_SPI_FLASH_SST > +#define CONFIG_SPI_FLASH_WINBOND > + > +/* GPIO */ > +#define CONFIG_MXC_GPIO > + > +/* Boot */ > +#define CONFIG_ZERO_BOOTDELAY_CHECK > +#define CONFIG_LOADADDR 0x10800000 > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > +#define CONFIG_SYS_TEXT_BASE 0x10800000 > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) > +#define CONFIG_SETUP_MEMORY_TAGS > +#define CONFIG_INITRD_TAG > + > +/* misc */ > +#define CONFIG_SYS_GENERIC_BOARD > +#define CONFIG_STACKSIZE (128 * 1024) > +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) > +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ > + > +/* SPL */ > +#define CONFIG_SPL > +#define CONFIG_SPL_FRAMEWORK > +#define CONFIG_SPL_BOARD_INIT > +#define CONFIG_SPL_STACK 0x0091FFB8 > +#define CONFIG_SPL_TEXT_BASE 0x00908000 > +#define CONFIG_SPL_BSS_START_ADDR 0x18200000 > +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 > +#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x03200000 > +#define CONFIG_SPL_MAX_SIZE (62 * 1024) > +#define CONFIG_SPL_LIBDISK_SUPPORT > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > +#define CONFIG_SPL_GPIO_SUPPORT > +#define CONFIG_SPL_SERIAL_SUPPORT > +#define CONFIG_SPL_MMC_SUPPORT > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */ > +#define CONFIG_SPL_SPI_SUPPORT > +#define CONFIG_SPL_SPI_FLASH_SUPPORT > +#define CONFIG_SPL_SPI_BUS CONFIG_SF_DEFAULT_BUS > +#define CONFIG_SPL_SPI_CS CONFIG_SF_DEFAULT_CS > +#define CONFIG_SPL_SPI_MODE CONFIG_SF_DEFAULT_MODE > +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) > +#define CONFIG_SPL_SPI_LOAD
Nikita,
Are the values in include/configs/imx6_spl.h too inflexible to use? If so, I can submit a patch in the future to remove that file and pull them all in my board config files as I'm the only user of it.
This is actually something I forgot to make use of when I was rebasing the code over mainline. I'll try to use it in a v2.
Regards,
Tim
On 04/08/14 17:24, Nikita Kiryanov wrote:
On 04/08/14 09:02, Tim Harvey wrote:
Nikita,
Are the values in include/configs/imx6_spl.h too inflexible to use? If so, I can submit a patch in the future to remove that file and pull them all in my board config files as I'm the only user of it.
This is actually something I forgot to make use of when I was rebasing the code over mainline. I'll try to use it in a v2.
I came across an unexpected problem when using imx6_spl.h. Due to the way the makefile is written, it is impossible to redefine imx6_spl.h's definition of CONFIG_SYS_TEXT_BASE using standard #undef/#define pair.
This happens because the makefile passes the CONFIG_SYS_TEXT_BASE define using the -D option to the compiler, and it clashes with the contents of common.h. For example:
The relevant code from Makefile: ifneq ($(CONFIG_SYS_TEXT_BASE),) KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) endif
The include hierarchy and contents of include/configs/someboard.h: include/common.h |---> include/config.h |---> include/configs/someboard.h #include "imx6_spl.h" #undef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE <NEW_VALUE>
During build: Makefile obtains CONFIG_SYS_TEXT_BASE <NEW_VALUE> and passes it to the compiler using: -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
For every file that #includes common.h we get this:
#define CONFIG_SYS_TEXT_BASE <NEW_VALUE> <-- from compiler #define CONFIG_SYS_TEXT_BASE 0x17800000 <-- from imx6_spl.h (redefinition!) #undef CONFIG_SYS_TEXT_BASE <-- from someboard.h #define CONFIG_SYS_TEXT_BASE <NEW_VALUE>
Sample output during compilation: include/configs/imx6_spl.h:68:0: warning: "CONFIG_SYS_TEXT_BASE" redefined [enabled by default] #define CONFIG_SYS_TEXT_BASE 0x17800000 ^ <command-line>:0:0: note: this is the location of the previous definition LD arch/arm/cpu/armv7/mx6/built-in.o CC arch/arm/lib/reset.o In file included from include/configs/cm_fx6.h:273:0, from include/config.h:10, from include/common.h:18, from arch/arm/lib/interrupts.c:22:
This goes on and on for quite a lot of files, and I wonder if passing -DCONFIG_SYS_TEXT_BASE to the compiler is even necessary. It looks like the includes already take care of bringing this value where it is needed.
I tried to remove KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) and run MAKEALL for arm boards, and most of them compiled without problems. Only these two boards failed: cam_enc_4xx, hawkboard.
Tom, any insight as to the necessity of this practice?
Add NAND support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_fx6/cm_fx6.c | 38 ++++++++++++++++++++++++++++++++++++++ board/compulab/cm_fx6/spl.c | 9 +++++++++ include/configs/cm_fx6.h | 14 ++++++++++++++ 3 files changed, 61 insertions(+)
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index b55b99e..6d37c21 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -9,10 +9,46 @@ */
#include <common.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> #include "common.h"
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void cm_fx6_setup_gpmi_nand(void) +{ + SETUP_IOMUX_PADS(nand_pads); + /* Enable clock roots */ + enable_usdhc_clk(1, 3); + enable_usdhc_clk(1, 4); + + setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); +} +#else +static void cm_fx6_setup_gpmi_nand(void) {} +#endif + #ifdef CONFIG_FSL_ESDHC int board_mmc_init(bd_t *bis) { @@ -33,6 +69,8 @@ int board_mmc_init(bd_t *bis) int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + cm_fx6_setup_gpmi_nand(); + return 0; }
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c index 9f9e5f8..5c432b4 100644 --- a/board/compulab/cm_fx6/spl.c +++ b/board/compulab/cm_fx6/spl.c @@ -15,6 +15,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> #include <asm/imx-common/iomux-v3.h> #include <fsl_esdhc.h> #include "common.h" @@ -355,7 +356,15 @@ static void cm_fx6_setup_ecspi(void) { }
void board_init_f(ulong dummy) { + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + gd = &gdata; + /* + * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot + * initializes DMA very early (before all board code), so the only + * opportunity we have to initialize APBHDMA clocks is in SPL. + */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); enable_usdhc_clk(1, 2); arch_cpu_init(); timer_init(); diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 285af33..973150f 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -179,6 +179,20 @@ #define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_WINBOND
+/* NAND */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_MXS +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* APBH DMA is required for NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + /* GPIO */ #define CONFIG_MXC_GPIO
Add ethernet support for Compulab CM-FX6 CoM
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_fx6/cm_fx6.c | 100 +++++++++++++++++++++++++++++++++++++++++ board/compulab/cm_fx6/common.h | 1 + include/configs/cm_fx6.h | 16 ++++++- 3 files changed, 115 insertions(+), 2 deletions(-)
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 6d37c21..d074af4 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -9,13 +9,100 @@ */
#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <fdt_support.h> #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <asm/gpio.h> #include "common.h"
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_FEC_MXC +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +static int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* Ar8031 phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= ~(0x1 << 8); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), +}; + +int board_eth_init(bd_t *bis) +{ + SETUP_IOMUX_PADS(enet_pads); + /* phy reset */ + gpio_direction_output(CM_FX6_ENET_NRST, 0); + udelay(500); + gpio_set_value(CM_FX6_ENET_NRST, 1); + enable_enet_clk(1); + return cpu_eth_init(bis); +} +#endif + #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t const nand_pads[] = { IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -66,6 +153,19 @@ int board_mmc_init(bd_t *bis) } #endif
+#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + uint8_t enetaddr[6]; + + /* MAC addr */ + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + fdt_find_and_setprop(blob, "/fec", "local-mac-address", + enetaddr, 6, 1); + } +} +#endif + int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h index 05eab34..94ff39e 100644 --- a/board/compulab/cm_fx6/common.h +++ b/board/compulab/cm_fx6/common.h @@ -15,6 +15,7 @@
#define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30) #define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8)
#if defined(CONFIG_FSL_ESDHC) #include <fsl_esdhc.h> diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 973150f..1923214 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -39,8 +39,6 @@ #undef CONFIG_CMD_XIMG #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS
/* MMC */ #define CONFIG_MMC @@ -193,6 +191,19 @@ #define CONFIG_APBH_DMA_BURST8 #endif
+/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RGMII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_ARP_TIMEOUT 200UL +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_NET_RETRY_COUNT 5 + /* GPIO */ #define CONFIG_MXC_GPIO
@@ -211,6 +222,7 @@ #define CONFIG_STACKSIZE (128 * 1024) #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_OF_BOARD_SETUP
/* SPL */ #define CONFIG_SPL
Add USB and USB OTG host support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_fx6/cm_fx6.c | 75 ++++++++++++++++++++++++++++++++++++++++++ board/compulab/cm_fx6/common.h | 3 ++ include/configs/cm_fx6.h | 10 ++++++ 3 files changed, 88 insertions(+)
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index d074af4..f8b3ad8 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -14,12 +14,87 @@ #include <fdt_support.h> #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/iomux.h> #include <asm/io.h> #include <asm/gpio.h> #include "common.h"
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_USB_EHCI_MX6 +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +static int cm_fx6_usb_hub_reset(void) +{ + int err; + + err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); + if (err) { + printf("USB hub rst gpio request failed: %d\n", err); + return -1; + } + + SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(CM_FX6_USB_HUB_RST, 0); + udelay(10); + gpio_direction_output(CM_FX6_USB_HUB_RST, 1); + mdelay(1); + + return 0; +} + +static void cm_fx6_init_usb_otg(void) +{ + int ret; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); + if (ret) + printf("USB OTG pwr gpio request failed: %d\n", ret); + + SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | + MUX_PAD_CTRL(WEAK_PULLDOWN)); + clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); + /* disable ext. charger detect, or it'll affect signal quality at dp. */ + gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); +} + +#define MX6_USBNC_BASEADDR 0x2184800 +#define USBNC_USB_H1_PWR_POL (1 << 9) +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); + u32 val; + + switch (port) { + case 0: + cm_fx6_init_usb_otg(); + break; + case 1: + SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | + MUX_PAD_CTRL(NO_PAD_CTRL)); + + /* Set PWR polarity to match power switch's enable polarity */ + val = __raw_readl(usbnc_usb_uh1_ctrl); + val |= USBNC_USB_H1_PWR_POL; + __raw_writel(val, usbnc_usb_uh1_ctrl); + return cm_fx6_usb_hub_reset(); + default: + break; + } + + return 0; +} + +int board_ehci_power(int port, int on) +{ + return port ? 0 : gpio_direction_output(SB_FX6_USB_OTG_PWR, on); +} +#endif + #ifdef CONFIG_FEC_MXC #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h index 94ff39e..bd04d62 100644 --- a/board/compulab/cm_fx6/common.h +++ b/board/compulab/cm_fx6/common.h @@ -16,6 +16,9 @@ #define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30) #define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31) #define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) +#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22)
#if defined(CONFIG_FSL_ESDHC) #include <fsl_esdhc.h> diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 1923214..7ad2eb9 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -204,6 +204,16 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NET_RETRY_COUNT 5
+/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ + /* GPIO */ #define CONFIG_MXC_GPIO
Add support for all 3 I2C busses on Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_fx6/cm_fx6.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/configs/cm_fx6.h | 11 +++++++++++ 2 files changed, 53 insertions(+)
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index f8b3ad8..194b2ed 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -15,12 +15,53 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/arch/iomux.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/io.h> #include <asm/gpio.h> #include "common.h"
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_I2C_MXC +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +I2C_PADS(i2c0_pads, + PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(3, 21), + PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(3, 28)); + +I2C_PADS(i2c1_pads, + PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(4, 12), + PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(4, 13)); + +I2C_PADS(i2c2_pads, + PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(1, 3), + PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(1, 6)); + + +static void cm_fx6_setup_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads)); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads)); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads)); +} +#else +static void cm_fx6_setup_i2c(void) { } +#endif + #ifdef CONFIG_USB_EHCI_MX6 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ @@ -245,6 +286,7 @@ int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; cm_fx6_setup_gpmi_nand(); + cm_fx6_setup_i2c();
return 0; } diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 7ad2eb9..fd0210e 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -214,6 +214,17 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 2 + /* GPIO */ #define CONFIG_MXC_GPIO
Use Compulab eeprom module to obtain revision number, serial number, and mac address from the EEPROM.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_fx6/cm_fx6.c | 26 +++++++++++++++++++++++++- include/configs/cm_fx6.h | 2 ++ 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 194b2ed..d06b00e 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -19,6 +19,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include "common.h" +#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -207,8 +208,31 @@ static iomux_v3_cfg_t const enet_pads[] = { MUX_PAD_CTRL(ENET_PAD_CTRL)), };
+static int handle_mac_address(void) +{ + unsigned char enetaddr[6]; + int rc; + + rc = eth_getenv_enetaddr("ethaddr", enetaddr); + if (rc) + return 0; + + rc = cl_eeprom_read_mac_addr(enetaddr); + if (rc) + return rc; + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("ethaddr", enetaddr); +} + int board_eth_init(bd_t *bis) { + int res = handle_mac_address(); + if (res) + puts("No MAC address found\n"); + SETUP_IOMUX_PADS(enet_pads); /* phy reset */ gpio_direction_output(CM_FX6_ENET_NRST, 0); @@ -359,5 +383,5 @@ int dram_init(void)
u32 get_board_rev(void) { - return 100; + return cl_eeprom_get_board_rev(); } diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index fd0210e..b49fd29 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -237,6 +237,8 @@ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG
/* misc */ #define CONFIG_SYS_GENERIC_BOARD
Add support for SATA.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_fx6/cm_fx6.c | 90 ++++++++++++++++++++++++++++++++++++++++++ board/compulab/cm_fx6/common.h | 13 ++++++ include/configs/cm_fx6.h | 36 ++++++++++++++++- 3 files changed, 138 insertions(+), 1 deletion(-)
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index d06b00e..fe80376 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -12,10 +12,12 @@ #include <miiphy.h> #include <netdev.h> #include <fdt_support.h> +#include <sata.h> #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/arch/iomux.h> #include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/sata.h> #include <asm/io.h> #include <asm/gpio.h> #include "common.h" @@ -23,6 +25,94 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_DWC_AHSATA +static int cm_fx6_issd_gpios[] = { + /* The order of the GPIOs in the array is important! */ + CM_FX6_SATA_PHY_SLP, + CM_FX6_SATA_NRSTDLY, + CM_FX6_SATA_PWREN, + CM_FX6_SATA_NSTANDBY1, + CM_FX6_SATA_NSTANDBY2, + CM_FX6_SATA_LDO_EN, +}; + +static void cm_fx6_sata_power(int on) +{ + int i; + + if (!on) { /* tell the iSSD that the power will be removed */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); + mdelay(10); + } + + for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { + gpio_direction_output(cm_fx6_issd_gpios[i], on); + udelay(100); + } + + if (!on) /* for compatibility lower the power loss interrupt */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); +} + +static iomux_v3_cfg_t const sata_pads[] = { + /* SATA PWR */ + IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* SATA CTRL */ + IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), + +}; + +static void cm_fx6_setup_issd(void) +{ + SETUP_IOMUX_PADS(sata_pads); + /* Make sure this gpio has logical 0 value */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); + udelay(100); + + cm_fx6_sata_power(0); + mdelay(250); + cm_fx6_sata_power(1); +} + +#define CM_FX6_SATA_INIT_RETRIES 10 +int sata_initialize(void) +{ + int err, i; + + cm_fx6_setup_issd(); + for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { + err = setup_sata(); + if (err) { + printf("SATA setup failed: %d\n", err); + return err; + } + + udelay(100); + + err = __sata_initialize(); + if (!err) + break; + + /* There is no device on the SATA port */ + if (sata_port_status(0, 0) == 0) + break; + + /* There's a device, but link not established. Retry */ + } + + return err; +} +#else +static void cm_fx6_setup_issd(void) {} +#endif + #ifdef CONFIG_SYS_I2C_MXC #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h index bd04d62..ddccffb 100644 --- a/board/compulab/cm_fx6/common.h +++ b/board/compulab/cm_fx6/common.h @@ -19,6 +19,19 @@ #define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) #define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) #define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) +#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define CM_FX6_SATA_PWREN IMX_GPIO_NR(1, 28) +#define CM_FX6_SATA_VDDC_CTRL IMX_GPIO_NR(1, 30) +#define CM_FX6_SATA_LDO_EN IMX_GPIO_NR(2, 16) +#define CM_FX6_SATA_NSTANDBY1 IMX_GPIO_NR(3, 20) +#define CM_FX6_SATA_PHY_SLP IMX_GPIO_NR(3, 23) +#define CM_FX6_SATA_STBY_REQ IMX_GPIO_NR(3, 29) +#define CM_FX6_SATA_NSTANDBY2 IMX_GPIO_NR(5, 2) +#define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6) +#define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31) +
#if defined(CONFIG_FSL_ESDHC) #include <fsl_esdhc.h> diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index b49fd29..8021299 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -133,6 +133,19 @@ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "run doboot\0" \ + "satadev=0\0" \ + "sataroot=/dev/sda2 rw rootwait\0" \ + "sataargs=setenv bootargs console=${console} " \ + "root=${sataroot} " \ + "${video}\0" \ + "loadsatabootscript=fatload sata ${satadev} ${loadaddr} ${bootscr}\0" \ + "satabootscript=echo Running bootscript from sata ...; " \ + "source ${loadaddr}\0" \ + "sataloadkernel=fatload sata ${satadev} ${loadaddr} ${kernel}\0" \ + "sataloadfdt=fatload sata ${satadev} ${fdtaddr} ${fdtfile}\0" \ + "sataboot=echo Booting from sata ...; "\ + "run sataargs; " \ + "run doboot\0" \ "nandroot=/dev/mtdblock4 rw\0" \ "nandrootfstype=ubifs\0" \ "nandargs=setenv bootargs console=${console} " \ @@ -159,7 +172,19 @@ "run mmcboot;" \ "fi;" \ "fi;" \ - "fi;" + "fi;" \ + "if sata init; then " \ + "if run loadsatabootscript; then " \ + "run satabootscript;" \ + "else "\ + "if run sataloadkernel; then " \ + "if ${loadfdt}; then " \ + "run sataloadfdt; " \ + "fi;" \ + "run sataboot;" \ + "fi;" \ + "fi;" \ + "fi;\0"
#define CONFIG_BOOTCOMMAND \ "run setboottypem; run boot" @@ -225,6 +250,15 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_BUS 2
+/* SATA */ +#define CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_LIBATA +#define CONFIG_LBA48 +#define CONFIG_DWC_AHSATA +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + /* GPIO */ #define CONFIG_MXC_GPIO
On Sunday, August 03, 2014 at 09:34:48 AM, Nikita Kiryanov wrote:
Add support for SATA.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
I'd just squash all the cf_mx6 patches into the "add cf_mx6 board" patch.
Best regards, Marek Vasut
Hi Marek,
On 08/03/14 17:10, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:48 AM, Nikita Kiryanov wrote:
Add support for SATA.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
I'd just squash all the cf_mx6 patches into the "add cf_mx6 board" patch.
Well, I tend to disagree on this. I find extremely hard to review the "long long squashed into one patch" patches. It is much easier to review small, functionality oriented, patches.
On Monday, August 04, 2014 at 09:23:12 AM, Igor Grinberg wrote:
Hi Marek,
On 08/03/14 17:10, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:48 AM, Nikita Kiryanov wrote:
Add support for SATA.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
I'd just squash all the cf_mx6 patches into the "add cf_mx6 board" patch.
Well, I tend to disagree on this. I find extremely hard to review the "long long squashed into one patch" patches. It is much easier to review small, functionality oriented, patches.
You do have a valid point when it comes to review, all right. There's no point in keeping them separate when they're applied though. Tough decisions this is. Let's see what others think then .
Best regards, Marek Vasut
On 08/04/14 11:27, Marek Vasut wrote:
On Monday, August 04, 2014 at 09:23:12 AM, Igor Grinberg wrote:
Hi Marek,
On 08/03/14 17:10, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:48 AM, Nikita Kiryanov wrote:
Add support for SATA.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
I'd just squash all the cf_mx6 patches into the "add cf_mx6 board" patch.
Well, I tend to disagree on this. I find extremely hard to review the "long long squashed into one patch" patches. It is much easier to review small, functionality oriented, patches.
You do have a valid point when it comes to review, all right. There's no point in keeping them separate when they're applied though. Tough decisions this is.
When it comes to keeping them separate when applied, I'd disagree also... Keeping the changes small and functionality oriented helps: a) bisect-ability and blaming/reverting granularity b) gives an opportunity to better explain the change in the commit message c) easier fixing of merge conflicts (if any) d) learning curve for new developers in the log (as to how to add features/fix bugs) e) a bit more burden on maintainers ;-)
On Monday, August 04, 2014 at 12:47:38 PM, Igor Grinberg wrote:
On 08/04/14 11:27, Marek Vasut wrote:
On Monday, August 04, 2014 at 09:23:12 AM, Igor Grinberg wrote:
Hi Marek,
On 08/03/14 17:10, Marek Vasut wrote:
On Sunday, August 03, 2014 at 09:34:48 AM, Nikita Kiryanov wrote:
Add support for SATA.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il
I'd just squash all the cf_mx6 patches into the "add cf_mx6 board" patch.
Well, I tend to disagree on this. I find extremely hard to review the "long long squashed into one patch" patches. It is much easier to review small, functionality oriented, patches.
You do have a valid point when it comes to review, all right. There's no point in keeping them separate when they're applied though. Tough decisions this is.
When it comes to keeping them separate when applied, I'd disagree also... Keeping the changes small and functionality oriented helps: a) bisect-ability and blaming/reverting granularity b) gives an opportunity to better explain the change in the commit message c) easier fixing of merge conflicts (if any) d) learning curve for new developers in the log (as to how to add features/fix bugs) e) a bit more burden on maintainers ;-)
I cannot disagree with neither ;-) Let's go with the split approach then
Best regards, Marek Vasut
participants (6)
-
Igor Grinberg -
Marek Vasut -
Nikita Kiryanov -
Stefano Babic -
Tim Harvey -
Tom Rini