Some devices (e.g. the RK3368) have only limited SRAM, but provide support for loading the next boot stage after our SPL performs basic setup (e.g. DRAM).

For target systems like these, we add a boot device BOOTROM that will invoke a board-specific hook to return to the bootrom (if supported).

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Tom Rini trini@konsulko.com Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

arch/arm/include/asm/spl.h | 1 + common/spl/Kconfig | 11 +++++++++++ common/spl/Makefile | 1 + common/spl/spl_bootrom.c | 27 +++++++++++++++++++++++++++ include/spl.h | 10 ++++++++++ 5 files changed, 50 insertions(+) create mode 100644 common/spl/spl_bootrom.c

diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 0e67470..df45511 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -30,6 +30,7 @@ enum { BOOT_DEVICE_BOARD, BOOT_DEVICE_DFU, BOOT_DEVICE_XIP, + BOOT_DEVICE_BOOTROM, BOOT_DEVICE_NONE }; #endif diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 4de8139..ee767b7 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -25,6 +25,17 @@ config SPL_BOARD_INIT spl_board_init() from board_init_r(). This function should be provided by the board.

+config SPL_BOOTROM_SUPPORT + bool "Support returning to the BOOTROM" + help + Some platforms (e.g. the Rockchip RK3368) provide support in their + ROM for loading the next boot-stage after performing basic setup + from the SPL stage. + + Enable this option, to return to the BOOTROM through the + BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the + boot device list, if not implemented for a given board) + config SPL_RAW_IMAGE_SUPPORT bool "Support SPL loading and booting of RAW images" default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) diff --git a/common/spl/Makefile b/common/spl/Makefile index 47a64dd..189b272 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -10,6 +10,7 @@

ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o +obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_bootrom.o obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o diff --git a/common/spl/spl_bootrom.c b/common/spl/spl_bootrom.c new file mode 100644 index 0000000..6804246 --- /dev/null +++ b/common/spl/spl_bootrom.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +__weak void board_return_to_bootrom(void) +{ +} + +static int spl_return_to_bootrom(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + /* + * If the board implements a way to return to its ROM (with + * the expectation that the next stage of will be booted by + * the ROM), it will implement board_return_to_bootrom() and + * should not return from it. + */ + board_return_to_bootrom(); + return false; +} + +SPL_LOAD_IMAGE_METHOD("BOOTROM", 0, BOOT_DEVICE_BOOTROM, spl_return_to_bootrom); diff --git a/include/spl.h b/include/spl.h index ccb1404..b5c2994 100644 --- a/include/spl.h +++ b/include/spl.h @@ -278,4 +278,14 @@ int spl_mmc_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev);

void bl31_entry(void); + +/** + * board_return_to_bootrom - allow for boards to continue with the boot ROM + * + * If a board (e.g. the Rockchip RK3368 boards) provide some + * supporting functionality for SPL in their boot ROM and the SPL + * stage wants to return to the ROM code to continue booting, boards + * can implement 'board_return_to_bootrom'. + */ +void board_return_to_bootrom(void); #endif

The back-to-bootrom support for Rockchip is equivalent to an (assembly) implementation of setjmp/longjmp (i.e. it saves the stack-pointer, link-register and callee-saved registers). Up until now, this had only been implemented for AArch32 (i.e. ARMv7 or older), which puts the new ARMv8 devices (which boot in AArch64 mode) at a slight disadvantage.

To allow use of the 'back-to-bootrom' feature on new devices (e.g. the RK3368), this commit adds an implementation for AArch64.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com ---

Changes in v3: None Changes in v2: None

arch/arm/mach-rockchip/save_boot_param.S | 37 ++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S index 5e6c8db..945a9dd 100644 --- a/arch/arm/mach-rockchip/save_boot_param.S +++ b/arch/arm/mach-rockchip/save_boot_param.S @@ -1,11 +1,47 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */

#include <linux/linkage.h>

+#if defined(CONFIG_ARM64) +.globl SAVE_SP_ADDR +SAVE_SP_ADDR: + .quad 0 + +ENTRY(save_boot_params) + sub sp, sp, #0x100 + stp x29, x30, [sp, #0x50] + stp x27, x28, [sp, #0x40] + stp x25, x26, [sp, #0x30] + stp x23, x24, [sp, #0x20] + stp x21, x22, [sp, #0x10] + stp x19, x20, [sp, #0] + ldr x8, =SAVE_SP_ADDR + mov x9, sp + str x9, [x8] + b save_boot_params_ret /* back to my caller */ +ENDPROC(save_boot_params) + +.globl _back_to_bootrom_s +ENTRY(_back_to_bootrom_s) + ldr x0, =SAVE_SP_ADDR + ldr x0, [x0] + mov sp, x0 + ldp x29, x30, [sp, #0x50] + ldp x27, x28, [sp, #0x40] + ldp x25, x26, [sp, #0x30] + ldp x23, x24, [sp, #0x20] + ldp x21, x22, [sp, #0x10] + ldp x19, x20, [sp] + add sp, sp, #0x100 + mov x0, xzr + ret +ENDPROC(_back_to_bootrom_s) +#else .globl SAVE_SP_ADDR SAVE_SP_ADDR: .word 0 @@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s) mov r0, #0 pop {r1-r12, pc} ENDPROC(_back_to_bootrom_s) +#endif

With the finer-grained control over LIBGENERIC_SUPPORT for TPL/SPL (i.e. with the newly introduced distinction between TPL_LIBGENERIC_SUPPORT and SPL_LIBGENERIC_SUPPORT), we can simplify the #ifdef-check to simply use CONFIG_IS_ENABELD.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com ---

Changes in v3: None Changes in v2: None

arch/arm/mach-rockchip/bootrom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index 4ca9962..4d38ed6 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -9,8 +9,8 @@

void back_to_bootrom(void) { -#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD) - puts("Returning to boot ROM..."); +#if CONFIG_IS_ENABLED(LIBGENERIC_SUPPORT) + printf("Returning to boot ROM...\n"); #endif _back_to_bootrom_s(); }

The (upstream) changes to break up SYS_MALLOC_F_LEN for the full U-Boot and the SPL stage, break TPL (if simple malloc is enabled in TPL).

This adds support for a TPL-variant of SYS_MALLOC_F_LEN: - adds TPL_SYS_MALLOC_F_LEN - rewrites a test for CONFIG_SPL_SYS_MALLOC_F_LEN to access CONFIG_VAL(SYS_MALLOC_F_LEN)

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Version-changes: 3 - (new patch) adds changes to SYS_MALLOC_F_LEN for TPL to fix breakage from rebasing to u-boot-rockchip/master

---

Changes in v3: None Changes in v2: None

Kconfig | 12 +++++++++++- common/spl/spl.c | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/Kconfig b/Kconfig index c1451bc..27c64fe 100644 --- a/Kconfig +++ b/Kconfig @@ -96,7 +96,17 @@ config SYS_MALLOC_F_LEN initial serial device and any others that are needed.

config SPL_SYS_MALLOC_F_LEN - hex "Size of malloc() pool in spl before relocation" + hex "Size of malloc() pool in SPL before relocation" + depends on SYS_MALLOC_F + default SYS_MALLOC_F_LEN + help + Before relocation, memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. Driver model in + particular needs this to operate, so that it can allocate the + initial serial device and any others that are needed. + +config TPL_SYS_MALLOC_F_LEN + hex "Size of malloc() pool in TPL before relocation" depends on SYS_MALLOC_F default SYS_MALLOC_F_LEN help diff --git a/common/spl/spl.c b/common/spl/spl.c index b61993f..c84ffd8 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -487,7 +487,7 @@ ulong spl_relocate_stack_gd(void) gd_t *new_gd; ulong ptr = CONFIG_SPL_STACK_R_ADDR;

-#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_SPL_SYS_MALLOC_F_LEN +#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_VAL(SYS_MALLOC_F_LEN) if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) { ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN; gd->malloc_base = ptr;

TPL_NAND_SUPPORT, TPL_SERIAL_SUPPORT, TPL_SPI_FLASH_SUPPORT and TPL_SPI_SUPPORT refer to SPL in their help text. This fixes up the description to correctly reference TPL.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

---

Changes in v3: - (new patch) added fix-up of SPL/TPL confusion in help text

Changes in v2: None

common/spl/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index dd94801..8ce9c39 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -717,7 +717,7 @@ config TPL_ENV_SUPPORT config TPL_I2C_SUPPORT bool "Support I2C" help - Enable support for the I2C bus in SPL. See SPL_I2C_SUPPORT for + Enable support for the I2C bus in TPL. See SPL_I2C_SUPPORT for details.

config TPL_LIBCOMMON_SUPPORT @@ -747,24 +747,24 @@ config TPL_MMC_SUPPORT config TPL_NAND_SUPPORT bool "Support NAND flash" help - Enable support for NAND in SPL. See SPL_NAND_SUPPORT for details. + Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details.

config TPL_SERIAL_SUPPORT bool "Support serial" help - Enable support for serial in SPL. See SPL_SERIAL_SUPPORT for + Enable support for serial in TPL. See SPL_SERIAL_SUPPORT for details.

config TPL_SPI_FLASH_SUPPORT bool "Support SPI flash drivers" help - Enable support for using SPI flash in SPL. See SPL_SPI_FLASH_SUPPORT + Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT for details.

config TPL_SPI_SUPPORT bool "Support SPI drivers" help - Enable support for using SPI in SPL. See SPL_SPI_SUPPORT for + Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for details.

endif # TPL

SPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a stricter dependency of SPL_DM was possible. This commit makes the prereq more specific.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com ---

Changes in v3: None Changes in v2: None

drivers/core/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index f8b19a4..79a25c6 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -97,7 +97,7 @@ config REGMAP

config SPL_REGMAP bool "Support register maps in SPL" - depends on DM + depends on SPL_DM help Hardware peripherals tend to have one or more sets of registers which can be accessed to control the hardware. A register map @@ -116,7 +116,7 @@ config SYSCON

config SPL_SYSCON bool "Support system controllers in SPL" - depends on REGMAP + depends on SPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided

This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com ---

Changes in v3: None Changes in v2: None

drivers/ram/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 61afd7a..e75c23f 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -10,7 +10,7 @@ config RAM

config SPL_RAM bool "Enable RAM support in SPL" - depends on RAM + depends on RAM && SPL_DM help The RAM subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use RAM drivers in

SPL_CLK should also depend on SPL_DM (and not just on CLK). Add the additional dependency.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com ---

Changes in v3: None Changes in v2: None

drivers/clk/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 44da716..9c13587 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -12,7 +12,7 @@ config CLK

config SPL_CLK bool "Enable clock support in SPL" - depends on CLK + depends on CLK && SPL_DM help The clock subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use clock drivers in

For the RK3368, we want to use OF_PLATDATA in TPL, but full OF_CONTROL in SPL: this requires the introduction of a new family of configuration options to decouple SPL_OF_CONTROL and SPL_OF_PLATDATA from TPL.

Consequently, Makefile.spl needs to be adjusted to test for these configuration items through the $(SPL_TPL_) macro instead of hard-coding the SPL variant.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com ---

Changes in v3: None Changes in v2: None

Makefile | 2 +- dts/Kconfig | 29 +++++++++++++++++++++++++++++ scripts/Makefile.spl | 4 ++-- 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile index 3d2b66a..8d19a03 100644 --- a/Makefile +++ b/Makefile @@ -1398,7 +1398,7 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE spl/u-boot-spl.bin: spl/u-boot-spl @: spl/u-boot-spl: tools prepare \ - $(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),dts/dt.dtb) $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all

spl/sunxi-spl.bin: spl/u-boot-spl diff --git a/dts/Kconfig b/dts/Kconfig index 1bc9656..b4b7ddc 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -32,6 +32,14 @@ config SPL_OF_CONTROL which is not enough to support device tree. Enable this option to allow such boards to be supported by U-Boot SPL.

+config TPL_OF_CONTROL + bool "Enable run-time configuration via Device Tree in TPL" + depends on TPL && OF_CONTROL + help + Some boards use device tree in U-Boot but only have 4KB of SRAM + which is not enough to support device tree. Enable this option to + allow such boards to be supported by U-Boot TPL. + config OF_LIVE bool "Enable use of a live tree" depends on OF_CONTROL @@ -136,4 +144,25 @@ config SPL_OF_PLATDATA declarations for each node. See README.platdata for more information.

+config TPL_OF_PLATDATA + bool "Generate platform data for use in TPL" + depends on TPL_OF_CONTROL + help + For very constrained SPL environments the overhead of decoding + device tree nodes and converting their contents into platform data + is too large. This overhead includes libfdt code as well as the + device tree contents itself. The latter is fairly compact, but the + former can add 3KB or more to a Thumb 2 Image. + + This option enables generation of platform data from the device + tree as C code. This code creates devices using U_BOOT_DEVICE() + declarations. The benefit is that it allows driver code to access + the platform data directly in C structures, avoidin the libfdt + overhead. + + This option works by generating C structure declarations for each + compatible string, then adding platform data and U_BOOT_DEVICE + declarations for each node. See README.platdata for more + information. + endmenu diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index ac3c2c7..3e35cd6 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -98,7 +98,7 @@ endif

u-boot-spl-init := $(head-y) u-boot-spl-main := $(libs-y) -ifdef CONFIG_SPL_OF_PLATDATA +ifdef CONFIG_$(SPL_TPL_)OF_PLATDATA u-boot-spl-platdata := $(obj)/dts/dt-platdata.o endif

@@ -202,7 +202,7 @@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@ quiet_cmd_copy = COPY $@ cmd_copy = cp $< $@

-ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy) +ifeq ($(CONFIG_$(SPL_TPL_)OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ $(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ $(obj)/$(SPL_BIN).dtb FORCE

TPL builds today don't need to call into firmware or set up the MMU (if this changes, it should be controlled through a config option whether to include this or not), but include the needed support code for this anyway. By moving these unused low-level functions into seperate function-sections, the linker can garbage-collect the unused sections.

Note that (if DM support is enabled), there will be a call to the cache-flushing code from alloc_priv(...) in drivers/core/device.c. This then add 52 bytes of binary size (an increase from 20589 to 20641 bytes) compared to completely removing this code.

Even for a feature-rich TPL (including DM support as for the RK3368), this equates to a size difference of significantly more than 10% in TPL binary size.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

---

Changes in v3: - change to use function-sections (instead of disabling at the Makefile-level for TPL builds) per Tom's suggestion

Changes in v2: None

arch/arm/cpu/armv8/Makefile | 2 +- arch/arm/cpu/armv8/cache.S | 22 ++++++++++++++++++++++ arch/arm/cpu/armv8/tlb.S | 4 +++- arch/arm/cpu/armv8/transition.S | 6 ++++++ 4 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index c447085..64f35f1 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -10,11 +10,11 @@ extra-y := start.o obj-y += cpu.o obj-y += generic_timer.o obj-y += cache_v8.o -obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o obj-y += fwcall.o +obj-y += exceptions.o obj-y += cpu-dt.o obj-$(CONFIG_ARM_SMCCC) += smccc-call.o

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 7cba308..ea845d1 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -22,6 +22,7 @@ * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ +.pushsection .text.__asm_dcache_level, "ax" ENTRY(__asm_dcache_level) lsl x12, x0, #1 msr csselr_el1, x12 /* select cache level */ @@ -58,6 +59,7 @@ loop_way:

ret ENDPROC(__asm_dcache_level) +.popsection

/* * void __asm_flush_dcache_all(int invalidate_only) @@ -66,6 +68,7 @@ ENDPROC(__asm_dcache_level) * * flush or invalidate all data cache by SET/WAY. */ +.pushsection .text.__asm_dcache_all, "ax" ENTRY(__asm_dcache_all) mov x1, x0 dsb sy @@ -102,16 +105,21 @@ skip: finished: ret ENDPROC(__asm_dcache_all) +.popsection

+.pushsection .text.__asm_flush_dcache_all, "ax" ENTRY(__asm_flush_dcache_all) mov x0, #0 b __asm_dcache_all ENDPROC(__asm_flush_dcache_all) +.popsection

+.pushsection .text.__asm_invalidate_dcache_all, "ax" ENTRY(__asm_invalidate_dcache_all) mov x0, #0x1 b __asm_dcache_all ENDPROC(__asm_invalidate_dcache_all) +.popsection

/* * void __asm_flush_dcache_range(start, end) @@ -121,6 +129,7 @@ ENDPROC(__asm_invalidate_dcache_all) * x0: start address * x1: end address */ +.pushsection .text.__asm_flush_dcache_range, "ax" ENTRY(__asm_flush_dcache_range) mrs x3, ctr_el0 lsr x3, x3, #16 @@ -138,6 +147,7 @@ ENTRY(__asm_flush_dcache_range) dsb sy ret ENDPROC(__asm_flush_dcache_range) +.popsection /* * void __asm_invalidate_dcache_range(start, end) * @@ -146,6 +156,7 @@ ENDPROC(__asm_flush_dcache_range) * x0: start address * x1: end address */ +.pushsection .text.__asm_invalidate_dcache_range, "ax" ENTRY(__asm_invalidate_dcache_range) mrs x3, ctr_el0 ubfm x3, x3, #16, #19 @@ -162,41 +173,51 @@ ENTRY(__asm_invalidate_dcache_range) dsb sy ret ENDPROC(__asm_invalidate_dcache_range) +.popsection

/* * void __asm_invalidate_icache_all(void) * * invalidate all tlb entries. */ +.pushsection .text.__asm_invalidate_icache_all, "ax" ENTRY(__asm_invalidate_icache_all) ic ialluis isb sy ret ENDPROC(__asm_invalidate_icache_all) +.popsection

+.pushsection .text.__asm_invalidate_l3_dcache, "ax" ENTRY(__asm_invalidate_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_dcache) .weak __asm_invalidate_l3_dcache +.popsection

+.pushsection .text.__asm_flush_l3_dcache, "ax" ENTRY(__asm_flush_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_flush_l3_dcache) .weak __asm_flush_l3_dcache +.popsection

+.pushsection .text.__asm_invalidate_l3_icache, "ax" ENTRY(__asm_invalidate_l3_icache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_icache) .weak __asm_invalidate_l3_icache +.popsection

/* * void __asm_switch_ttbr(ulong new_ttbr) * * Safely switches to a new page table. */ +.pushsection .text.__asm_switch_ttbr, "ax" ENTRY(__asm_switch_ttbr) /* x2 = SCTLR (alive throghout the function) */ switch_el x4, 3f, 2f, 1f @@ -244,3 +265,4 @@ ENTRY(__asm_switch_ttbr)

ret x3 ENDPROC(__asm_switch_ttbr) +.popsection diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S index 945445b..6743111 100644 --- a/arch/arm/cpu/armv8/tlb.S +++ b/arch/arm/cpu/armv8/tlb.S @@ -14,7 +14,8 @@ * void __asm_invalidate_tlb_all(void) * * invalidate all tlb entries. - */ +*/ +.pushsection .text.__asm_invalidate_tlb_all, "ax" ENTRY(__asm_invalidate_tlb_all) switch_el x9, 3f, 2f, 1f 3: tlbi alle3 @@ -31,3 +32,4 @@ ENTRY(__asm_invalidate_tlb_all) 0: ret ENDPROC(__asm_invalidate_tlb_all) +.popsection diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index ca07465..7aa6935 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -10,6 +10,7 @@ #include <linux/linkage.h> #include <asm/macro.h>

+.pushsection .text.armv8_switch_to_el2, "ax" ENTRY(armv8_switch_to_el2) switch_el x6, 1f, 0f, 0f 0: @@ -30,7 +31,9 @@ ENTRY(armv8_switch_to_el2) br x4 1: armv8_switch_to_el2_m x4, x5, x6 ENDPROC(armv8_switch_to_el2) +.popsection

+.pushsection .text.armv8_switch_to_el1, "ax" ENTRY(armv8_switch_to_el1) switch_el x6, 0f, 1f, 0f 0: @@ -40,7 +43,10 @@ ENTRY(armv8_switch_to_el1) br x4 1: armv8_switch_to_el1_m x4, x5, x6 ENDPROC(armv8_switch_to_el1) +.popsection

+.pushsection .text.armv8_el2_to_aarch32, "ax" WEAK(armv8_el2_to_aarch32) ret ENDPROC(armv8_el2_to_aarch32) +.popsection

To allow a TPL and SPL to run from different addresses/memories, we need to split setup of the TPL and SPL stacks. To do so, we introduce CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override the initial stack pointer for TPL.

To provide backward compatibility for existing boards, this is added as an optional configuration item and the normal search order (i.e. SPL_STACK, then SYS_STACK) apply if not defined.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com ---

Changes in v3: None Changes in v2: None

arch/arm/lib/crt0_64.S | 4 +++- scripts/config_whitelist.txt | 1 + 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 57e728f..177b5bf 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -69,7 +69,9 @@ ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_STACK) + ldr x0, =(CONFIG_TPL_STACK) +#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) #else ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 93f0bf4..0a06dff 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4983,6 +4983,7 @@ CONFIG_TI_SPI_MMAP CONFIG_TMU_TIMER CONFIG_TPL_DRIVERS_MISC_SUPPORT CONFIG_TPL_PAD_TO +CONFIG_TPL_STACK CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPS6586X_POWER CONFIG_TQM834X

This splits the compilation of code modules for TPL and SPL for OF_CONTROL (and related) features between TPL and SPL. The typical use-case of this is a TPL stage that uses OF_PLATDATA at TPL and provides full OF_CONTROL at SPL (e.g. on the RK3368).

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com ---

Changes in v3: None Changes in v2: None

lib/Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/lib/Makefile b/lib/Makefile index eacc7d6..2eef1eb 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -49,11 +49,11 @@ obj-$(CONFIG_RSA) += rsa/ obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o

-obj-$(CONFIG_SPL_SAVEENV) += qsort.o -obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/ -ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy) -obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o -obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o +obj-$(CONFIG_$(SPL_TPL_)SAVEENV) += qsort.o +obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ +ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) +obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o +obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o endif

ifdef CONFIG_SPL_BUILD

This adds the TPL_DRIVER_MISC_SUPPORT option to allow activation of DRIVER_MISC_SUPPORT for devices that need it in the TPL stage.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com

Version-changes: 3 - removes TPL_MISC_DRIVERS_SUPPORT from the whitelist

---

Changes in v3: None Changes in v2: None

common/spl/Kconfig | 8 ++++++++ scripts/config_whitelist.txt | 1 - 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ad7747e..64f9e1f 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -718,6 +718,14 @@ config TPL_BOOTROM_SUPPORT BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the boot device list, if not implemented for a given board)

+config TPL_DRIVERS_MISC_SUPPORT + bool "Support misc drivers in TPL" + help + Enable miscellaneous drivers in TPL. These drivers perform various + tasks that don't fall nicely into other categories, Enable this + option to build the drivers in drivers/misc as part of an TPL + build, for those that support building in TPL (not all drivers do). + config TPL_ENV_SUPPORT bool "Support an environment" help diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e2f1797..ee3fcd0 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4981,7 +4981,6 @@ CONFIG_TI_KEYSTONE_SERDES CONFIG_TI_KSNAV CONFIG_TI_SPI_MMAP CONFIG_TMU_TIMER -CONFIG_TPL_DRIVERS_MISC_SUPPORT CONFIG_TPL_LDSCRIPT CONFIG_TPL_MAX_SIZE CONFIG_TPL_PAD_TO

The utility functions in sdram_common.c will be useful both for some SPL implementations (and if unused, the linked will discard these anyway) and for the full U-Boot stage.

This changes selects sdram_common.o through the $(SPL_TPL_) macro to allow better control of its inclusion through the CONFIG_ROM, CONFIG_SPL_RAM or CONFIG_TPL_RAM options.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

arch/arm/mach-rockchip/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index cb8d3ef..8a3cb9f 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -5,6 +5,7 @@ #

obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o +obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o

ifdef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o @@ -21,9 +22,6 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o -ifdef CONFIG_RAM -obj-y += sdram_common.o -endif endif ifndef CONFIG_ARM64 obj-y += rk_timer.o

This commit adds support for RK3368 SoC in mkimage.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

tools/rkcommon.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 25b0340..04e8272 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -77,6 +77,7 @@ static struct spl_info spl_infos[] = { { "rk322x", "RK32", 0x8000 - 0x1000, false, false }, { "rk3288", "RK32", 0x8000, false, false }, { "rk3328", "RK32", 0x8000 - 0x1000, false, false }, + { "rk3368", "RK33", 0x8000 - 0x1000, false, true }, { "rk3399", "RK33", 0x30000 - 0x2000, false, true }, { "rv1108", "RK11", 0x1800, false, false}, };

The BootROM of the RK3368 Boot ROM does not initialise cntfrq_el0. This change defines COUNTER_FREQUENCY, which is used by the AArch64 init code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0.

If the counter-frequency is not correctly set up, the calculation of delays using the ARMv8 generic timer can not work correctly.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

include/configs/rk3368_common.h | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index b0c858c..ddb7df0 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT

+#define COUNTER_FREQUENCY 24000000 + #define CONFIG_SYS_NS16550_MEM32

#define CONFIG_SYS_TEXT_BASE 0x00200000

The RK3368 has both a limited TPL size (just 0x7000 bytes) and the added challenge of booting in AArch64, which increases the code size for TPL (particularily when using the LP64 programming model). For this reason we expect the RK3368 to always use OF_PLATDATA for its TPL stage.

This change adds support for the MSCH, PMUGRF and GRF register regions in syscon, which are necessary for initialising the RK3368's DRAM controller.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org

---

Changes in v3: - commit message now correctly refers to TPL

Changes in v2: None

arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index 03e97eb..90a993e 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -1,6 +1,8 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd * Author: Andy Yan andy.yan@rock-chips.com + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * * SPDX-License-Identifier: GPL-2.0+ */

@@ -14,6 +16,8 @@ static const struct udevice_id rk3368_syscon_ids[] = { .data = ROCKCHIP_SYSCON_GRF }, { .compatible = "rockchip,rk3368-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { .compatible = "rockchip,rk3368-msch", + .data = ROCKCHIP_SYSCON_MSCH }, { } };

@@ -22,3 +26,34 @@ U_BOOT_DRIVER(syscon_rk3368) = { .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids, }; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3368_syscon_bind_of_platdata(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3368_grf) = { + .name = "rockchip_rk3368_grf", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = { + .name = "rockchip_rk3368_pmugrf", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids + 1, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3368_msch) = { + .name = "rockchip_rk3368_msch", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids + 2, + .bind = rk3368_syscon_bind_of_platdata, +}; +#endif

We will to drop device security temporarily (until the ATF initialises it fully) from the TPL/SPL stage: this requires access to some registers in the SGRF.

This adds the sgrf node to the rk3368.dtsi, so we can then bind a syscon device onto it and access its memory ranges.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---

Changes in v3: None Changes in v2: None

arch/arm/dts/rk3368.dtsi | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 9daf765..59c20da 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -652,6 +652,11 @@ reg = <0x0 0xff738000 0x0 0x1000>; };

+ sgrf: syscon@ff740000 { + compatible = "rockchip,rk3368-sgrf", "syscon"; + reg = <0x0 0xff740000 0x0 0x1000>; + }; + cru: clock-controller@ff760000 { compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>;

To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII mode: * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID * configures the RGMII pins

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: - removed the RK3368-prefix on bit-definitions for GMAC pinctrl

drivers/pinctrl/rockchip/pinctrl_rk3368.c | 36 +++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c index c96459f..22cd593 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c @@ -52,6 +52,33 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv, } }

+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id) +{ + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B0_MASK | GPIO3B1_MASK | + GPIO3B2_MASK | GPIO3B5_MASK | + GPIO3B6_MASK | GPIO3B7_MASK, + GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 | + GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN | + GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0); + rk_clrsetreg(&grf->gpio3c_iomux, + GPIO3C0_MASK | GPIO3C1_MASK | + GPIO3C2_MASK | GPIO3C3_MASK | + GPIO3C4_MASK | GPIO3C5_MASK | + GPIO3C6_MASK, + GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 | + GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC | + GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN | + GPIO3C6_MAC_CLK); + rk_clrsetreg(&grf->gpio3d_iomux, + GPIO3D0_MASK | GPIO3D1_MASK | + GPIO3D4_MASK, + GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK | + GPIO3D4_MAC_TXCLK); +} +#endif + static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk3368_pinctrl_priv *priv = dev_get_priv(dev); @@ -65,6 +92,11 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_UART4: pinctrl_rk3368_uart_config(priv, func); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case PERIPH_ID_GMAC: + pinctrl_rk3368_gmac_config(priv->grf, func); + break; +#endif default: return -EINVAL; } @@ -94,6 +126,10 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_UART1; case 55: return PERIPH_ID_UART0; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 27: + return PERIPH_ID_GMAC; +#endif }

return -ENOENT;

There is no real reason to keep the bit-definitions for the IOMUX in the grf header file (which defines the register layout of the GRF block): these should only be used by our pinctrl driver (with the possible exception of early debug-init code in TPL/SPL).

This moves the relevant definitions from the grf_rk3368.h header into the pinctrl driver pinctrl_rk3368.c.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: - moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX definitions) to the rk3368 pinctrl driver implementation

arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 316 ----------------------- drivers/pinctrl/rockchip/pinctrl_rk3368.c | 325 ++++++++++++++++++++++++ 2 files changed, 325 insertions(+), 316 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index 1966960..ec42d7a 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -100,322 +100,6 @@ struct rk3368_pmu_grf { check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); check_member(rk3368_pmu_grf, os_reg[0], 0x200);

-/*GRF_GPIO0C_IOMUX*/ -enum { - GPIO0C7_MASK = GENMASK(15, 14), - GPIO0C7_GPIO = 0, - GPIO0C7_LCDC_D19 = (1 << 14), - GPIO0C7_TRACE_D9 = (2 << 14), - GPIO0C7_UART1_RTSN = (3 << 14), - - GPIO0C6_MASK = GENMASK(13, 12), - GPIO0C6_GPIO = 0, - GPIO0C6_LCDC_D18 = (1 << 12), - GPIO0C6_TRACE_D8 = (2 << 12), - GPIO0C6_UART1_CTSN = (3 << 12), - - GPIO0C5_MASK = GENMASK(11, 10), - GPIO0C5_GPIO = 0, - GPIO0C5_LCDC_D17 = (1 << 10), - GPIO0C5_TRACE_D7 = (2 << 10), - GPIO0C5_UART1_SOUT = (3 << 10), - - GPIO0C4_MASK = GENMASK(9, 8), - GPIO0C4_GPIO = 0, - GPIO0C4_LCDC_D16 = (1 << 8), - GPIO0C4_TRACE_D6 = (2 << 8), - GPIO0C4_UART1_SIN = (3 << 8), - - GPIO0C3_MASK = GENMASK(7, 6), - GPIO0C3_GPIO = 0, - GPIO0C3_LCDC_D15 = (1 << 6), - GPIO0C3_TRACE_D5 = (2 << 6), - GPIO0C3_MCU_JTAG_TDO = (3 << 6), - - GPIO0C2_MASK = GENMASK(5, 4), - GPIO0C2_GPIO = 0, - GPIO0C2_LCDC_D14 = (1 << 4), - GPIO0C2_TRACE_D4 = (2 << 4), - GPIO0C2_MCU_JTAG_TDI = (3 << 4), - - GPIO0C1_MASK = GENMASK(3, 2), - GPIO0C1_GPIO = 0, - GPIO0C1_LCDC_D13 = (1 << 2), - GPIO0C1_TRACE_D3 = (2 << 2), - GPIO0C1_MCU_JTAG_TRTSN = (3 << 2), - - GPIO0C0_MASK = GENMASK(1, 0), - GPIO0C0_GPIO = 0, - GPIO0C0_LCDC_D12 = (1 << 0), - GPIO0C0_TRACE_D2 = (2 << 0), - GPIO0C0_MCU_JTAG_TDO = (3 << 0), -}; - -/*GRF_GPIO0D_IOMUX*/ -enum { - GPIO0D7_MASK = GENMASK(15, 14), - GPIO0D7_GPIO = 0, - GPIO0D7_LCDC_DCLK = (1 << 14), - GPIO0D7_TRACE_CTL = (2 << 14), - GPIO0D7_PMU_DEBUG5 = (3 << 14), - - GPIO0D6_MASK = GENMASK(13, 12), - GPIO0D6_GPIO = 0, - GPIO0D6_LCDC_DEN = (1 << 12), - GPIO0D6_TRACE_CLK = (2 << 12), - GPIO0D6_PMU_DEBUG4 = (3 << 12), - - GPIO0D5_MASK = GENMASK(11, 10), - GPIO0D5_GPIO = 0, - GPIO0D5_LCDC_VSYNC = (1 << 10), - GPIO0D5_TRACE_D15 = (2 << 10), - GPIO0D5_PMU_DEBUG3 = (3 << 10), - - GPIO0D4_MASK = GENMASK(9, 8), - GPIO0D4_GPIO = 0, - GPIO0D4_LCDC_HSYNC = (1 << 8), - GPIO0D4_TRACE_D14 = (2 << 8), - GPIO0D4_PMU_DEBUG2 = (3 << 8), - - GPIO0D3_MASK = GENMASK(7, 6), - GPIO0D3_GPIO = 0, - GPIO0D3_LCDC_D23 = (1 << 6), - GPIO0D3_TRACE_D13 = (2 << 6), - GPIO0D3_UART4_SIN = (3 << 6), - - GPIO0D2_MASK = GENMASK(5, 4), - GPIO0D2_GPIO = 0, - GPIO0D2_LCDC_D22 = (1 << 4), - GPIO0D2_TRACE_D12 = (2 << 4), - GPIO0D2_UART4_SOUT = (3 << 4), - - GPIO0D1_MASK = GENMASK(3, 2), - GPIO0D1_GPIO = 0, - GPIO0D1_LCDC_D21 = (1 << 2), - GPIO0D1_TRACE_D11 = (2 << 2), - GPIO0D1_UART4_RTSN = (3 << 2), - - GPIO0D0_MASK = GENMASK(1, 0), - GPIO0D0_GPIO = 0, - GPIO0D0_LCDC_D20 = (1 << 0), - GPIO0D0_TRACE_D10 = (2 << 0), - GPIO0D0_UART4_CTSN = (3 << 0), -}; - -/*GRF_GPIO2A_IOMUX*/ -enum { - GPIO2A7_MASK = GENMASK(15, 14), - GPIO2A7_GPIO = 0, - GPIO2A7_SDMMC0_D2 = (1 << 14), - GPIO2A7_JTAG_TCK = (2 << 14), - - GPIO2A6_MASK = GENMASK(13, 12), - GPIO2A6_GPIO = 0, - GPIO2A6_SDMMC0_D1 = (1 << 12), - GPIO2A6_UART2_SIN = (2 << 12), - - GPIO2A5_MASK = GENMASK(11, 10), - GPIO2A5_GPIO = 0, - GPIO2A5_SDMMC0_D0 = (1 << 10), - GPIO2A5_UART2_SOUT = (2 << 10), - - GPIO2A4_MASK = GENMASK(9, 8), - GPIO2A4_GPIO = 0, - GPIO2A4_FLASH_DQS = (1 << 8), - GPIO2A4_EMMC_CLKOUT = (2 << 8), - - GPIO2A3_MASK = GENMASK(7, 6), - GPIO2A3_GPIO = 0, - GPIO2A3_FLASH_CSN3 = (1 << 6), - GPIO2A3_EMMC_RSTNOUT = (2 << 6), - - GPIO2A2_MASK = GENMASK(5, 4), - GPIO2A2_GPIO = 0, - GPIO2A2_FLASH_CSN2 = (1 << 4), - - GPIO2A1_MASK = GENMASK(3, 2), - GPIO2A1_GPIO = 0, - GPIO2A1_FLASH_CSN1 = (1 << 2), - - GPIO2A0_MASK = GENMASK(1, 0), - GPIO2A0_GPIO = 0, - GPIO2A0_FLASH_CSN0 = (1 << 0), -}; - -/*GRF_GPIO2D_IOMUX*/ -enum { - GPIO2D7_MASK = GENMASK(15, 14), - GPIO2D7_GPIO = 0, - GPIO2D7_SDIO0_D3 = (1 << 14), - - GPIO2D6_MASK = GENMASK(13, 12), - GPIO2D6_GPIO = 0, - GPIO2D6_SDIO0_D2 = (1 << 12), - - GPIO2D5_MASK = GENMASK(11, 10), - GPIO2D5_GPIO = 0, - GPIO2D5_SDIO0_D1 = (1 << 10), - - GPIO2D4_MASK = GENMASK(9, 8), - GPIO2D4_GPIO = 0, - GPIO2D4_SDIO0_D0 = (1 << 8), - - GPIO2D3_MASK = GENMASK(7, 6), - GPIO2D3_GPIO = 0, - GPIO2D3_UART0_RTS0 = (1 << 6), - - GPIO2D2_MASK = GENMASK(5, 4), - GPIO2D2_GPIO = 0, - GPIO2D2_UART0_CTS0 = (1 << 4), - - GPIO2D1_MASK = GENMASK(3, 2), - GPIO2D1_GPIO = 0, - GPIO2D1_UART0_SOUT = (1 << 2), - - GPIO2D0_MASK = GENMASK(1, 0), - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_SIN = (1 << 0), -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C7_MASK = GENMASK(15, 14), - GPIO1C7_GPIO = 0, - GPIO1C7_EMMC_DATA5 = (2 << 14), - - GPIO1C6_MASK = GENMASK(13, 12), - GPIO1C6_GPIO = 0, - GPIO1C6_EMMC_DATA4 = (2 << 12), - - GPIO1C5_MASK = GENMASK(11, 10), - GPIO1C5_GPIO = 0, - GPIO1C5_EMMC_DATA3 = (2 << 10), - - GPIO1C4_MASK = GENMASK(9, 8), - GPIO1C4_GPIO = 0, - GPIO1C4_EMMC_DATA2 = (2 << 8), - - GPIO1C3_MASK = GENMASK(7, 6), - GPIO1C3_GPIO = 0, - GPIO1C3_EMMC_DATA1 = (2 << 6), - - GPIO1C2_MASK = GENMASK(5, 4), - GPIO1C2_GPIO = 0, - GPIO1C2_EMMC_DATA0 = (2 << 4), -}; - -/* GRF_GPIO1D_IOMUX*/ -enum { - GPIO1D3_MASK = GENMASK(7, 6), - GPIO1D3_GPIO = 0, - GPIO1D3_EMMC_PWREN = (2 << 6), - - GPIO1D2_MASK = GENMASK(5, 4), - GPIO1D2_GPIO = 0, - GPIO1D2_EMMC_CMD = (2 << 4), - - GPIO1D1_MASK = GENMASK(3, 2), - GPIO1D1_GPIO = 0, - GPIO1D1_EMMC_DATA7 = (2 << 2), - - GPIO1D0_MASK = GENMASK(1, 0), - GPIO1D0_GPIO = 0, - GPIO1D0_EMMC_DATA6 = (2 << 0), -}; - - -/*GRF_GPIO3B_IOMUX*/ -enum { - GPIO3B7_MASK = GENMASK(15, 14), - GPIO3B7_GPIO = 0, - GPIO3B7_MAC_RXD0 = (1 << 14), - - GPIO3B6_MASK = GENMASK(13, 12), - GPIO3B6_GPIO = 0, - GPIO3B6_MAC_TXD3 = (1 << 12), - - GPIO3B5_MASK = GENMASK(11, 10), - GPIO3B5_GPIO = 0, - GPIO3B5_MAC_TXEN = (1 << 10), - - GPIO3B4_MASK = GENMASK(9, 8), - GPIO3B4_GPIO = 0, - GPIO3B4_MAC_COL = (1 << 8), - - GPIO3B3_MASK = GENMASK(7, 6), - GPIO3B3_GPIO = 0, - GPIO3B3_MAC_CRS = (1 << 6), - - GPIO3B2_MASK = GENMASK(5, 4), - GPIO3B2_GPIO = 0, - GPIO3B2_MAC_TXD2 = (1 << 4), - - GPIO3B1_MASK = GENMASK(3, 2), - GPIO3B1_GPIO = 0, - GPIO3B1_MAC_TXD1 = (1 << 2), - - GPIO3B0_MASK = GENMASK(1, 0), - GPIO3B0_GPIO = 0, - GPIO3B0_MAC_TXD0 = (1 << 0), - GPIO3B0_PWM0 = (2 << 0), -}; - -/*GRF_GPIO3C_IOMUX*/ -enum { - GPIO3C6_MASK = GENMASK(13, 12), - GPIO3C6_GPIO = 0, - GPIO3C6_MAC_CLK = (1 << 12), - - GPIO3C5_MASK = GENMASK(11, 10), - GPIO3C5_GPIO = 0, - GPIO3C5_MAC_RXEN = (1 << 10), - - GPIO3C4_MASK = GENMASK(9, 8), - GPIO3C4_GPIO = 0, - GPIO3C4_MAC_RXDV = (1 << 8), - - GPIO3C3_MASK = GENMASK(7, 6), - GPIO3C3_GPIO = 0, - GPIO3C3_MAC_MDC = (1 << 6), - - GPIO3C2_MASK = GENMASK(5, 4), - GPIO3C2_GPIO = 0, - GPIO3C2_MAC_RXD3 = (1 << 4), - - GPIO3C1_MASK = GENMASK(3, 2), - GPIO3C1_GPIO = 0, - GPIO3C1_MAC_RXD2 = (1 << 2), - - GPIO3C0_MASK = GENMASK(1, 0), - GPIO3C0_GPIO = 0, - GPIO3C0_MAC_RXD1 = (1 << 0), -}; - -/*GRF_GPIO3D_IOMUX*/ -enum { - GPIO3D4_MASK = GENMASK(9, 8), - GPIO3D4_GPIO = 0, - GPIO3D4_MAC_TXCLK = (1 << 8), - - GPIO3D1_MASK = GENMASK(3, 2), - GPIO3D1_GPIO = 0, - GPIO3D1_MAC_RXCLK = (1 << 2), - - GPIO3D0_MASK = GENMASK(1, 0), - GPIO3D0_GPIO = 0, - GPIO3D0_MAC_MDIO = (1 << 0), -}; - -/* GRF_SOC_CON0 */ -enum { - NOC_RSP_ERR_STALL = BIT(9), - MOBILE_DDR_SEL = BIT(4), - DDR0_16BIT_EN = BIT(3), - MSCH0_MAINDDR3_DDR3 = BIT(2), - MSCH0_MAINPARTIALPOP = BIT(1), - UPCTL_C_ACTIVE = BIT(0), -}; - /*GRF_SOC_CON11/12/13*/ enum { MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0, diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c index cf2f834..67695ab 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c @@ -16,6 +16,331 @@

DECLARE_GLOBAL_DATA_PTR;

+/*GRF_GPIO0C_IOMUX*/ +enum { + GPIO0C7_MASK = GENMASK(15, 14), + GPIO0C7_GPIO = 0, + GPIO0C7_LCDC_D19 = (1 << 14), + GPIO0C7_TRACE_D9 = (2 << 14), + GPIO0C7_UART1_RTSN = (3 << 14), + + GPIO0C6_MASK = GENMASK(13, 12), + GPIO0C6_GPIO = 0, + GPIO0C6_LCDC_D18 = (1 << 12), + GPIO0C6_TRACE_D8 = (2 << 12), + GPIO0C6_UART1_CTSN = (3 << 12), + + GPIO0C5_MASK = GENMASK(11, 10), + GPIO0C5_GPIO = 0, + GPIO0C5_LCDC_D17 = (1 << 10), + GPIO0C5_TRACE_D7 = (2 << 10), + GPIO0C5_UART1_SOUT = (3 << 10), + + GPIO0C4_MASK = GENMASK(9, 8), + GPIO0C4_GPIO = 0, + GPIO0C4_LCDC_D16 = (1 << 8), + GPIO0C4_TRACE_D6 = (2 << 8), + GPIO0C4_UART1_SIN = (3 << 8), + + GPIO0C3_MASK = GENMASK(7, 6), + GPIO0C3_GPIO = 0, + GPIO0C3_LCDC_D15 = (1 << 6), + GPIO0C3_TRACE_D5 = (2 << 6), + GPIO0C3_MCU_JTAG_TDO = (3 << 6), + + GPIO0C2_MASK = GENMASK(5, 4), + GPIO0C2_GPIO = 0, + GPIO0C2_LCDC_D14 = (1 << 4), + GPIO0C2_TRACE_D4 = (2 << 4), + GPIO0C2_MCU_JTAG_TDI = (3 << 4), + + GPIO0C1_MASK = GENMASK(3, 2), + GPIO0C1_GPIO = 0, + GPIO0C1_LCDC_D13 = (1 << 2), + GPIO0C1_TRACE_D3 = (2 << 2), + GPIO0C1_MCU_JTAG_TRTSN = (3 << 2), + + GPIO0C0_MASK = GENMASK(1, 0), + GPIO0C0_GPIO = 0, + GPIO0C0_LCDC_D12 = (1 << 0), + GPIO0C0_TRACE_D2 = (2 << 0), + GPIO0C0_MCU_JTAG_TDO = (3 << 0), +}; + +/*GRF_GPIO0D_IOMUX*/ +enum { + GPIO0D7_MASK = GENMASK(15, 14), + GPIO0D7_GPIO = 0, + GPIO0D7_LCDC_DCLK = (1 << 14), + GPIO0D7_TRACE_CTL = (2 << 14), + GPIO0D7_PMU_DEBUG5 = (3 << 14), + + GPIO0D6_MASK = GENMASK(13, 12), + GPIO0D6_GPIO = 0, + GPIO0D6_LCDC_DEN = (1 << 12), + GPIO0D6_TRACE_CLK = (2 << 12), + GPIO0D6_PMU_DEBUG4 = (3 << 12), + + GPIO0D5_MASK = GENMASK(11, 10), + GPIO0D5_GPIO = 0, + GPIO0D5_LCDC_VSYNC = (1 << 10), + GPIO0D5_TRACE_D15 = (2 << 10), + GPIO0D5_PMU_DEBUG3 = (3 << 10), + + GPIO0D4_MASK = GENMASK(9, 8), + GPIO0D4_GPIO = 0, + GPIO0D4_LCDC_HSYNC = (1 << 8), + GPIO0D4_TRACE_D14 = (2 << 8), + GPIO0D4_PMU_DEBUG2 = (3 << 8), + + GPIO0D3_MASK = GENMASK(7, 6), + GPIO0D3_GPIO = 0, + GPIO0D3_LCDC_D23 = (1 << 6), + GPIO0D3_TRACE_D13 = (2 << 6), + GPIO0D3_UART4_SIN = (3 << 6), + + GPIO0D2_MASK = GENMASK(5, 4), + GPIO0D2_GPIO = 0, + GPIO0D2_LCDC_D22 = (1 << 4), + GPIO0D2_TRACE_D12 = (2 << 4), + GPIO0D2_UART4_SOUT = (3 << 4), + + GPIO0D1_MASK = GENMASK(3, 2), + GPIO0D1_GPIO = 0, + GPIO0D1_LCDC_D21 = (1 << 2), + GPIO0D1_TRACE_D11 = (2 << 2), + GPIO0D1_UART4_RTSN = (3 << 2), + + GPIO0D0_MASK = GENMASK(1, 0), + GPIO0D0_GPIO = 0, + GPIO0D0_LCDC_D20 = (1 << 0), + GPIO0D0_TRACE_D10 = (2 << 0), + GPIO0D0_UART4_CTSN = (3 << 0), +}; + +/*GRF_GPIO2A_IOMUX*/ +enum { + GPIO2A7_MASK = GENMASK(15, 14), + GPIO2A7_GPIO = 0, + GPIO2A7_SDMMC0_D2 = (1 << 14), + GPIO2A7_JTAG_TCK = (2 << 14), + + GPIO2A6_MASK = GENMASK(13, 12), + GPIO2A6_GPIO = 0, + GPIO2A6_SDMMC0_D1 = (1 << 12), + GPIO2A6_UART2_SIN = (2 << 12), + + GPIO2A5_MASK = GENMASK(11, 10), + GPIO2A5_GPIO = 0, + GPIO2A5_SDMMC0_D0 = (1 << 10), + GPIO2A5_UART2_SOUT = (2 << 10), + + GPIO2A4_MASK = GENMASK(9, 8), + GPIO2A4_GPIO = 0, + GPIO2A4_FLASH_DQS = (1 << 8), + GPIO2A4_EMMC_CLKOUT = (2 << 8), + + GPIO2A3_MASK = GENMASK(7, 6), + GPIO2A3_GPIO = 0, + GPIO2A3_FLASH_CSN3 = (1 << 6), + GPIO2A3_EMMC_RSTNOUT = (2 << 6), + + GPIO2A2_MASK = GENMASK(5, 4), + GPIO2A2_GPIO = 0, + GPIO2A2_FLASH_CSN2 = (1 << 4), + + GPIO2A1_MASK = GENMASK(3, 2), + GPIO2A1_GPIO = 0, + GPIO2A1_FLASH_CSN1 = (1 << 2), + + GPIO2A0_MASK = GENMASK(1, 0), + GPIO2A0_GPIO = 0, + GPIO2A0_FLASH_CSN0 = (1 << 0), +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D7_MASK = GENMASK(15, 14), + GPIO2D7_GPIO = 0, + GPIO2D7_SDIO0_D3 = (1 << 14), + + GPIO2D6_MASK = GENMASK(13, 12), + GPIO2D6_GPIO = 0, + GPIO2D6_SDIO0_D2 = (1 << 12), + + GPIO2D5_MASK = GENMASK(11, 10), + GPIO2D5_GPIO = 0, + GPIO2D5_SDIO0_D1 = (1 << 10), + + GPIO2D4_MASK = GENMASK(9, 8), + GPIO2D4_GPIO = 0, + GPIO2D4_SDIO0_D0 = (1 << 8), + + GPIO2D3_MASK = GENMASK(7, 6), + GPIO2D3_GPIO = 0, + GPIO2D3_UART0_RTS0 = (1 << 6), + + GPIO2D2_MASK = GENMASK(5, 4), + GPIO2D2_GPIO = 0, + GPIO2D2_UART0_CTS0 = (1 << 4), + + GPIO2D1_MASK = GENMASK(3, 2), + GPIO2D1_GPIO = 0, + GPIO2D1_UART0_SOUT = (1 << 2), + + GPIO2D0_MASK = GENMASK(1, 0), + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_SIN = (1 << 0), +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_MASK = GENMASK(15, 14), + GPIO1B7_GPIO = 0, + GPIO1B7_SPI1_CSN0 = (2 << 14), + + GPIO1B6_MASK = GENMASK(13, 12), + GPIO1B6_GPIO = 0, + GPIO1B6_SPI1_CLK = (2 << 12), +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C7_MASK = GENMASK(15, 14), + GPIO1C7_GPIO = 0, + GPIO1C7_EMMC_DATA5 = (2 << 14), + + GPIO1C6_MASK = GENMASK(13, 12), + GPIO1C6_GPIO = 0, + GPIO1C6_EMMC_DATA4 = (2 << 12), + + GPIO1C5_MASK = GENMASK(11, 10), + GPIO1C5_GPIO = 0, + GPIO1C5_EMMC_DATA3 = (2 << 10), + + GPIO1C4_MASK = GENMASK(9, 8), + GPIO1C4_GPIO = 0, + GPIO1C4_EMMC_DATA2 = (2 << 8), + + GPIO1C3_MASK = GENMASK(7, 6), + GPIO1C3_GPIO = 0, + GPIO1C3_EMMC_DATA1 = (2 << 6), + + GPIO1C2_MASK = GENMASK(5, 4), + GPIO1C2_GPIO = 0, + GPIO1C2_EMMC_DATA0 = (2 << 4), + + GPIO1C1_MASK = GENMASK(3, 2), + GPIO1C1_GPIO = 0, + GPIO1C1_SPI1_RXD = (2 << 2), + + GPIO1C0_MASK = GENMASK(1, 0), + GPIO1C0_GPIO = 0, + GPIO1C0_SPI1_TXD = (2 << 0), +}; + +/* GRF_GPIO1D_IOMUX*/ +enum { + GPIO1D3_MASK = GENMASK(7, 6), + GPIO1D3_GPIO = 0, + GPIO1D3_EMMC_PWREN = (2 << 6), + + GPIO1D2_MASK = GENMASK(5, 4), + GPIO1D2_GPIO = 0, + GPIO1D2_EMMC_CMD = (2 << 4), + + GPIO1D1_MASK = GENMASK(3, 2), + GPIO1D1_GPIO = 0, + GPIO1D1_EMMC_DATA7 = (2 << 2), + + GPIO1D0_MASK = GENMASK(1, 0), + GPIO1D0_GPIO = 0, + GPIO1D0_EMMC_DATA6 = (2 << 0), +}; + + +/*GRF_GPIO3B_IOMUX*/ +enum { + GPIO3B7_MASK = GENMASK(15, 14), + GPIO3B7_GPIO = 0, + GPIO3B7_MAC_RXD0 = (1 << 14), + + GPIO3B6_MASK = GENMASK(13, 12), + GPIO3B6_GPIO = 0, + GPIO3B6_MAC_TXD3 = (1 << 12), + + GPIO3B5_MASK = GENMASK(11, 10), + GPIO3B5_GPIO = 0, + GPIO3B5_MAC_TXEN = (1 << 10), + + GPIO3B4_MASK = GENMASK(9, 8), + GPIO3B4_GPIO = 0, + GPIO3B4_MAC_COL = (1 << 8), + + GPIO3B3_MASK = GENMASK(7, 6), + GPIO3B3_GPIO = 0, + GPIO3B3_MAC_CRS = (1 << 6), + + GPIO3B2_MASK = GENMASK(5, 4), + GPIO3B2_GPIO = 0, + GPIO3B2_MAC_TXD2 = (1 << 4), + + GPIO3B1_MASK = GENMASK(3, 2), + GPIO3B1_GPIO = 0, + GPIO3B1_MAC_TXD1 = (1 << 2), + + GPIO3B0_MASK = GENMASK(1, 0), + GPIO3B0_GPIO = 0, + GPIO3B0_MAC_TXD0 = (1 << 0), + GPIO3B0_PWM0 = (2 << 0), +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C6_MASK = GENMASK(13, 12), + GPIO3C6_GPIO = 0, + GPIO3C6_MAC_CLK = (1 << 12), + + GPIO3C5_MASK = GENMASK(11, 10), + GPIO3C5_GPIO = 0, + GPIO3C5_MAC_RXEN = (1 << 10), + + GPIO3C4_MASK = GENMASK(9, 8), + GPIO3C4_GPIO = 0, + GPIO3C4_MAC_RXDV = (1 << 8), + + GPIO3C3_MASK = GENMASK(7, 6), + GPIO3C3_GPIO = 0, + GPIO3C3_MAC_MDC = (1 << 6), + + GPIO3C2_MASK = GENMASK(5, 4), + GPIO3C2_GPIO = 0, + GPIO3C2_MAC_RXD3 = (1 << 4), + + GPIO3C1_MASK = GENMASK(3, 2), + GPIO3C1_GPIO = 0, + GPIO3C1_MAC_RXD2 = (1 << 2), + + GPIO3C0_MASK = GENMASK(1, 0), + GPIO3C0_GPIO = 0, + GPIO3C0_MAC_RXD1 = (1 << 0), +}; + +/* GRF_GPIO3D_IOMUX */ +enum { + GPIO3D4_MASK = GENMASK(9, 8), + GPIO3D4_GPIO = 0, + GPIO3D4_MAC_TXCLK = (1 << 8), + + GPIO3D1_MASK = GENMASK(3, 2), + GPIO3D1_GPIO = 0, + GPIO3D1_MAC_RXCLK = (1 << 2), + + GPIO3D0_MASK = GENMASK(1, 0), + GPIO3D0_GPIO = 0, + GPIO3D0_MAC_MDIO = (1 << 0), +}; + struct rk3368_pinctrl_priv { struct rk3368_grf *grf; struct rk3368_pmu_grf *pmugrf;

The RK3368 TRM recommends to configure the bandwith adjustment (CON2) for PLLs to NF/2. This implements this for all reconfigurations of PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the bandwidth-adjustment feature according to its manual).

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

drivers/clk/rockchip/clk_rk3368.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index e1d9aeb..d8f06d5 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -1,6 +1,7 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd * Author: Andy Yan andy.yan@rock-chips.com + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * SPDX-License-Identifier: GPL-2.0 */

@@ -74,7 +75,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, }

static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, - const struct pll_div *div, bool has_bwadj) + const struct pll_div *div) { struct rk3368_pll *pll = &cru->pll[pll_id]; /* All PLLs have same VCO and output frequency range restrictions*/ @@ -92,6 +93,12 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, ((div->nr - 1) << PLL_NR_SHIFT) | ((div->no - 1) << PLL_OD_SHIFT)); writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); + /* + * BWADJ should be set to NF / 2 to ensure the nominal bandwidth. + * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment". + */ + clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); + udelay(10);

/* return from reset */ @@ -111,10 +118,10 @@ static void rkclk_init(struct rk3368_cru *cru) { u32 apllb, aplll, dpll, cpll, gpll;

- rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false); - rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false); - rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false); - rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false); + rkclk_set_pll(cru, APLLB, &apll_b_init_cfg); + rkclk_set_pll(cru, APLLL, &apll_l_init_cfg); + rkclk_set_pll(cru, GPLL, &gpll_init_cfg); + rkclk_set_pll(cru, CPLL, &cpll_init_cfg);

apllb = rkclk_pll_get_rate(cru, APLLB); aplll = rkclk_pll_get_rate(cru, APLLL);

The RK3368 has a somewhat temperamental BootROM (which I learned the hard way) when it comes to reconfiguring the CPLL and GPLL (in fact, experiments show that changing the GPLL broke things for me, while changing the CPLL seems to be more benign). These should not be modified by the SPL stage, if we intend to return to the BootROM for chain booting the next stage.

This commit changes the clock initialisation to not change CPLL/GPLL before returning to the BootROM (i.e. in TPL). As it's safe to change these settings if we no longer intend to return to U-Boot, we'll run the full PLL setup a little later (i.e. in SPL).

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

drivers/clk/rockchip/clk_rk3368.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 809ad19..d05be72 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -50,10 +50,14 @@ struct pll_div { (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \ "divisors on line " __stringify(__LINE__));

+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); +#if !defined(CONFIG_TPL_BUILD) static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); +#endif +#endif

/* Get pll rate by id */ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, @@ -82,6 +86,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, } }

+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, const struct pll_div *div) { @@ -121,15 +126,23 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,

return 0; } +#endif

+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static void rkclk_init(struct rk3368_cru *cru) { u32 apllb, aplll, dpll, cpll, gpll;

rkclk_set_pll(cru, APLLB, &apll_b_init_cfg); rkclk_set_pll(cru, APLLL, &apll_l_init_cfg); +#if !defined(CONFIG_TPL_BUILD) + /* + * If we plan to return to the boot ROM, we can't increase the + * GPLL rate from the SPL stage. + */ rkclk_set_pll(cru, GPLL, &gpll_init_cfg); rkclk_set_pll(cru, CPLL, &cpll_init_cfg); +#endif

apllb = rkclk_pll_get_rate(cru, APLLB); aplll = rkclk_pll_get_rate(cru, APLLL); @@ -140,6 +153,7 @@ static void rkclk_init(struct rk3368_cru *cru) debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n", __func__, apllb, aplll, dpll, cpll, gpll); } +#endif

static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) { @@ -261,13 +275,15 @@ static struct clk_ops rk3368_clk_ops = {

static int rk3368_clk_probe(struct udevice *dev) { - struct rk3368_clk_priv *priv = dev_get_priv(dev); + struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev); #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3368_clk_plat *plat = dev_get_platdata(dev);

priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); #endif +#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) rkclk_init(priv->cru); +#endif

return 0; }

On he RK3368, we need to temporarily disable security on the DMA engines during TPL and SPL to allow the MMC host to DMA into DRAM. To do so, we need to reset the two DMA engines, which in turn requires the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the appropriate bits in the CRU.

As the ATF correctly initialises security (and only leaves EL3 after doing so), this can not pose a security issue.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 24a9cc0..bf09e2f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -102,6 +102,10 @@ enum { /* SOFTRST1_CON */ MCU_PO_SRST_MASK = BIT(13), MCU_SYS_SRST_MASK = BIT(12), + DMA1_SRST_REQ = BIT(2), + + /* SOFTRST4_CON */ + DMA2_SRST_REQ = BIT(0),

/* GLB_RST_CON */ PMU_GLB_SRST_CTRL_SHIFT = 2,

As part of the DRAM initialisation process (running as part of the TPL stage) on the RK3368, we need to set up the DRAM PLL.

This implements support for configuring the PLL to for 1200, 1332 or 1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

drivers/clk/rockchip/clk_rk3368.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 1327116..1bed4e2 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -308,18 +308,16 @@ static ulong rk3368_clk_get_rate(struct clk *clk) return rate; }

+#if IS_ENABLED(CONFIG_TPL_BUILD) static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate) { const struct pll_div *dpll_cfg = NULL; const ulong MHz = 1000000;

/* Fout = ((Fin /NR) * NF )/ NO */ - static const struct pll_div dpll_1200 = - PLL_DIVISORS(1200 * MHz, 1, 1); - static const struct pll_div dpll_1332 = - PLL_DIVISORS(1332 * MHz, 2, 1); - static const struct pll_div dpll_1600 = - PLL_DIVISORS(1600 * MHz, 3, 2); + static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); + static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); + static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);

switch (set_rate) { case 1200*MHz: @@ -338,6 +336,7 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)

return set_rate; } +#endif

static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) { @@ -346,9 +345,11 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)

debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate); switch (clk->id) { +#if IS_ENABLED(CONFIG_TPL_BUILD) case CLK_DDR: ret = rk3368_ddr_set_clk(priv->cru, rate); break; +#endif #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) case HCLK_SDMMC: case HCLK_EMMC:

With the clock support in rk3368_clk_set_rate() conditionalized on various feature definitions, 'priv' can remain unused (e.g. in the SPL build when only MMC is enabled).

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

drivers/clk/rockchip/clk_rk3368.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 2b6c8da..d3f6c29 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -353,7 +353,7 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,

static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) { - struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); + __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); ulong ret = 0;

debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);

The GMAC in the RK3368 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF.

This adds the RK3368-specific logic necessary to reuse this driver.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v3: None Changes in v2: - moves the bit-definitions (for GRF registers) specific to the GMAC into the GMAC driver: these include interface speed selection and configuring the RGMII output mode

arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 1 + drivers/net/gmac_rockchip.c | 78 +++++++++++++++++++++++++ 2 files changed, 79 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index ec42d7a..1f84ff9 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -129,4 +129,5 @@ enum { MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), }; + #endif diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index c9f9e83..586ccbf 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -16,6 +16,7 @@ #include <asm/arch/clock.h> #include <asm/arch/hardware.h> #include <asm/arch/grf_rk3288.h> +#include <asm/arch/grf_rk3368.h> #include <asm/arch/grf_rk3399.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> @@ -83,6 +84,38 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }

+static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3368_grf *grf; + int clk; + enum { + RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, + RK3368_GMAC_CLK_SEL_25M = 3 << 4, + RK3368_GMAC_CLK_SEL_125M = 0 << 4, + RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3368_GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = RK3368_GMAC_CLK_SEL_25M; + break; + case 1000: + clk = RK3368_GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); + + return 0; +} + static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) { struct rk3399_grf_regs *grf; @@ -129,6 +162,44 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); }

+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3368_grf *grf; + enum { + RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, + RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), + RK3368_RMII_MODE_MASK = BIT(6), + RK3368_RMII_MODE = BIT(6), + }; + enum { + RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), + RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), + RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), + RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), + RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, + RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), + RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, + RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con15, + RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, + RK3368_GMAC_PHY_INTF_SEL_RGMII); + + rk_clrsetreg(&grf->soc_con16, + RK3368_RXCLK_DLY_ENA_GMAC_MASK | + RK3368_TXCLK_DLY_ENA_GMAC_MASK | + RK3368_CLK_RX_DL_CFG_GMAC_MASK | + RK3368_CLK_TX_DL_CFG_GMAC_MASK, + RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | + RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | + pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); +} + static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3399_grf_regs *grf; @@ -208,6 +279,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = { .set_to_rgmii = rk3288_gmac_set_to_rgmii, };

+const struct rk_gmac_ops rk3368_gmac_ops = { + .fix_mac_speed = rk3368_gmac_fix_mac_speed, + .set_to_rgmii = rk3368_gmac_set_to_rgmii, +}; + const struct rk_gmac_ops rk3399_gmac_ops = { .fix_mac_speed = rk3399_gmac_fix_mac_speed, .set_to_rgmii = rk3399_gmac_set_to_rgmii, @@ -216,6 +292,8 @@ const struct rk_gmac_ops rk3399_gmac_ops = { static const struct udevice_id rockchip_gmac_ids[] = { { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, + { .compatible = "rockchip,rk3368-gmac", + .data = (ulong)&rk3368_gmac_ops }, { .compatible = "rockchip,rk3399-gmac", .data = (ulong)&rk3399_gmac_ops }, { }

This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600).

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: - correctly states the location of the driver in the commit message

Changes in v2: None

arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++ arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 + arch/arm/mach-rockchip/rk3368/Makefile | 1 - arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 -- .../clock/rockchip,rk3368-dmc.txt | 67 ++ drivers/ram/Makefile | 2 + drivers/ram/rockchip/Makefile | 7 + drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++ include/dt-bindings/memory/rk3368-dmc.h | 30 + 9 files changed, 1286 insertions(+), 61 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt create mode 100644 drivers/ram/rockchip/Makefile create mode 100644 drivers/ram/rockchip/dmc-rk3368.c create mode 100644 include/dt-bindings/memory/rk3368-dmc.h

diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file mode 100644 index 0000000..4e2b233 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only + * in a few details. Most notably, it has an additional field to track + * tREFI in controller cycles (i.e. trefi_mem_ddr3). + */ +struct rk3368_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 trefi_mem_ddr3; + u32 reserved5[45]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3368_ddr_pctl, iptr, 0x03fc); + +struct rk3368_ddrphy { + u32 reg[0x100]; +}; +check_member(rk3368_ddrphy, reg[0xff], 0x03fc); + +struct rk3368_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 reserved1[8]; + u32 activate; + u32 devtodev; +}; +check_member(rk3368_msch, devtodev, 0x003c); + +/* GRF_SOC_CON0 */ +enum { + NOC_RSP_ERR_STALL = BIT(9), + MOBILE_DDR_SEL = BIT(4), + DDR0_16BIT_EN = BIT(3), + MSCH0_MAINDDR3_DDR3 = BIT(2), + MSCH0_MAINPARTIALPOP = BIT(1), + UPCTL_C_ACTIVE = BIT(0), +}; + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index 1f84ff9..6b6651a 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -76,8 +76,11 @@ struct rk3368_grf { u32 soc_con15; u32 soc_con16; u32 soc_con17; + u32 reserved5[0x6e]; + u32 ddrc0_con0; }; check_member(rk3368_grf, soc_con17, 0x444); +check_member(rk3368_grf, ddrc0_con0, 0x600);

struct rk3368_pmu_grf { u32 gpio0a_iomux; diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile index 0390716..46798c2 100644 --- a/arch/arm/mach-rockchip/rk3368/Makefile +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted file mode 100644 index d0d0900..0000000 --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR; -struct dram_info { - struct ram_info info; - struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe(struct udevice *dev) -{ - struct dram_info *priv = dev_get_priv(dev); - - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - debug("%s: grf=%p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->pmugrf->os_reg[2]); - - return 0; -} - -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) -{ - struct dram_info *priv = dev_get_priv(dev); - - *info = priv->info; - - return 0; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible = "rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER(dmc_rk3368) = { - .name = "rockchip_rk3368_dmc", - .id = UCLASS_RAM, - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size = sizeof(struct dram_info), -}; diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file mode 100644 index 0000000..8e7357d --- /dev/null +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt @@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc@ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + }; diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index c409c48..51ae6be 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile new file mode 100644 index 0000000..b09d03c --- /dev/null +++ b/drivers/ram/rockchip/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c new file mode 100644 index 0000000..fea96a5 --- /dev/null +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -0,0 +1,990 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-bindings/memory/rk3368-dmc.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/ddr_rk3368.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct dram_info { + struct ram_info info; + struct clk ddr_clk; + struct rk3368_cru *cru; + struct rk3368_grf *grf; + struct rk3368_ddr_pctl *pctl; + struct rk3368_ddrphy *phy; + struct rk3368_pmu_grf *pmugrf; + struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3368_dmc of_plat; +#endif + struct rk3288_sdram_pctl_timing pctl_timing; + u32 trefi_mem_ddr3; + struct rk3288_sdram_channel chan; + struct regmap *map; + u32 ddr_freq; + u32 memory_schedule; + u32 ddr_speed_bin; + u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { + /* PCTL_DFISTCFG0 */ + DFI_INIT_START = BIT(0), + DFI_DATA_BYTE_DISABLE_EN = BIT(2), + + /* PCTL_DFISTCFG1 */ + DFI_DRAM_CLK_SR_EN = BIT(0), + DFI_DRAM_CLK_DPD_EN = BIT(1), + ODT_LEN_BL8_W_SHIFT = 16, + + /* PCTL_DFISTCFG2 */ + DFI_PARITY_INTR_EN = BIT(0), + DFI_PARITY_EN = BIT(1), + + /* PCTL_DFILPCFG0 */ + TLP_RESP_TIME_SHIFT = 16, + LP_SR_EN = BIT(8), + LP_PD_EN = BIT(0), + + /* PCTL_DFIODTCFG */ + RANK0_ODT_WRITE_SEL = BIT(3), + RANK1_ODT_WRITE_SEL = BIT(11), + + /* PCTL_SCFG */ + HW_LOW_POWER_EN = BIT(0), + + /* PCTL_MCMD */ + START_CMD = BIT(31), + MCMD_RANK0 = BIT(20), + MCMD_RANK1 = BIT(21), + DESELECT_CMD = 0, + PREA_CMD, + REF_CMD, + MRS_CMD, + ZQCS_CMD, + ZQCL_CMD, + RSTL_CMD, + MRR_CMD = 8, + DPDE_CMD, + + /* PCTL_POWCTL */ + POWER_UP_START = BIT(0), + + /* PCTL_POWSTAT */ + POWER_UP_DONE = BIT(0), + + /* PCTL_SCTL */ + INIT_STATE = 0, + CFG_STATE, + GO_STATE, + SLEEP_STATE, + WAKEUP_STATE, + + /* PCTL_STAT */ + LP_TRIG_SHIFT = 4, + LP_TRIG_MASK = 7, + PCTL_STAT_MSK = 7, + INIT_MEM = 0, + CONFIG, + CONFIG_REQ, + ACCESS, + ACCESS_REQ, + LOW_POWER, + LOW_POWER_ENTRY_REQ, + LOW_POWER_EXIT_REQ, + + /* PCTL_MCFG */ + DDR2_DDR3_BL_8 = BIT(0), + DDR3_EN = BIT(5), + TFAW_TRRD_MULT4 = (0 << 18), + TFAW_TRRD_MULT5 = (1 << 18), + TFAW_TRRD_MULT6 = (2 << 18), +}; + +#define DDR3_MR0_WR(n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL(n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL(n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable) +{ + if (enable) + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); + else + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); +} + +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode) +{ + if (ddr3_mode) + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); + else + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); +} + +static void ddrphy_config(struct rk3368_ddrphy *phy, + u32 tcl, u32 tal, u32 tcwl) +{ + int i; + + /* Set to DDR3 mode */ + clrsetbits_le32(&phy->reg[1], 0x3, 0x0); + + /* DDRPHY_REGB: CL, AL */ + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal); + /* DDRPHY_REGC: CWL */ + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl); + + /* Update drive-strength */ + writel(0xcc, &phy->reg[0x11]); + writel(0xaa, &phy->reg[0x16]); + /* + * Update NRCOMP/PRCOMP for all 4 channels (for details of all + * affected registers refer to the documentation of DDRPHY_REG20 + * and DDRPHY_REG21 in the RK3368 TRM. + */ + for (i = 0; i < 4; ++i) { + writel(0xcc, &phy->reg[0x20 + i * 0x10]); + writel(0x44, &phy->reg[0x21 + i * 0x10]); + } + + /* Enable write-leveling calibration bypass */ + setbits_le32(&phy->reg[2], BIT(3)); +} + +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) + writel(*src++, dest++); +} + +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd) +{ + u32 mcmd = START_CMD | cmd | rank; + + debug("%s: writing %x to MCMD\n", __func__, mcmd); + writel(mcmd, &pctl->mcmd); + while (readl(&pctl->mcmd) & START_CMD) + /* spin */; +} + +static void send_mrs(struct rk3368_ddr_pctl *pctl, + u32 rank, u32 mr_num, u32 mr_data) +{ + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4); + + debug("%s: writing %x to MCMD\n", __func__, mcmd); + writel(mcmd, &pctl->mcmd); + while (readl(&pctl->mcmd) & START_CMD) + /* spin */; +} + +static int memory_init(struct rk3368_ddr_pctl *pctl, + struct rk3368_sdram_params *params) +{ + u32 mr[4]; + const ulong timeout_ms = 500; + ulong tmp; + + /* + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register + * of PCTL. + */ + writel(POWER_UP_START, &pctl->powctl); + + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + error("%s: POWER_UP_START did not complete in %ld ms\n", + __func__, timeout_ms); + return -ETIME; + } + } while (!(readl(&pctl->powstat) & POWER_UP_DONE)); + + /* Configure MR0 through MR3 */ + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) | + DDR3_MR0_CL(params->pctl_timing.tcl) | + DDR3_MR0_DLL_RESET; + mr[1] = DDR3_MR1_RTT120OHM; + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl); + mr[3] = 0; + + /* + * Also see RK3368 Technical Reference Manual: + * "16.6.2 Initialization (DDR3 Initialization Sequence)" + */ + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD); + udelay(1); + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]); + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]); + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]); + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]); + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD); + + return 0; +} + +static void move_to_config_state(struct rk3368_ddr_pctl *pctl) +{ + /* + * Also see RK3368 Technical Reference Manual: + * "16.6.1 State transition of PCTL (Moving to Config State)" + */ + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + /* spin */; + + /* fall-through */ + case ACCESS: + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + /* spin */; + break; + + case CONFIG: + return; + + default: + break; + } +} + +static void move_to_access_state(struct rk3368_ddr_pctl *pctl) +{ + /* + * Also see RK3368 Technical Reference Manual: + * "16.6.1 State transition of PCTL (Moving to Access State)" + */ + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & + LP_TRIG_MASK) == 1) + return; + + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + /* spin */; + + /* fall-through */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + /* spin */; + + /* fall-through */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) + /* spin */; + break; + + case ACCESS: + return; + + default: + break; + } +} + +static void ddrctl_reset(struct rk3368_cru *cru) +{ + const u32 ctl_reset = BIT(3) | BIT(2); + const u32 phy_reset = BIT(1) | BIT(0); + + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset); + udelay(1); + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset); +} + +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy) +{ + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2)); + udelay(1); + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2)); +} + +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq) +{ + u32 dqs_dll_delay; + + setbits_le32(&ddrphy->reg[0x13], BIT(4)); + clrbits_le32(&ddrphy->reg[0x14], BIT(3)); + + setbits_le32(&ddrphy->reg[0x26], BIT(4)); + clrbits_le32(&ddrphy->reg[0x27], BIT(3)); + + setbits_le32(&ddrphy->reg[0x36], BIT(4)); + clrbits_le32(&ddrphy->reg[0x37], BIT(3)); + + setbits_le32(&ddrphy->reg[0x46], BIT(4)); + clrbits_le32(&ddrphy->reg[0x47], BIT(3)); + + setbits_le32(&ddrphy->reg[0x56], BIT(4)); + clrbits_le32(&ddrphy->reg[0x57], BIT(3)); + + if (freq <= 400000000) + setbits_le32(&ddrphy->reg[0xa4], 0x1f); + else + clrbits_le32(&ddrphy->reg[0xa4], 0x1f); + + if (freq < 681000000) + dqs_dll_delay = 3; /* 67.5 degree delay */ + else + dqs_dll_delay = 2; /* 45 degree delay */ + + writel(dqs_dll_delay, &ddrphy->reg[0x28]); + writel(dqs_dll_delay, &ddrphy->reg[0x38]); + writel(dqs_dll_delay, &ddrphy->reg[0x48]); + writel(dqs_dll_delay, &ddrphy->reg[0x58]); +} + +static int dfi_cfg(struct rk3368_ddr_pctl *pctl) +{ + const ulong timeout_ms = 200; + ulong tmp; + + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); + + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, + &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(1, &pctl->dfitphyupdtype0); + + writel(0x1f, &pctl->dfitphyrdlat); + writel(0, &pctl->dfitphywrdata); + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */ + + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START); + + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + error("%s: DFI init did not complete within %ld ms\n", + __func__, timeout_ms); + return -ETIME; + } + } while ((readl(&pctl->dfiststat0) & 1) == 0); + + return 0; +} + +static inline u32 ps_to_tCK(const u32 ps, const ulong freq) +{ + const ulong MHz = 1000000; + return DIV_ROUND_UP(ps * freq, 1000000 * MHz); +} + +static inline u32 ns_to_tCK(const u32 ns, const ulong freq) +{ + return ps_to_tCK(ns * 1000, freq); +} + +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq) +{ + const ulong MHz = 1000000; + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq); +} + +static int pctl_calc_timings(struct rk3368_sdram_params *params, + ulong freq) +{ + struct rk3288_sdram_pctl_timing *pctl_timing = &params->pctl_timing; + const ulong MHz = 1000000; + u32 tccd; + u32 tfaw_as_ps; + + if (params->ddr_speed_bin != DDR3_1600K) { + error("%s: unimplemented DDR3 speed bin %d\n", + __func__, params->ddr_speed_bin); + return -1; + } + + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz); + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz); + + pctl_timing->tinit = 200; /* 200 usec */ + pctl_timing->trsth = 500; /* 500 usec */ + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq); + + if (freq <= (400 * MHz)) { + pctl_timing->tcl = 6; + pctl_timing->tcwl = 10; + } else if (freq <= (533 * MHz)) { + pctl_timing->tcl = 8; + pctl_timing->tcwl = 6; + } else if (freq <= (666 * MHz)) { + pctl_timing->tcl = 10; + pctl_timing->tcwl = 7; + } else { + pctl_timing->tcl = 11; + pctl_timing->tcwl = 8; + } + + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */ + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq)); + /* + * JESD-79: + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL + */ + tccd = 4; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; + pctl_timing->tal = 0; + pctl_timing->tras = ps_to_tCK(35000, freq); + pctl_timing->trc = ps_to_tCK(48750, freq); + pctl_timing->trcd = ps_to_tCK(13750, freq); + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq)); + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq)); + pctl_timing->twr = ps_to_tCK(15000, freq); + /* The DDR3 mode-register does only support even values for tWR > 8. */ + if (pctl_timing->twr > 8) + pctl_timing->twr = (pctl_timing->twr + 1) & ~1; + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq)); + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */ + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq)); + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq)); + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq)); + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */ + pctl_timing->tdqs = 1; /* fixed for DDR3 */ + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq)); + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq)); + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq)); + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq)); + pctl_timing->trstl = ns_to_tCK(100, freq); + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */ + pctl_timing->tmrr = 0; + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */ + + + /* + * The controller can represent tFAW as 4x, 5x or 6x tRRD only. + * We want to use the smallest multiplier that satisfies the tFAW + * requirements of the given speed-bin. If necessary, we stretch out + * tRRD to allow us to operate on a 6x multiplier for tFAW. + */ + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */ + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) { + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq); + params->tfaw_mult = TFAW_TRRD_MULT6; + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) { + params->tfaw_mult = TFAW_TRRD_MULT6; + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) { + params->tfaw_mult = TFAW_TRRD_MULT5; + } else { + params->tfaw_mult = TFAW_TRRD_MULT4; + } + + return 0; +} + +static void pctl_cfg(struct rk3368_ddr_pctl *pctl, + struct rk3368_sdram_params *params, + struct rk3368_grf *grf) +{ + /* Configure PCTL timing registers */ + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */ + copy_to_reg(&pctl->togcnt1u, &params->pctl_timing.togcnt1u, + sizeof(params->pctl_timing)); + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + + /* Set up ODT write selector and ODT write length */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg); + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + + /* Set up the CL/CWL-dependent timings of DFI */ + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen); + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat); + + /* DDR3 */ + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg); + writel(0x001c0004, &grf->ddrc0_con0); + + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); +} + +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl, + struct rk3368_ddrphy *ddrphy) +{ + const u32 trefi = readl(&pctl->trefi); + const ulong timeout_ms = 500; + ulong tmp; + + /* disable auto-refresh */ + writel(0 | BIT(31), &pctl->trefi); + + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21); + + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + error("%s: did not complete within %ld ms\n", + __func__, timeout_ms); + return -ETIME; + } + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf); + + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); + /* resume auto-refresh */ + writel(trefi | BIT(31), &pctl->trefi); + + return 0; +} + +static int sdram_col_row_detect(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3368_sdram_params *params = dev_get_platdata(dev); + struct rk3368_ddr_pctl *pctl = priv->pctl; + struct rk3368_msch *msch = priv->msch; + const u32 test_pattern = 0x5aa5f00f; + int row, col; + uintptr_t addr; + + move_to_config_state(pctl); + writel(6, &msch->ddrconf); + move_to_access_state(pctl); + + /* Detect col */ + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw - 1)); + writel(test_pattern, addr); + if ((readl(addr) == test_pattern) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + + if (col == 8) { + error("%s: col detect error\n", __func__); + return -EINVAL; + } + + move_to_config_state(pctl); + writel(15, &msch->ddrconf); + move_to_access_state(pctl); + + /* Detect row*/ + for (row = 16; row >= 12; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(test_pattern, addr); + if ((readl(addr) == test_pattern) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + + if (row == 11) { + error("%s: row detect error\n", __func__); + return -EINVAL; + } + + /* Record results */ + debug("%s: col %d, row %d\n", __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 = 0; + + return 0; +} + +static int msch_niu_config(struct rk3368_msch *msch, + struct rk3368_sdram_params *params) +{ + int i; + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1); + const u8 rows = params->chan.cs0_row; + + /* + * The DDR address-translation table always assumes a 32bit + * bus and the comparison below takes care of adjusting for + * a 16bit bus (i.e. one column-address is consumed). + */ + const struct { + u8 rows; + u8 columns; + u8 type; + } ddrconf_table[] = { + /* + * C-B-R-D patterns are first. For these we require an + * exact match for the columns and rows (as there's + * one entry per possible configuration). + */ + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD }, + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD }, + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD }, + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD }, + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD }, + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD }, + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD }, + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD }, + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD }, + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD }, + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD }, + /* + * 11 through 13 are C-R-B-D patterns. These are + * matched for an exact number of columns and to + * ensure that the hardware uses at least as many rows + * as the pattern requires (i.e. we make sure that + * there's no gaps up until we hit the device/chip-select; + * however, these patterns can accept up to 16 rows, + * as the row-address continues right after the CS + * switching) + */ + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD }, + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD }, + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD }, + /* + * 14 and 15 are catch-all variants using a C-B-D-R + * scheme (i.e. alternating the chip-select every time + * C-B overflows) and stuffing the remaining C-bits + * into the top. Matching needs to make sure that the + * number of columns is either an exact match (i.e. we + * can use less the the maximum number of rows) -or- + * that the columns exceed what is given in this table + * and the rows are an exact match (in which case the + * remaining C-bits will be stuffed onto the top after + * the device/chip-select switches). + */ + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR }, + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR }, + }; + + /* + * For C-B-R-D, we need an exact match (i.e. both for the number of + * columns and rows), while for C-B-D-R, only the the number of + * columns needs to match. + */ + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) { + bool match = false; + + /* If this entry if for a different matcher, then skip it */ + if (ddrconf_table[i].type != params->memory_schedule) + continue; + + /* + * Match according to the rules (exact/inexact/at-least) + * documented in the ddrconf_table above. + */ + switch (params->memory_schedule) { + case DMC_MSCH_CBRD: + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); + break; + + case DMC_MSCH_CRBD: + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); + break; + + case DMC_MSCH_CBDR: + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); + break; + + default: + break; + } + + if (match) { + debug("%s: setting ddrconf 0x%x\n", __func__, i); + writel(i, &msch->ddrconf); + return 0; + } + } + + error("%s: ddrconf (NIU config) not found\n", __func__); + return -EINVAL; +} + +static void dram_all_config(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3368_pmu_grf *pmugrf = priv->pmugrf; + struct rk3368_sdram_params *params = dev_get_platdata(dev); + const struct rk3288_sdram_channel *info = &params->chan; + u32 sys_reg = 0; + const int chan = 0; + + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT; + + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); + + writel(sys_reg, &pmugrf->os_reg[2]); +} + +static int setup_sdram(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3368_sdram_params *params = dev_get_platdata(dev); + + struct rk3368_ddr_pctl *pctl = priv->pctl; + struct rk3368_ddrphy *ddrphy = priv->phy; + struct rk3368_cru *cru = priv->cru; + struct rk3368_grf *grf = priv->grf; + struct rk3368_msch *msch = priv->msch; + + int ret; + + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); + if (ret < 0) { + debug("%s: could not set DDR clock: %d\n", __func__, ret); + return ret; + } + + /* Update the read-latency for the RK3368 */ + writel(0x32, &msch->readlatency); + + /* Initialise the DDR PCTL and DDR PHY */ + ddrctl_reset(cru); + ddrphy_reset(ddrphy); + ddrphy_config_delays(ddrphy, params->ddr_freq); + dfi_cfg(pctl); + /* Configure relative system information of grf_ddrc0_con0 register */ + ddr_set_ddr3_mode(grf, true); + ddr_set_noc_spr_err_stall(grf, true); + /* Calculate timings */ + pctl_calc_timings(params, params->ddr_freq); + /* Initialise the device timings in protocol controller */ + pctl_cfg(pctl, params, grf); + /* Configure AL, CL ... information of PHY registers */ + ddrphy_config(ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + + /* Initialize DRAM and configure with mode-register values */ + ret = memory_init(pctl, params); + if (ret) + goto error; + + move_to_config_state(pctl); + /* Perform data-training */ + ddrphy_data_training(pctl, ddrphy); + move_to_access_state(pctl); + + /* TODO(prt): could detect rank in training... */ + params->chan.rank = 2; + /* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw = 2; /* 32bit wide bus */ + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */ + + /* DDR3 is always 8 bank */ + params->chan.bk = 3; + /* Detect col and row number */ + ret = sdram_col_row_detect(dev); + if (ret) + goto error; + + /* Configure NIU DDR configuration */ + ret = msch_niu_config(msch, params); + if (ret) + goto error; + + /* set up OS_REG to communicate w/ next stage and OS */ + dram_all_config(dev); + + return 0; + +error: + printf("DRAM init failed!\n"); + hang(); +} +#endif + +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev) +{ + int ret = 0; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3368_sdram_params *plat = dev_get_platdata(dev); + + ret = regmap_init_mem(dev, &plat->map); + if (ret) + return ret; +#endif + + return ret; +} + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rk3368_sdram_params *plat = dev_get_platdata(dev); + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; + int ret; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + ret = regmap_init_mem_platdata(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, + &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static int rk3368_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD + struct rk3368_sdram_params *plat = dev_get_platdata(dev); + struct rk3368_ddr_pctl *pctl; + struct rk3368_ddrphy *ddrphy; + struct rk3368_cru *cru; + struct rk3368_grf *grf; + struct rk3368_msch *msch; + int ret; + struct udevice *dev_clk; +#endif + struct dram_info *priv = dev_get_priv(dev); + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_platdata(dev); + if (ret) + return ret; +#endif + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl = regmap_get_range(plat->map, 0); + ddrphy = regmap_get_range(plat->map, 1); + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + priv->ddr_clk.id = CLK_DDR; + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + cru = rockchip_get_cru(); + priv->cru = cru; + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); + + ret = setup_sdram(dev); + if (ret) + return ret; +#endif + + priv->info.base = 0; + priv->info.size = + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); + + /* + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is + * inaccessible for some IP controller. + */ + priv->info.size = min(priv->info.size, (size_t)0xfe000000); + + return 0; +} + +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + return 0; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible = "rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3368) = { + .name = "rockchip_rk3368_dmc", + .id = UCLASS_RAM, + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params), +}; diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h new file mode 100644 index 0000000..b06ffde --- /dev/null +++ b/include/dt-bindings/memory/rk3368-dmc.h @@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif