[U-Boot] [PATCH 00/10] arm: vf610/vf610twr: vybrid tower fixes and enhancements
arm: vf610: vf610twr: vybrid tower fixes and enhancements
This patch series addresses several vixes and enhancements for the vybrid tower.
Tested on a TWR-VF65GS10 Rev G.
Marcel Ziswiler (10): arm: vf610: fix anadig register struct arm: vf610: clean-up anadig register struct arm: vf610: add uart0 clock definition arm: vf610: add anadig pll5 definitions arm: vf610: add enet1 base address definition arm: vf610: add rmii clkout iomux definition arm: vf610: add uart0 tx/rx iomux definitions arm: vf610: add rmii1 iomux definitions arm: vf610: fix double iomux configuration for vf610twr board arm: vf610: remove obsolete uart port configuration
arch/arm/include/asm/arch-vf610/crm_regs.h | 57 ++++++++++++++----------- arch/arm/include/asm/arch-vf610/imx-regs.h | 1 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 12 ++++++ board/freescale/vf610twr/vf610twr.c | 1 - include/configs/vf610twr.h | 1 - 5 files changed, 45 insertions(+), 27 deletions(-)
The anadig_reg structure started at the wrong offset (fixed by adding resvA[4]), was missing some reserved field required for alignment purpose (resvB[3] between pll4_denom and pll6_ctrl) and further contained too short a reserved field causing further miss-alignment (resv10[7]).
Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl);
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- arch/arm/include/asm/arch-vf610/crm_regs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 85f1fda..57a0242 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -55,6 +55,7 @@ struct ccm_reg {
/* Analog components control digital interface (ANADIG) */ struct anadig_reg { + u32 resvA[4]; u32 pll3_ctrl; u32 resv0[3]; u32 pll7_ctrl; @@ -72,12 +73,13 @@ struct anadig_reg { u32 pll4_num; u32 resv7[3]; u32 pll4_denom; + u32 resvB[3]; u32 pll6_ctrl; u32 resv8[3]; u32 pll6_num; u32 resv9[3]; u32 pll6_denom; - u32 resv10[3]; + u32 resv10[7]; u32 pll5_ctrl; u32 resv11[3]; u32 pll3_pfd;
On Tue, Sep 17, 2013 at 7:45 AM, Marcel Ziswiler marcel@ziswiler.com wrote:
The anadig_reg structure started at the wrong offset (fixed by adding resvA[4]), was missing some reserved field required for alignment purpose (resvB[3] between pll4_denom and pll6_ctrl) and further contained too short a reserved field causing further miss-alignment (resv10[7]).
Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl);
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com
I agree with the way to fix it but it is a little bit hard to get it is a 'reserved'; we used reserved_<where> to make it more explicit.
Take a look at http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-mxs/regs... for an usage example.
On 09/17/2013 03:27 PM, Otavio Salvador wrote:
I agree with the way to fix it but it is a little bit hard to get it is a 'reserved'; we used reserved_<where> to make it more explicit. Take a look at http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-mxs/regs... for an usage example.
At the end of the day those reserved fields are just memory holes in the register set. I don't think they really belong to either the previous last nor the first next valid register. Also I don't really see how the naming convention in use at above mentioned link is much more consistent.
If we really do want do change the way this is done then probably naming it after the actual memory offset would be most helpful (e.g. reserved_0x014[3]). If you agree I will cook up a new patch series in that respect.
Re-number all the resv reserved fields.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- arch/arm/include/asm/arch-vf610/crm_regs.h | 54 ++++++++++++++-------------- 1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 57a0242..d5c9387 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -55,59 +55,59 @@ struct ccm_reg {
/* Analog components control digital interface (ANADIG) */ struct anadig_reg { - u32 resvA[4]; + u32 resv0[4]; u32 pll3_ctrl; - u32 resv0[3]; - u32 pll7_ctrl; u32 resv1[3]; - u32 pll2_ctrl; + u32 pll7_ctrl; u32 resv2[3]; - u32 pll2_ss; + u32 pll2_ctrl; u32 resv3[3]; - u32 pll2_num; + u32 pll2_ss; u32 resv4[3]; - u32 pll2_denom; + u32 pll2_num; u32 resv5[3]; - u32 pll4_ctrl; + u32 pll2_denom; u32 resv6[3]; - u32 pll4_num; + u32 pll4_ctrl; u32 resv7[3]; + u32 pll4_num; + u32 resv8[3]; u32 pll4_denom; - u32 resvB[3]; + u32 resv9[3]; u32 pll6_ctrl; - u32 resv8[3]; + u32 resv10[3]; u32 pll6_num; - u32 resv9[3]; + u32 resv11[3]; u32 pll6_denom; - u32 resv10[7]; + u32 resv12[7]; u32 pll5_ctrl; - u32 resv11[3]; + u32 resv13[3]; u32 pll3_pfd; - u32 resv12[3]; + u32 resv14[3]; u32 pll2_pfd; - u32 resv13[3]; + u32 resv15[3]; u32 reg_1p1; - u32 resv14[3]; + u32 resv16[3]; u32 reg_3p0; - u32 resv15[3]; + u32 resv17[3]; u32 reg_2p5; - u32 resv16[7]; + u32 resv18[7]; u32 ana_misc0; - u32 resv17[3]; + u32 resv19[3]; u32 ana_misc1; - u32 resv18[63]; + u32 resv20[63]; u32 anadig_digprog; - u32 resv19[3]; + u32 resv21[3]; u32 pll1_ctrl; - u32 resv20[3]; + u32 resv22[3]; u32 pll1_ss; - u32 resv21[3]; + u32 resv23[3]; u32 pll1_num; - u32 resv22[3]; + u32 resv24[3]; u32 pll1_denom; - u32 resv23[3]; + u32 resv25[3]; u32 pll1_pdf; - u32 resv24[3]; + u32 resv26[3]; u32 pll_lock; }; #endif
Add CCM_CCGR0_UART0_CTRL_MASK clock definition for UART0 aka SCI0.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- arch/arm/include/asm/arch-vf610/crm_regs.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index d5c9387..490e368 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -166,6 +166,7 @@ struct anadig_reg { #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
#define CCM_REG_CTRL_MASK 0xffffffff +#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
Add ANADIG PLL5 control definitions required for Ethernet RMII clock configuration.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 490e368..d4ad957 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -187,6 +187,10 @@ struct anadig_reg { #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
+#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL5_CTRL_DIV_SELECT 1 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL2_CTRL_DIV_SELECT 1
Add secondary Ethernet MAC RMII1 base address definition in preparation of potential secondary only board configurations.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- arch/arm/include/asm/arch-vf610/imx-regs.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index b8c877f..c2f9761 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -85,6 +85,7 @@ #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) +#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
/* MUX mode and PAD ctrl are in one register */ #define CONFIG_IOMUX_SHARE_CONF_REG
Add VF610_PAD_PTA6__RMII0_CLKOUT iomux definition eventually required for internal (e.g. crystal-less) Ethernet clocking.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 4a39eb0..e315fe4 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -22,6 +22,7 @@
enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
Add UART0 aka SCI0 TX/RX iomux definitions.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index e315fe4..a6f7132 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -25,6 +25,8 @@ enum { VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
Add secondary RMII1 iomux definitions.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index a6f7132..1b410c3 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -36,6 +36,15 @@ enum { VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
-----Original Message----- From: Marcel Ziswiler [mailto:marcel@ziswiler.com] Sent: Tuesday, September 17, 2013 6:45 PM To: u-boot@lists.denx.de Cc: Wang Huan-B18965; Marcel Ziswiler Subject: [PATCH 08/10] arm: vf610: add rmii1 iomux definitions
Add secondary RMII1 iomux definitions.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index a6f7132..1b410c3 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -36,6 +36,15 @@ enum { VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00b8, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00b4, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00bc, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00c0, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00c4, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00c8, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00cc, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00D0, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00D4, 1,
__NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
[Alison Wang] For these RMII1 IOMUX definitions, the mux_ctrl_ofs parameter should be the same as pad_ctrL_ofs parameter. In this patch, the mux_ctrl_ofs are all for RMII0.
Best Regards, Alison Wang
On 09/22/2013 07:56 AM, Wang Huan-B18965 wrote:
-----Original Message----- From: Marcel Ziswiler [mailto:marcel@ziswiler.com] Sent: Tuesday, September 17, 2013 6:45 PM To: u-boot@lists.denx.de Cc: Wang Huan-B18965; Marcel Ziswiler Subject: [PATCH 08/10] arm: vf610: add rmii1 iomux definitions
Add secondary RMII1 iomux definitions.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index a6f7132..1b410c3 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -36,6 +36,15 @@ enum { VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00b8, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00b4, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00bc, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00c0, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00c4, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00c8, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00cc, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00D0, 1,
__NA_, 0, VF610_ENET_PAD_CTRL),
- VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00D4, 1,
__NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
[Alison Wang] For these RMII1 IOMUX definitions, the mux_ctrl_ofs parameter should be the same as pad_ctrL_ofs parameter. In this patch, the mux_ctrl_ofs are all for RMII0.
Yes, you are absolutely right. How could I have missed that one - stupid me. Strange that it actually worked at all.
I will cook up a new patch series shortly.
Get rid of double VF610_PAD_DDR_A15__DDR_A_15 iomux configuration.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- board/freescale/vf610twr/vf610twr.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 699ea7f..4ee74c0 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -31,7 +31,6 @@ void setup_iomux_ddr(void) { static const iomux_v3_cfg_t ddr_pads[] = { VF610_PAD_DDR_A15__DDR_A_15, - VF610_PAD_DDR_A15__DDR_A_15, VF610_PAD_DDR_A14__DDR_A_14, VF610_PAD_DDR_A13__DDR_A_13, VF610_PAD_DDR_A12__DDR_A_12,
Get rid of obsolete CONFIG_SYS_UART_PORT configuration option.
Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- include/configs/vf610twr.h | 1 - 1 file changed, 1 deletion(-)
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 5a7a066..432a69d 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -39,7 +39,6 @@
/* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_UART_PORT (1) #define CONFIG_BAUDRATE 115200
#undef CONFIG_CMD_IMLS
participants (3)
-
Marcel Ziswiler -
Otavio Salvador -
Wang Huan-B18965