You are right. We used to have this bit set for 8555 and 8541. I believe it was removed/dropped/lost by this commit 457caecdbca3df21a93abff19eab12dbc61b7897.

York

On 02/12/2015 11:35 PM, Curt Brune wrote:

Hello,

I am curious about the setting of the SS_EN bit in the DDR_SDRAM_CLK_CNLT register:

Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, “DDR SDRAM Initialization Sequence,” for details.

0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously.

The MPC8555E reference manual and this app note are pretty clear that this bit should be set:

http://cache.freescale.com/files/32bit/doc/app_note/AN2805.pdf (page 17)

set_ddr_sdram_clk_cntl() in u-boot/drivers/ddr/fsl/ctrl_regs.c has this:

    clk_adjust = popts->clk_adjust;
    ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;

There is no accounting for the SS_EN bit on 8541/8555E. I would have expected to see an #ifdef for the MPC8555 that sets the SS_EN bit.

I know 8541 has been around forever and is working fine. I am just trying to find some back ground information on this setting.

Searching the old mailing lists did not turn up anything useful.

Any insight is appreciated.

Cheers, Curt