[PATCH 1/2] stm32mp: fdt: update etzpc for STM32MP15x

Introduce STM32MP15 function and defines to prepare the STM32MP13 introduction.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---
arch/arm/mach-stm32mp/fdt.c | 123 ++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 56 deletions(-)
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index ad45728949..5d37a44d97 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -28,13 +28,13 @@
#define ETZPC_RESERVED 0xffffffff
-#define STM32_FDCAN_BASE 0x4400e000 -#define STM32_CRYP2_BASE 0x4c005000 -#define STM32_CRYP1_BASE 0x54001000 -#define STM32_GPU_BASE 0x59000000 -#define STM32_DSI_BASE 0x5a000000 +#define STM32MP15_FDCAN_BASE 0x4400e000 +#define STM32MP15_CRYP2_BASE 0x4c005000 +#define STM32MP15_CRYP1_BASE 0x54001000 +#define STM32MP15_GPU_BASE 0x59000000 +#define STM32MP15_DSI_BASE 0x5a000000
-static const u32 stm32mp1_ip_addr[] = { +static const u32 stm32mp15_ip_addr[] = { 0x5c008000, /* 00 stgenc */ 0x54000000, /* 01 bkpsram */ 0x5c003000, /* 02 iwdg1 */ @@ -44,7 +44,7 @@ static const u32 stm32mp1_ip_addr[] = { ETZPC_RESERVED, /* 06 reserved */ 0x54003000, /* 07 rng1 */ 0x54002000, /* 08 hash1 */ - STM32_CRYP1_BASE, /* 09 cryp1 */ + STM32MP15_CRYP1_BASE, /* 09 cryp1 */ 0x5a003000, /* 0A ddrctrl */ 0x5a004000, /* 0B ddrphyc */ 0x5c009000, /* 0C i2c6 */ @@ -97,7 +97,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x4400b000, /* 3B sai2 */ 0x4400c000, /* 3C sai3 */ 0x4400d000, /* 3D dfsdm */ - STM32_FDCAN_BASE, /* 3E tt_fdcan */ + STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ ETZPC_RESERVED, /* 3F reserved */ 0x50021000, /* 40 lptim2 */ 0x50022000, /* 41 lptim3 */ @@ -110,7 +110,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x48003000, /* 48 adc */ 0x4c002000, /* 49 hash2 */ 0x4c003000, /* 4A rng2 */ - STM32_CRYP2_BASE, /* 4B cryp2 */ + STM32MP15_CRYP2_BASE, /* 4B cryp2 */ ETZPC_RESERVED, /* 4C reserved */ ETZPC_RESERVED, /* 4D reserved */ ETZPC_RESERVED, /* 4E reserved */ @@ -163,8 +163,13 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) int offset, shift; u32 addr, status, decprot[ETZPC_DECPROT_NB];
- array = stm32mp1_ip_addr; - array_size = ARRAY_SIZE(stm32mp1_ip_addr); + if (IS_ENABLED(CONFIG_STM32MP13x)) + return 0; + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + array = stm32mp15_ip_addr; + array_size = ARRAY_SIZE(stm32mp15_ip_addr); + }
for (i = 0; i < ETZPC_DECPROT_NB; i++) decprot[i] = readl(ETZPC_DECPROT(i)); @@ -248,33 +253,9 @@ static void stm32_fdt_disable_optee(void *blob) } }
-/* - * This function is called right before the kernel is booted. "blob" is the - * device tree that will be passed to the kernel. - */ -int ft_system_setup(void *blob, struct bd_info *bd) +static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) { - int ret = 0; - int soc; - u32 pkg, cpu; - char name[SOC_NAME_SIZE]; - - if (IS_ENABLED(CONFIG_STM32MP13x)) - return 0; - - soc = fdt_path_offset(blob, "/soc"); - if (soc < 0) - return soc; - - if (CONFIG_IS_ENABLED(STM32_ETZPC)) { - ret = stm32_fdt_fixup_etzpc(blob, soc); - if (ret) - return ret; - } - - /* MPUs Part Numbers and name*/ - cpu = get_cpu_type(); - get_soc_name(name); + u32 pkg;
switch (cpu) { case CPU_STM32MP151Fxx: @@ -284,19 +265,18 @@ int ft_system_setup(void *blob, struct bd_info *bd) stm32_fdt_fixup_cpu(blob, name); /* after cpu delete we can't trust the soc offsets anymore */ soc = fdt_path_offset(blob, "/soc"); - stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name); - /* fall through */ + stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name); + fallthrough; case CPU_STM32MP153Fxx: case CPU_STM32MP153Dxx: case CPU_STM32MP153Cxx: case CPU_STM32MP153Axx: - stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name); - stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name); + stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name); + stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name); break; default: break; } - switch (cpu) { case CPU_STM32MP157Dxx: case CPU_STM32MP157Axx: @@ -304,13 +284,14 @@ int ft_system_setup(void *blob, struct bd_info *bd) case CPU_STM32MP153Axx: case CPU_STM32MP151Dxx: case CPU_STM32MP151Axx: - stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name); - stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp", + name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp", + name); break; default: break; } - switch (get_cpu_package()) { case STM32MP15_PKG_AA_LBGA448: pkg = STM32MP_PKG_AA; @@ -334,18 +315,48 @@ int ft_system_setup(void *blob, struct bd_info *bd) do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", "st,package", pkg, false); } +} + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + int ret = 0; + int soc; + u32 cpu; + char name[SOC_NAME_SIZE]; + + soc = fdt_path_offset(blob, "/soc"); + if (soc < 0) + return soc; + + if (CONFIG_IS_ENABLED(STM32_ETZPC)) { + ret = stm32_fdt_fixup_etzpc(blob, soc); + if (ret) + return ret; + }
- /* - * TEMP: remove OP-TEE nodes in kernel device tree - * copied from U-Boot device tree by optee_copy_fdt_nodes - * when OP-TEE is not detected (probe failed) - * these OP-TEE nodes are present in <board>-u-boot.dtsi - * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility - * when FIP is not used by TF-A - */ - if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && - !tee_find_device(NULL, NULL, NULL, NULL)) - stm32_fdt_disable_optee(blob); + /* MPUs Part Numbers and name*/ + cpu = get_cpu_type(); + get_soc_name(name); + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + stm32mp15_fdt_fixup(blob, soc, cpu, name); + + /* + * TEMP: remove OP-TEE nodes in kernel device tree + * copied from U-Boot device tree by optee_copy_fdt_nodes + * when OP-TEE is not detected (probe failed) + * these OP-TEE nodes are present in <board>-u-boot.dtsi + * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility + * when FIP is not used by TF-A + */ + if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && + !tee_find_device(NULL, NULL, NULL, NULL)) + stm32_fdt_disable_optee(blob); + }
return ret; }

Add support of STM32MP13x the ETZPC part of fdt.c
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---
arch/arm/mach-stm32mp/fdt.c | 153 +++++++++++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index 5d37a44d97..bf2ef66034 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -28,12 +28,119 @@
#define ETZPC_RESERVED 0xffffffff
+#define STM32MP13_FDCAN_BASE 0x4400F000 +#define STM32MP13_ADC1_BASE 0x48003000 +#define STM32MP13_TSC_BASE 0x5000B000 +#define STM32MP13_CRYP_BASE 0x54002000 +#define STM32MP13_ETH2_BASE 0x5800E000 +#define STM32MP13_DCMIPP_BASE 0x5A000000 +#define STM32MP13_LTDC_BASE 0x5A010000 + #define STM32MP15_FDCAN_BASE 0x4400e000 #define STM32MP15_CRYP2_BASE 0x4c005000 #define STM32MP15_CRYP1_BASE 0x54001000 #define STM32MP15_GPU_BASE 0x59000000 #define STM32MP15_DSI_BASE 0x5a000000
+static const u32 stm32mp13_ip_addr[] = { + 0x50025000, /* 0 VREFBUF APB3 */ + 0x50021000, /* 1 LPTIM2 APB3 */ + 0x50022000, /* 2 LPTIM3 APB3 */ + STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */ + STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */ + 0x5A006000, /* 5 USBPHYCTRL APB4 */ + 0x5A003000, /* 6 DDRCTRLPHY APB4 */ + ETZPC_RESERVED, /* 7 Reserved*/ + ETZPC_RESERVED, /* 8 Reserved*/ + ETZPC_RESERVED, /* 9 Reserved*/ + 0x5C006000, /* 10 TZC APB5 */ + 0x58001000, /* 11 MCE APB5 */ + 0x5C000000, /* 12 IWDG1 APB5 */ + 0x5C008000, /* 13 STGENC APB5 */ + ETZPC_RESERVED, /* 14 Reserved*/ + ETZPC_RESERVED, /* 15 Reserved*/ + 0x4C000000, /* 16 USART1 APB6 */ + 0x4C001000, /* 17 USART2 APB6 */ + 0x4C002000, /* 18 SPI4 APB6 */ + 0x4C003000, /* 19 SPI5 APB6 */ + 0x4C004000, /* 20 I2C3 APB6 */ + 0x4C005000, /* 21 I2C4 APB6 */ + 0x4C006000, /* 22 I2C5 APB6 */ + 0x4C007000, /* 23 TIM12 APB6 */ + 0x4C008000, /* 24 TIM13 APB6 */ + 0x4C009000, /* 25 TIM14 APB6 */ + 0x4C00A000, /* 26 TIM15 APB6 */ + 0x4C00B000, /* 27 TIM16 APB6 */ + 0x4C00C000, /* 28 TIM17 APB6 */ + ETZPC_RESERVED, /* 29 Reserved*/ + ETZPC_RESERVED, /* 30 Reserved*/ + ETZPC_RESERVED, /* 31 Reserved*/ + STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */ + 0x48004000, /* 33 ADC2 AHB2 */ + 0x49000000, /* 34 OTG AHB2 */ + ETZPC_RESERVED, /* 35 Reserved*/ + ETZPC_RESERVED, /* 36 Reserved*/ + STM32MP13_TSC_BASE, /* 37 TSC AHB4 */ + ETZPC_RESERVED, /* 38 Reserved*/ + ETZPC_RESERVED, /* 39 Reserved*/ + 0x54004000, /* 40 RNG AHB5 */ + 0x54003000, /* 41 HASH AHB5 */ + STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */ + 0x54005000, /* 43 SAES AHB5 */ + 0x54006000, /* 44 PKA AHB5 */ + 0x54000000, /* 45 BKPSRAM AHB5 */ + ETZPC_RESERVED, /* 46 Reserved*/ + ETZPC_RESERVED, /* 47 Reserved*/ + 0x5800A000, /* 48 ETH1 AHB6 */ + STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */ + 0x58005000, /* 50 SDMMC1 AHB6 */ + 0x58007000, /* 51 SDMMC2 AHB6 */ + ETZPC_RESERVED, /* 52 Reserved*/ + ETZPC_RESERVED, /* 53 Reserved*/ + 0x58002000, /* 54 FMC AHB6 */ + 0x58003000, /* 55 QSPI AHB6 */ + ETZPC_RESERVED, /* 56 Reserved*/ + ETZPC_RESERVED, /* 57 Reserved*/ + ETZPC_RESERVED, /* 58 Reserved*/ + ETZPC_RESERVED, /* 59 Reserved*/ + 0x30000000, /* 60 SRAM1 MLAHB */ + 0x30004000, /* 61 SRAM2 MLAHB */ + 0x30006000, /* 62 SRAM3 MLAHB */ + ETZPC_RESERVED, /* 63 Reserved*/ + ETZPC_RESERVED, /* 64 Reserved*/ + ETZPC_RESERVED, /* 65 Reserved*/ + ETZPC_RESERVED, /* 66 Reserved*/ + ETZPC_RESERVED, /* 67 Reserved*/ + ETZPC_RESERVED, /* 68 Reserved*/ + ETZPC_RESERVED, /* 69 Reserved*/ + ETZPC_RESERVED, /* 70 Reserved*/ + ETZPC_RESERVED, /* 71 Reserved*/ + ETZPC_RESERVED, /* 72 Reserved*/ + ETZPC_RESERVED, /* 73 Reserved*/ + ETZPC_RESERVED, /* 74 Reserved*/ + ETZPC_RESERVED, /* 75 Reserved*/ + ETZPC_RESERVED, /* 76 Reserved*/ + ETZPC_RESERVED, /* 77 Reserved*/ + ETZPC_RESERVED, /* 78 Reserved*/ + ETZPC_RESERVED, /* 79 Reserved*/ + ETZPC_RESERVED, /* 80 Reserved*/ + ETZPC_RESERVED, /* 81 Reserved*/ + ETZPC_RESERVED, /* 82 Reserved*/ + ETZPC_RESERVED, /* 83 Reserved*/ + ETZPC_RESERVED, /* 84 Reserved*/ + ETZPC_RESERVED, /* 85 Reserved*/ + ETZPC_RESERVED, /* 86 Reserved*/ + ETZPC_RESERVED, /* 87 Reserved*/ + ETZPC_RESERVED, /* 88 Reserved*/ + ETZPC_RESERVED, /* 89 Reserved*/ + ETZPC_RESERVED, /* 90 Reserved*/ + ETZPC_RESERVED, /* 91 Reserved*/ + ETZPC_RESERVED, /* 92 Reserved*/ + ETZPC_RESERVED, /* 93 Reserved*/ + ETZPC_RESERVED, /* 94 Reserved*/ + ETZPC_RESERVED, /* 95 Reserved*/ +}; + static const u32 stm32mp15_ip_addr[] = { 0x5c008000, /* 00 stgenc */ 0x54000000, /* 01 bkpsram */ @@ -163,8 +270,10 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) int offset, shift; u32 addr, status, decprot[ETZPC_DECPROT_NB];
- if (IS_ENABLED(CONFIG_STM32MP13x)) - return 0; + if (IS_ENABLED(CONFIG_STM32MP13x)) { + array = stm32mp13_ip_addr; + array_size = ARRAY_SIZE(stm32mp13_ip_addr); + }
if (IS_ENABLED(CONFIG_STM32MP15x)) { array = stm32mp15_ip_addr; @@ -253,6 +362,43 @@ static void stm32_fdt_disable_optee(void *blob) } }
+static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name) +{ + switch (cpu) { + case CPU_STM32MP131Fxx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Cxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name); + stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name); + fallthrough; + case CPU_STM32MP133Fxx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Cxx: + case CPU_STM32MP133Axx: + stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name); + stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp", + name); + stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name); + break; + default: + break; + } + + switch (cpu) { + case CPU_STM32MP135Dxx: + case CPU_STM32MP135Axx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Axx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name); + break; + default: + break; + } +} + static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) { u32 pkg; @@ -342,6 +488,9 @@ int ft_system_setup(void *blob, struct bd_info *bd) cpu = get_cpu_type(); get_soc_name(name);
+ if (IS_ENABLED(CONFIG_STM32MP13x)) + stm32mp13_fdt_fixup(blob, soc, cpu, name); + if (IS_ENABLED(CONFIG_STM32MP15x)) { stm32mp15_fdt_fixup(blob, soc, cpu, name);

Hi Patrick
On 5/9/22 17:13, Patrick Delaunay wrote:
Add support of STM32MP13x the ETZPC part of fdt.c
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com
arch/arm/mach-stm32mp/fdt.c | 153 +++++++++++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index 5d37a44d97..bf2ef66034 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -28,12 +28,119 @@
#define ETZPC_RESERVED 0xffffffff
+#define STM32MP13_FDCAN_BASE 0x4400F000 +#define STM32MP13_ADC1_BASE 0x48003000 +#define STM32MP13_TSC_BASE 0x5000B000 +#define STM32MP13_CRYP_BASE 0x54002000 +#define STM32MP13_ETH2_BASE 0x5800E000 +#define STM32MP13_DCMIPP_BASE 0x5A000000 +#define STM32MP13_LTDC_BASE 0x5A010000
#define STM32MP15_FDCAN_BASE 0x4400e000 #define STM32MP15_CRYP2_BASE 0x4c005000 #define STM32MP15_CRYP1_BASE 0x54001000 #define STM32MP15_GPU_BASE 0x59000000 #define STM32MP15_DSI_BASE 0x5a000000
+static const u32 stm32mp13_ip_addr[] = {
- 0x50025000, /* 0 VREFBUF APB3 */
- 0x50021000, /* 1 LPTIM2 APB3 */
- 0x50022000, /* 2 LPTIM3 APB3 */
- STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */
- STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
- 0x5A006000, /* 5 USBPHYCTRL APB4 */
- 0x5A003000, /* 6 DDRCTRLPHY APB4 */
- ETZPC_RESERVED, /* 7 Reserved*/
- ETZPC_RESERVED, /* 8 Reserved*/
- ETZPC_RESERVED, /* 9 Reserved*/
- 0x5C006000, /* 10 TZC APB5 */
- 0x58001000, /* 11 MCE APB5 */
- 0x5C000000, /* 12 IWDG1 APB5 */
- 0x5C008000, /* 13 STGENC APB5 */
- ETZPC_RESERVED, /* 14 Reserved*/
- ETZPC_RESERVED, /* 15 Reserved*/
- 0x4C000000, /* 16 USART1 APB6 */
- 0x4C001000, /* 17 USART2 APB6 */
- 0x4C002000, /* 18 SPI4 APB6 */
- 0x4C003000, /* 19 SPI5 APB6 */
- 0x4C004000, /* 20 I2C3 APB6 */
- 0x4C005000, /* 21 I2C4 APB6 */
- 0x4C006000, /* 22 I2C5 APB6 */
- 0x4C007000, /* 23 TIM12 APB6 */
- 0x4C008000, /* 24 TIM13 APB6 */
- 0x4C009000, /* 25 TIM14 APB6 */
- 0x4C00A000, /* 26 TIM15 APB6 */
- 0x4C00B000, /* 27 TIM16 APB6 */
- 0x4C00C000, /* 28 TIM17 APB6 */
- ETZPC_RESERVED, /* 29 Reserved*/
- ETZPC_RESERVED, /* 30 Reserved*/
- ETZPC_RESERVED, /* 31 Reserved*/
- STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */
- 0x48004000, /* 33 ADC2 AHB2 */
- 0x49000000, /* 34 OTG AHB2 */
- ETZPC_RESERVED, /* 35 Reserved*/
- ETZPC_RESERVED, /* 36 Reserved*/
- STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
- ETZPC_RESERVED, /* 38 Reserved*/
- ETZPC_RESERVED, /* 39 Reserved*/
- 0x54004000, /* 40 RNG AHB5 */
- 0x54003000, /* 41 HASH AHB5 */
- STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */
- 0x54005000, /* 43 SAES AHB5 */
- 0x54006000, /* 44 PKA AHB5 */
- 0x54000000, /* 45 BKPSRAM AHB5 */
- ETZPC_RESERVED, /* 46 Reserved*/
- ETZPC_RESERVED, /* 47 Reserved*/
- 0x5800A000, /* 48 ETH1 AHB6 */
- STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */
- 0x58005000, /* 50 SDMMC1 AHB6 */
- 0x58007000, /* 51 SDMMC2 AHB6 */
- ETZPC_RESERVED, /* 52 Reserved*/
- ETZPC_RESERVED, /* 53 Reserved*/
- 0x58002000, /* 54 FMC AHB6 */
- 0x58003000, /* 55 QSPI AHB6 */
- ETZPC_RESERVED, /* 56 Reserved*/
- ETZPC_RESERVED, /* 57 Reserved*/
- ETZPC_RESERVED, /* 58 Reserved*/
- ETZPC_RESERVED, /* 59 Reserved*/
- 0x30000000, /* 60 SRAM1 MLAHB */
- 0x30004000, /* 61 SRAM2 MLAHB */
- 0x30006000, /* 62 SRAM3 MLAHB */
- ETZPC_RESERVED, /* 63 Reserved*/
- ETZPC_RESERVED, /* 64 Reserved*/
- ETZPC_RESERVED, /* 65 Reserved*/
- ETZPC_RESERVED, /* 66 Reserved*/
- ETZPC_RESERVED, /* 67 Reserved*/
- ETZPC_RESERVED, /* 68 Reserved*/
- ETZPC_RESERVED, /* 69 Reserved*/
- ETZPC_RESERVED, /* 70 Reserved*/
- ETZPC_RESERVED, /* 71 Reserved*/
- ETZPC_RESERVED, /* 72 Reserved*/
- ETZPC_RESERVED, /* 73 Reserved*/
- ETZPC_RESERVED, /* 74 Reserved*/
- ETZPC_RESERVED, /* 75 Reserved*/
- ETZPC_RESERVED, /* 76 Reserved*/
- ETZPC_RESERVED, /* 77 Reserved*/
- ETZPC_RESERVED, /* 78 Reserved*/
- ETZPC_RESERVED, /* 79 Reserved*/
- ETZPC_RESERVED, /* 80 Reserved*/
- ETZPC_RESERVED, /* 81 Reserved*/
- ETZPC_RESERVED, /* 82 Reserved*/
- ETZPC_RESERVED, /* 83 Reserved*/
- ETZPC_RESERVED, /* 84 Reserved*/
- ETZPC_RESERVED, /* 85 Reserved*/
- ETZPC_RESERVED, /* 86 Reserved*/
- ETZPC_RESERVED, /* 87 Reserved*/
- ETZPC_RESERVED, /* 88 Reserved*/
- ETZPC_RESERVED, /* 89 Reserved*/
- ETZPC_RESERVED, /* 90 Reserved*/
- ETZPC_RESERVED, /* 91 Reserved*/
- ETZPC_RESERVED, /* 92 Reserved*/
- ETZPC_RESERVED, /* 93 Reserved*/
- ETZPC_RESERVED, /* 94 Reserved*/
- ETZPC_RESERVED, /* 95 Reserved*/
+};
static const u32 stm32mp15_ip_addr[] = { 0x5c008000, /* 00 stgenc */ 0x54000000, /* 01 bkpsram */ @@ -163,8 +270,10 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) int offset, shift; u32 addr, status, decprot[ETZPC_DECPROT_NB];
- if (IS_ENABLED(CONFIG_STM32MP13x))
return 0;
if (IS_ENABLED(CONFIG_STM32MP13x)) {
array = stm32mp13_ip_addr;
array_size = ARRAY_SIZE(stm32mp13_ip_addr);
}
if (IS_ENABLED(CONFIG_STM32MP15x)) { array = stm32mp15_ip_addr;
@@ -253,6 +362,43 @@ static void stm32_fdt_disable_optee(void *blob) } }
+static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name) +{
- switch (cpu) {
- case CPU_STM32MP131Fxx:
- case CPU_STM32MP131Dxx:
- case CPU_STM32MP131Cxx:
- case CPU_STM32MP131Axx:
stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name);
stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name);
fallthrough;
- case CPU_STM32MP133Fxx:
- case CPU_STM32MP133Dxx:
- case CPU_STM32MP133Cxx:
- case CPU_STM32MP133Axx:
stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name);
stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp",
name);
stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name);
break;
- default:
break;
- }
- switch (cpu) {
- case CPU_STM32MP135Dxx:
- case CPU_STM32MP135Axx:
- case CPU_STM32MP133Dxx:
- case CPU_STM32MP133Axx:
- case CPU_STM32MP131Dxx:
- case CPU_STM32MP131Axx:
stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name);
break;
- default:
break;
- }
+}
static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) { u32 pkg; @@ -342,6 +488,9 @@ int ft_system_setup(void *blob, struct bd_info *bd) cpu = get_cpu_type(); get_soc_name(name);
- if (IS_ENABLED(CONFIG_STM32MP13x))
stm32mp13_fdt_fixup(blob, soc, cpu, name);
- if (IS_ENABLED(CONFIG_STM32MP15x)) { stm32mp15_fdt_fixup(blob, soc, cpu, name);
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice

Hi,
On 5/9/22 17:13, Patrick Delaunay wrote:
Add support of STM32MP13x the ETZPC part of fdt.c
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com
arch/arm/mach-stm32mp/fdt.c | 153 +++++++++++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 2 deletions(-)
Applied to u-boot-stm/next, thanks!
Regards Patrick

Hi Patrick
On 5/9/22 17:13, Patrick Delaunay wrote:
Introduce STM32MP15 function and defines to prepare the STM32MP13 introduction.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com
arch/arm/mach-stm32mp/fdt.c | 123 ++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 56 deletions(-)
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index ad45728949..5d37a44d97 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -28,13 +28,13 @@
#define ETZPC_RESERVED 0xffffffff
-#define STM32_FDCAN_BASE 0x4400e000 -#define STM32_CRYP2_BASE 0x4c005000 -#define STM32_CRYP1_BASE 0x54001000 -#define STM32_GPU_BASE 0x59000000 -#define STM32_DSI_BASE 0x5a000000 +#define STM32MP15_FDCAN_BASE 0x4400e000 +#define STM32MP15_CRYP2_BASE 0x4c005000 +#define STM32MP15_CRYP1_BASE 0x54001000 +#define STM32MP15_GPU_BASE 0x59000000 +#define STM32MP15_DSI_BASE 0x5a000000
-static const u32 stm32mp1_ip_addr[] = { +static const u32 stm32mp15_ip_addr[] = { 0x5c008000, /* 00 stgenc */ 0x54000000, /* 01 bkpsram */ 0x5c003000, /* 02 iwdg1 */ @@ -44,7 +44,7 @@ static const u32 stm32mp1_ip_addr[] = { ETZPC_RESERVED, /* 06 reserved */ 0x54003000, /* 07 rng1 */ 0x54002000, /* 08 hash1 */
- STM32_CRYP1_BASE, /* 09 cryp1 */
- STM32MP15_CRYP1_BASE, /* 09 cryp1 */ 0x5a003000, /* 0A ddrctrl */ 0x5a004000, /* 0B ddrphyc */ 0x5c009000, /* 0C i2c6 */
@@ -97,7 +97,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x4400b000, /* 3B sai2 */ 0x4400c000, /* 3C sai3 */ 0x4400d000, /* 3D dfsdm */
- STM32_FDCAN_BASE, /* 3E tt_fdcan */
- STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ ETZPC_RESERVED, /* 3F reserved */ 0x50021000, /* 40 lptim2 */ 0x50022000, /* 41 lptim3 */
@@ -110,7 +110,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x48003000, /* 48 adc */ 0x4c002000, /* 49 hash2 */ 0x4c003000, /* 4A rng2 */
- STM32_CRYP2_BASE, /* 4B cryp2 */
- STM32MP15_CRYP2_BASE, /* 4B cryp2 */ ETZPC_RESERVED, /* 4C reserved */ ETZPC_RESERVED, /* 4D reserved */ ETZPC_RESERVED, /* 4E reserved */
@@ -163,8 +163,13 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) int offset, shift; u32 addr, status, decprot[ETZPC_DECPROT_NB];
- array = stm32mp1_ip_addr;
- array_size = ARRAY_SIZE(stm32mp1_ip_addr);
if (IS_ENABLED(CONFIG_STM32MP13x))
return 0;
if (IS_ENABLED(CONFIG_STM32MP15x)) {
array = stm32mp15_ip_addr;
array_size = ARRAY_SIZE(stm32mp15_ip_addr);
}
for (i = 0; i < ETZPC_DECPROT_NB; i++) decprot[i] = readl(ETZPC_DECPROT(i));
@@ -248,33 +253,9 @@ static void stm32_fdt_disable_optee(void *blob) } }
-/*
- This function is called right before the kernel is booted. "blob" is the
- device tree that will be passed to the kernel.
- */
-int ft_system_setup(void *blob, struct bd_info *bd) +static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) {
- int ret = 0;
- int soc;
- u32 pkg, cpu;
- char name[SOC_NAME_SIZE];
- if (IS_ENABLED(CONFIG_STM32MP13x))
return 0;
- soc = fdt_path_offset(blob, "/soc");
- if (soc < 0)
return soc;
- if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
ret = stm32_fdt_fixup_etzpc(blob, soc);
if (ret)
return ret;
- }
- /* MPUs Part Numbers and name*/
- cpu = get_cpu_type();
- get_soc_name(name);
u32 pkg;
switch (cpu) { case CPU_STM32MP151Fxx:
@@ -284,19 +265,18 @@ int ft_system_setup(void *blob, struct bd_info *bd) stm32_fdt_fixup_cpu(blob, name); /* after cpu delete we can't trust the soc offsets anymore */ soc = fdt_path_offset(blob, "/soc");
stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
/* fall through */
stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name);
case CPU_STM32MP153Fxx: case CPU_STM32MP153Dxx: case CPU_STM32MP153Cxx: case CPU_STM32MP153Axx:fallthrough;
stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name);
break; default: break; }stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name);
- switch (cpu) { case CPU_STM32MP157Dxx: case CPU_STM32MP157Axx:
@@ -304,13 +284,14 @@ int ft_system_setup(void *blob, struct bd_info *bd) case CPU_STM32MP153Axx: case CPU_STM32MP151Dxx: case CPU_STM32MP151Axx:
stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp",
name);
stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp",
break; default: break; }name);
- switch (get_cpu_package()) { case STM32MP15_PKG_AA_LBGA448: pkg = STM32MP_PKG_AA;
@@ -334,18 +315,48 @@ int ft_system_setup(void *blob, struct bd_info *bd) do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", "st,package", pkg, false); } +}
+/*
- This function is called right before the kernel is booted. "blob" is the
- device tree that will be passed to the kernel.
- */
+int ft_system_setup(void *blob, struct bd_info *bd) +{
- int ret = 0;
- int soc;
- u32 cpu;
- char name[SOC_NAME_SIZE];
- soc = fdt_path_offset(blob, "/soc");
- if (soc < 0)
return soc;
- if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
ret = stm32_fdt_fixup_etzpc(blob, soc);
if (ret)
return ret;
- }
- /*
* TEMP: remove OP-TEE nodes in kernel device tree
* copied from U-Boot device tree by optee_copy_fdt_nodes
* when OP-TEE is not detected (probe failed)
* these OP-TEE nodes are present in <board>-u-boot.dtsi
* under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
* when FIP is not used by TF-A
*/
- if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
!tee_find_device(NULL, NULL, NULL, NULL))
stm32_fdt_disable_optee(blob);
/* MPUs Part Numbers and name*/
cpu = get_cpu_type();
get_soc_name(name);
if (IS_ENABLED(CONFIG_STM32MP15x)) {
stm32mp15_fdt_fixup(blob, soc, cpu, name);
/*
* TEMP: remove OP-TEE nodes in kernel device tree
* copied from U-Boot device tree by optee_copy_fdt_nodes
* when OP-TEE is not detected (probe failed)
* these OP-TEE nodes are present in <board>-u-boot.dtsi
* under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
* when FIP is not used by TF-A
*/
if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
!tee_find_device(NULL, NULL, NULL, NULL))
stm32_fdt_disable_optee(blob);
}
return ret;
}
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice

Hi,
On 5/9/22 17:13, Patrick Delaunay wrote:
Introduce STM32MP15 function and defines to prepare the STM32MP13 introduction.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com
arch/arm/mach-stm32mp/fdt.c | 123 ++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 56 deletions(-)
Applied to u-boot-stm/next, thanks!
Regards Patrick
participants (3)
-
Patrice CHOTARD
-
Patrick DELAUNAY
-
Patrick Delaunay