Signed-off-by: Dzmitry Sankouski dsankouski@gmail.com Cc: Minkyu Kang mk7.kang@samsung.com --- Changes for v2: - if CONFIG_DEBUG_UART_SKIP_INIT, return from init function

drivers/serial/serial_s5p.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 6d09952a5d..6823da79f8 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -221,6 +221,9 @@ U_BOOT_DRIVER(serial_s5p) = {

static inline void _debug_uart_init(void) { + if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT)) + return; + struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;

s5p_serial_init(uart);

Iterate all pin banks to find a pin

Signed-off-by: Dzmitry Sankouski dsankouski@gmail.com Cc: Minkyu Kang mk7.kang@samsung.com --- drivers/pinctrl/exynos/pinctrl-exynos.c | 28 +++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c index 2640c8fcef..898185479b 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos.c @@ -5,6 +5,7 @@ * Thomas Abraham thomas.ab@samsung.com */

+#include <log.h> #include <common.h> #include <dm.h> #include <errno.h> @@ -38,9 +39,9 @@ static unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name, u32 *pin) { struct exynos_pinctrl_priv *priv = dev_get_priv(dev); - const struct samsung_pin_ctrl *pin_ctrl = priv->pin_ctrl; - const struct samsung_pin_bank_data *bank_data = pin_ctrl->pin_banks; - u32 nr_banks = pin_ctrl->nr_banks, idx = 0; + const struct samsung_pin_ctrl *pin_ctrl_array = priv->pin_ctrl; + const struct samsung_pin_bank_data *bank_data; + u32 nr_banks, pin_ctrl_idx = 0, idx = 0, bank_base; char bank[10];

/* @@ -55,11 +56,26 @@ static unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name, *pin = pin_name[++idx] - '0';

/* lookup the pin bank data using the pin bank name */ - for (idx = 0; idx < nr_banks; idx++) - if (!strcmp(bank, bank_data[idx].name)) + while (true) { + const struct samsung_pin_ctrl *pin_ctrl = &pin_ctrl_array[pin_ctrl_idx]; + + nr_banks = pin_ctrl->nr_banks; + if (!nr_banks) break;

- return priv->base + bank_data[idx].offset; + bank_data = pin_ctrl->pin_banks; + for (idx = 0; idx < nr_banks; idx++) { + debug("pinctrl[%d] bank_data[%d] name is: %s\n", + pin_ctrl_idx, idx, bank_data[idx].name); + if (!strcmp(bank, bank_data[idx].name)) { + bank_base = priv->base + bank_data[idx].offset; + break; + } + } + pin_ctrl_idx++; + } + + return bank_base; }

/**

Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets introduced on March 2017. Features: - 8 Cortex A53 cores - ARM Mali-T830 MP3 GPU - LTE Cat. 7 (7880) or 6 (7870) modem

Signed-off-by: Dzmitry Sankouski dsankouski@gmail.com Cc: Minkyu Kang mk7.kang@samsung.com --- arch/arm/dts/exynos78x0-gpio.dtsi | 204 ++++++++++++++ arch/arm/dts/exynos78x0-pinctrl.dtsi | 280 ++++++++++++++++++++ arch/arm/dts/exynos78x0.dtsi | 98 +++++++ arch/arm/mach-exynos/mmu-arm64.c | 66 +++++ drivers/gpio/s5p_gpio.c | 1 + drivers/pinctrl/exynos/Kconfig | 8 + drivers/pinctrl/exynos/Makefile | 1 + drivers/pinctrl/exynos/pinctrl-exynos78x0.c | 119 +++++++++ include/configs/exynos78x0-common.h | 112 ++++++++ 9 files changed, 889 insertions(+) create mode 100644 arch/arm/dts/exynos78x0-gpio.dtsi create mode 100644 arch/arm/dts/exynos78x0-pinctrl.dtsi create mode 100644 arch/arm/dts/exynos78x0.dtsi create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos78x0.c create mode 100644 include/configs/exynos78x0-common.h

diff --git a/arch/arm/dts/exynos78x0-gpio.dtsi b/arch/arm/dts/exynos78x0-gpio.dtsi new file mode 100644 index 0000000000..a7f75c5ca9 --- /dev/null +++ b/arch/arm/dts/exynos78x0-gpio.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung's Exynos7880 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + /* ALIVE */ + gpio@139F0000 { + etc0: etc0 { + gpio-controller; + #gpio-cells = <2>; + }; + + etc1: etc1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpq0: gpq0 { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* CCORE */ + gpio@10630000 { + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* DISP/AUD */ + gpio@148C0000 { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpz2: gpz2 { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* FSYS0 */ + gpio@13750000 { + gpr0: gpr0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpr1: gpr1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpr2: gpr2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpr3: gpr3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpr4: gpr4 { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* TOP */ + gpio@139B0000 { + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc5: gpc5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc6: gpc6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc8: gpc8 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc9: gpc9 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd3: gpd3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd4: gpd4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd5: gpd5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf4: gpf4 { + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/arch/arm/dts/exynos78x0-pinctrl.dtsi b/arch/arm/dts/exynos78x0-pinctrl.dtsi new file mode 100644 index 0000000000..4958c55119 --- /dev/null +++ b/arch/arm/dts/exynos78x0-pinctrl.dtsi @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung's Exynos7880 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + * + * Samsung's Exynos7880 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + /* ALIVE */ + pinctrl@139F0000 { + uart2_bus: uart2-bus { + samsung,pins = "gpa1-1", "gpa1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq { + samsung,pins = "gpa3-3"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + key_power: key-power { + samsung,pins = "gpa0-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + key_voldown: key-voldown { + samsung,pins = "gpa2-1"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + key_volup: key-volup { + samsung,pins = "gpa2-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + key_home: key-home { + samsung,pins = "gpa1-7"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + /* TOP */ + pinctrl@139B0000 { + i2c0_bus: i2c0-bus { + samsung,pins = "gpc1-1", "gpc1-0"; + samsung,pin-function = <2>; + }; + + sd0_rst: sd0_rst { + samsung,pins = "gpc0-2"; + samsung,pin-function = <0>; + }; + }; + + /* DISP/AUD */ + pinctrl@148C0000 { + i2s_pmic_bus: i2s-pmic-bus { + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + i2s_pmic_bus_idle: i2s-pmic-bus_idle { + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + }; + + /* FSYS0 */ + pinctrl@13750000 { + sd0_clk: sd0-clk { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpr0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpr0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_1x: sd0-clk_fast_slew_rate_1x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd0_clk_fast_slew_rate_2x: sd0-clk_fast_slew_rate_2x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <1>; + }; + + sd0_clk_fast_slew_rate_3x: sd0-clk_fast_slew_rate_3x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_4x: sd0-clk_fast_slew_rate_4x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_clk_fast_slew_rate_5x: sd0-clk_fast_slew_rate_5x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd0_clk_fast_slew_rate_6x: sd0-clk_fast_slew_rate_6x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <5>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpr1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpr2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpr2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpr3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + samsung,pin-con-pdn = <2>; + samsung,pin-pud-pdn = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + samsung,pin-con-pdn = <2>; + samsung,pin-pud-pdn = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpr4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpr4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpr4-3", "gpr4-4", "gpr4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_clk_output: sd2-clk-output { + samsung,pins = "gpr4-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd_output: sd2-cmd-output { + samsung,pins = "gpr4-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk_fast_slew_rate_1x { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk_fast_slew_rate_2x { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <1>; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk_fast_slew_rate_3x { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk_fast_slew_rate_4x { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + }; +}; diff --git a/arch/arm/dts/exynos78x0.dtsi b/arch/arm/dts/exynos78x0.dtsi new file mode 100644 index 0000000000..fb9c9cbdf9 --- /dev/null +++ b/arch/arm/dts/exynos78x0.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung Exynos7880 SoC device tree source + * + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + */ + +/dts-v1/; +#include "skeleton.dtsi" +#include "exynos78x0-pinctrl.dtsi" +#include "exynos78x0-gpio.dtsi" +/ { + compatible = "samsung,exynos7880"; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + u-boot,dm-pre-reloc; + #clock-cells = <0>; + }; + + /* Dummy clock for uart */ + fin_uart: uart_dummy_fin { + compatible = "fixed-clock"; + clock-output-names = "fin_uart"; + clock-frequency = <132710400>; + u-boot,dm-pre-reloc; + #clock-cells = <0>; + }; + + uart2: serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + u-boot,dm-pre-reloc; + clocks = <&fin_uart>, <&fin_uart>; // driver uses 1st clock + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus>; + }; + + gpioi2c0: i2c-0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + gpios = < + &gpc1 0 0 /* sda */ + &gpc1 1 0 /* scl */ + >; + i2c-gpio,delay-us = <5>; + + s2mu004@3d { + compatible = "samsung,s2mu004mfd"; + }; + }; + + /* ALIVE */ + pinctrl_0: pinctrl@139F0000 { + compatible = "samsung,exynos78x0-pinctrl"; + reg = <0x139F0000 0x1000>; + }; + + /* DISP/AUD */ + pinctrl_2: pinctrl@148C0000 { + compatible = "samsung,exynos78x0-pinctrl"; + reg = <0x148C0000 0x1000>; + }; + + /* FSYS0 */ + pinctrl_4: pinctrl@13750000 { + compatible = "samsung,exynos78x0-pinctrl"; + reg = <0x13750000 0x1000>; + }; + + /* ALIVE */ + gpio_0: gpio@139F0000 { + compatible = "samsung,exynos78x0-gpio"; + reg = <0x139F0000 0x1000>; + }; + + /* DISP/AUD */ + gpio_2: gpio@148C0000 { + compatible = "samsung,exynos78x0-gpio"; + reg = <0x148C0000 0x1000>; + }; + + /* FSYS0 */ + gpio_4: gpio@13750000 { + compatible = "samsung,exynos78x0-gpio"; + reg = <0x13750000 0x1000>; + }; + + /* TOP */ + gpio_6: gpio@139B0000 { + compatible = "samsung,exynos78x0-gpio"; + reg = <0x139B0000 0x1000>; + }; +}; diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c index 46b8169d19..e3bd995143 100644 --- a/arch/arm/mach-exynos/mmu-arm64.c +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -29,3 +29,69 @@ static struct mm_region exynos7420_mem_map[] = {

struct mm_region *mem_map = exynos7420_mem_map; #endif + +#ifdef CONFIG_EXYNOS7870 +static struct mm_region exynos7870_mem_map[] = { + { + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x3E400000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + + { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = exynos7870_mem_map; +#endif + +#ifdef CONFIG_EXYNOS7880 +static struct mm_region exynos7880_mem_map[] = { + { + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x3E400000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + + { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = exynos7880_mem_map; +#endif diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 76f35ac5d9..06ed585f3d 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -357,6 +357,7 @@ static const struct udevice_id exynos_gpio_ids[] = { { .compatible = "samsung,exynos4x12-pinctrl" }, { .compatible = "samsung,exynos5250-pinctrl" }, { .compatible = "samsung,exynos5420-pinctrl" }, + { .compatible = "samsung,exynos78x0-gpio" }, { } };

diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig index 84b6aaae09..a60f49869b 100644 --- a/drivers/pinctrl/exynos/Kconfig +++ b/drivers/pinctrl/exynos/Kconfig @@ -8,3 +8,11 @@ config PINCTRL_EXYNOS7420 help Support pin multiplexing and pin configuration control on Samsung's Exynos7420 SoC. + +config PINCTRL_EXYNOS78x0 + bool "Samsung Exynos78x0 pinctrl driver" + depends on ARCH_EXYNOS && PINCTRL_FULL + select PINCTRL_EXYNOS + help + Support pin multiplexing and pin configuration control on + Samsung's Exynos78x0 SoC. diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile index 6a14a474bf..07db970ca9 100644 --- a/drivers/pinctrl/exynos/Makefile +++ b/drivers/pinctrl/exynos/Makefile @@ -5,3 +5,4 @@

obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o +obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o diff --git a/drivers/pinctrl/exynos/pinctrl-exynos78x0.c b/drivers/pinctrl/exynos/pinctrl-exynos78x0.c new file mode 100644 index 0000000000..01e9a4fede --- /dev/null +++ b/drivers/pinctrl/exynos/pinctrl-exynos78x0.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Exynos78x0 pinctrl driver. + * + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + * + * based on drivers/pinctrl/exynos/pinctrl-exynos7420.c : + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham thomas.ab@samsung.com + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <fdtdec.h> +#include <asm/arch/pinmux.h> +#include "pinctrl-exynos.h" + +static struct pinctrl_ops exynos78x0_pinctrl_ops = { + .set_state = exynos_pinctrl_set_state +}; + +/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos78x0_pin_banks0[] = { + EXYNOS_PIN_BANK(6, 0x000, "etc0"), + EXYNOS_PIN_BANK(3, 0x020, "etc1"), + EXYNOS_PIN_BANK(8, 0x040, "gpa0"), + EXYNOS_PIN_BANK(8, 0x060, "gpa1"), + EXYNOS_PIN_BANK(8, 0x080, "gpa2"), + EXYNOS_PIN_BANK(5, 0x0a0, "gpa3"), + EXYNOS_PIN_BANK(2, 0x0c0, "gpq0"), +}; + +/* pin banks of exynos78x0 pin-controller 1 (CCORE) */ +static struct samsung_pin_bank_data exynos78x0_pin_banks1[] = { + EXYNOS_PIN_BANK(2, 0x000, "gpm0"), +}; + +/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */ +static struct samsung_pin_bank_data exynos78x0_pin_banks2[] = { + EXYNOS_PIN_BANK(4, 0x000, "gpz0"), + EXYNOS_PIN_BANK(6, 0x020, "gpz1"), + EXYNOS_PIN_BANK(4, 0x040, "gpz2"), +}; + +/* pin banks of exynos78x0 pin-controller 4 (FSYS) */ +static struct samsung_pin_bank_data exynos78x0_pin_banks4[] = { + EXYNOS_PIN_BANK(3, 0x000, "gpr0"), + EXYNOS_PIN_BANK(8, 0x020, "gpr1"), + EXYNOS_PIN_BANK(2, 0x040, "gpr2"), + EXYNOS_PIN_BANK(4, 0x060, "gpr3"), + EXYNOS_PIN_BANK(6, 0x080, "gpr4"), +}; + +/* pin banks of exynos78x0 pin-controller 6 (TOP) */ +static struct samsung_pin_bank_data exynos78x0_pin_banks6[] = { + EXYNOS_PIN_BANK(4, 0x000, "gpb0"), + EXYNOS_PIN_BANK(3, 0x020, "gpc0"), + EXYNOS_PIN_BANK(4, 0x040, "gpc1"), + EXYNOS_PIN_BANK(4, 0x060, "gpc4"), + EXYNOS_PIN_BANK(2, 0x080, "gpc5"), + EXYNOS_PIN_BANK(4, 0x0a0, "gpc6"), + EXYNOS_PIN_BANK(2, 0x0c0, "gpc8"), + EXYNOS_PIN_BANK(2, 0x0e0, "gpc9"), + EXYNOS_PIN_BANK(7, 0x100, "gpd1"), + EXYNOS_PIN_BANK(6, 0x120, "gpd2"), + EXYNOS_PIN_BANK(8, 0x140, "gpd3"), + EXYNOS_PIN_BANK(7, 0x160, "gpd4"), + EXYNOS_PIN_BANK(5, 0x180, "gpd5"), + EXYNOS_PIN_BANK(3, 0x1a0, "gpe0"), + EXYNOS_PIN_BANK(4, 0x1c0, "gpf0"), + EXYNOS_PIN_BANK(2, 0x1e0, "gpf1"), + EXYNOS_PIN_BANK(2, 0x200, "gpf2"), + EXYNOS_PIN_BANK(4, 0x220, "gpf3"), + EXYNOS_PIN_BANK(5, 0x240, "gpf4"), +}; + +struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = { + { + /* pin-controller instance 0 Alive data */ + .pin_banks = exynos78x0_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks0), + }, { + /* pin-controller instance 1 CCORE data */ + .pin_banks = exynos78x0_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks1), + }, { + /* pin-controller instance 2 DISPAUD data */ + .pin_banks = exynos78x0_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks2), + }, { + /* pin-controller instance 4 FSYS data */ + .pin_banks = exynos78x0_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks4), + }, { + /* pin-controller instance 6 TOP data */ + .pin_banks = exynos78x0_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks6), + }, + {/* list terminator */} +}; + +static const struct udevice_id exynos78x0_pinctrl_ids[] = { + { .compatible = "samsung,exynos78x0-pinctrl", + .data = (ulong)exynos78x0_pin_ctrl }, + { } +}; + +U_BOOT_DRIVER(pinctrl_exynos78x0) = { + .name = "pinctrl_exynos78x0", + .id = UCLASS_PINCTRL, + .of_match = exynos78x0_pinctrl_ids, + .priv_auto = sizeof(struct exynos_pinctrl_priv), + .ops = &exynos78x0_pinctrl_ops, + .probe = exynos_pinctrl_probe, +}; diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h new file mode 100644 index 0000000000..478a0c42b1 --- /dev/null +++ b/include/configs/exynos78x0-common.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the EXYNOS 78x0 based boards. + * + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + * based on include/exynos7420-common.h + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham thomas.ab@samsung.com + */ + +#ifndef __CONFIG_EXYNOS78x0_COMMON_H +#define __CONFIG_EXYNOS78x0_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <linux/sizes.h> + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Timer input clock frequency */ +#define COUNTER_FREQUENCY 26000000 + +/* Device Tree */ +#define CONFIG_DEVICE_TREE_LIST "EXYNOS78x0-a5y17lte" + +#define CPU_RELEASE_ADDR secondary_boot_addr + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE) +/* DRAM Memory Banks */ +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE + +#define CONFIG_DEBUG_UART_CLOCK 132710400 + +#define CONFIG_PREBOOT \ +"echo Read pressed buttons status;" \ +"KEY_VOLUMEUP=gpa20;" \ +"KEY_HOME=gpa17;" \ +"KEY_VOLUMEDOWN=gpa21;" \ +"KEY_POWER=gpa00;" \ +"PRESSED=0;" \ +"RELEASED=1;" \ +"if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; " \ +"else setenv VOLUME_UP $RELEASED; fi;" \ +"if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; " \ +"else setenv VOLUME_DOWN $RELEASED; fi;" \ +"if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;" \ +"if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;" + +#ifndef MEM_LAYOUT_ENV_SETTINGS +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "bootm_low=0x40000000\0" +#endif + +#ifndef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#ifndef EXYNOS_FDTFILE_SETTING +#define EXYNOS_FDTFILE_SETTING +#endif + +#define EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + EXYNOS_FDTFILE_SETTING \ + MEM_LAYOUT_ENV_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS + +#endif /* __CONFIG_EXYNOS78x0_COMMON_H */

Samsung Galaxy A3, A5, A7 (2017) - middle class Samsung smartphones. U-boot can be used as chain-loaded bootloader to gain control on booting vanilla linux(and possibly others) kernels

Signed-off-by: Dzmitry Sankouski dsankouski@gmail.com Cc: Minkyu Kang mk7.kang@samsung.com --- arch/arm/dts/Makefile | 3 + arch/arm/dts/exynos78x0-axy17lte.dts | 29 +++++++++ arch/arm/mach-exynos/Kconfig | 28 +++++++++ board/samsung/axy17lte/Kconfig | 58 ++++++++++++++++++ board/samsung/axy17lte/MAINTAINERS | 8 +++ board/samsung/axy17lte/Makefile | 3 + board/samsung/axy17lte/axy17lte.c | 11 ++++ configs/a3y17lte_defconfig | 24 ++++++++ configs/a5y17lte_defconfig | 24 ++++++++ configs/a7y17lte_defconfig | 24 ++++++++ doc/board/index.rst | 1 + doc/board/samsung/axy17lte.rst | 92 ++++++++++++++++++++++++++++ doc/board/samsung/index.rst | 9 +++ 13 files changed, 314 insertions(+) create mode 100644 arch/arm/dts/exynos78x0-axy17lte.dts create mode 100644 board/samsung/axy17lte/Kconfig create mode 100644 board/samsung/axy17lte/MAINTAINERS create mode 100644 board/samsung/axy17lte/Makefile create mode 100644 board/samsung/axy17lte/axy17lte.c create mode 100644 configs/a3y17lte_defconfig create mode 100644 configs/a5y17lte_defconfig create mode 100644 configs/a7y17lte_defconfig create mode 100644 doc/board/samsung/axy17lte.rst create mode 100644 doc/board/samsung/index.rst

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8a382d153..947c15aa50 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -28,6 +28,9 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5800-peach-pi.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb +dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb

dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-evm.dtb \ diff --git a/arch/arm/dts/exynos78x0-axy17lte.dts b/arch/arm/dts/exynos78x0-axy17lte.dts new file mode 100644 index 0000000000..7fae8db874 --- /dev/null +++ b/arch/arm/dts/exynos78x0-axy17lte.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung Exynos78x0 SoC device tree source + * + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + */ + +/dts-v1/; +#include "exynos78x0.dtsi" +/ { + compatible = "samsung,exynos78x0", "samsung,exynos7880", "samsung,exynos7870"; + + aliases { + console = &uart2; + }; + + chosen { + stdout-path = &uart2; + }; +}; + +&gpioi2c0 { + status = "okay"; +}; + +&fin_pll { + clock-frequency = <26000000>; +}; + diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 7df0e17617..7f3aee5712 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -151,6 +151,33 @@ config TARGET_ESPRESSO7420 select PINCTRL_EXYNOS7420 select SUPPORT_SPL

+config TARGET_A5Y17LTE + bool "Samsung SM-A520F board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS78x0 + select SUPPORT_SPL + +config TARGET_A7Y17LTE + bool "Samsung SM-A520F board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS78x0 + select SUPPORT_SPL + +config TARGET_A3Y17LTE + bool "Samsung SM-A520F board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS7880 + select SUPPORT_SPL + endchoice endif

@@ -167,6 +194,7 @@ source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" +source "board/samsung/axy17lte/Kconfig"

config SPL_LDSCRIPT default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig new file mode 100644 index 0000000000..2abf8e7acf --- /dev/null +++ b/board/samsung/axy17lte/Kconfig @@ -0,0 +1,58 @@ +config SYS_CONFIG_NAME + string "Board configuration name" + default "exynos78x0-common.h" + help + This option contains information about board configuration name. + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header + will be used for board configuration. + +if TARGET_A5Y17LTE +config SYS_BOARD + default "axy17lte" + help + a5y17lte is a production board for SM-A520F phone on Exynos7880 SoC. + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "a5y17lte" + +config EXYNOS7880 + bool "Exynos 7880 SOC support" + default y +endif + +if TARGET_A7Y17LTE +config SYS_BOARD + default "axy17lte" + help + a5y17lte is a production board for SM-A520F phone on Exynos7880 SoC. + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "a5y17lte" + +config EXYNOS7880 + bool "Exynos 7880 SOC support" + default y +endif + +if TARGET_A3Y17LTE +config SYS_BOARD + default "axy17lte" + help + a3y17lte is a production board for SM-A520F phone on Exynos7880 SoC. + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "a3y17lte" + +config EXYNOS7870 + bool "Exynos 7870 SOC support" + default y +endif diff --git a/board/samsung/axy17lte/MAINTAINERS b/board/samsung/axy17lte/MAINTAINERS new file mode 100644 index 0000000000..13feba62a7 --- /dev/null +++ b/board/samsung/axy17lte/MAINTAINERS @@ -0,0 +1,8 @@ +Samsung A series 2017 phones Board +M: Dzmitry Sankouski dsankouski@gmail.com +S: Maintained +F: board/samsung/axy17lte/ +F: include/configs/exynos78x0-common.h +F: configs/a3y17lte_defconfig +F: configs/a5y17lte_defconfig +F: configs/a7y17lte_defconfig diff --git a/board/samsung/axy17lte/Makefile b/board/samsung/axy17lte/Makefile new file mode 100644 index 0000000000..4e11f289dc --- /dev/null +++ b/board/samsung/axy17lte/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += axy17lte.o diff --git a/board/samsung/axy17lte/axy17lte.c b/board/samsung/axy17lte/axy17lte.c new file mode 100644 index 0000000000..c38297a05b --- /dev/null +++ b/board/samsung/axy17lte/axy17lte.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung A5Y17 and A3Y17 LTE boards based on Exynos 7880 and Exynos 7870 SoCs + */ + +#include <common.h> + +int exynos_init(void) +{ + return 0; +} diff --git a/configs/a3y17lte_defconfig b/configs/a3y17lte_defconfig new file mode 100644 index 0000000000..36404d15f7 --- /dev/null +++ b/configs/a3y17lte_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y +CONFIG_S5P=y +CONFIG_TARGET_A3Y17LTE=y +# This option is a number of 256MB DRAM banks, i.e. (ram size) / 256MB. +# Used in samsung common board dram_init function. +CONFIG_NR_DRAM_BANKS=8 +CONFIG_SYS_CONFIG_NAME="exynos78x0-common" +CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte" +CONFIG_SYS_TEXT_BASE=0x40001000 +CONFIG_SYS_LOAD_ADDR=0x40001000 +CONFIG_HUSH_PARSER=y +CONFIG_FIT=y +CONFIG_BOARD_EARLY_INIT_F=n +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_CMD_GPIO=y +CONFIG_DISPLAY_CPUINFO=n +CONFIG_CMD_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_PINCTRL_EXYNOS78x0=y +CONFIG_PINCTRL_EXYNOS=y +# CONFIG_DEBUG_UART_S5P=y +# CONFIG_DEBUG_UART_BASE=0x13820000 \ No newline at end of file diff --git a/configs/a5y17lte_defconfig b/configs/a5y17lte_defconfig new file mode 100644 index 0000000000..273ad1078e --- /dev/null +++ b/configs/a5y17lte_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y +CONFIG_S5P=y +CONFIG_TARGET_A5Y17LTE=y +# This option is a number of 256MB DRAM banks, i.e. (ram size) / 256MB. +# Used in samsung common board dram_init function. +CONFIG_NR_DRAM_BANKS=12 +CONFIG_SYS_CONFIG_NAME="exynos78x0-common" +CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte" +CONFIG_SYS_TEXT_BASE=0x40001000 +CONFIG_SYS_LOAD_ADDR=0x40001000 +CONFIG_HUSH_PARSER=y +CONFIG_FIT=y +CONFIG_BOARD_EARLY_INIT_F=n +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_CMD_GPIO=y +CONFIG_DISPLAY_CPUINFO=n +CONFIG_CMD_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_PINCTRL_EXYNOS78x0=y +CONFIG_PINCTRL_EXYNOS=y +# CONFIG_DEBUG_UART_S5P=y +# CONFIG_DEBUG_UART_BASE=0x13820000 \ No newline at end of file diff --git a/configs/a7y17lte_defconfig b/configs/a7y17lte_defconfig new file mode 100644 index 0000000000..f544f629ef --- /dev/null +++ b/configs/a7y17lte_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS7=y +CONFIG_S5P=y +CONFIG_TARGET_A7Y17LTE=y +# This option is a number of 256MB DRAM banks, i.e. (ram size) / 256MB. +# Used in samsung common board dram_init function. +CONFIG_NR_DRAM_BANKS=12 +CONFIG_SYS_CONFIG_NAME="exynos78x0-common" +CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte" +CONFIG_SYS_TEXT_BASE=0x40001000 +CONFIG_SYS_LOAD_ADDR=0x40001000 +CONFIG_HUSH_PARSER=y +CONFIG_FIT=y +CONFIG_BOARD_EARLY_INIT_F=n +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_CMD_GPIO=y +CONFIG_DISPLAY_CPUINFO=n +CONFIG_CMD_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_PINCTRL_EXYNOS78x0=y +CONFIG_PINCTRL_EXYNOS=y +# CONFIG_DEBUG_UART_S5P=y +# CONFIG_DEBUG_UART_BASE=0x13820000 \ No newline at end of file diff --git a/doc/board/index.rst b/doc/board/index.rst index aa397ab942..c09339480b 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -22,6 +22,7 @@ Board-specific doc openpiton/index qualcomm/index rockchip/index + samsung/index siemens/index sifive/index sipeed/index diff --git a/doc/board/samsung/axy17lte.rst b/doc/board/samsung/axy17lte.rst new file mode 100644 index 0000000000..b3f718dfc8 --- /dev/null +++ b/doc/board/samsung/axy17lte.rst @@ -0,0 +1,92 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Dzmitry Sankouski dsankouski@gmail.com + +Samsung 2017 A series phones +================ + +About this +---------- +This document describes the information about Samsung A(7/5/3) 2017 midrange +phones and u-boot usage steps. + +U-Boot can be used as a chain-loaded bootloader to replace Samsung's original SBOOT bootloader. +It is loaded as an Android boot image through SBOOT. + +Phone specs +---------- +A3 (SM-320) (a3y17lte) +^^^^^^^^^^ +- 4.7 AMOLED display +- Exynos 7870 SoC +- 16GB flash +- 2GB RAM + +.. A3 2017 wiki page: https://en.wikipedia.org/wiki/Samsung_Galaxy_A3_(2017) + +A5 (SM-520) (a5y17lte) +^^^^^^^^^^ +- 5.2 AMOLED display +- Exynos 7880 SoC +- 32GB flash +- 3GB RAM +.. A5 2017 wiki page: https://en.wikipedia.org/wiki/Samsung_Galaxy_A5_(2017) + +A7 (SM-720) (a5y17lte) +^^^^^^^^^^ +- 5.7 AMOLED display +- Exynos 7880 SoC +- 32GB flash +- 3GB RAM +.. A7 2017 wiki page: https://en.wikipedia.org/wiki/Samsung_Galaxy_A7_(2017) + +Installation +------------ + +Building u-boot +^^^^^^^^^^ + +First, setup ``CROSS_COMPILE`` for aarch64. +Then, build U-Boot for your phone, for example ``a5y17lte``:: + + $ export CROSS_COMPILE=<aarch64 toolchain prefix> + $ make a5y17lte_defconfig + $ make + +This will build ``u-boot.bin`` in the configured output directory. + +Payload +^^^^^^^^^^ +What is a payload? +"""""""""" +A payload file is a file to be used instead of linux kernel in android boot image. +This file will be loaded into memory, and executed by SBOOT, +and is therefore SBOOT's payload. +It may be pure u-boot (with loading u-boot's payload from flash in mind), +or u-boot + u-boot's payload. + +It should be kept in mind, that SBOOT binary patches it's payload after loading +in address range 0x401f8550-0x401f9280. Given SBOOT loads payload to 0x40001000, +a range of 0x1f7550-0x1f8280 (2061648-2065024) in a payload file +will be corrupted after loading to RAM. + +Creating payload file +"""""""""" +- Assemble FIT image for your kernel +- Create a file for u-boot payload ``touch sboot-payload`` +- Write zeroes till 0x200000 address to be sure SBOOT won't corrupt your info + ``dd if=/dev/zero of=sboot-payload bs=$((0x200000)) count=1`` +- Write u-boot to the start of the payload ``dd if=<u-boot.bin path> of=sboot-payload`` +- Write FIT image to payload from 0x200000 address + ``dd if=<FIT image path> of=sboot-payload seek=1 bs=2M`` + +Creating android boot image +"""""""""" +Once payload created, it's time for android image:: + + mkbootimg --base 0x40000000 --kernel_offset 0x00000000 --ramdisk_offset 0x01000000 --tags_offset 0x00000100 --pagesize 2048 --second_offset 0x00f00000 --kernel <sboot-payload path> -o uboot.img + +Note, that stock Samsung bootloader ignores offsets, set in mkbootimg. + +Flashing +"""""""""" +Flash like regular android boot image. diff --git a/doc/board/samsung/index.rst b/doc/board/samsung/index.rst new file mode 100644 index 0000000000..c904372dff --- /dev/null +++ b/doc/board/samsung/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Samsung +======== + +.. toctree:: + :maxdepth: 2 + + axy17lte