[PATCH v2 00/10] rockchip: pinctrl: Add support for pinmux status cmd
This series includes some cleanup, add support for using the pinmux status cmd and add support for the gpio request ops.
Following is an example on a Radxa ROCK 5A (RK3588S):
=> pinmux dev pinctrl dev: pinctrl => pinmux status GPIO0_A0 : gpio GPIO0_A1 : func-2 GPIO0_A2 : gpio GPIO0_A3 : gpio GPIO0_A4 : func-1 GPIO0_A5 : func-2 GPIO0_A6 : gpio GPIO0_A7 : gpio GPIO0_B0 : gpio GPIO0_B1 : gpio GPIO0_B2 : gpio GPIO0_B3 : gpio GPIO0_B4 : gpio GPIO0_B5 : func-10 GPIO0_B6 : func-10 GPIO0_B7 : gpio [...]
and on a ASUS TinkerBoard R2.0 (RK3288W):
=> pinmux dev pinctrl dev: pinctrl => pinmux status [...] GPIO2_C6 : gpio GPIO2_C7 : gpio GPIO2_D0 : unrouted GPIO2_D1 : unrouted GPIO2_D2 : unrouted GPIO2_D3 : unrouted GPIO2_D4 : unrouted GPIO2_D5 : unrouted GPIO2_D6 : unrouted GPIO2_D7 : unrouted GPIO3_A0 : func-2 GPIO3_A1 : func-2 [...]
Patch 1 refactor to use syscon_regmap_lookup_by_phandle() helper. Patch 6 refactor to get pinctrl device from gpio-ranges prop.
Patch 2, 3 and 7 change to use pinctrl pin offset instead of bank num to get current pinmux. Patch 4 add required ops for use of the pinmux status cmd.
Patch 5 and 8 add gpio_request_enable() and request() ops.
Patch 9 add gpio-ranges props for remaining RK SoCs, this is strictly not needed for pinmux status cmd to function. However, the change to not require the pin controller offset to be 32 aligned was required to add gpio-ranges props for RK3288.
Patch 10 add gpio aliases for RK SoCs that is missing alias for gpio controllers.
Changes in v2: - Drop fixes patches already applied - Split adding pin_to_bank() helper into own patch - Add gpio_request_enable() and request() ops patch from the "rockchip: Add gpio request() ops" series - Add missing gpio aliases - Collect r-b tags
Jonas Karlman (10): pinctrl: rockchip: Use syscon_regmap_lookup_by_phandle() pinctrl: rockchip: Add a pin_to_bank() helper pinctrl: rockchip: Update get_gpio_mux() ops pinctrl: rockchip: Add pinmux status related ops pinctrl: rockchip: Add gpio_request_enable() ops gpio: rockchip: Get pinctrl device from gpio-ranges prop gpio: rockchip: Use pinctrl pin offset to get_gpio_mux() gpio: rockchip: Add request() ops rockchip: gpio: Add gpio-ranges props rockchip: gpio: Add missing gpio aliases
arch/arm/dts/px30-u-boot.dtsi | 4 + arch/arm/dts/rk3036-u-boot.dtsi | 12 ++ arch/arm/dts/rk3066a-u-boot.dtsi | 10 +- arch/arm/dts/rk3128-u-boot.dtsi | 16 ++ arch/arm/dts/rk322x-u-boot.dtsi | 16 ++ arch/arm/dts/rk3288-u-boot.dtsi | 42 ++++-- arch/arm/dts/rk3308-u-boot.dtsi | 20 +++ arch/arm/dts/rk3328-u-boot.dtsi | 13 ++ arch/arm/dts/rk3368-u-boot.dtsi | 16 ++ arch/arm/dts/rk3399-u-boot.dtsi | 20 +++ arch/arm/dts/rk3xxx-u-boot.dtsi | 7 + arch/arm/dts/rv1108-u-boot.dtsi | 25 +++ arch/arm/dts/rv1126-u-boot.dtsi | 22 +++ drivers/gpio/rk_gpio.c | 54 +++++-- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 142 ++++++++++++++---- 15 files changed, 364 insertions(+), 55 deletions(-)
Use syscon_regmap_lookup_by_phandle() to simplify the code.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: Collect r-b tag --- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 39 ++++++------------- 1 file changed, 12 insertions(+), 27 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index d449d07d32e7..f6af22501c36 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -10,6 +10,7 @@ #include <syscon.h> #include <fdtdec.h> #include <linux/bitops.h> +#include <linux/err.h> #include <linux/libfdt.h>
#include "pinctrl-rockchip.h" @@ -640,37 +641,21 @@ int rockchip_pinctrl_probe(struct udevice *dev) { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); struct rockchip_pin_ctrl *ctrl; - struct udevice *syscon; - struct regmap *regmap; - int ret = 0;
- /* get rockchip grf syscon phandle */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", - &syscon); - if (ret) { - debug("unable to find rockchip,grf syscon device (%d)\n", ret); - return ret; + priv->regmap_base = + syscon_regmap_lookup_by_phandle(dev, "rockchip,grf"); + if (IS_ERR(priv->regmap_base)) { + debug("unable to find rockchip,grf regmap\n"); + return PTR_ERR(priv->regmap_base); }
- /* get grf-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - debug("unable to find rockchip grf regmap\n"); - return -ENODEV; - } - priv->regmap_base = regmap; - - /* option: get pmu-reg base address */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", - &syscon); - if (!ret) { - /* get pmugrf-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - debug("unable to find rockchip pmu regmap\n"); - return -ENODEV; + if (dev_read_bool(dev, "rockchip,pmu")) { + priv->regmap_pmu = + syscon_regmap_lookup_by_phandle(dev, "rockchip,pmu"); + if (IS_ERR(priv->regmap_pmu)) { + debug("unable to find rockchip,pmu regmap\n"); + return PTR_ERR(priv->regmap_pmu); } - priv->regmap_pmu = regmap; }
ctrl = rockchip_pinctrl_get_soc_data(dev);
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Use syscon_regmap_lookup_by_phandle() to simplify the code.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com
Reviewed-by: Quentin Schulz quentin.schulz@cherry.de
Thanks! Quentin
Add a pin_to_bank() helper that can locate a pin bank based on the pin offset, to be used in get_gpio_mux() and gpio_request_enable() ops.
Reset ctrl->nr_pins to 0 so that pin_to_bank() can locate a bank after the second probe in U-Boot proper.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v2: New patch split from "pinctrl: rockchip: Add gpio_request_enable() ops" of "rockchip: Add gpio request() ops" series --- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index f6af22501c36..894ff74aee98 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -176,6 +176,23 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) return ((val >> bit) & mask); }
+static struct rockchip_pin_bank *rockchip_pin_to_bank(struct udevice *dev, + unsigned int pin) +{ + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (pin >= bank->pin_base && + pin < bank->pin_base + bank->nr_pins) + return bank; + } + + return NULL; +} + static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index) { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); @@ -539,6 +556,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d drv_pmu_offs = ctrl->pmu_drv_offset; drv_grf_offs = ctrl->grf_drv_offset; bank = ctrl->pin_banks; + ctrl->nr_pins = 0;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0;
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Add a pin_to_bank() helper that can locate a pin bank based on the pin offset, to be used in get_gpio_mux() and gpio_request_enable() ops.
Reset ctrl->nr_pins to 0 so that pin_to_bank() can locate a bank after the second probe in U-Boot proper.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
v2: New patch split from "pinctrl: rockchip: Add gpio_request_enable() ops" of "rockchip: Add gpio request() ops" series
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index f6af22501c36..894ff74aee98 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -176,6 +176,23 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) return ((val >> bit) & mask); }
+static struct rockchip_pin_bank *rockchip_pin_to_bank(struct udevice *dev,
unsigned int pin)+{
- struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
- struct rockchip_pin_ctrl *ctrl = priv->ctrl;
- struct rockchip_pin_bank *bank = ctrl->pin_banks;
- int i;
- for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (pin >= bank->pin_base &&pin < bank->pin_base + bank->nr_pins)return bank;- }
- return NULL;
+}
- static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index) { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
@@ -539,6 +556,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d drv_pmu_offs = ctrl->pmu_drv_offset; drv_grf_offs = ctrl->grf_drv_offset; bank = ctrl->pin_banks;
- ctrl->nr_pins = 0;
Please in a separate commit, this seems to be an important bug to fix.
Now, I don't understand why we would probe twice in U-Boot proper. This seems very bad, shouldn't one probe be enough?
Further, I assume the issue is that we modify the static struct rockchip_pin_ctrl from within the pre-reloc probe and since the content won't have changed after relocation, whatever we modify in this struct will persist. This is.... bad. I would therefore suggest we migrate to const struct instead and have some kind of priv data that is allocated and initialized during probe and doesn't persist between probes (though I'm still perplexed by the double probe thingy).
Cheers, Quentin
On 2024/8/3 06:56, Jonas Karlman wrote:
Add a pin_to_bank() helper that can locate a pin bank based on the pin offset, to be used in get_gpio_mux() and gpio_request_enable() ops.
Reset ctrl->nr_pins to 0 so that pin_to_bank() can locate a bank after the second probe in U-Boot proper.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
v2: New patch split from "pinctrl: rockchip: Add gpio_request_enable() ops" of "rockchip: Add gpio request() ops" series
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index f6af22501c36..894ff74aee98 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -176,6 +176,23 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) return ((val >> bit) & mask); }
+static struct rockchip_pin_bank *rockchip_pin_to_bank(struct udevice *dev,
unsigned int pin)+{
- struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
- struct rockchip_pin_ctrl *ctrl = priv->ctrl;
- struct rockchip_pin_bank *bank = ctrl->pin_banks;
- int i;
- for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (pin >= bank->pin_base &&pin < bank->pin_base + bank->nr_pins)return bank;- }
- return NULL;
+}
- static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index) { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
@@ -539,6 +556,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d drv_pmu_offs = ctrl->pmu_drv_offset; drv_grf_offs = ctrl->grf_drv_offset; bank = ctrl->pin_banks;
ctrl->nr_pins = 0;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0;
Add a way to get_gpio_mux() based on the pinctrl pin offset, use -1 as banknum to use the pinctrl pin offset mode instead of bank pin offset.
This mode will be used by the gpio driver to ensure a pin used by gpio request() and get_function() ops always refer to the same pinctrl pin.
Also add verify_config() of banknum and index to avoid an out of range access of the pin_banks array, i.e. with gpio6 on rk3066a.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: Collect r-b tag
The pin_to_mux() helper will also be used in the get_pin_muxing() ops added in next patch to support the pinmux status cmd. --- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 894ff74aee98..8ede74da40c9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -193,10 +193,30 @@ static struct rockchip_pin_bank *rockchip_pin_to_bank(struct udevice *dev, return NULL; }
+static int rockchip_pin_to_mux(struct udevice *dev, unsigned int pin) +{ + struct rockchip_pin_bank *bank; + + bank = rockchip_pin_to_bank(dev, pin); + if (!bank) + return -EINVAL; + + return rockchip_get_mux(bank, pin - bank->pin_base); +} + static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index) -{ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); +{ + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); struct rockchip_pin_ctrl *ctrl = priv->ctrl; + int ret; + + if (banknum == -1) + return rockchip_pin_to_mux(dev, index); + + ret = rockchip_verify_config(dev, banknum, index); + if (ret) + return ret;
return rockchip_get_mux(&ctrl->pin_banks[banknum], index); }
Add get_pins_count(), get_pin_name() and get_pin_muxing() ops to support the pinmux status cmd.
=> pinmux dev pinctrl dev: pinctrl => pinmux status GPIO0_A0 : gpio GPIO0_A1 : func-1 GPIO0_A2 : gpio GPIO0_A3 : gpio GPIO0_A4 : func-1 GPIO0_A5 : gpio GPIO0_A6 : gpio GPIO0_A7 : func-1 GPIO0_B0 : gpio GPIO0_B1 : func-1 GPIO0_B2 : func-1 GPIO0_B3 : gpio [...]
The change to use ENOENT for unrouted pins also help hide a "Error -22" message for unrouted pins using the gpio status -a cmd.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: Collect r-b tag --- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 8ede74da40c9..345e0abdf5d1 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -126,7 +126,7 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { debug("pin %d is unrouted\n", pin); - return -EINVAL; + return -ENOENT; }
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) @@ -193,6 +193,32 @@ static struct rockchip_pin_bank *rockchip_pin_to_bank(struct udevice *dev, return NULL; }
+static int rockchip_pinctrl_get_pins_count(struct udevice *dev) +{ + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_ctrl *ctrl = priv->ctrl; + + return ctrl->nr_pins; +} + +static const char *rockchip_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + static char name[PINNAME_SIZE]; + struct rockchip_pin_bank *bank; + unsigned int index; + + bank = rockchip_pin_to_bank(dev, selector); + if (!bank) + return NULL; + + index = selector - bank->pin_base; + snprintf(name, sizeof(name), "GPIO%u_%c%u", + bank->bank_num, 'A' + (index / 8), index % 8); + + return name; +} + static int rockchip_pin_to_mux(struct udevice *dev, unsigned int pin) { struct rockchip_pin_bank *bank; @@ -221,6 +247,25 @@ static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, return rockchip_get_mux(&ctrl->pin_banks[banknum], index); }
+static int rockchip_pinctrl_get_pin_muxing(struct udevice *dev, + unsigned int selector, + char *buf, int size) +{ + int mux; + + mux = rockchip_pin_to_mux(dev, selector); + if (mux == -ENOENT) + strlcpy(buf, "unrouted", size); + else if (mux < 0) + return mux; + else if (mux) + snprintf(buf, size, "func-%d", mux); + else + strlcpy(buf, "gpio", size); + + return 0; +} + static int rockchip_verify_mux(struct rockchip_pin_bank *bank, int pin, int mux) { @@ -558,8 +603,11 @@ static int rockchip_pinctrl_set_state(struct udevice *dev, }
const struct pinctrl_ops rockchip_pinctrl_ops = { + .get_pins_count = rockchip_pinctrl_get_pins_count, + .get_pin_name = rockchip_pinctrl_get_pin_name, .set_state = rockchip_pinctrl_set_state, .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, + .get_pin_muxing = rockchip_pinctrl_get_pin_muxing, };
/* retrieve the soc specific data */
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Add get_pins_count(), get_pin_name() and get_pin_muxing() ops to support the pinmux status cmd.
=> pinmux dev pinctrl dev: pinctrl => pinmux status GPIO0_A0 : gpio GPIO0_A1 : func-1 GPIO0_A2 : gpio GPIO0_A3 : gpio GPIO0_A4 : func-1 GPIO0_A5 : gpio GPIO0_A6 : gpio GPIO0_A7 : func-1 GPIO0_B0 : gpio GPIO0_B1 : func-1 GPIO0_B2 : func-1 GPIO0_B3 : gpio [...]
The change to use ENOENT for unrouted pins also help hide a "Error -22" message for unrouted pins using the gpio status -a cmd.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com
v2: Collect r-b tag
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 8ede74da40c9..345e0abdf5d1 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -126,7 +126,7 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { debug("pin %d is unrouted\n", pin);
return -EINVAL;
return -ENOENT;
Rather ENODEV or ENXIO according to the comments in https://elixir.bootlin.com/u-boot/v2024.07/source/include/linux/errno.h?
}
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) @@ -193,6 +193,32 @@ static struct rockchip_pin_bank *rockchip_pin_to_bank(struct udevice *dev, return NULL; }
+static int rockchip_pinctrl_get_pins_count(struct udevice *dev) +{
- struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
- struct rockchip_pin_ctrl *ctrl = priv->ctrl;
- return ctrl->nr_pins;
+}
+static const char *rockchip_pinctrl_get_pin_name(struct udevice *dev,
unsigned int selector)+{
- static char name[PINNAME_SIZE];
- struct rockchip_pin_bank *bank;
- unsigned int index;
- bank = rockchip_pin_to_bank(dev, selector);
- if (!bank)
return NULL;- index = selector - bank->pin_base;
- snprintf(name, sizeof(name), "GPIO%u_%c%u",
bank->bank_num, 'A' + (index / 8), index % 8);
So before I forget, I think we have an issue on PX30 (unrelated to this patch) because GPIO0 is said to have 32 pins but it doesn't, it has 24, c.f. the TRM where GPIO0 doesn't have a D "sub-bank". I'll have to check the Linux kernel driver(s) too, but considering we've been using sysfs for setting GPIOs on PX30 for a while in the kernel, I assume somehow this is handled properly (or just luck).
I'm also wondering if the name shouldn't rather be the one coming from gpio-line-names too? This probably is more for the gpio command than the pinctrl one though I assume? I guess we could also tackle this in the future if someone would like to have this instead.
Cheers, Quentin
Implement gpio_request_enable() ops so that the gpio request() ops can be implemented and a gpio requested pin automatically is pinmuxed for gpio use, similar to Linux kernel.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v2: New patch from "rockchip: Add gpio request() ops" series --- drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 345e0abdf5d1..e164af0d8f61 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -358,6 +358,18 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) return 0; }
+static int rockchip_pinctrl_gpio_request_enable(struct udevice *dev, + unsigned int selector) +{ + struct rockchip_pin_bank *bank; + + bank = rockchip_pin_to_bank(dev, selector); + if (!bank) + return -EINVAL; + + return rockchip_set_mux(bank, selector - bank->pin_base, RK_FUNC_GPIO); +} + static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { { 2, 4, 8, 12, -1, -1, -1, -1 }, { 3, 6, 9, 12, -1, -1, -1, -1 }, @@ -608,6 +620,7 @@ const struct pinctrl_ops rockchip_pinctrl_ops = { .set_state = rockchip_pinctrl_set_state, .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, .get_pin_muxing = rockchip_pinctrl_get_pin_muxing, + .gpio_request_enable = rockchip_pinctrl_gpio_request_enable, };
/* retrieve the soc specific data */
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Implement gpio_request_enable() ops so that the gpio request() ops can be implemented and a gpio requested pin automatically is pinmuxed for gpio use, similar to Linux kernel.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Quentin Schulz quentin.schulz@cherry.de
Thanks! Quentin
On 2024/8/3 06:56, Jonas Karlman wrote:
Implement gpio_request_enable() ops so that the gpio request() ops can be implemented and a gpio requested pin automatically is pinmuxed for gpio use, similar to Linux kernel.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
v2: New patch from "rockchip: Add gpio request() ops" series
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 345e0abdf5d1..e164af0d8f61 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -358,6 +358,18 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) return 0; }
+static int rockchip_pinctrl_gpio_request_enable(struct udevice *dev,
unsigned int selector)+{
- struct rockchip_pin_bank *bank;
- bank = rockchip_pin_to_bank(dev, selector);
- if (!bank)
return -EINVAL;- return rockchip_set_mux(bank, selector - bank->pin_base, RK_FUNC_GPIO);
+}
- static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { { 2, 4, 8, 12, -1, -1, -1, -1 }, { 3, 6, 9, 12, -1, -1, -1, -1 },
@@ -608,6 +620,7 @@ const struct pinctrl_ops rockchip_pinctrl_ops = { .set_state = rockchip_pinctrl_set_state, .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, .get_pin_muxing = rockchip_pinctrl_get_pin_muxing,
.gpio_request_enable = rockchip_pinctrl_gpio_request_enable, };
/* retrieve the soc specific data */
Get pinctrl device from gpio-ranges phandle when the property exists, fallback to get the first pinctrl device.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: Collect r-b tag --- drivers/gpio/rk_gpio.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 24ba12dd820e..abece6409ae0 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -181,12 +181,6 @@ static int rockchip_gpio_probe(struct udevice *dev)
priv->regs = dev_read_addr_ptr(dev);
- if (CONFIG_IS_ENABLED(PINCTRL)) { - ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); - if (ret) - return ret; - } - /* * If "gpio-ranges" is present in the devicetree use it to parse * the GPIO bank ID, otherwise use the legacy method. @@ -194,16 +188,33 @@ static int rockchip_gpio_probe(struct udevice *dev) ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges", NULL, 3, 0, &args); - if (!ret || ret != -ENOENT) { + if (!ret) { uc_priv->gpio_count = args.args[2]; priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK; - } else { + + if (CONFIG_IS_ENABLED(PINCTRL)) { + ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL, + args.node, + &priv->pinctrl); + if (ret) + return ret; + } + } else if (ret == -ENOENT || !CONFIG_IS_ENABLED(PINCTRL)) { uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; ret = dev_read_alias_seq(dev, &priv->bank); if (ret) { end = strrchr(dev->name, '@'); priv->bank = trailing_strtoln(dev->name, end); } + + if (CONFIG_IS_ENABLED(PINCTRL)) { + ret = uclass_first_device_err(UCLASS_PINCTRL, + &priv->pinctrl); + if (ret) + return ret; + } + } else { + return ret; }
priv->name[0] = 'A' + priv->bank;
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Get pinctrl device from gpio-ranges phandle when the property exists, fallback to get the first pinctrl device.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com
v2: Collect r-b tag
drivers/gpio/rk_gpio.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 24ba12dd820e..abece6409ae0 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -181,12 +181,6 @@ static int rockchip_gpio_probe(struct udevice *dev)
priv->regs = dev_read_addr_ptr(dev);
- if (CONFIG_IS_ENABLED(PINCTRL)) {
ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);if (ret)return ret;- }
- /*
- If "gpio-ranges" is present in the devicetree use it to parse
- the GPIO bank ID, otherwise use the legacy method.
@@ -194,16 +188,33 @@ static int rockchip_gpio_probe(struct udevice *dev) ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges", NULL, 3, 0, &args);
- if (!ret || ret != -ENOENT) {
- if (!ret) { uc_priv->gpio_count = args.args[2]; priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK;
I assume this is broken if a bank has less than 32 GPIOs, e.g. rk3288 and px30's GPIO0?
E.g. this would mean if gpio-ranges is proper in the DT (it isn't for PX30 today), GPIO1 would be detected as being GPIO0 because GPIO0 is only 24 pins?
I assume we could trick this by doing (base+nrpins-1)/32 which would make it much less likely to have overlaps (we would need multiple smaller banks to offset bank's bases enough).
- } else {
if (CONFIG_IS_ENABLED(PINCTRL)) {ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL,args.node,&priv->pinctrl);
Could have been two separate commits here: 1) getting pinctrl from property 2) switching the order to save a call to uclass_first_device_err if we have a gpio-ranges property
if (ret)return ret;}- } else if (ret == -ENOENT || !CONFIG_IS_ENABLED(PINCTRL)) { uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
Oof, another issue here wrt amount of gpios in a bank. Seems like I opened another can of worms :/
ret = dev_read_alias_seq(dev, &priv->bank); if (ret) { end = strrchr(dev->name, '@'); priv->bank = trailing_strtoln(dev->name, end); }
if (CONFIG_IS_ENABLED(PINCTRL)) {ret = uclass_first_device_err(UCLASS_PINCTRL,&priv->pinctrl);if (ret)return ret;}- } else {
return ret;
I'm getting a bit confused by the change of if conditions here...
Wouldn't it be much simpler to just do:
if (!priv->pinctrl && CONFIG_IS_ENABLED(PINCTRL)) { ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); if (ret) return ret; }
after the existing if-else and removing the uclass_first_device_err currently before it?
Also not sure to understand why we suddenly do not accept any error code (we used to accept everything but ENOENT).
Cheers, Quentin
Use the pinctrl pin offset to get_gpio_mux() to remove the bank num dependency and instead only use the bank num to assign a bank name.
Most Rockchip SoCs use all 32 pins of each gpio controller, meaning the pinctrl pin offset typically is aligned to 32.
However, for gpio0 on RK3288 only 24 pins are used meaning the pinctrl pin offset start at pin 24 for gpio1. Use DIV_ROUND_UP to get the 32 pin aligned bank num.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: Collect r-b tag --- drivers/gpio/rk_gpio.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index abece6409ae0..5972f7f8612d 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -34,7 +34,7 @@ enum { struct rockchip_gpio_priv { void __iomem *regs; struct udevice *pinctrl; - int bank; + int pfc_offset; char name[2]; u32 version; }; @@ -108,7 +108,8 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) int ret;
if (CONFIG_IS_ENABLED(PINCTRL)) { - ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); + ret = pinctrl_get_gpio_mux(priv->pinctrl, -1, + priv->pfc_offset + offset); if (ret < 0) return ret; else if (ret != RK_FUNC_GPIO) @@ -177,7 +178,7 @@ static int rockchip_gpio_probe(struct udevice *dev) struct rockchip_gpio_priv *priv = dev_get_priv(dev); struct ofnode_phandle_args args; char *end; - int ret; + int bank, ret;
priv->regs = dev_read_addr_ptr(dev);
@@ -190,7 +191,8 @@ static int rockchip_gpio_probe(struct udevice *dev) 0, &args); if (!ret) { uc_priv->gpio_count = args.args[2]; - priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK; + bank = DIV_ROUND_UP(args.args[1], ROCKCHIP_GPIOS_PER_BANK); + priv->pfc_offset = args.args[1];
if (CONFIG_IS_ENABLED(PINCTRL)) { ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL, @@ -201,11 +203,12 @@ static int rockchip_gpio_probe(struct udevice *dev) } } else if (ret == -ENOENT || !CONFIG_IS_ENABLED(PINCTRL)) { uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; - ret = dev_read_alias_seq(dev, &priv->bank); + ret = dev_read_alias_seq(dev, &bank); if (ret) { end = strrchr(dev->name, '@'); - priv->bank = trailing_strtoln(dev->name, end); + bank = trailing_strtoln(dev->name, end); } + priv->pfc_offset = bank * ROCKCHIP_GPIOS_PER_BANK;
if (CONFIG_IS_ENABLED(PINCTRL)) { ret = uclass_first_device_err(UCLASS_PINCTRL, @@ -217,7 +220,7 @@ static int rockchip_gpio_probe(struct udevice *dev) return ret; }
- priv->name[0] = 'A' + priv->bank; + priv->name[0] = 'A' + bank; uc_priv->bank_name = priv->name;
priv->version = readl(priv->regs + VER_ID_V2);
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Use the pinctrl pin offset to get_gpio_mux() to remove the bank num dependency and instead only use the bank num to assign a bank name.
Most Rockchip SoCs use all 32 pins of each gpio controller, meaning the pinctrl pin offset typically is aligned to 32.
However, for gpio0 on RK3288 only 24 pins are used meaning the pinctrl pin offset start at pin 24 for gpio1. Use DIV_ROUND_UP to get the 32 pin aligned bank num.
I now see that someone had already opened the can of worms :)
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com
Reviewed-by: Quentin Schulz quentin.schulz@cherry.de
Thanks! Quentin
Add a request() ops that call pinctrl_gpio_request() when the required gpio-ranges prop has been defined to signal pinctrl driver to use gpio pinmux.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v2: New patch from "rockchip: Add gpio request() ops" series --- drivers/gpio/rk_gpio.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 5972f7f8612d..65811dbc78d6 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -126,6 +126,15 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) return (data & mask) ? GPIOF_OUTPUT : GPIOF_INPUT; }
+static int rockchip_gpio_request(struct udevice *dev, unsigned offset, + const char *label) +{ + if (CONFIG_IS_ENABLED(PINCTRL) && dev_read_bool(dev, "gpio-ranges")) + return pinctrl_gpio_request(dev, offset, label); + + return 0; +} + /* Simple SPL interface to GPIOs */ #ifdef CONFIG_SPL_BUILD
@@ -229,6 +238,7 @@ static int rockchip_gpio_probe(struct udevice *dev) }
static const struct dm_gpio_ops gpio_rockchip_ops = { + .request = rockchip_gpio_request, .direction_input = rockchip_gpio_direction_input, .direction_output = rockchip_gpio_direction_output, .get_value = rockchip_gpio_get_value,
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Add a request() ops that call pinctrl_gpio_request() when the required gpio-ranges prop has been defined to signal pinctrl driver to use gpio pinmux.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
v2: New patch from "rockchip: Add gpio request() ops" series
drivers/gpio/rk_gpio.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 5972f7f8612d..65811dbc78d6 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -126,6 +126,15 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) return (data & mask) ? GPIOF_OUTPUT : GPIOF_INPUT; }
+static int rockchip_gpio_request(struct udevice *dev, unsigned offset,
const char *label)+{
- if (CONFIG_IS_ENABLED(PINCTRL) && dev_read_bool(dev, "gpio-ranges"))
I assume we check for gpio-ranges property because pinctrl_gpio_get_pinctrl_and_offset called by pinctrl_gpio_request will return an error if the property isn't there?
I see that you're adding the gpio-ranges to Rockchip SoCs that are missing them (as well as the aliases), wouldn't it make more sense to move this commit after that commit and remove the dependency on gpio-ranges property and let pinctrl_gpio_request fail if it isn't there?
Cheers, Quentin
On 2024/8/3 06:56, Jonas Karlman wrote:
Add a request() ops that call pinctrl_gpio_request() when the required gpio-ranges prop has been defined to signal pinctrl driver to use gpio pinmux.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
v2: New patch from "rockchip: Add gpio request() ops" series
drivers/gpio/rk_gpio.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 5972f7f8612d..65811dbc78d6 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -126,6 +126,15 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) return (data & mask) ? GPIOF_OUTPUT : GPIOF_INPUT; }
+static int rockchip_gpio_request(struct udevice *dev, unsigned offset,
const char *label)+{
- if (CONFIG_IS_ENABLED(PINCTRL) && dev_read_bool(dev, "gpio-ranges"))
return pinctrl_gpio_request(dev, offset, label);- return 0;
+}
- /* Simple SPL interface to GPIOs */ #ifdef CONFIG_SPL_BUILD
@@ -229,6 +238,7 @@ static int rockchip_gpio_probe(struct udevice *dev) }
static const struct dm_gpio_ops gpio_rockchip_ops = {
- .request = rockchip_gpio_request, .direction_input = rockchip_gpio_direction_input, .direction_output = rockchip_gpio_direction_output, .get_value = rockchip_gpio_get_value,
Add gpio-ranges props to supported SoCs based on the following Linux patches:
ARM: dts: rockchip: add gpio-ranges property to gpio nodes https://lore.kernel.org/all/26007385-81dc-9961-05d5-8b9a0969d0b6@gmail.com/
arm64: dts: rockchip: add gpio-ranges property to gpio nodes https://lore.kernel.org/all/18c8c89a-9962-40f0-814f-81e2c420c957@gmail.com/
For RK3066 and RK3288 the gpio-ranges props is adjusted to match https://lore.kernel.org/all/541b7633-af3b-4392-ac29-7ee1f2c6f943@kwiboo.se/
Re-enable gpio6 on RK3066 now that the pinctrl pin offset is used with get_gpio_mux().
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: Collect r-b tag
Cc: Johan Jonker jbx6244@gmail.com --- arch/arm/dts/rk3036-u-boot.dtsi | 12 ++++++++++++ arch/arm/dts/rk3066a-u-boot.dtsi | 3 +-- arch/arm/dts/rk3128-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk322x-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3288-u-boot.dtsi | 33 ++++++++++++++++++++++++++++++++ arch/arm/dts/rk3308-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/rk3328-u-boot.dtsi | 13 +++++++++++++ arch/arm/dts/rk3368-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/rv1108-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rv1126-u-boot.dtsi | 14 ++++++++++++++ 11 files changed, 177 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3036-u-boot.dtsi b/arch/arm/dts/rk3036-u-boot.dtsi index 41ac054b81e8..3e788187f630 100644 --- a/arch/arm/dts/rk3036-u-boot.dtsi +++ b/arch/arm/dts/rk3036-u-boot.dtsi @@ -4,3 +4,15 @@ */
#include "rockchip-u-boot.dtsi" + +&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi index 06f405ca2c5e..35b52d6fb7f3 100644 --- a/arch/arm/dts/rk3066a-u-boot.dtsi +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -24,6 +24,5 @@ };
&gpio6 { - status = "disabled"; + gpio-ranges = <&pinctrl 0 160 16>; }; - diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi index 6d1965e6b520..dd1208e7cf40 100644 --- a/arch/arm/dts/rk3128-u-boot.dtsi +++ b/arch/arm/dts/rk3128-u-boot.dtsi @@ -14,6 +14,22 @@ bootph-all; };
+&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; + &grf { bootph-all; }; diff --git a/arch/arm/dts/rk322x-u-boot.dtsi b/arch/arm/dts/rk322x-u-boot.dtsi index aea917544b1c..f0e2a1f95aa0 100644 --- a/arch/arm/dts/rk322x-u-boot.dtsi +++ b/arch/arm/dts/rk322x-u-boot.dtsi @@ -47,6 +47,22 @@ max-frequency = <150000000>; };
+&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; + &grf { bootph-all; }; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index a43d320ade7b..0f8053a8b690 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -95,8 +95,41 @@ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; };
+&gpio0 { + gpio-ranges = <&pinctrl 0 0 24>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 24 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 56 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 88 32>; +}; + +&gpio4 { + gpio-ranges = <&pinctrl 0 120 32>; +}; + +&gpio5 { + gpio-ranges = <&pinctrl 0 152 32>; +}; + +&gpio6 { + gpio-ranges = <&pinctrl 0 184 32>; +}; + &gpio7 { bootph-all; + gpio-ranges = <&pinctrl 0 216 32>; +}; + +&gpio8 { + gpio-ranges = <&pinctrl 0 248 16>; };
&grf { diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index b7964e2756f3..c2d56b532f80 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -54,6 +54,26 @@ bootph-some-ram; };
+&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; + +&gpio4 { + gpio-ranges = <&pinctrl 0 128 32>; +}; + &grf { bootph-all; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 0135bc08d491..3bc776146a82 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -57,6 +57,19 @@
&gpio0 { bootph-pre-ram; + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; };
&grf { diff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi index 811d59ac346e..be2ebda83529 100644 --- a/arch/arm/dts/rk3368-u-boot.dtsi +++ b/arch/arm/dts/rk3368-u-boot.dtsi @@ -26,3 +26,19 @@ reg = <0x0 0xff740000 0x0 0x1000>; }; }; + +&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index c4c8bb1401ea..cead23ea7c20 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -91,6 +91,26 @@ bootph-some-ram; };
+&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; + +&gpio4 { + gpio-ranges = <&pinctrl 0 128 32>; +}; + &grf { bootph-all; }; diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi index ccf2d8bd83ec..f772d618bd1d 100644 --- a/arch/arm/dts/rv1108-u-boot.dtsi +++ b/arch/arm/dts/rv1108-u-boot.dtsi @@ -5,6 +5,22 @@
#include "rockchip-u-boot.dtsi"
+&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; + &grf { bootph-all; }; diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi index 448598013578..3e6df1e433db 100644 --- a/arch/arm/dts/rv1126-u-boot.dtsi +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -31,10 +31,24 @@
&gpio0 { bootph-pre-ram; + gpio-ranges = <&pinctrl 0 0 32>; };
&gpio1 { bootph-pre-ram; + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; + +&gpio4 { + gpio-ranges = <&pinctrl 0 128 2>; };
&grf {
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Add gpio-ranges props to supported SoCs based on the following Linux patches:
ARM: dts: rockchip: add gpio-ranges property to gpio nodes https://lore.kernel.org/all/26007385-81dc-9961-05d5-8b9a0969d0b6@gmail.com/
arm64: dts: rockchip: add gpio-ranges property to gpio nodes https://lore.kernel.org/all/18c8c89a-9962-40f0-814f-81e2c420c957@gmail.com/
For RK3066 and RK3288 the gpio-ranges props is adjusted to match https://lore.kernel.org/all/541b7633-af3b-4392-ac29-7ee1f2c6f943@kwiboo.se/
Re-enable gpio6 on RK3066 now that the pinctrl pin offset is used with get_gpio_mux().
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com
v2: Collect r-b tag
Cc: Johan Jonker jbx6244@gmail.com
arch/arm/dts/rk3036-u-boot.dtsi | 12 ++++++++++++ arch/arm/dts/rk3066a-u-boot.dtsi | 3 +-- arch/arm/dts/rk3128-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk322x-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3288-u-boot.dtsi | 33 ++++++++++++++++++++++++++++++++ arch/arm/dts/rk3308-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/rk3328-u-boot.dtsi | 13 +++++++++++++ arch/arm/dts/rk3368-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/rv1108-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rv1126-u-boot.dtsi | 14 ++++++++++++++ 11 files changed, 177 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3036-u-boot.dtsi b/arch/arm/dts/rk3036-u-boot.dtsi index 41ac054b81e8..3e788187f630 100644 --- a/arch/arm/dts/rk3036-u-boot.dtsi +++ b/arch/arm/dts/rk3036-u-boot.dtsi @@ -4,3 +4,15 @@ */
#include "rockchip-u-boot.dtsi"
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+}; diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi index 06f405ca2c5e..35b52d6fb7f3 100644 --- a/arch/arm/dts/rk3066a-u-boot.dtsi +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -24,6 +24,5 @@ };
&gpio6 {
- status = "disabled";
- gpio-ranges = <&pinctrl 0 160 16>; };
diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi index 6d1965e6b520..dd1208e7cf40 100644 --- a/arch/arm/dts/rk3128-u-boot.dtsi +++ b/arch/arm/dts/rk3128-u-boot.dtsi @@ -14,6 +14,22 @@ bootph-all; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
- &grf { bootph-all; };
diff --git a/arch/arm/dts/rk322x-u-boot.dtsi b/arch/arm/dts/rk322x-u-boot.dtsi index aea917544b1c..f0e2a1f95aa0 100644 --- a/arch/arm/dts/rk322x-u-boot.dtsi +++ b/arch/arm/dts/rk322x-u-boot.dtsi @@ -47,6 +47,22 @@ max-frequency = <150000000>; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
- &grf { bootph-all; };
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index a43d320ade7b..0f8053a8b690 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -95,8 +95,41 @@ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 24>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 24 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 56 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 88 32>;
+};
+&gpio4 {
- gpio-ranges = <&pinctrl 0 120 32>;
+};
+&gpio5 {
- gpio-ranges = <&pinctrl 0 152 32>;
+};
+&gpio6 {
- gpio-ranges = <&pinctrl 0 184 32>;
+};
- &gpio7 { bootph-all;
- gpio-ranges = <&pinctrl 0 216 32>;
+};
+&gpio8 {
gpio-ranges = <&pinctrl 0 248 16>; };
&grf {
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index b7964e2756f3..c2d56b532f80 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -54,6 +54,26 @@ bootph-some-ram; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
+&gpio4 {
- gpio-ranges = <&pinctrl 0 128 32>;
+};
- &grf { bootph-all; };
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 0135bc08d491..3bc776146a82 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -57,6 +57,19 @@
&gpio0 { bootph-pre-ram;
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
gpio-ranges = <&pinctrl 0 96 32>; };
&grf {
diff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi index 811d59ac346e..be2ebda83529 100644 --- a/arch/arm/dts/rk3368-u-boot.dtsi +++ b/arch/arm/dts/rk3368-u-boot.dtsi @@ -26,3 +26,19 @@ reg = <0x0 0xff740000 0x0 0x1000>; }; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index c4c8bb1401ea..cead23ea7c20 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -91,6 +91,26 @@ bootph-some-ram; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
Only 15 available here... /me sobs
TRM part 1: GPIO0_A[7:0] GPIO0_B[6:0]
no GPIO0_C or D it seems (though the TRM somehow mentions GPIO0_C but nothing to configure it and the Linux kernel driver says bank0 is 16 pins (which is also incorrect as there's no GPIO0_B7)...
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
This also is incorrect, GPIO1_D only has one pin.
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
This also is incorrect...
GPIO2_B stops at pin4, no 5,6,7.
Same for GPIO2_D.
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
This also is incorrect..........
GPIO3_C stops at pin1. GPIO3_D stops at pin
+};
+&gpio4 {
- gpio-ranges = <&pinctrl 0 128 32>;
This also is incorrect.................. (the number of dots matches the number of tears rolling down my face).
GPIO4_B stops at pin5. GPIO4_D stops at pin1.
I only checked for the SoC I personally care (RK3399).
Quentin
On 2024/8/3 06:56, Jonas Karlman wrote:
Add gpio-ranges props to supported SoCs based on the following Linux patches:
ARM: dts: rockchip: add gpio-ranges property to gpio nodes https://lore.kernel.org/all/26007385-81dc-9961-05d5-8b9a0969d0b6@gmail.com/
arm64: dts: rockchip: add gpio-ranges property to gpio nodes https://lore.kernel.org/all/18c8c89a-9962-40f0-814f-81e2c420c957@gmail.com/
For RK3066 and RK3288 the gpio-ranges props is adjusted to match https://lore.kernel.org/all/541b7633-af3b-4392-ac29-7ee1f2c6f943@kwiboo.se/
Re-enable gpio6 on RK3066 now that the pinctrl pin offset is used with get_gpio_mux().
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
v2: Collect r-b tag
Cc: Johan Jonker jbx6244@gmail.com
arch/arm/dts/rk3036-u-boot.dtsi | 12 ++++++++++++ arch/arm/dts/rk3066a-u-boot.dtsi | 3 +-- arch/arm/dts/rk3128-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk322x-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3288-u-boot.dtsi | 33 ++++++++++++++++++++++++++++++++ arch/arm/dts/rk3308-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/rk3328-u-boot.dtsi | 13 +++++++++++++ arch/arm/dts/rk3368-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/rv1108-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rv1126-u-boot.dtsi | 14 ++++++++++++++ 11 files changed, 177 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3036-u-boot.dtsi b/arch/arm/dts/rk3036-u-boot.dtsi index 41ac054b81e8..3e788187f630 100644 --- a/arch/arm/dts/rk3036-u-boot.dtsi +++ b/arch/arm/dts/rk3036-u-boot.dtsi @@ -4,3 +4,15 @@ */
#include "rockchip-u-boot.dtsi"
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+}; diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi index 06f405ca2c5e..35b52d6fb7f3 100644 --- a/arch/arm/dts/rk3066a-u-boot.dtsi +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -24,6 +24,5 @@ };
&gpio6 {
- status = "disabled";
- gpio-ranges = <&pinctrl 0 160 16>; };
diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi index 6d1965e6b520..dd1208e7cf40 100644 --- a/arch/arm/dts/rk3128-u-boot.dtsi +++ b/arch/arm/dts/rk3128-u-boot.dtsi @@ -14,6 +14,22 @@ bootph-all; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
- &grf { bootph-all; };
diff --git a/arch/arm/dts/rk322x-u-boot.dtsi b/arch/arm/dts/rk322x-u-boot.dtsi index aea917544b1c..f0e2a1f95aa0 100644 --- a/arch/arm/dts/rk322x-u-boot.dtsi +++ b/arch/arm/dts/rk322x-u-boot.dtsi @@ -47,6 +47,22 @@ max-frequency = <150000000>; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
- &grf { bootph-all; };
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index a43d320ade7b..0f8053a8b690 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -95,8 +95,41 @@ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 24>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 24 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 56 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 88 32>;
+};
+&gpio4 {
- gpio-ranges = <&pinctrl 0 120 32>;
+};
+&gpio5 {
- gpio-ranges = <&pinctrl 0 152 32>;
+};
+&gpio6 {
- gpio-ranges = <&pinctrl 0 184 32>;
+};
- &gpio7 { bootph-all;
- gpio-ranges = <&pinctrl 0 216 32>;
+};
+&gpio8 {
gpio-ranges = <&pinctrl 0 248 16>; };
&grf {
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index b7964e2756f3..c2d56b532f80 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -54,6 +54,26 @@ bootph-some-ram; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
+&gpio4 {
- gpio-ranges = <&pinctrl 0 128 32>;
+};
- &grf { bootph-all; };
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 0135bc08d491..3bc776146a82 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -57,6 +57,19 @@
&gpio0 { bootph-pre-ram;
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
gpio-ranges = <&pinctrl 0 96 32>; };
&grf {
diff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi index 811d59ac346e..be2ebda83529 100644 --- a/arch/arm/dts/rk3368-u-boot.dtsi +++ b/arch/arm/dts/rk3368-u-boot.dtsi @@ -26,3 +26,19 @@ reg = <0x0 0xff740000 0x0 0x1000>; }; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index c4c8bb1401ea..cead23ea7c20 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -91,6 +91,26 @@ bootph-some-ram; };
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
+&gpio4 {
- gpio-ranges = <&pinctrl 0 128 32>;
+};
- &grf { bootph-all; };
diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi index ccf2d8bd83ec..f772d618bd1d 100644 --- a/arch/arm/dts/rv1108-u-boot.dtsi +++ b/arch/arm/dts/rv1108-u-boot.dtsi @@ -5,6 +5,22 @@
#include "rockchip-u-boot.dtsi"
+&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+};
+&gpio1 {
- gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
- &grf { bootph-all; };
diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi index 448598013578..3e6df1e433db 100644 --- a/arch/arm/dts/rv1126-u-boot.dtsi +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -31,10 +31,24 @@
&gpio0 { bootph-pre-ram;
gpio-ranges = <&pinctrl 0 0 32>; };
&gpio1 { bootph-pre-ram;
gpio-ranges = <&pinctrl 0 32 32>;
+};
+&gpio2 {
- gpio-ranges = <&pinctrl 0 64 32>;
+};
+&gpio3 {
- gpio-ranges = <&pinctrl 0 96 32>;
+};
+&gpio4 {
gpio-ranges = <&pinctrl 0 128 2>; };
&grf {
Add aliases for gpio controllers to soc u-boot dtsi files that are missing aliases in soc dtsi files to ensure dev_seq() return the expected number when a gpio controller is included in SPL.
Also drop the aliases from rk3288-u-boot.dtsi, they are already part of rk3288.dtsi.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v2: New patch --- arch/arm/dts/px30-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3066a-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3288-u-boot.dtsi | 9 --------- arch/arm/dts/rk3xxx-u-boot.dtsi | 7 +++++++ arch/arm/dts/rv1108-u-boot.dtsi | 9 +++++++++ arch/arm/dts/rv1126-u-boot.dtsi | 8 ++++++++ 6 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index abc6b49e6663..3dc70d4e432b 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -7,6 +7,10 @@
/ { aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; mmc0 = &emmc; mmc1 = &sdmmc; }; diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi index 35b52d6fb7f3..60d18d2daeac 100644 --- a/arch/arm/dts/rk3066a-u-boot.dtsi +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -3,6 +3,13 @@ #include "rockchip-u-boot.dtsi" #include "rk3xxx-u-boot.dtsi"
+/ { + aliases { + gpio4 = &gpio4; + gpio6 = &gpio6; + }; +}; + &gpio0 { gpio-ranges = <&pinctrl 0 0 32>; }; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 0f8053a8b690..379d9413adee 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -7,15 +7,6 @@
/ { aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - gpio8 = &gpio8; mmc0 = &emmc; mmc1 = &sdmmc; mmc2 = &sdio0; diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi index 6af6a451ea78..097407ca72dc 100644 --- a/arch/arm/dts/rk3xxx-u-boot.dtsi +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -1,6 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/ { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + }; + noc: syscon@10128000 { compatible = "rockchip,rk3188-noc", "syscon"; reg = <0x10128000 0x2000>; diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi index f772d618bd1d..58711e8b2f8a 100644 --- a/arch/arm/dts/rv1108-u-boot.dtsi +++ b/arch/arm/dts/rv1108-u-boot.dtsi @@ -5,6 +5,15 @@
#include "rockchip-u-boot.dtsi"
+/ { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + }; +}; + &gpio0 { gpio-ranges = <&pinctrl 0 0 32>; }; diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi index 3e6df1e433db..05b5f5260dd5 100644 --- a/arch/arm/dts/rv1126-u-boot.dtsi +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -6,6 +6,14 @@ #include "rockchip-u-boot.dtsi"
/ { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + }; + chosen { u-boot,spl-boot-order = \ "same-as-spl", &emmc, &sdmmc;
Hi Jonas,
On 8/3/24 12:56 AM, Jonas Karlman wrote:
Add aliases for gpio controllers to soc u-boot dtsi files that are missing aliases in soc dtsi files to ensure dev_seq() return the expected number when a gpio controller is included in SPL.
Also drop the aliases from rk3288-u-boot.dtsi, they are already part of rk3288.dtsi.
I know that dt-bindings folks usually complain about those aliases in dtsi, but for Rockchip Heiko merges those usually, c.f. RK3399 for example. So I would suggest to send those patches upstream so we don't keep those forever in U-Boot?
The changes themselves look good to me though.
Cheers, Quentin
On 2024/8/3 06:56, Jonas Karlman wrote:
Add aliases for gpio controllers to soc u-boot dtsi files that are missing aliases in soc dtsi files to ensure dev_seq() return the expected number when a gpio controller is included in SPL.
Also drop the aliases from rk3288-u-boot.dtsi, they are already part of rk3288.dtsi.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
v2: New patch
arch/arm/dts/px30-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3066a-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3288-u-boot.dtsi | 9 --------- arch/arm/dts/rk3xxx-u-boot.dtsi | 7 +++++++ arch/arm/dts/rv1108-u-boot.dtsi | 9 +++++++++ arch/arm/dts/rv1126-u-boot.dtsi | 8 ++++++++ 6 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index abc6b49e6663..3dc70d4e432b 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -7,6 +7,10 @@
/ { aliases {
gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi index 35b52d6fb7f3..60d18d2daeac 100644 --- a/arch/arm/dts/rk3066a-u-boot.dtsi +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -3,6 +3,13 @@ #include "rockchip-u-boot.dtsi" #include "rk3xxx-u-boot.dtsi"
+/ {
- aliases {
gpio4 = &gpio4;gpio6 = &gpio6;- };
+};
- &gpio0 { gpio-ranges = <&pinctrl 0 0 32>; };
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 0f8053a8b690..379d9413adee 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -7,15 +7,6 @@
/ { aliases {
gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;gpio4 = &gpio4;gpio5 = &gpio5;gpio6 = &gpio6;gpio7 = &gpio7;gpio8 = &gpio8;diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi index 6af6a451ea78..097407ca72dc 100644 --- a/arch/arm/dts/rk3xxx-u-boot.dtsi +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -1,6 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/ {
- aliases {
gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;- };
- noc: syscon@10128000 { compatible = "rockchip,rk3188-noc", "syscon"; reg = <0x10128000 0x2000>;
diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi index f772d618bd1d..58711e8b2f8a 100644 --- a/arch/arm/dts/rv1108-u-boot.dtsi +++ b/arch/arm/dts/rv1108-u-boot.dtsi @@ -5,6 +5,15 @@
#include "rockchip-u-boot.dtsi"
+/ {
- aliases {
gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;- };
+};
- &gpio0 { gpio-ranges = <&pinctrl 0 0 32>; };
diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi index 3e6df1e433db..05b5f5260dd5 100644 --- a/arch/arm/dts/rv1126-u-boot.dtsi +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -6,6 +6,14 @@ #include "rockchip-u-boot.dtsi"
/ {
- aliases {
gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;gpio4 = &gpio4;- };
- chosen { u-boot,spl-boot-order = \ "same-as-spl", &emmc, &sdmmc;
Hi Jonas,
On 2024/8/3 06:56, Jonas Karlman wrote:
This series includes some cleanup, add support for using the pinmux status cmd and add support for the gpio request ops.
Following is an example on a Radxa ROCK 5A (RK3588S):
=> pinmux dev pinctrl dev: pinctrl => pinmux status GPIO0_A0 : gpio GPIO0_A1 : func-2 GPIO0_A2 : gpio GPIO0_A3 : gpio GPIO0_A4 : func-1 GPIO0_A5 : func-2 GPIO0_A6 : gpio GPIO0_A7 : gpio GPIO0_B0 : gpio GPIO0_B1 : gpio GPIO0_B2 : gpio GPIO0_B3 : gpio GPIO0_B4 : gpio GPIO0_B5 : func-10 GPIO0_B6 : func-10 GPIO0_B7 : gpio [...]
and on a ASUS TinkerBoard R2.0 (RK3288W):
=> pinmux dev pinctrl dev: pinctrl => pinmux status [...] GPIO2_C6 : gpio GPIO2_C7 : gpio GPIO2_D0 : unrouted GPIO2_D1 : unrouted GPIO2_D2 : unrouted GPIO2_D3 : unrouted GPIO2_D4 : unrouted GPIO2_D5 : unrouted GPIO2_D6 : unrouted GPIO2_D7 : unrouted GPIO3_A0 : func-2 GPIO3_A1 : func-2 [...]
Patch 1 refactor to use syscon_regmap_lookup_by_phandle() helper. Patch 6 refactor to get pinctrl device from gpio-ranges prop.
Patch 2, 3 and 7 change to use pinctrl pin offset instead of bank num to get current pinmux. Patch 4 add required ops for use of the pinmux status cmd.
Patch 5 and 8 add gpio_request_enable() and request() ops.
Patch 9 add gpio-ranges props for remaining RK SoCs, this is strictly not needed for pinmux status cmd to function. However, the change to not require the pin controller offset to be 32 aligned was required to add gpio-ranges props for RK3288.
Patch 10 add gpio aliases for RK SoCs that is missing alias for gpio controllers.
Changes in v2:
- Drop fixes patches already applied
- Split adding pin_to_bank() helper into own patch
- Add gpio_request_enable() and request() ops patch from the "rockchip: Add gpio request() ops" series
- Add missing gpio aliases
- Collect r-b tags
Jonas Karlman (10): pinctrl: rockchip: Use syscon_regmap_lookup_by_phandle() pinctrl: rockchip: Add a pin_to_bank() helper pinctrl: rockchip: Update get_gpio_mux() ops pinctrl: rockchip: Add pinmux status related ops pinctrl: rockchip: Add gpio_request_enable() ops gpio: rockchip: Get pinctrl device from gpio-ranges prop gpio: rockchip: Use pinctrl pin offset to get_gpio_mux() gpio: rockchip: Add request() ops rockchip: gpio: Add gpio-ranges props rockchip: gpio: Add missing gpio aliases
arch/arm/dts/px30-u-boot.dtsi | 4 + arch/arm/dts/rk3036-u-boot.dtsi | 12 ++ arch/arm/dts/rk3066a-u-boot.dtsi | 10 +- arch/arm/dts/rk3128-u-boot.dtsi | 16 ++ arch/arm/dts/rk322x-u-boot.dtsi | 16 ++ arch/arm/dts/rk3288-u-boot.dtsi | 42 ++++--
This series extend the pinctrl driver size and cause a board "miqi-rk3288" build fail:
binman: Error 1 running 'mkimage -d ./mkimage-in-simple-bin.mkimage-u-boot-spl -n rk3288 -T rksd ./idbloader.img': Error: SPL image is too large (size 0x8800 than 0x8000)
We use to met this kind of issue very frequently, and add "CONFIG_SPL_BUILD" to limit the SPL size in driver, we may need to do this again for this feature.
Thanks,
- Kever
arch/arm/dts/rk3308-u-boot.dtsi | 20 +++ arch/arm/dts/rk3328-u-boot.dtsi | 13 ++ arch/arm/dts/rk3368-u-boot.dtsi | 16 ++ arch/arm/dts/rk3399-u-boot.dtsi | 20 +++ arch/arm/dts/rk3xxx-u-boot.dtsi | 7 + arch/arm/dts/rv1108-u-boot.dtsi | 25 +++ arch/arm/dts/rv1126-u-boot.dtsi | 22 +++ drivers/gpio/rk_gpio.c | 54 +++++-- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 142 ++++++++++++++---- 15 files changed, 364 insertions(+), 55 deletions(-)
participants (3)
-
Jonas Karlman -
Kever Yang -
Quentin Schulz