[U-Boot] [PATCH] nios2: set default cache configuration in start.S
Set default icache and dcache configuration for start.S. The values are chosen so that it will work for most configurations. During initialization, cpu information will be extracted from device tree. Then cache flush operations will have correct cache configurations.
Signed-off-by: Thomas Chou thomas@wytron.com.tw --- arch/nios2/cpu/start.S | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 00cec40..83d1576 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -9,6 +9,15 @@ #include <config.h> #include <version.h>
+/* + * icache and dcache configuration used only for start.S. + * the values are chosen so that it will work for all configuration. + */ +#define ICACHE_LINE_SIZE 32 /* fixed 32 */ +#define ICACHE_SIZE_MAX 0x10000 /* 64k max */ +#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */ +#define DCACHE_SIZE_MAX 0x10000 /* 64k max */ + /************************************************************************* * RESTART ************************************************************************/ @@ -25,9 +34,9 @@ _start: * just be invalidating the cache a second time. If cache * is not implemented initi behaves as nop. */ - ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE) - movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE) - ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE) + ori r4, r0, %lo(ICACHE_LINE_SIZE) + movhi r5, %hi(ICACHE_SIZE_MAX) + ori r5, r5, %lo(ICACHE_SIZE_MAX) 0: initi r5 sub r5, r5, r4 bgt r5, r0, 0b @@ -54,10 +63,9 @@ _except_end: * DCACHE INIT -- if dcache not implemented, initd behaves as * nop. */ - movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE) - ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE) - movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE) - ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE) + ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN) + movhi r5, %hi(DCACHE_SIZE_MAX) + ori r5, r5, %lo(DCACHE_SIZE_MAX) mov r6, r0 1: initd 0(r6) add r6, r6, r4
On Tuesday, October 06, 2015 at 10:21:48 AM, Thomas Chou wrote:
Set default icache and dcache configuration for start.S. The values are chosen so that it will work for most configurations. During initialization, cpu information will be extracted from device tree. Then cache flush operations will have correct cache configurations.
Signed-off-by: Thomas Chou thomas@wytron.com.tw
arch/nios2/cpu/start.S | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 00cec40..83d1576 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -9,6 +9,15 @@ #include <config.h> #include <version.h>
+/*
- icache and dcache configuration used only for start.S.
- the values are chosen so that it will work for all configuration.
- */
+#define ICACHE_LINE_SIZE 32 /* fixed 32 */ +#define ICACHE_SIZE_MAX 0x10000 /* 64k max */ +#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */ +#define DCACHE_SIZE_MAX 0x10000 /* 64k max */
/*************************************************************************
- RESTART
************************************************************************/ @@ -25,9 +34,9 @@ _start: * just be invalidating the cache a second time. If cache * is not implemented initi behaves as nop. */
- ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
- movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE)
- ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
- ori r4, r0, %lo(ICACHE_LINE_SIZE)
- movhi r5, %hi(ICACHE_SIZE_MAX)
- ori r5, r5, %lo(ICACHE_SIZE_MAX)
0: initi r5 sub r5, r5, r4 bgt r5, r0, 0b @@ -54,10 +63,9 @@ _except_end: * DCACHE INIT -- if dcache not implemented, initd behaves as * nop. */
- movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE)
- ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE)
- movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE)
- ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE)
- ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
- movhi r5, %hi(DCACHE_SIZE_MAX)
- ori r5, r5, %lo(DCACHE_SIZE_MAX) mov r6, r0
1: initd 0(r6) add r6, r6, r4
Did I miss the DT part somewhere or is that not part of this patch ?
Another question I have is -- why don't we set CONFIG_SYS_{I,D}CACHE_SIZE to maximum value? This should work for all nios2 cache configurations and it should also be correct, no ? Speed might be a bit of an issue here, but I doubt the impact would be that large.
Best regards, Marek Vasut
Hi Marek,
On 10/09/2015 05:14 AM, Marek Vasut wrote:
Did I miss the DT part somewhere or is that not part of this patch ?
As we are just barely starting from reset, there is no luxury of DT. After this, DT will be used with the cache flush patch.
Another question I have is -- why don't we set CONFIG_SYS_{I,D}CACHE_SIZE to maximum value? This should work for all nios2 cache configurations and it should also be correct, no ? Speed might be a bit of an issue here, but I doubt the impact would be that large.
I am doing all the best to get rid of the CONFIG_SYS_{I,D}CACHE_SIZE... So I avoid to use the same macro names. Here I use the maximum value in this startup only. The speed penalty is only once here. After we get DT initialized, we have the correct values of cache configuration.
It might be awful to use the maximum value all the time. See, we flush cache for every eth packet!
Thanks a lot for your review.
Best regards, Thomas
On Friday, October 09, 2015 at 11:03:36 AM, Thomas Chou wrote:
Hi Marek,
Hi,
On 10/09/2015 05:14 AM, Marek Vasut wrote:
Did I miss the DT part somewhere or is that not part of this patch ?
As we are just barely starting from reset, there is no luxury of DT. After this, DT will be used with the cache flush patch.
That's right.
Another question I have is -- why don't we set CONFIG_SYS_{I,D}CACHE_SIZE to maximum value? This should work for all nios2 cache configurations and it should also be correct, no ? Speed might be a bit of an issue here, but I doubt the impact would be that large.
I am doing all the best to get rid of the CONFIG_SYS_{I,D}CACHE_SIZE... So I avoid to use the same macro names. Here I use the maximum value in this startup only. The speed penalty is only once here. After we get DT initialized, we have the correct values of cache configuration.
Ah, right. That's good.
It might be awful to use the maximum value all the time. See, we flush cache for every eth packet!
You should only flush the part where the packet is located ;-) I finally have the MAX10 kit, so I can check the ethernet at least :)
Thanks a lot for your review.
Thanks for keeping up with my weird questions ;-)
Best regards, Marek Vasut
Hi Marek,
On 10/09/2015 10:39 PM, Marek Vasut wrote:
It might be awful to use the maximum value all the time. See, we flush cache for every eth packet!
You should only flush the part where the packet is located ;-) I finally have the MAX10 kit, so I can check the ethernet at least :)
Sure. We shall flush only where the packet is located.
Great to know that you got a MAX10 kit. I received a MAX10 kit, too. I am going to convert altera_tse.c to driver model.
I keep all the pending patches on u-boot-nios/next. You may try out. You will need the fdt address translation patch of Stefan, too.
Best regards, Thomas
On Saturday, October 10, 2015 at 02:21:24 PM, Thomas Chou wrote:
Hi Marek,
Hi!
On 10/09/2015 10:39 PM, Marek Vasut wrote:
It might be awful to use the maximum value all the time. See, we flush cache for every eth packet!
You should only flush the part where the packet is located ;-) I finally have the MAX10 kit, so I can check the ethernet at least :)
Sure. We shall flush only where the packet is located.
Great to know that you got a MAX10 kit. I received a MAX10 kit, too. I am going to convert altera_tse.c to driver model.
I keep all the pending patches on u-boot-nios/next. You may try out. You will need the fdt address translation patch of Stefan, too.
I'll do it once I handle my email queue, which exploded during ELCE ;-)
Best regards, Marek Vasut
Set default icache and dcache configuration for start.S.
We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE... configuration macros. As we are just barely starting from reset, there is no luxury of device tree.
We will set some maximum cache configuration so that it will work for most configurations. This is used only in this start.S. The speed penalty is only once here.
After start up, during board initialization, cpu information will be extracted from device tree. Then cache flush operations will have correct cache configurations.
Signed-off-by: Thomas Chou thomas@wytron.com.tw --- v2 change commit message.
arch/nios2/cpu/start.S | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 17cab6a..8758e7e 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -9,6 +9,15 @@ #include <config.h> #include <version.h>
+/* + * icache and dcache configuration used only for start.S. + * the values are chosen so that it will work for all configuration. + */ +#define ICACHE_LINE_SIZE 32 /* fixed 32 */ +#define ICACHE_SIZE_MAX 0x10000 /* 64k max */ +#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */ +#define DCACHE_SIZE_MAX 0x10000 /* 64k max */ + /* RESTART */ .text .global _start, _except_start, _except_end @@ -22,9 +31,9 @@ _start: * just be invalidating the cache a second time. If cache * is not implemented initi behaves as nop. */ - ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE) - movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE) - ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE) + ori r4, r0, %lo(ICACHE_LINE_SIZE) + movhi r5, %hi(ICACHE_SIZE_MAX) + ori r5, r5, %lo(ICACHE_SIZE_MAX) 0: initi r5 sub r5, r5, r4 bgt r5, r0, 0b @@ -51,10 +60,9 @@ _except_end: * DCACHE INIT -- if dcache not implemented, initd behaves as * nop. */ - movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE) - ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE) - movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE) - ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE) + ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN) + movhi r5, %hi(DCACHE_SIZE_MAX) + ori r5, r5, %lo(DCACHE_SIZE_MAX) mov r6, r0 1: initd 0(r6) add r6, r6, r4
On Friday, October 09, 2015 at 02:11:48 PM, Thomas Chou wrote:
Set default icache and dcache configuration for start.S.
We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE... configuration macros. As we are just barely starting from reset, there is no luxury of device tree.
We will set some maximum cache configuration so that it will work for most configurations. This is used only in this start.S. The speed penalty is only once here.
After start up, during board initialization, cpu information will be extracted from device tree. Then cache flush operations will have correct cache configurations.
Signed-off-by: Thomas Chou thomas@wytron.com.tw
Acked-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut
On 10/09/2015 08:11 PM, Thomas Chou wrote:
Set default icache and dcache configuration for start.S.
We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE... configuration macros. As we are just barely starting from reset, there is no luxury of device tree.
We will set some maximum cache configuration so that it will work for most configurations. This is used only in this start.S. The speed penalty is only once here.
After start up, during board initialization, cpu information will be extracted from device tree. Then cache flush operations will have correct cache configurations.
Signed-off-by: Thomas Chou thomas@wytron.com.tw
v2 change commit message.
arch/nios2/cpu/start.S | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-)
Applied to u-boot-nios.
participants (2)
-
Marek Vasut -
Thomas Chou