[U-Boot] [PATCH 00/13] x86: ivybridge: cougarcanyon2: Various enhancements
This adds some enhancements to the Intel Cougar Canyon 2 board.
This series is available at u-boot-x86/cc2-working for testing.
Bin Meng (13): usb: xhci-pci: Fix compiler warning x86: ivybridge: Imply USB_XHCI_HCD x86: cougarcanyon2: Update dts for SPI lock down x86: cougarcanyon2: Remove CONFIG_HAVE_INTEL_ME x86: ivybridge: Enable 206ax cpu driver for FSP build x86: ivybridge: Drop CONFIG_USBDEBUG x86: chromebook_link: Remove dm-pre-reloc property in the cpu nodes x86: cougarcanyon2: Enable CPU driver and SMP support x86: irq: Remove chipset specific irq router drivers x86: irq: Change LINK_V2N and LINK_N2V to inline functions x86: irq: Introduce CONFIG_DISCRETE_PIRQ_ROUT x86: ivybridge: Implement IvyBridge-specific IRQ converting logic x86: cougarcanyon2: Add missing chipset interrupt information
arch/x86/Kconfig | 9 ++++ arch/x86/cpu/intel_common/mrc.c | 5 --- arch/x86/cpu/irq.c | 28 ++++++------ arch/x86/cpu/ivybridge/Kconfig | 5 +++ arch/x86/cpu/ivybridge/Makefile | 2 +- arch/x86/cpu/ivybridge/model_206ax.c | 15 ------- arch/x86/cpu/quark/Makefile | 2 +- arch/x86/cpu/quark/irq.c | 48 --------------------- arch/x86/cpu/quark/quark.c | 26 +++++++++++ arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/irq.c | 64 ---------------------------- arch/x86/cpu/queensbay/tnc.c | 39 +++++++++++++++++ arch/x86/dts/chromebook_link.dts | 5 --- arch/x86/dts/cougarcanyon2.dts | 71 +++++++++++++++++++++++++++++++ arch/x86/dts/crownbay.dts | 2 +- arch/x86/dts/galileo.dts | 2 +- arch/x86/include/asm/arch-ivybridge/irq.h | 45 ++++++++++++++++++++ arch/x86/include/asm/irq.h | 31 ++++++++++---- configs/cougarcanyon2_defconfig | 6 +++ doc/README.x86 | 4 +- drivers/usb/host/xhci-pci.c | 5 +-- scripts/config_whitelist.txt | 1 - 22 files changed, 249 insertions(+), 168 deletions(-) delete mode 100644 arch/x86/cpu/quark/irq.c delete mode 100644 arch/x86/cpu/queensbay/irq.c create mode 100644 arch/x86/include/asm/arch-ivybridge/irq.h
This fixes the following compiler warning:
"warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]"
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
drivers/usb/host/xhci-pci.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index e8fd6bf..b995aef 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -23,9 +23,8 @@ static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, hcor = (struct xhci_hcor *)((uintptr_t) hccr + HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
- debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", - (u32)hccr, (u32)hcor, - (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); + debug("XHCI-PCI init hccr %p and hcor %p hc_length %d\n", + hccr, hcor, (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
*ret_hccr = hccr; *ret_hcor = hcor;
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
This fixes the following compiler warning:
"warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]"
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/usb/host/xhci-pci.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:29 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
This fixes the following compiler warning:
"warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]"
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/usb/host/xhci-pci.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
The Panther Point chipset connected to Ivybridge has xHC integrated, imply it.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/ivybridge/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 82d5489..eec92df 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE imply SPI_FLASH imply USB imply USB_EHCI_HCD + imply USB_XHCI_HCD imply VIDEO_VESA
if NORTHBRIDGE_INTEL_IVYBRIDGE
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
The Panther Point chipset connected to Ivybridge has xHC integrated, imply it.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Kconfig | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:30 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
The Panther Point chipset connected to Ivybridge has xHC integrated, imply it.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Kconfig | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
It turns out that like Braswell, Intel FSP for IvyBridge requires SPI controller settings to be locked down, as the U-Boot ICH SPI driver fails with the following message on Cougar Canyon 2 board:
"ICH SPI: Opcode 9f not found"
Update the SPI node property to indicate this fact.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/dts/cougarcanyon2.dts | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index ea836ee..8c71e98 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -70,6 +70,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; + intel,spi-lock-down; + spi-flash@0 { reg = <0>; compatible = "winbond,w25q64bv", "spi-flash";
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
It turns out that like Braswell, Intel FSP for IvyBridge requires SPI controller settings to be locked down, as the U-Boot ICH SPI driver fails with the following message on Cougar Canyon 2 board:
"ICH SPI: Opcode 9f not found"
Update the SPI node property to indicate this fact.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/cougarcanyon2.dts | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:31 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
It turns out that like Braswell, Intel FSP for IvyBridge requires SPI controller settings to be locked down, as the U-Boot ICH SPI driver fails with the following message on Cougar Canyon 2 board:
"ICH SPI: Opcode 9f not found"
Update the SPI node property to indicate this fact.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/cougarcanyon2.dts | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
As README.x86 already mentions, there are two SPI flashes mounted on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively. SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores the actual BIOS image which is U-Boot. Building a single image with both ME firmware and U-Boot does not make sense.
This also describes the exact flash location where the u-boot.rom should be programmed in the documentation.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
configs/cougarcanyon2_defconfig | 1 + doc/README.x86 | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 6c79b77..04ad232 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2" CONFIG_TARGET_COUGARCANYON2=y +# CONFIG_HAVE_INTEL_ME is not set # CONFIG_ENABLE_MRC_CACHE is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" diff --git a/doc/README.x86 b/doc/README.x86 index 04f0220..78664c3 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -256,7 +256,9 @@ the board manual. The SPI-0 flash should have flash descriptor plus ME firmware and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0 flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program this image to the SPI-0 flash according to the board manual just once and we are -all set. For programming U-Boot we just need to program SPI-1 flash. +all set. For programming U-Boot we just need to program SPI-1 flash. Since the +default u-boot.rom image for this board is set to 2MB, it should be programmed +to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
---
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
As README.x86 already mentions, there are two SPI flashes mounted on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively. SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores the actual BIOS image which is U-Boot. Building a single image with both ME firmware and U-Boot does not make sense.
This also describes the exact flash location where the u-boot.rom should be programmed in the documentation.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/cougarcanyon2_defconfig | 1 + doc/README.x86 | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:31 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
As README.x86 already mentions, there are two SPI flashes mounted on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively. SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores the actual BIOS image which is U-Boot. Building a single image with both ME firmware and U-Boot does not make sense.
This also describes the exact flash location where the u-boot.rom should be programmed in the documentation.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/cougarcanyon2_defconfig | 1 + doc/README.x86 | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
At present this 206ax cpu driver is only built when FSP is not used. This updates the Makefile to enable the build for both cases.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/ivybridge/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 27cfb26..716134e 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -8,7 +8,6 @@ else obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o obj-y += early_me.o obj-y += lpc.o -obj-y += model_206ax.o obj-y += northbridge.o ifndef CONFIG_SPL_BUILD obj-y += sata.o @@ -18,4 +17,5 @@ ifndef CONFIG_$(SPL_)X86_32BIT_INIT obj-y += sdram_nop.o endif endif +obj-y += model_206ax.o obj-y += bd82x6x.o
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
At present this 206ax cpu driver is only built when FSP is not used. This updates the Makefile to enable the build for both cases.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:31 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
At present this 206ax cpu driver is only built when FSP is not used. This updates the Makefile to enable the build for both cases.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/ivybridge/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
This is not used anywhere. Clean this up.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/intel_common/mrc.c | 5 ----- arch/x86/cpu/ivybridge/model_206ax.c | 15 --------------- scripts/config_whitelist.txt | 1 - 3 files changed, 21 deletions(-)
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index a5697a6..b35102a 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -242,11 +242,6 @@ static int sdram_initialise(struct udevice *dev, struct udevice *me_dev, version >> 24 , (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff);
-#if CONFIG_USBDEBUG - /* mrc.bin reconfigures USB, so reinit it to have debug */ - early_usbdebug_init(); -#endif - return 0; }
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index c5441aa..33e5c62 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -393,10 +393,6 @@ static void configure_mca(void) msr_write(IA32_MC0_STATUS + (i * 4), msr); }
-#if CONFIG_USBDEBUG -static unsigned ehci_debug_addr; -#endif - static int model_206ax_init(struct udevice *dev) { int ret; @@ -404,17 +400,6 @@ static int model_206ax_init(struct udevice *dev) /* Clear out pending MCEs */ configure_mca();
-#if CONFIG_USBDEBUG - /* Is this caution really needed? */ - if (!ehci_debug_addr) - ehci_debug_addr = get_ehci_debug(); - set_ehci_debug(0); -#endif - -#if CONFIG_USBDEBUG - set_ehci_debug(ehci_debug_addr); -#endif - /* Enable the local cpu apics */ enable_lapic_tpr();
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 705ed89..580304a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4596,7 +4596,6 @@ CONFIG_USART1 CONFIG_USART_BASE CONFIG_USART_ID CONFIG_USBBOOTCOMMAND -CONFIG_USBDEBUG CONFIG_USBD_CONFIGURATION_STR CONFIG_USBD_CTRL_INTERFACE_STR CONFIG_USBD_DATA_INTERFACE_STR
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
This is not used anywhere. Clean this up.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/intel_common/mrc.c | 5 ----- arch/x86/cpu/ivybridge/model_206ax.c | 15 --------------- scripts/config_whitelist.txt | 1 - 3 files changed, 21 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:32 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
This is not used anywhere. Clean this up.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/intel_common/mrc.c | 5 ----- arch/x86/cpu/ivybridge/model_206ax.c | 15 --------------- scripts/config_whitelist.txt | 1 - 3 files changed, 21 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
The 206ax cpu driver does not require pre-relocation flag to work.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/dts/chromebook_link.dts | 5 ----- 1 file changed, 5 deletions(-)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index fab919a..26b9f85 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -26,14 +26,12 @@ cpus { #address-cells = <1>; #size-cells = <0>; - u-boot,dm-pre-reloc;
cpu@0 { device_type = "cpu"; compatible = "intel,core-gen3"; reg = <0>; intel,apic-id = <0>; - u-boot,dm-pre-reloc; };
cpu@1 { @@ -41,7 +39,6 @@ compatible = "intel,core-gen3"; reg = <1>; intel,apic-id = <1>; - u-boot,dm-pre-reloc; };
cpu@2 { @@ -49,7 +46,6 @@ compatible = "intel,core-gen3"; reg = <2>; intel,apic-id = <2>; - u-boot,dm-pre-reloc; };
cpu@3 { @@ -57,7 +53,6 @@ compatible = "intel,core-gen3"; reg = <3>; intel,apic-id = <3>; - u-boot,dm-pre-reloc; };
};
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
The 206ax cpu driver does not require pre-relocation flag to work.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/chromebook_link.dts | 5 ----- 1 file changed, 5 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:33 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
The 206ax cpu driver does not require pre-relocation flag to work.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/chromebook_link.dts | 5 ----- 1 file changed, 5 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
This enables the 206ax cpu driver on Intel Cougar Canyon 2 board, so that SMP can be supported too.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/dts/cougarcanyon2.dts | 33 +++++++++++++++++++++++++++++++++ configs/cougarcanyon2_defconfig | 3 +++ 2 files changed, 36 insertions(+)
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index 8c71e98..946ba06 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -27,6 +27,39 @@ stdout-path = "/serial"; };
+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <3>; + intel,apic-id = <3>; + }; + }; + microcode { update@0 { #include "microcode/m12306a2_00000008.dtsi" diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 04ad232..98d9aa0 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -5,12 +5,14 @@ CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2" CONFIG_TARGET_COUGARCANYON2=y # CONFIG_HAVE_INTEL_ME is not set # CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_SMP=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y @@ -32,6 +34,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_CPU=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_USB_STORAGE=y
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
This enables the 206ax cpu driver on Intel Cougar Canyon 2 board, so that SMP can be supported too.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/cougarcanyon2.dts | 33 +++++++++++++++++++++++++++++++++ configs/cougarcanyon2_defconfig | 3 +++ 2 files changed, 36 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:32 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
This enables the 206ax cpu driver on Intel Cougar Canyon 2 board, so that SMP can be supported too.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/cougarcanyon2.dts | 33 +++++++++++++++++++++++++++++++++ configs/cougarcanyon2_defconfig | 3 +++ 2 files changed, 36 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
At present there are 3 irq router drivers. One is the common one and the other two are chipset specific for queensbay and quark. However these are really the same drivers as the core logic is the same. The two chipset specific drivers configure some registers that are outside the irq router block which should really be part of the chipset initialization.
Now we remove these specific drivers and make all x86 boards use the common one.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/irq.c | 7 +---- arch/x86/cpu/quark/Makefile | 2 +- arch/x86/cpu/quark/irq.c | 48 ------------------------------- arch/x86/cpu/quark/quark.c | 26 +++++++++++++++++ arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/irq.c | 64 ----------------------------------------- arch/x86/cpu/queensbay/tnc.c | 39 +++++++++++++++++++++++++ arch/x86/dts/crownbay.dts | 2 +- arch/x86/dts/galileo.dts | 2 +- arch/x86/include/asm/irq.h | 7 ----- 10 files changed, 70 insertions(+), 129 deletions(-) delete mode 100644 arch/x86/cpu/quark/irq.c delete mode 100644 arch/x86/cpu/queensbay/irq.c
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 305cd3d..a1d6a84 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -237,7 +237,7 @@ static void irq_enable_sci(struct udevice *dev) } }
-int irq_router_common_init(struct udevice *dev) +int irq_router_probe(struct udevice *dev) { int ret;
@@ -256,11 +256,6 @@ int irq_router_common_init(struct udevice *dev) return 0; }
-int irq_router_probe(struct udevice *dev) -{ - return irq_router_common_init(dev); -} - ulong write_pirq_routing_table(ulong addr) { if (!gd->arch.pirq_routing_table) diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile index 476e37c..7039f8b 100644 --- a/arch/x86/cpu/quark/Makefile +++ b/arch/x86/cpu/quark/Makefile @@ -2,6 +2,6 @@ # # Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
-obj-y += car.o dram.o irq.o msg_port.o quark.o +obj-y += car.o dram.o msg_port.o quark.o obj-y += mrc.o mrc_util.o hte.o smc.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o diff --git a/arch/x86/cpu/quark/irq.c b/arch/x86/cpu/quark/irq.c deleted file mode 100644 index 6928c33..0000000 --- a/arch/x86/cpu/quark/irq.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com - * Copyright (C) 2015 Google, Inc - */ - -#include <common.h> -#include <dm.h> -#include <asm/irq.h> -#include <asm/arch/device.h> -#include <asm/arch/quark.h> - -int quark_irq_router_probe(struct udevice *dev) -{ - struct quark_rcba *rcba; - u32 base; - - qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); - base &= ~MEM_BAR_EN; - rcba = (struct quark_rcba *)base; - - /* - * Route Quark PCI device interrupt pin to PIRQ - * - * Route device#23's INTA/B/C/D to PIRQA/B/C/D - * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H - */ - writew(PIRQC, &rcba->rmu_ir); - writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), - &rcba->d23_ir); - writew(PIRQD, &rcba->core_ir); - writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), - &rcba->d20d21_ir); - - return irq_router_common_init(dev); -} - -static const struct udevice_id quark_irq_router_ids[] = { - { .compatible = "intel,quark-irq-router" }, - { } -}; - -U_BOOT_DRIVER(quark_irq_router_drv) = { - .name = "quark_intel_irq", - .id = UCLASS_IRQ, - .of_match = quark_irq_router_ids, - .probe = quark_irq_router_probe, -}; diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 46141c4..4fd6864 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -7,6 +7,7 @@ #include <mmc.h> #include <asm/io.h> #include <asm/ioapic.h> +#include <asm/irq.h> #include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/pci.h> @@ -313,12 +314,37 @@ static void quark_usb_init(void) writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); }
+static void quark_irq_init(void) +{ + struct quark_rcba *rcba; + u32 base; + + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); + base &= ~MEM_BAR_EN; + rcba = (struct quark_rcba *)base; + + /* + * Route Quark PCI device interrupt pin to PIRQ + * + * Route device#23's INTA/B/C/D to PIRQA/B/C/D + * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H + */ + writew(PIRQC, &rcba->rmu_ir); + writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), + &rcba->d23_ir); + writew(PIRQD, &rcba->core_ir); + writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), + &rcba->d20d21_ir); +} + int arch_early_init_r(void) { quark_pcie_init();
quark_usb_init();
+ quark_irq_init(); + return 0; }
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index b535b2a..ac29613 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
-obj-y += fsp_configs.o irq.o +obj-y += fsp_configs.o obj-y += tnc.o diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c deleted file mode 100644 index 208cd61..0000000 --- a/arch/x86/cpu/queensbay/irq.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com - * Copyright (C) 2015 Google, Inc - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/pci.h> -#include <asm/arch/device.h> -#include <asm/arch/tnc.h> - -int queensbay_irq_router_probe(struct udevice *dev) -{ - struct tnc_rcba *rcba; - u32 base; - - dm_pci_read_config32(dev->parent, LPC_RCBA, &base); - base &= ~MEM_BAR_EN; - rcba = (struct tnc_rcba *)base; - - /* Make sure all internal PCI devices are using INTA */ - writel(INTA, &rcba->d02ip); - writel(INTA, &rcba->d03ip); - writel(INTA, &rcba->d27ip); - writel(INTA, &rcba->d31ip); - writel(INTA, &rcba->d23ip); - writel(INTA, &rcba->d24ip); - writel(INTA, &rcba->d25ip); - writel(INTA, &rcba->d26ip); - - /* - * Route TunnelCreek PCI device interrupt pin to PIRQ - * - * Since PCIe downstream ports received INTx are routed to PIRQ - * A/B/C/D directly and not configurable, we have to route PCIe - * root ports' INTx to PIRQ A/B/C/D as well. For other devices - * on TunneCreek, route them to PIRQ E/F/G/H. - */ - writew(PIRQE, &rcba->d02ir); - writew(PIRQF, &rcba->d03ir); - writew(PIRQG, &rcba->d27ir); - writew(PIRQH, &rcba->d31ir); - writew(PIRQA, &rcba->d23ir); - writew(PIRQB, &rcba->d24ir); - writew(PIRQC, &rcba->d25ir); - writew(PIRQD, &rcba->d26ir); - - return irq_router_common_init(dev); -} - -static const struct udevice_id queensbay_irq_router_ids[] = { - { .compatible = "intel,queensbay-irq-router" }, - { } -}; - -U_BOOT_DRIVER(queensbay_irq_router_drv) = { - .name = "queensbay_intel_irq", - .id = UCLASS_IRQ, - .of_match = queensbay_irq_router_ids, - .probe = queensbay_irq_router_probe, -}; diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 439c14d..76556fc 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -98,6 +98,43 @@ int arch_cpu_init(void) return x86_cpu_init_f(); }
+static void tnc_irq_init(void) +{ + struct tnc_rcba *rcba; + u32 base; + + pci_read_config32(TNC_LPC, LPC_RCBA, &base); + base &= ~MEM_BAR_EN; + rcba = (struct tnc_rcba *)base; + + /* Make sure all internal PCI devices are using INTA */ + writel(INTA, &rcba->d02ip); + writel(INTA, &rcba->d03ip); + writel(INTA, &rcba->d27ip); + writel(INTA, &rcba->d31ip); + writel(INTA, &rcba->d23ip); + writel(INTA, &rcba->d24ip); + writel(INTA, &rcba->d25ip); + writel(INTA, &rcba->d26ip); + + /* + * Route TunnelCreek PCI device interrupt pin to PIRQ + * + * Since PCIe downstream ports received INTx are routed to PIRQ + * A/B/C/D directly and not configurable, we have to route PCIe + * root ports' INTx to PIRQ A/B/C/D as well. For other devices + * on TunneCreek, route them to PIRQ E/F/G/H. + */ + writew(PIRQE, &rcba->d02ir); + writew(PIRQF, &rcba->d03ir); + writew(PIRQG, &rcba->d27ir); + writew(PIRQH, &rcba->d31ir); + writew(PIRQA, &rcba->d23ir); + writew(PIRQB, &rcba->d24ir); + writew(PIRQC, &rcba->d25ir); + writew(PIRQD, &rcba->d26ir); +} + int arch_early_init_r(void) { int ret = 0; @@ -106,5 +143,7 @@ int arch_early_init_r(void) ret = disable_igd(); #endif
+ tnc_irq_init(); + return ret; } diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 4fe076a..d8faa9d 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -151,7 +151,7 @@ #size-cells = <1>;
irq-router { - compatible = "intel,queensbay-irq-router"; + compatible = "intel,irq-router"; intel,pirq-config = "pci"; intel,actl-addr = <0x58>; intel,pirq-link = <0x60 8>; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index d86fdc0..3454abd 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -97,7 +97,7 @@ #size-cells = <1>;
irq-router { - compatible = "intel,quark-irq-router"; + compatible = "intel,irq-router"; intel,pirq-config = "pci"; intel,actl-addr = <0x58>; intel,pirq-link = <0x60 8>; diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 169b281..ad95bb4 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -58,11 +58,4 @@ struct pirq_routing {
#define PIRQ_BITMAP 0xdef8
-/** - * irq_router_common_init() - Perform common x86 interrupt init - * - * This creates the PIRQ routing table and routes the IRQs - */ -int irq_router_common_init(struct udevice *dev); - #endif /* _ARCH_IRQ_H_ */
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
At present there are 3 irq router drivers. One is the common one and the other two are chipset specific for queensbay and quark. However these are really the same drivers as the core logic is the same. The two chipset specific drivers configure some registers that are outside the irq router block which should really be part of the chipset initialization.
Now we remove these specific drivers and make all x86 boards use the common one.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/irq.c | 7 +---- arch/x86/cpu/quark/Makefile | 2 +- arch/x86/cpu/quark/irq.c | 48 ------------------------------- arch/x86/cpu/quark/quark.c | 26 +++++++++++++++++ arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/irq.c | 64 ----------------------------------------- arch/x86/cpu/queensbay/tnc.c | 39 +++++++++++++++++++++++++ arch/x86/dts/crownbay.dts | 2 +- arch/x86/dts/galileo.dts | 2 +- arch/x86/include/asm/irq.h | 7 ----- 10 files changed, 70 insertions(+), 129 deletions(-) delete mode 100644 arch/x86/cpu/quark/irq.c delete mode 100644 arch/x86/cpu/queensbay/irq.c
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:33 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
At present there are 3 irq router drivers. One is the common one and the other two are chipset specific for queensbay and quark. However these are really the same drivers as the core logic is the same. The two chipset specific drivers configure some registers that are outside the irq router block which should really be part of the chipset initialization.
Now we remove these specific drivers and make all x86 boards use the common one.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/irq.c | 7 +---- arch/x86/cpu/quark/Makefile | 2 +- arch/x86/cpu/quark/irq.c | 48 ------------------------------- arch/x86/cpu/quark/quark.c | 26 +++++++++++++++++ arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/irq.c | 64 ----------------------------------------- arch/x86/cpu/queensbay/tnc.c | 39 +++++++++++++++++++++++++ arch/x86/dts/crownbay.dts | 2 +- arch/x86/dts/galileo.dts | 2 +- arch/x86/include/asm/irq.h | 7 ----- 10 files changed, 70 insertions(+), 129 deletions(-) delete mode 100644 arch/x86/cpu/quark/irq.c delete mode 100644 arch/x86/cpu/queensbay/irq.c
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
LINK_V2N and LINK_N2V are currently defines, so they cannot handle complex logics. Change to inline functions for future extension.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/irq.c | 18 +++++++++++------- arch/x86/include/asm/irq.h | 26 +++++++++++++++++++++++--- 2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index a1d6a84..ec556d3 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -23,9 +23,11 @@ bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) int base = priv->link_base;
if (priv->config == PIRQ_VIA_PCI) - dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq); + dm_pci_read_config8(dev->parent, + pirq_linkno_to_reg(link, base), &pirq); else - pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base)); + pirq = readb((uintptr_t)priv->ibase + + pirq_linkno_to_reg(link, base));
pirq &= 0xf;
@@ -40,7 +42,7 @@ int pirq_translate_link(struct udevice *dev, int link) { struct irq_router *priv = dev_get_priv(dev);
- return LINK_V2N(link, priv->link_base); + return pirq_reg_to_linkno(link, priv->link_base); }
void pirq_assign_irq(struct udevice *dev, int link, u8 irq) @@ -53,9 +55,11 @@ void pirq_assign_irq(struct udevice *dev, int link, u8 irq) return;
if (priv->config == PIRQ_VIA_PCI) - dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq); + dm_pci_write_config8(dev->parent, + pirq_linkno_to_reg(link, base), irq); else - writeb(irq, (uintptr_t)priv->ibase + LINK_N2V(link, base)); + writeb(irq, (uintptr_t)priv->ibase + + pirq_linkno_to_reg(link, base)); }
static struct irq_info *check_dup_entry(struct irq_info *slot_base, @@ -78,7 +82,7 @@ static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot, { slot->bus = bus; slot->devfn = (device << 3) | 0; - slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base); + slot->irq[pin - 1].link = pirq_linkno_to_reg(pirq, priv->link_base); slot->irq[pin - 1].bitmap = priv->irq_mask; }
@@ -199,7 +203,7 @@ static int create_pirq_routing_table(struct udevice *dev) * routing information in the device tree. */ if (slot->irq[pr.pin - 1].link != - LINK_N2V(pr.pirq, priv->link_base)) + pirq_linkno_to_reg(pr.pirq, priv->link_base)) debug("WARNING: Inconsistent PIRQ routing information\n"); continue; } diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index ad95bb4..bfa58cf 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -52,9 +52,29 @@ struct pirq_routing { int pirq; };
-/* PIRQ link number and value conversion */ -#define LINK_V2N(link, base) (link - base) -#define LINK_N2V(link, base) (link + base) +/** + * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number + * + * @reg: PIRQ routing register offset from the base address + * @base: PIRQ routing register block base address + * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) + */ +static inline int pirq_reg_to_linkno(int reg, int base) +{ + return reg - base; +} + +/** + * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset + * + * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) + * @base: PIRQ routing register block base address + * @return: PIRQ routing register offset from the base address + */ +static inline int pirq_linkno_to_reg(int linkno, int base) +{ + return linkno + base; +}
#define PIRQ_BITMAP 0xdef8
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
LINK_V2N and LINK_N2V are currently defines, so they cannot handle complex logics. Change to inline functions for future extension.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/irq.c | 18 +++++++++++------- arch/x86/include/asm/irq.h | 26 +++++++++++++++++++++++--- 2 files changed, 34 insertions(+), 10 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Jun 8, 2018 at 4:33 AM, Simon Glass sjg@chromium.org wrote:
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
LINK_V2N and LINK_N2V are currently defines, so they cannot handle complex logics. Change to inline functions for future extension.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/irq.c | 18 +++++++++++------- arch/x86/include/asm/irq.h | 26 +++++++++++++++++++++++--- 2 files changed, 34 insertions(+), 10 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume consecutive PIRQ routing control registers. But this is not always the case on some platforms. Introduce a Kconfig option for this and adjust the irq router driver to be able to use platform-specific converting logic.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/Kconfig | 9 +++++++++ arch/x86/cpu/irq.c | 3 +++ arch/x86/include/asm/irq.h | 2 ++ 3 files changed, 14 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5c23b2c..c145799 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -686,6 +686,15 @@ config STACK_SIZE Estimated U-Boot's runtime stack size that needs to be reserved during an ACPI S3 resume.
+config DISCRETE_PIRQ_ROUT + bool + help + This variable indicates that the chipset's PIRQ routing control + registers are not consecutive. If this is the case, the platform + codes must provide two inline functions for the IRQ router driver + to convert PIRQ routing control register offset to link number. + See pirq_reg_to_linkno() and pirq_linkno_to_reg(). + config MAX_PIRQ_LINKS int default 8 diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index ec556d3..e33be61 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -13,6 +13,9 @@ #include <asm/pci.h> #include <asm/pirq_routing.h> #include <asm/tables.h> +#ifdef CONFIG_DISCRETE_PIRQ_ROUT +#include <asm/arch/irq.h> +#endif
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index bfa58cf..468a29f 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -52,6 +52,7 @@ struct pirq_routing { int pirq; };
+#ifndef CONFIG_DISCRETE_PIRQ_ROUT /** * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number * @@ -75,6 +76,7 @@ static inline int pirq_linkno_to_reg(int linkno, int base) { return linkno + base; } +#endif
#define PIRQ_BITMAP 0xdef8
Hi Bin,
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume consecutive PIRQ routing control registers. But this is not always the case on some platforms. Introduce a Kconfig option for this and adjust the irq router driver to be able to use platform-specific converting logic.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/Kconfig | 9 +++++++++ arch/x86/cpu/irq.c | 3 +++ arch/x86/include/asm/irq.h | 2 ++ 3 files changed, 14 insertions(+)
Wouldn't it make sense to put the mapping in the device tree?
Regards, Simon
This adds pirq_reg_to_linkno() and pirq_linkno_to_reg() for IvyBridge.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/ivybridge/Kconfig | 4 +++ arch/x86/include/asm/arch-ivybridge/irq.h | 45 +++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 arch/x86/include/asm/arch-ivybridge/irq.h
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index eec92df..e31c33c 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -58,6 +58,10 @@ config ENABLE_VMX will be unable to support virtualisation, or it will run very slowly.
+config DISCRETE_PIRQ_ROUT + bool + default y + config FSP_ADDR hex default 0xfff80000 diff --git a/arch/x86/include/asm/arch-ivybridge/irq.h b/arch/x86/include/asm/arch-ivybridge/irq.h new file mode 100644 index 0000000..d8ddf55 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/irq.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com + * + * IvyBridge specific IRQ converting logic + */ + +#ifndef _IVYBRIDGE_IRQ_H_ +#define _IVYBRIDGE_IRQ_H_ + +/** + * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number + * + * @reg: PIRQ routing register offset from the base address + * @base: PIRQ routing register block base address + * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) + */ +static inline int pirq_reg_to_linkno(int reg, int base) +{ + int linkno = reg - base; + + if (linkno > PIRQH) + linkno -= 4; + + return linkno; +} + +/** + * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset + * + * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) + * @base: PIRQ routing register block base address + * @return: PIRQ routing register offset from the base address + */ +static inline int pirq_linkno_to_reg(int linkno, int base) +{ + int reg = linkno + base; + + if (linkno > PIRQD) + reg += 4; + + return reg; +} + +#endif /* _IVYBRIDGE_IRQ_H_ */
Add Panther Point chipset interrupt pin/PIRQ information, and enable the generation of PIRQ routing table and MP table.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
arch/x86/dts/cougarcanyon2.dts | 36 ++++++++++++++++++++++++++++++++++++ configs/cougarcanyon2_defconfig | 2 ++ 2 files changed, 38 insertions(+)
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index 946ba06..65c8ffd 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/interrupt-router/intel-irq.h> + /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "keyboard.dtsi" @@ -99,6 +101,40 @@ #address-cells = <1>; #size-cells = <1>;
+ irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,actl-8bit; + intel,actl-addr = <0x44>; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xcee0>; + intel,pirq-routing = < + /* Panther Point PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 22, 1) INTB PIRQB + PCI_BDF(0, 22, 2) INTC PIRQC + PCI_BDF(0, 22, 3) INTD PIRQD + PCI_BDF(0, 25, 0) INTA PIRQA + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTB PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 28, 4) INTA PIRQA + PCI_BDF(0, 28, 5) INTB PIRQB + PCI_BDF(0, 28, 6) INTC PIRQC + PCI_BDF(0, 28, 7) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 31, 2) INTB PIRQB + PCI_BDF(0, 31, 3) INTC PIRQC + PCI_BDF(0, 31, 5) INTB PIRQB + PCI_BDF(0, 31, 6) INTC PIRQC + >; + }; + spi0: spi { #address-cells = <1>; #size-cells = <0>; diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 98d9aa0..eeee252 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -6,6 +6,8 @@ CONFIG_TARGET_COUGARCANYON2=y # CONFIG_HAVE_INTEL_ME is not set # CONFIG_ENABLE_MRC_CACHE is not set CONFIG_SMP=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y
On 3 June 2018 at 18:04, Bin Meng bmeng.cn@gmail.com wrote:
Add Panther Point chipset interrupt pin/PIRQ information, and enable the generation of PIRQ routing table and MP table.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/cougarcanyon2.dts | 36 ++++++++++++++++++++++++++++++++++++ configs/cougarcanyon2_defconfig | 2 ++ 2 files changed, 38 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
participants (2)
-
Bin Meng -
Simon Glass