[PATCH v5 00/11] Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622>
From: Frank Wunderlich frank-w@public-files.de
This series adds Mediatek AHCI driver, makes neccessary phy modifications creates new dts for bananapi-r64 (because it's a bit different to rfb) and adds all DTS nodes to get SATA and USB working on mt7622 and mt7623
they are based on top of this:
Add PCIe and its clock support for mt7622 https://patchwork.ozlabs.org/project/uboot/list/?series=194888
and to get USB working (no hard depency, ports get enumerated without it): usb: xhci: add a member hci_version in xhci_ctrl struct https://patchwork.ozlabs.org/project/uboot/list/?series=195331
v4->v5: - rebased on master because old series got merged v3->v4: - fix wrong squashing of pciesys-comment v2->v3: - fixed code style suggested by sam v1->v2: - made register of phy optional for tphy v1 and remove it in dts
Frank Wunderlich (8): phy: mtk-tphy: make shared reg optional for v1 reset: add basic reset controller for pciesys ahci: mediatek: add ahci driver clk: mt7622: add needed clocks for ssusb-node arm: dts: add dts for Bananapi-R64 arm: dts: mt7622: add sata- and asm_sel nodes arm: dts: mt7622: add USB nodes arm: dts: mt7623: add USB nodes
arch/arm/dts/Makefile | 1 + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 223 +++++++++++++++++++++++ arch/arm/dts/mt7622-rfb.dts | 8 + arch/arm/dts/mt7622.dtsi | 57 +++++- arch/arm/dts/mt7623.dtsi | 46 +++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 ++ drivers/ata/mtk_ahci.c | 6 +- drivers/clk/mediatek/clk-mt7622.c | 43 ++++- drivers/phy/phy-mtk-tphy.c | 5 +- 9 files changed, 396 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts
From: Frank Wunderlich frank-w@public-files.de
make the shared reg optional when version is v1 for sata
Suggested-by: Chunfeng Yun chunfeng.yun@mediatek.com Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- drivers/phy/phy-mtk-tphy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 326227a30d..3d7b9cd2b1 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -698,11 +698,10 @@ static int mtk_tphy_probe(struct udevice *dev) tphy->dev = dev; tphy->version = dev_get_driver_data(dev);
- /* v1 has shared banks */ + /* v1 has shared banks for usb/pcie mode, */ + /* but not for sata mode */ if (tphy->version == MTK_TPHY_V1) { tphy->sif_base = dev_read_addr_ptr(dev); - if (!tphy->sif_base) - return -ENOENT; }
dev_for_each_subnode(subnode, dev) {
From: Frank Wunderlich frank-w@public-files.de
bind reset controller to pciesys
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- drivers/clk/mediatek/clk-mt7622.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index d53ed69189..a1a35f72a3 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -599,7 +599,6 @@ static int mt7622_pciesys_bind(struct udevice *dev) int ret = 0;
if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { -// PCIESYS uses in linux also 0x34 = ETHSYS reset controller ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); if (ret) debug("Warning: failed to bind reset controller\n");
From: Frank Wunderlich frank-w@public-files.de
add AHCI driver ported from linux
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/driv...
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- drivers/ata/mtk_ahci.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c index 8e09c5f9e6..4ad260a5bb 100644 --- a/drivers/ata/mtk_ahci.c +++ b/drivers/ata/mtk_ahci.c @@ -2,12 +2,10 @@ /* * MTK SATA platform driver * - * (C) Copyright 2020 - * Mediatek + * Copyright (C) 2020 MediaTek Inc. * - * Author: Frank Wunderlich frank-w@public-files.de - * based on https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/driv... * Author: Ryder Lee ryder.lee@mediatek.com + * Author: Frank Wunderlich frank-w@public-files.de */
#include <common.h>
mhm, maybe i should change commit-subject/message because there are only changes suggested from sam...same for part2
regards Frank
Gesendet: Donnerstag, 20. August 2020 um 15:40 Uhr Von: "Frank Wunderlich" linux@fw-web.de Betreff: [PATCH v5 3/8] ahci: mediatek: add ahci driver
add AHCI driver ported from linux diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c index 8e09c5f9e6..4ad260a5bb 100644 --- a/drivers/ata/mtk_ahci.c +++ b/drivers/ata/mtk_ahci.c @@ -2,12 +2,10 @@ /*
- MTK SATA platform driver
- (C) Copyright 2020
Mediatek
- Copyright (C) 2020 MediaTek Inc.
- Author: Frank Wunderlich frank-w@public-files.de
- based on https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/driv...
- Author: Ryder Lee ryder.lee@mediatek.com
*/
- Author: Frank Wunderlich frank-w@public-files.de
From: Frank Wunderlich frank-w@public-files.de
MT7622 needs additional clock definitions to work properly
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- drivers/clk/mediatek/clk-mt7622.c | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index a1a35f72a3..0246149107 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = { .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ }
+static const struct mtk_gate_regs ssusb_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_SSUSB(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &ssusb_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2), GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), @@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), };
+static const struct mtk_gate ssusb_cgs[] = { + GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0), + GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1), + GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5), + GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6), + GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7), + GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8), +}; + static const struct mtk_clk_tree mt7622_clk_tree = { .xtal_rate = 25 * MHZ, .xtal2_rate = 25 * MHZ, @@ -630,6 +653,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs); }
+static int mt7622_ssusbsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs); +} + static const struct udevice_id mt7622_apmixed_compat[] = { { .compatible = "mediatek,mt7622-apmixedsys" }, { } @@ -670,6 +698,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = { { } };
+static const struct udevice_id mt7622_ssusbsys_compat[] = { + { .compatible = "mediatek,mt7622-ssusbsys" }, + { } +}; + U_BOOT_DRIVER(mtk_mcucfg) = { .name = "mt7622-mcucfg", .id = UCLASS_SYSCON, @@ -746,3 +779,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = { .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; + +U_BOOT_DRIVER(mtk_clk_ssusbsys) = { + .name = "mt7622-clock-ssusbsys", + .id = UCLASS_CLK, + .of_match = mt7622_ssusbsys_compat, + .probe = mt7622_ssusbsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +};
From: Frank Wunderlich frank-w@public-files.de
add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support
Signed-off-by: Frank Wunderlich frank-w@public-files.de --- v1->v2: - changed name --- arch/arm/dts/Makefile | 1 + arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 206 +++++++++++++++++++++++ 2 files changed, 207 insertions(+) create mode 100644 arch/arm/dts/mt7622-bananapi-bpi-r64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b2b5360f6d..68a29faa6a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -961,6 +961,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ + mt7622-bananapi-bpi-r64.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bpi-r64.dtb \ mt7623n-bananapi-bpi-r2.dtb \ diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts new file mode 100644 index 0000000000..768f15bc2c --- /dev/null +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Sam Shih sam.shih@mediatek.com + */ + +/dts-v1/; +#include "mt7622.dtsi" +#include "mt7622-u-boot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7622-bpi-r64"; + compatible = "mediatek,mt7622", "mediatek,mt7622-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + aliases { + spi0 = &snfi; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + + +&pinctrl { + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + snor_pins: snor-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0 { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + pwm_pins: pwm1 { + mux { + function = "pwm"; + groups = "pwm_ch1_0" ; + }; + }; + + watchdog_pins: watchdog-default { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "emmc"; + groups = "emmc"; + }; + + /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", + * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, + * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively + */ + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + bias-pull-down; + }; + + }; + + mmc1_pins_default: mmc1default { + mux { + function = "sd"; + groups = "sd_0"; + }; + /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", + * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, + * DAT2, DAT3, CMD, CLK for SD respectively. + */ + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + drive-strength = <8>; + bias-pull-up; + }; + conf-clk { + pins = "I2S3_OUT"; + drive-strength = <12>; + bias-pull-down; + }; + conf-cd { + pins = "TXD3"; + bias-pull-up; + }; + + }; +}; + +&snfi { + pinctrl-names = "default", "snfi"; + pinctrl-0 = <&snor_pins>; + pinctrl-1 = <&snfi_pins>; + status = "okay"; + + spi-flash@0{ + compatible = "jedec,spi-nor"; + reg = <0>; + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + r_smpl = <1>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +};
Here i change to rename the now existing bpi-r64.dts to bananapi-bpi-r64 to follow naming sheme like bpi-2 instead of creating a new one regards Frank
From: Frank Wunderlich frank-w@public-files.de
asm_sel is for switching between sata and pcie mode on r64 there is GPIO90 connected to ASM1480 which switches RX/TX pairs to PCIe/SATA connector output-low means sata-controller is active
Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 9 +++++++++ arch/arm/dts/mt7622.dtsi | 1 - 2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts index 768f15bc2c..c36ec8f8d0 100644 --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts @@ -204,3 +204,12 @@ full-duplex; }; }; + +&gpio { + /*gpio 90 for setting mode to sata*/ + asm_sel { + gpio-hog; + gpios = <90 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index c43ad65702..6b4260407e 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -287,7 +287,6 @@
sata_phy: sata-phy@1a243000 { compatible = "mediatek,generic-tphy-v1"; - reg = <0x1a243000 0x0100>; #address-cells = <1>; #size-cells = <1>; ranges;
From: Frank Wunderlich frank-w@public-files.de
Add DTS nodes for MT7622/BPI-R64
Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- v1->v2: - remove clk25m as it's not needed --- arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 8 ++++ arch/arm/dts/mt7622-rfb.dts | 8 ++++ arch/arm/dts/mt7622.dtsi | 56 ++++++++++++++++++++++++ 3 files changed, 72 insertions(+)
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts index c36ec8f8d0..7cd581cf7d 100644 --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts @@ -213,3 +213,11 @@ output-low; }; }; + +&ssusb { + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts index 317fc78abd..ef7d0f0270 100644 --- a/arch/arm/dts/mt7622-rfb.dts +++ b/arch/arm/dts/mt7622-rfb.dts @@ -222,3 +222,11 @@ full-duplex; }; }; + +&ssusb { + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 6b4260407e..5a4dab185f 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -192,6 +192,14 @@ status = "disabled"; };
+ ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", + "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pciesys: pciesys@1a100800 { compatible = "mediatek,mt7622-pciesys", "syscon"; reg = <0x1a100800 0x1000>; @@ -301,6 +309,54 @@ }; };
+ ssusb: usb@1a0c0000 { + compatible = "mediatek,mt7622-xhci", + "mediatek,mtk-xhci"; + reg = <0x1a0c0000 0x01000>, + <0x1a0c4700 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>; + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, + <&ssusbsys CLK_SSUSB_REF_EN>, + <&ssusbsys CLK_SSUSB_MCU_EN>, + <&ssusbsys CLK_SSUSB_DMA_EN>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + status = "disabled"; + }; + + u3phy: usb-phy@1a0c4000 { + compatible = "mediatek,mt7622-u3phy", + "mediatek,generic-tphy-v1"; + reg = <0x1a0c4000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a0c4800 { + reg = <0x1a0c4800 0x0100>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; + clock-names = "ref"; + }; + + u3port0: usb-phy@1a0c4900 { + reg = <0x1a0c4900 0x0700>; + #phy-cells = <1>; + }; + + u2port1: usb-phy@1a0c5000 { + reg = <0x1a0c5000 0x0100>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; + clock-names = "ref"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0x1b000000 0x1000>;
From: Frank Wunderlich frank-w@public-files.de
This adds USB nodes for MT7623/BPI-R2
Signed-off-by: Frank Wunderlich frank-w@public-files.de Reviewed-by: Chunfeng Yun chunfeng.yun@mediatek.com --- arch/arm/dts/mt7623.dtsi | 46 ++++++++++++++++++++++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 16 +++++++++ 2 files changed, 62 insertions(+)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 0452889ef8..b5a802552b 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -352,6 +352,52 @@ }; };
+ usb1: usb@1a1c0000 { + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci"; + reg = <0x1a1c0000 0x1000>, <0x1a1c4700 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + u3phy1: usb-phy@1a1c4000 { + compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1"; + + reg = <0x1a1c4000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a1c4800 { + reg = <0x1a1c4800 0x0100>; + #phy-cells = <1>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + }; + + u3port0: usb-phy@1a1c4900 { + reg = <0x1a1c4900 0x0700>; + #phy-cells = <1>; + clocks = <&clk26m>; + clock-names = "ref"; + }; + }; + + usb2: usb@1a240000 { + compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci"; + reg = <0x1a240000 0x1000>, <0x1a244700 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "sys_ck", "ref_ck"; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + status = "disabled"; + }; + u3phy2: usb-phy@1a244000 { compatible = "mediatek,generic-tphy-v1"; reg = <0x1a244000 0x0700>; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts index bcedcf20f1..ef07369627 100644 --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -248,3 +248,19 @@ pinctrl-0 = <&uart2_pins_a>; status = "okay"; }; + +&usb1 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +};
participants (2)
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Frank Wunderlich -
Frank Wunderlich