Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.

Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/include/asm/arch-exynos/system.h | 1 + board/samsung/common/board.c | 15 +++++++++++++++ drivers/video/exynos_fb.c | 20 ++++++-------------- include/configs/exynos5250-dt.h | 2 -- 4 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 7e2057c..4968d3d 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -39,5 +39,6 @@ struct exynos5_sysreg {

void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); +int exynos_lcd_early_init(const void *blob);

#endif /* _EXYNOS4_SYSTEM_H */ diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index cc83724..2536457 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -20,6 +20,7 @@ #include <asm/arch/mmc.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> +#include <asm/arch/system.h> #include <power/pmic.h> #include <asm/arch/sromc.h> #include <power/max77686_pmic.h> @@ -135,6 +136,20 @@ int board_early_init_f(void) #ifdef CONFIG_SYS_I2C_INIT_BOARD board_i2c_init(gd->fdt_blob); #endif + +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB) +/* + * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs + * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve + * FB memory at a very early stage. So, we need to fill panel_info.vl_col, + * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called. + */ + err = exynos_lcd_early_init(gd->fdt_blob); + if (err) { + debug("LCD early init failed\n"); + return err; + } +#endif return err; } #endif diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 7d4c6e0..69899a1 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -27,17 +27,12 @@ DECLARE_GLOBAL_DATA_PTR;

static unsigned int panel_width, panel_height;

-/* - * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs - * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve - * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt() - * is called. So, we are forced to statically assign it. - */ #ifdef CONFIG_OF_CONTROL vidinfo_t panel_info = { - .vl_col = LCD_XRES, - .vl_row = LCD_YRES, - .vl_bpix = LCD_COLOR16, + /* Insert a value here so that we don't end up in the BSS + * Reference: drivers/video/tegra.c + */ + .vl_col = -1, }; #endif

@@ -159,7 +154,7 @@ static void lcd_panel_on(vidinfo_t *vid) }

#ifdef CONFIG_OF_CONTROL -int exynos_fimd_parse_dt(const void *blob) +int exynos_lcd_early_init(const void *blob) { unsigned int node; node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); @@ -303,10 +298,7 @@ void lcd_ctrl_init(void *lcdbase) set_system_display_ctrl(); set_lcd_clk();

-#ifdef CONFIG_OF_CONTROL - if (exynos_fimd_parse_dt(gd->fdt_blob)) - debug("Can't get proper panel info\n"); -#else +#ifndef CONFIG_OF_CONTROL /* initialize parameters which is specific to panel. */ init_panel_info(&panel_info); #endif diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 689919d..508962c 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -50,8 +50,6 @@ #ifdef CONFIG_LCD #define CONFIG_EXYNOS_FB #define CONFIG_EXYNOS_DP -#define LCD_XRES 2560 -#define LCD_YRES 1600 #define LCD_BPP LCD_COLOR16 #endif #endif /* __CONFIG_5250_H */

RPLL is needed to drive the LCD panel on Exynos5420 based boards.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/cpu/armv7/exynos/clock_init.h | 3 +++ arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +++++++++++++ 2 files changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index a875d0b..fce502f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -75,6 +75,9 @@ struct mem_timings { unsigned spll_mdiv; unsigned spll_pdiv; unsigned spll_sdiv; + unsigned rpll_mdiv; + unsigned rpll_pdiv; + unsigned rpll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];

diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index e7f1496..c91c4a1 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, + /* RPLL @266MHz */ + .rpll_mdiv = 0x10A, + .rpll_pdiv = 0x3, + .rpll_sdiv = 0x3,

.direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, @@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void) writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock); + writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);

setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);

@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void) while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) ;

+ /* Set RPLL */ + writel(RPLL_CON2_VAL, &clk->rpll_con2); + writel(RPLL_CON1_VAL, &clk->rpll_con1); + val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv); + writel(val, &clk->rpll_con0); + while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0) + ; + writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 74 +++++++++++++++++++++++++++++-- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/include/asm/arch-exynos/clk.h | 1 + 3 files changed, 73 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index b52e61a..60ca7ea 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) * VPLL_CON: MIDV [24:16] * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) + if (pllreg == APLL || pllreg == MPLL || + pllreg == BPLL || pllreg == SPLL) mask = 0x3ff; else mask = 0x1ff; @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg) r = readl(&clk->rpll_con0); k = readl(&clk->rpll_con1); break; + case SPLL: + r = readl(&clk->spll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -1038,6 +1042,40 @@ static unsigned long exynos5_get_lcd_clk(void) return pclk; }

+static unsigned long exynos5420_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + sel = readl(&clk->src_disp10); + sel &= (1 << 4); + + if (sel) + sclk = get_pll_clk(SPLL); + else + sclk = get_pll_clk(RPLL); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10); + ratio = ratio & 0xf; + + pclk = sclk / (ratio + 1); + + return pclk; +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1162,6 +1200,33 @@ void exynos5_set_lcd_clk(void) writel(cfg, &clk->div_disp1_0); }

+void exynos5420_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + cfg = readl(&clk->src_disp10); + cfg &= ~(0x1 << 4); + cfg |= (0 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + cfg = readl(&clk->div_disp10); + cfg &= ~(0xf << 0); + cfg |= (0 << 0); + writel(cfg, &clk->div_disp10); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1657,14 +1722,17 @@ unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); - else - return exynos5_get_lcd_clk(); + else if (proid_is_exynos5420()) + return exynos5420_get_lcd_clk(); + return exynos5_get_lcd_clk(); }

void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk(); + else if (proid_is_exynos5420()) + exynos5420_set_lcd_clk(); else exynos5_set_lcd_clk(); } diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 8e05a00..70b1c04 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -780,7 +780,7 @@ #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP5_VAL 0x11111101 #define CLK_SRC_TOP6_VAL 0x11110111 #define CLK_SRC_TOP7_VAL 0x00022200

diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index cdeef32..98faae7 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -15,6 +15,7 @@ #define VPLL 4 #define BPLL 5 #define RPLL 6 +#define SPLL 7

enum pll_src_bit { EXYNOS_SRC_MPLL = 6,

On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default. We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/dts/exynos5420.dtsi | 7 +++++++ doc/device-tree-bindings/video/exynos-fb.txt | 4 ++++ drivers/video/exynos_fimd.c | 24 ++++++++++++++++++++++++ 3 files changed, 35 insertions(+)

diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi index ca6c605..7443953 100644 --- a/arch/arm/dts/exynos5420.dtsi +++ b/arch/arm/dts/exynos5420.dtsi @@ -71,4 +71,11 @@ reg = <0x12E20000 0x100>; interrupts = <0 203 0>; }; + + fimd@14400000 { + /* sysmmu is not used in U-Boot */ + samsung,disable-sysmmu; + samsung,sysmmu-fimdm0 = <0x14640000>; + samsung,sysmmu-fimdm1 = <0x14680000>; + }; }; diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index bb7441c..9ba2c47 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -55,6 +55,10 @@ Board(panel specific): samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL) samsung,sclk-div: parent_clock/source_clock ratio samsung,dual-lcd-enabled: 1 if you support two LCD, else 0 + samsung,disable-sysmmu: present if you want to disable the sysmmu + (needed for Exynos5420 and newer versions) + samsung,sysmmu-fimdm0: Address of sysmmufimdm0 MMU_CTRL + samsung,sysmmu-fimdm1: Address of sysmmufimdm1 MMU_CTRL

Example: SOC specific part: diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index f962c4f..bffc8fa 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -257,6 +257,7 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) unsigned int offset; #ifdef CONFIG_OF_CONTROL unsigned int node; + u32 *sysmmufimdm0, *sysmmufimdm1;

node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); @@ -267,6 +268,29 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) node, "reg"); if (fimd_ctrl == NULL) debug("Can't get the FIMD base address\n"); + + if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu")) { + /* + * The reset value for FIMD SYSMMU register MMU_CTRL is 3 + * on Exynos5420 and newer versions. + * This means FIMD SYSMMU is on by default on Exynos5420 + * and newer versions. + * Since in u-boot we don't use SYSMMU, we should disable + * those FIMD SYSMMU. + */ + sysmmufimdm0 = (u32 *)fdtdec_get_int(gd->fdt_blob, node, + "samsung,sysmmu-fimdm0", 0); + if (!sysmmufimdm0) + debug("Can't get sysmmufimdm0"); + + sysmmufimdm1 = (u32 *)fdtdec_get_int(gd->fdt_blob, node, + "samsung,sysmmu-fimdm1", 0); + if (!sysmmufimdm1) + debug("Can't get sysmmufimdm1"); + + writel(0x0, sysmmufimdm0); + writel(0x0, sysmmufimdm1); + } #else fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd(); #endif

Add callbacks to set up DP-HPD, backlight and LCD power on SMDK5420.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- board/samsung/smdk5420/smdk5420.c | 102 +++++++------------------------------- 1 file changed, 17 insertions(+), 85 deletions(-)

diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index d85b953..75b22cc 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -43,98 +43,30 @@ int exynos_init(void) }

#ifdef CONFIG_LCD -void cfg_lcd_gpio(void) +void exynos_cfg_lcd_gpio(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - - /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); - - /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); + struct exynos5420_gpio_part2 *gpio2 = + (struct exynos5420_gpio_part2 *)samsung_get_base_gpio_part2();

/* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio2->x0, 7, GPIO_FUNC(0x3)); }

-vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 2560, - .vl_row = 1600, - .vl_width = 2560, - .vl_height = 1600, - .vl_clkp = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */ - - /* wDP panel timing infomation */ - .vl_hspw = 32, - .vl_hbpd = 80, - .vl_hfpd = 48, - - .vl_vspw = 6, - .vl_vbpd = 37, - .vl_vfpd = 3, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .cfg_gpio = cfg_lcd_gpio, - .backlight_on = NULL, - .lcd_power_on = NULL, - .reset_lcd = NULL, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .dp_enabled = 1, -}; - -static struct edp_device_info edp_info = { - .disp_info = { - .h_res = 2560, - .h_sync_width = 32, - .h_back_porch = 80, - .h_front_porch = 48, - .v_res = 1600, - .v_sync_width = 6, - .v_back_porch = 37, - .v_front_porch = 3, - .v_sync_rate = 60, - }, - .lt_info = { - .lt_status = DP_LT_NONE, - }, - .video_info = { - .master_mode = 0, - .bist_mode = DP_DISABLE, - .bist_pattern = NO_PATTERN, - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - }, -}; - -static struct exynos_dp_platform_data dp_platform_data = { - .phy_enable = set_dp_phy_ctrl, - .edp_dev_info = &edp_info, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_backlight_on(unsigned int onoff) { - vid->rgb_mode = MODE_RGB_P, + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + + struct exynos5420_gpio_part2 *gpio2 = + (struct exynos5420_gpio_part2 *)samsung_get_base_gpio_part2(); + + /* For PWM */ + s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); + s5p_gpio_set_value(&gpio1->b2, 0, 1);

- exynos_set_dp_platform_data(&dp_platform_data); + /* BL_EN */ + s5p_gpio_cfg_pin(&gpio2->x1, 5, GPIO_OUTPUT); + s5p_gpio_set_value(&gpio2->x1, 5, 1); } #endif

Enabling VDD_28IO_DP via LDO38 for SMDK5420.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- board/samsung/common/board.c | 3 +++ include/power/s2mps11_pmic.h | 3 +++ 2 files changed, 6 insertions(+)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 2536457..224f83d 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -180,6 +180,9 @@ int board_init_s2mps11(void) {PMIC_REG_WRITE, S2MPS11_BUCK3_CTRL2, S2MPS11_BUCK_CTRL2_1V}, {PMIC_REG_WRITE, S2MPS11_BUCK4_CTRL2, S2MPS11_BUCK_CTRL2_1V}, {PMIC_REG_WRITE, S2MPS11_BUCK6_CTRL2, S2MPS11_BUCK_CTRL2_1V}, +#ifdef CONFIG_SMDK5420 + {PMIC_REG_WRITE, S2MPS11_LDO38_CTRL, S2MPS11_LDO_CTRL_2_8V}, +#endif {PMIC_REG_UPDATE, S2MPS11_REG_RTC_CTRL, S2MPS11_RTC_CTRL_32KHZ_CP_EN | S2MPS11_RTC_CTRL_JIT}, {PMIC_REG_BAIL} diff --git a/include/power/s2mps11_pmic.h b/include/power/s2mps11_pmic.h index 20c781d..8c6bf4b 100644 --- a/include/power/s2mps11_pmic.h +++ b/include/power/s2mps11_pmic.h @@ -125,6 +125,8 @@ enum s2mps11_reg { #define S2MPS11_BUCK_CTRL2_1_2V 0x60 /* Value to set voltage as 1.2625V */ #define S2MPS11_BUCK_CTRL2_1_2625V 0x6A +/* Value to set voltage as 2.8V */ +#define S2MPS11_LDO_CTRL_2_8V 0x78

/* Buck register addresses */ #define S2MPS11_BUCK1_CTRL2 0x26 @@ -133,6 +135,7 @@ enum s2mps11_reg { #define S2MPS11_BUCK4_CTRL2 0x2c #define S2MPS11_BUCK6_CTRL2 0x34 #define S2MPS11_LDO22_CTRL 0x52 +#define S2MPS11_LDO38_CTRL 0x62

#define S2MPS11_DEVICE_NAME "S2MPS11_PMIC"