[PATCH 0/4] Align sama5 and sama7 DT's with Linux

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U-Boot support for IMX8MP dual-role

Sergiu Moga

1 Sep 2022 1 Sep '22

4:22 p.m.

This has been done in order to align the DT of U-Boot with the DT of Linux. In Linux, a phandle from a '-gpio' DT property is linked to the pinctrl driver, a single driver that handles both pinctrl settings and offers GPIO API to callers. On the other hand, U-Boot redirects such phandle to a corresponding UCLASS_GPIO driver, because U-Boot offers two different types of drivers in this case: UCLASS_PINCTRL which handles pin functions and UCLASS_GPIO which handles gpio requests as a gpio provider. Due to this, we have two drivers in Uboot, but the Devicetree has a single node. Thus, just one of the drivers can be probed for the DT node during platform initialization, before relocation.

Our previous solution in U-Boot was to have a different devicetree: the gpio node has a subnode for the pinctrl driver, which is not compliant with Linux ABI. Furthermore, our documentation for this type of nodes mentions no such gpio compatible.

After this patch, we can no longer add nodes with a gpio compatible in the DT. Thus, in order to link the pinctrl driver to the gpio one, a hook to the bind method of the former in U-Boot has been added and the GPIO related compatibles have been removed to avoid conflict when compatibles are enumerated and bound to drivers during platform start before relocation. The bind method will attach the GPIO driver to the pinctrl DT node so that every phandle coming from '-gpio' DT properties will be redirected to a valid driver attached to the pinctrl DT node.

Furthermore, this fixes a GPIO request issue existent on sama7g5, which was caused by the fact that there was no UCLASS_GPIO driver bound to the pioA node label.

To make the two Devicetrees even more similar (the one from Linux and the one from U-Boot), make the pinctrl driver's node support multiple subnodes for its subnode.

Sergiu Moga (4): ARM: dts: at91: sama5: Align with Linux Devicetree ARM: dts: at91: sama7: Align with Linux Devicetree pinctrl: at91-pio4: Bind GPIO driver to the pinctrl DT node pinctrl: at91-pio4: Add support for pinctrl config subnodes

arch/arm/dts/at91-sama5d27_giantboard.dts | 59 +++-- arch/arm/dts/at91-sama5d27_som1_ek.dts | 80 +++---- .../dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi | 6 +- arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 92 ++++---- arch/arm/dts/at91-sama5d2_icp.dts | 134 ++++++------ arch/arm/dts/at91-sama5d2_ptc_ek.dts | 98 ++++----- arch/arm/dts/at91-sama5d2_xplained.dts | 204 +++++++++--------- arch/arm/dts/at91-sama7g5ek-u-boot.dtsi | 2 +- arch/arm/dts/at91-sama7g5ek.dts | 85 +++++--- arch/arm/dts/sama5d2.dtsi | 9 +- arch/arm/dts/sama5d27_som1.dtsi | 94 ++++---- arch/arm/dts/sama5d27_wlsom1.dtsi | 54 +++-- arch/arm/dts/sama7g5.dtsi | 16 +- drivers/gpio/atmel_pio4.c | 2 - drivers/pinctrl/pinctrl-at91-pio4.c | 138 ++++++++++-- 15 files changed, 592 insertions(+), 481 deletions(-)

-- 2.25.1

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Sergiu Moga

1 Sep 1 Sep

4:22 p.m.

New subject: [PATCH 1/4] ARM: dts: at91: sama5: Align with Linux Devicetree

This patch makes sure that the Devicetree for the sama5 boards are aligned with the Devicetree from Linux. This implies removing the GPIO compatible and replacing it with the PINCTRL one, as well as unifying the SDMMC pinctrl related subnodes under one single subnode.

Signed-off-by: Sergiu Moga sergiu.moga@microchip.com --- arch/arm/dts/at91-sama5d27_giantboard.dts | 59 +++-- arch/arm/dts/at91-sama5d27_som1_ek.dts | 80 +++---- .../dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi | 6 +- arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 92 ++++---- arch/arm/dts/at91-sama5d2_icp.dts | 134 ++++++------ arch/arm/dts/at91-sama5d2_ptc_ek.dts | 98 ++++----- arch/arm/dts/at91-sama5d2_xplained.dts | 204 +++++++++--------- arch/arm/dts/sama5d2.dtsi | 9 +- arch/arm/dts/sama5d27_som1.dtsi | 94 ++++---- arch/arm/dts/sama5d27_wlsom1.dtsi | 54 +++-- 10 files changed, 411 insertions(+), 419 deletions(-)

diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts b/arch/arm/dts/at91-sama5d27_giantboard.dts index e81ca60ca0..2625f81c8b 100644 --- a/arch/arm/dts/at91-sama5d27_giantboard.dts +++ b/arch/arm/dts/at91-sama5d27_giantboard.dts @@ -30,7 +30,7 @@ sdmmc1: sdio-host@b0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; u-boot,dm-pre-reloc; }; @@ -73,10 +73,9 @@ u-boot,dm-pre-reloc; };

- pioA: gpio@fc038000 { - pinctrl { - - pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pioA: pinctrl@fc038000 { + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { pinmux = <PIN_PA28__SDMMC1_CMD>, <PIN_PA18__SDMMC1_DAT0>, <PIN_PA19__SDMMC1_DAT1>, @@ -86,41 +85,41 @@ u-boot,dm-pre-reloc; };

- pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + ck_cd { pinmux = <PIN_PA22__SDMMC1_CK>, <PIN_PA30__SDMMC1_CD>; bias-disable; u-boot,dm-pre-reloc; }; + };

- pinctrl_uart1_default: uart1_default { - pinmux = <PIN_PD2__URXD1>, - <PIN_PD3__UTXD1>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_uart1_default: uart1_default { + pinmux = <PIN_PD2__URXD1>, + <PIN_PD3__UTXD1>; + bias-disable; + u-boot,dm-pre-reloc; + };

- pinctrl_i2c0_default: i2c0_default { - pinmux = <PIN_PD21__TWD0>, - <PIN_PD22__TWCK0>; - bias-disable; - }; + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PD21__TWD0>, + <PIN_PD22__TWCK0>; + bias-disable; + };

- pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PD4__TWD1>, - <PIN_PD5__TWCK1>; - bias-disable; - }; + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + };

- pinctrl_usb_default: usb_default { - pinmux = <PIN_PB10__GPIO>; - bias-disable; - }; + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB10__GPIO>; + bias-disable; + };

- pinctrl_usba_vbus: usba_vbus { - pinmux = <PIN_PA31__GPIO>; - bias-disable; - }; + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PA31__GPIO>; + bias-disable; }; }; }; diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts index efd1a5d197..70d15c8a62 100644 --- a/arch/arm/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts @@ -83,7 +83,7 @@ sdmmc0: sdio-host@a0000000 { bus-width = <8>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; u-boot,dm-pre-reloc; }; @@ -91,7 +91,7 @@ sdmmc1: sdio-host@b0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; /* conflict with qspi0 */ u-boot,dm-pre-reloc; }; @@ -129,7 +129,7 @@ u-boot,dm-pre-reloc; };

- pioA: gpio@fc038000 { + pioA: pinctrl@fc038000 { pinctrl { pinctrl_lcd_base: pinctrl_lcd_base { pinmux = <PIN_PC5__LCDVSYNC>, @@ -166,43 +166,47 @@ bias-disable; };

- pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { - pinmux = <PIN_PA1__SDMMC0_CMD>, - <PIN_PA2__SDMMC0_DAT0>, - <PIN_PA3__SDMMC0_DAT1>, - <PIN_PA4__SDMMC0_DAT2>, - <PIN_PA5__SDMMC0_DAT3>, - <PIN_PA6__SDMMC0_DAT4>, - <PIN_PA7__SDMMC0_DAT5>, - <PIN_PA8__SDMMC0_DAT6>, - <PIN_PA9__SDMMC0_DAT7>; - bias-pull-up; - u-boot,dm-pre-reloc; - }; - - pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { - pinmux = <PIN_PA0__SDMMC0_CK>, - <PIN_PA10__SDMMC0_RSTN>, - <PIN_PA13__SDMMC0_CD>; - bias-disable; - u-boot,dm-pre-reloc; + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_dat { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA6__SDMMC0_DAT4>, + <PIN_PA7__SDMMC0_DAT5>, + <PIN_PA8__SDMMC0_DAT6>, + <PIN_PA9__SDMMC0_DAT7>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + ck_cd { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA10__SDMMC0_RSTN>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; };

- pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { - pinmux = <PIN_PA28__SDMMC1_CMD>, - <PIN_PA18__SDMMC1_DAT0>, - <PIN_PA19__SDMMC1_DAT1>, - <PIN_PA20__SDMMC1_DAT2>, - <PIN_PA21__SDMMC1_DAT3>; - bias-pull-up; - u-boot,dm-pre-reloc; - }; - - pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { - pinmux = <PIN_PA22__SDMMC1_CK>, - <PIN_PA30__SDMMC1_CD>; - bias-disable; - u-boot,dm-pre-reloc; + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_dat { + pinmux = <PIN_PA28__SDMMC1_CMD>, + <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + ck_cd { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; };

pinctrl_uart1_default: uart1_default { diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi b/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi index 8c84dd08fd..41cf9061a1 100644 --- a/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi @@ -37,11 +37,7 @@ u-boot,dm-pre-reloc; };

-&pinctrl_sdmmc0_cmd_dat_default { - u-boot,dm-pre-reloc; -}; - -&pinctrl_sdmmc0_ck_cd_default { +&pinctrl_sdmmc0_default { u-boot,dm-pre-reloc; };

diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts index f3f6942143..eec183d5de 100644 --- a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts @@ -34,7 +34,7 @@ sdmmc0: sdio-host@a0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; };

@@ -78,44 +78,44 @@ status = "okay"; };

- pioA: gpio@fc038000 { - pinctrl { - pinctrl_lcd_base: pinctrl_lcd_base { - pinmux = <PIN_PC30__LCDVSYNC>, - <PIN_PC31__LCDHSYNC>, - <PIN_PD1__LCDDEN>, - <PIN_PD0__LCDPCK>; - bias-disable; - }; + pioA: pinctrl@fc038000 { + pinctrl_lcd_base: pinctrl_lcd_base { + pinmux = <PIN_PC30__LCDVSYNC>, + <PIN_PC31__LCDHSYNC>, + <PIN_PD1__LCDDEN>, + <PIN_PD0__LCDPCK>; + bias-disable; + };

- pinctrl_lcd_pwm: pinctrl_lcd_pwm { - pinmux = <PIN_PC28__LCDPWM>; - bias-disable; - }; + pinctrl_lcd_pwm: pinctrl_lcd_pwm { + pinmux = <PIN_PC28__LCDPWM>; + bias-disable; + };

- pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { - pinmux = <PIN_PC10__LCDDAT2>, - <PIN_PC11__LCDDAT3>, - <PIN_PC12__LCDDAT4>, - <PIN_PC13__LCDDAT5>, - <PIN_PC14__LCDDAT6>, - <PIN_PC15__LCDDAT7>, - <PIN_PC16__LCDDAT10>, - <PIN_PC17__LCDDAT11>, - <PIN_PC18__LCDDAT12>, - <PIN_PC19__LCDDAT13>, - <PIN_PC20__LCDDAT14>, - <PIN_PC21__LCDDAT15>, - <PIN_PC22__LCDDAT18>, - <PIN_PC23__LCDDAT19>, - <PIN_PC24__LCDDAT20>, - <PIN_PC25__LCDDAT21>, - <PIN_PC26__LCDDAT22>, - <PIN_PC27__LCDDAT23>; - bias-disable; - }; + pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { + pinmux = <PIN_PC10__LCDDAT2>, + <PIN_PC11__LCDDAT3>, + <PIN_PC12__LCDDAT4>, + <PIN_PC13__LCDDAT5>, + <PIN_PC14__LCDDAT6>, + <PIN_PC15__LCDDAT7>, + <PIN_PC16__LCDDAT10>, + <PIN_PC17__LCDDAT11>, + <PIN_PC18__LCDDAT12>, + <PIN_PC19__LCDDAT13>, + <PIN_PC20__LCDDAT14>, + <PIN_PC21__LCDDAT15>, + <PIN_PC22__LCDDAT18>, + <PIN_PC23__LCDDAT19>, + <PIN_PC24__LCDDAT20>, + <PIN_PC25__LCDDAT21>, + <PIN_PC26__LCDDAT22>, + <PIN_PC27__LCDDAT23>; + bias-disable; + };

- pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { pinmux = <PIN_PA1__SDMMC0_CMD>, <PIN_PA2__SDMMC0_DAT0>, <PIN_PA3__SDMMC0_DAT1>, @@ -124,24 +124,24 @@ bias-disable; };

- pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + ck_cd_vddsel { pinmux = <PIN_PA0__SDMMC0_CK>, <PIN_PA11__SDMMC0_VDDSEL>, <PIN_PA12__SDMMC0_WP>, <PIN_PA13__SDMMC0_CD>; bias-disable; }; + };

- pinctrl_uart0_default: uart0_default { - pinmux = <PIN_PB26__URXD0>, - <PIN_PB27__UTXD0>; - bias-disable; - }; + pinctrl_uart0_default: uart0_default { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + };

- pinctrl_onewire_tm_default: onewire_tm_default { - pinmux = <PIN_PC9__GPIO>; - bias-pull-up; - }; + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PC9__GPIO>; + bias-pull-up; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts index 0b0db1b2be..2dffae9c5c 100644 --- a/arch/arm/dts/at91-sama5d2_icp.dts +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -86,75 +86,73 @@ }; };

- pioA: gpio@fc038000 { + pioA: pinctrl@fc038000 { status = "okay"; - pinctrl { - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PD19__TWD1>, - <PIN_PD20__TWCK1>; - bias-disable; - }; - - pinctrl_macb0_rmii: macb0_rmii { - pinmux = <PIN_PD1__GRXCK>, - <PIN_PD2__GTXER>, - <PIN_PD5__GRX2>, - <PIN_PD6__GRX3>, - <PIN_PD7__GTX2>, - <PIN_PD8__GTX3>, - <PIN_PD9__GTXCK>, - <PIN_PD10__GTXEN>, - <PIN_PD11__GRXDV>, - <PIN_PD12__GRXER>, - <PIN_PD13__GRX0>, - <PIN_PD14__GRX1>, - <PIN_PD15__GTX0>, - <PIN_PD16__GTX1>, - <PIN_PD17__GMDC>, - <PIN_PD18__GMDIO>; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PD3__GPIO>; - bias-disable; - }; - - pinctrl_macb0_rst: macb0_sw_rst { - pinmux = <PIN_PD4__GPIO>; - bias-pull-up; - }; - - pinctrl_mikrobus1_uart: mikrobus1_uart { - pinmux = <PIN_PB26__URXD0>, - <PIN_PB27__UTXD0>; - bias-disable; - }; - - pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { - pinmux = <PIN_PA6__QSPI1_SCK>, - <PIN_PA11__QSPI1_CS>; - bias-disable; - }; - - pinctrl_qspi1_dat_default: qspi1_dat_default { - pinmux = <PIN_PA7__QSPI1_IO0>, - <PIN_PA8__QSPI1_IO1>, - <PIN_PA9__QSPI1_IO2>, - <PIN_PA10__QSPI1_IO3>; - bias-pull-up; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - pinmux = <PIN_PA1__SDMMC0_CMD>, - <PIN_PA2__SDMMC0_DAT0>, - <PIN_PA3__SDMMC0_DAT1>, - <PIN_PA4__SDMMC0_DAT2>, - <PIN_PA5__SDMMC0_DAT3>, - <PIN_PA0__SDMMC0_CK>, - <PIN_PA13__SDMMC0_CD>; - bias-disable; - }; + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD19__TWD1>, + <PIN_PD20__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PD1__GRXCK>, + <PIN_PD2__GTXER>, + <PIN_PD5__GRX2>, + <PIN_PD6__GRX3>, + <PIN_PD7__GTX2>, + <PIN_PD8__GTX3>, + <PIN_PD9__GTXCK>, + <PIN_PD10__GTXEN>, + <PIN_PD11__GRXDV>, + <PIN_PD12__GRXER>, + <PIN_PD13__GRX0>, + <PIN_PD14__GRX1>, + <PIN_PD15__GTX0>, + <PIN_PD16__GTX1>, + <PIN_PD17__GMDC>, + <PIN_PD18__GMDIO>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PD3__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rst: macb0_sw_rst { + pinmux = <PIN_PD4__GPIO>; + bias-pull-up; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; + + pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { + pinmux = <PIN_PA6__QSPI1_SCK>, + <PIN_PA11__QSPI1_CS>; + bias-disable; + }; + + pinctrl_qspi1_dat_default: qspi1_dat_default { + pinmux = <PIN_PA7__QSPI1_IO0>, + <PIN_PA8__QSPI1_IO1>, + <PIN_PA9__QSPI1_IO2>, + <PIN_PA10__QSPI1_IO3>; + bias-pull-up; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA0__SDMMC0_CK>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/dts/at91-sama5d2_ptc_ek.dts index f45fb1ef26..36d52c2c5e 100644 --- a/arch/arm/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/dts/at91-sama5d2_ptc_ek.dts @@ -94,7 +94,7 @@ sdmmc0: sdio-host@a0000000 { bus-width = <8>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; u-boot,dm-pre-reloc; }; @@ -102,7 +102,7 @@ sdmmc1: sdio-host@b0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "disabled"; /* conflicts with nand and qspi0*/ u-boot,dm-pre-reloc; }; @@ -137,34 +137,34 @@ }; };

- pioA: gpio@fc038000 { - pinctrl { - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PC6__TWD1>, - <PIN_PC7__TWCK1>; - bias-disable; - }; + pioA: pinctrl@fc038000 { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PC6__TWD1>, + <PIN_PC7__TWCK1>; + bias-disable; + };

- pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PB24__GPIO>; - bias-disable; - }; + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + };

- pinctrl_macb0_rmii: macb0_rmii { - pinmux = <PIN_PB14__GTXCK>, - <PIN_PB15__GTXEN>, - <PIN_PB16__GRXDV>, - <PIN_PB17__GRXER>, - <PIN_PB18__GRX0>, - <PIN_PB19__GRX1>, - <PIN_PB20__GTX0>, - <PIN_PB21__GTX1>, - <PIN_PB22__GMDC>, - <PIN_PB23__GMDIO>; - bias-disable; - }; + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + };

- pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_dat { pinmux = <PIN_PA1__SDMMC0_CMD>, <PIN_PA2__SDMMC0_DAT0>, <PIN_PA3__SDMMC0_DAT1>, @@ -178,7 +178,7 @@ u-boot,dm-pre-reloc; };

- pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + ck_cd { pinmux = <PIN_PA0__SDMMC0_CK>, <PIN_PA10__SDMMC0_RSTN>, <PIN_PA11__SDMMC0_VDDSEL>, @@ -186,8 +186,10 @@ bias-disable; u-boot,dm-pre-reloc; }; + };

- pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_dat { pinmux = <PIN_PA28__SDMMC1_CMD>, <PIN_PA18__SDMMC1_DAT0>, <PIN_PA19__SDMMC1_DAT1>, @@ -197,34 +199,34 @@ u-boot,dm-pre-reloc; };

- pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + ck_cd { pinmux = <PIN_PA22__SDMMC1_CK>, <PIN_PA30__SDMMC1_CD>; bias-disable; u-boot,dm-pre-reloc; }; + };

- pinctrl_uart0_default: uart0_default { - pinmux = <PIN_PB26__URXD0>, - <PIN_PB27__UTXD0>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_uart0_default: uart0_default { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + u-boot,dm-pre-reloc; + };

- pinctrl_usb_default: usb_default { - pinmux = <PIN_PB12__GPIO>; - bias-disable; - }; + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB12__GPIO>; + bias-disable; + };

- pinctrl_usba_vbus: usba_vbus { - pinmux = <PIN_PB11__GPIO>; - bias-disable; - }; + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PB11__GPIO>; + bias-disable; + };

- pinctrl_onewire_tm_default: onewire_tm_default { - pinmux = <PIN_PB31__GPIO>; - bias-pull-up; - }; + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PB31__GPIO>; + bias-pull-up; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts index 34b64a22af..78a3a851bb 100644 --- a/arch/arm/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/dts/at91-sama5d2_xplained.dts @@ -44,7 +44,7 @@ sdmmc0: sdio-host@a0000000 { bus-width = <8>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; u-boot,dm-pre-reloc; }; @@ -52,7 +52,7 @@ sdmmc1: sdio-host@b0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; /* conflict with qspi0 */ u-boot,dm-pre-reloc; }; @@ -143,85 +143,85 @@ }; };

- pioA: gpio@fc038000 { - pinctrl { - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PD4__TWD1>, - <PIN_PD5__TWCK1>; - bias-disable; - }; + pioA: pinctrl@fc038000 { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + };

- pinctrl_lcd_base: pinctrl_lcd_base { - pinmux = <PIN_PC30__LCDVSYNC>, - <PIN_PC31__LCDHSYNC>, - <PIN_PD1__LCDDEN>, - <PIN_PD0__LCDPCK>; - bias-disable; - }; + pinctrl_lcd_base: pinctrl_lcd_base { + pinmux = <PIN_PC30__LCDVSYNC>, + <PIN_PC31__LCDHSYNC>, + <PIN_PD1__LCDDEN>, + <PIN_PD0__LCDPCK>; + bias-disable; + };

- pinctrl_lcd_pwm: pinctrl_lcd_pwm { - pinmux = <PIN_PC28__LCDPWM>; - bias-disable; - }; + pinctrl_lcd_pwm: pinctrl_lcd_pwm { + pinmux = <PIN_PC28__LCDPWM>; + bias-disable; + };

- pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PC9__GPIO>; - bias-disable; - }; + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PC9__GPIO>; + bias-disable; + };

- pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default { - pinmux = <PIN_PA22__QSPI0_SCK>, - <PIN_PA23__QSPI0_CS>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default { + pinmux = <PIN_PA22__QSPI0_SCK>, + <PIN_PA23__QSPI0_CS>; + bias-disable; + u-boot,dm-pre-reloc; + };

- pinctrl_qspi0_dat_default: qspi0_dat_default { - pinmux = <PIN_PA24__QSPI0_IO0>, - <PIN_PA25__QSPI0_IO1>, - <PIN_PA26__QSPI0_IO2>, - <PIN_PA27__QSPI0_IO3>; - bias-pull-up; - u-boot,dm-pre-reloc; - }; + pinctrl_qspi0_dat_default: qspi0_dat_default { + pinmux = <PIN_PA24__QSPI0_IO0>, + <PIN_PA25__QSPI0_IO1>, + <PIN_PA26__QSPI0_IO2>, + <PIN_PA27__QSPI0_IO3>; + bias-pull-up; + u-boot,dm-pre-reloc; + };

- pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + ck_cd_default { pinmux = <PIN_PA0__SDMMC0_CK>, <PIN_PA10__SDMMC0_RSTN>, <PIN_PA11__SDMMC0_VDDSEL>, @@ -243,8 +243,10 @@ bias-disable; u-boot,dm-pre-reloc; }; + };

- pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + ck_cd { pinmux = <PIN_PA22__SDMMC1_CK>, <PIN_PA30__SDMMC1_CD>; bias-disable; u-boot,dm-pre-reloc; }; + };

- pinctrl_spi0_default: spi0_default { - pinmux = <PIN_PA14__SPI0_SPCK>, - <PIN_PA15__SPI0_MOSI>, - <PIN_PA16__SPI0_MISO>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_spi0_default: spi0_default { + pinmux = <PIN_PA14__SPI0_SPCK>, + <PIN_PA15__SPI0_MOSI>, + <PIN_PA16__SPI0_MISO>; + bias-disable; + u-boot,dm-pre-reloc; + };

- pinctrl_usb_default: usb_default { - pinmux = <PIN_PB10__GPIO>; - bias-disable; - }; + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB10__GPIO>; + bias-disable; + };

- pinctrl_usba_vbus: usba_vbus { - pinmux = <PIN_PA31__GPIO>; - bias-disable; - }; + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PA31__GPIO>; + bias-disable; + };

- pinctrl_onewire_tm_default: onewire_tm_default { - pinmux = <PIN_PB0__GPIO>; - bias-pull-up; - }; + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PB0__GPIO>; + bias-pull-up; }; }; }; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index d92bdd5588..790b746ed1 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -799,18 +799,13 @@ status = "disabled"; };

- pioA: gpio@fc038000 { - compatible = "atmel,sama5d2-gpio"; + pioA: pinctrl@fc038000 { + compatible = "atmel,sama5d2-pinctrl"; reg = <0xfc038000 0x600>; clocks = <&pioA_clk>; gpio-controller; #gpio-cells = <2>; u-boot,dm-pre-reloc; - - pinctrl { - compatible = "atmel,sama5d2-pinctrl"; - u-boot,dm-pre-reloc; - }; }; }; }; diff --git a/arch/arm/dts/sama5d27_som1.dtsi b/arch/arm/dts/sama5d27_som1.dtsi index db4fefadcd..f920077449 100644 --- a/arch/arm/dts/sama5d27_som1.dtsi +++ b/arch/arm/dts/sama5d27_som1.dtsi @@ -103,54 +103,52 @@ status = "okay"; };

- pioA: gpio@fc038000 { - pinctrl { - pinctrl_i2c0_default: i2c0_default { - pinmux = <PIN_PD21__TWD0>, - <PIN_PD22__TWCK0>; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PD4__TWD1>, - <PIN_PD5__TWCK1>; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PD31__GPIO>; - bias-disable; - }; - - pinctrl_macb0_rmii: macb0_rmii { - pinmux = <PIN_PD9__GTXCK>, - <PIN_PD10__GTXEN>, - <PIN_PD11__GRXDV>, - <PIN_PD12__GRXER>, - <PIN_PD13__GRX0>, - <PIN_PD14__GRX1>, - <PIN_PD15__GTX0>, - <PIN_PD16__GTX1>, - <PIN_PD17__GMDC>, - <PIN_PD18__GMDIO>; - bias-disable; - }; - - pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { - pinmux = <PIN_PB5__QSPI1_SCK>, - <PIN_PB6__QSPI1_CS>; - bias-disable; - u-boot,dm-pre-reloc; - }; - - pinctrl_qspi1_dat_default: qspi1_dat_default { - pinmux = <PIN_PB7__QSPI1_IO0>, - <PIN_PB8__QSPI1_IO1>, - <PIN_PB9__QSPI1_IO2>, - <PIN_PB10__QSPI1_IO3>; - bias-pull-up; - u-boot,dm-pre-reloc; - }; + pioA: pinctrl@fc038000 { + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PD21__TWD0>, + <PIN_PD22__TWCK0>; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PD31__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PD9__GTXCK>, + <PIN_PD10__GTXEN>, + <PIN_PD11__GRXDV>, + <PIN_PD12__GRXER>, + <PIN_PD13__GRX0>, + <PIN_PD14__GRX1>, + <PIN_PD15__GTX0>, + <PIN_PD16__GTX1>, + <PIN_PD17__GMDC>, + <PIN_PD18__GMDIO>; + bias-disable; + }; + + pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { + pinmux = <PIN_PB5__QSPI1_SCK>, + <PIN_PB6__QSPI1_CS>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_qspi1_dat_default: qspi1_dat_default { + pinmux = <PIN_PB7__QSPI1_IO0>, + <PIN_PB8__QSPI1_IO1>, + <PIN_PB9__QSPI1_IO2>, + <PIN_PB10__QSPI1_IO3>; + bias-pull-up; + u-boot,dm-pre-reloc; }; }; }; diff --git a/arch/arm/dts/sama5d27_wlsom1.dtsi b/arch/arm/dts/sama5d27_wlsom1.dtsi index 889a0034d1..1c23b8c737 100644 --- a/arch/arm/dts/sama5d27_wlsom1.dtsi +++ b/arch/arm/dts/sama5d27_wlsom1.dtsi @@ -41,36 +41,34 @@ }; };

- pioA: gpio@fc038000 { - pinctrl { - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PB24__GPIO>; - bias-disable; - }; + pioA: pinctrl@fc038000 { + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + };

- pinctrl_qspi1_default: qspi1_default { - pinmux = <PIN_PB5__QSPI1_SCK>, - <PIN_PB6__QSPI1_CS>, - <PIN_PB7__QSPI1_IO0>, - <PIN_PB8__QSPI1_IO1>, - <PIN_PB9__QSPI1_IO2>, - <PIN_PB10__QSPI1_IO3>; - bias-pull-up; - }; + pinctrl_qspi1_default: qspi1_default { + pinmux = <PIN_PB5__QSPI1_SCK>, + <PIN_PB6__QSPI1_CS>, + <PIN_PB7__QSPI1_IO0>, + <PIN_PB8__QSPI1_IO1>, + <PIN_PB9__QSPI1_IO2>, + <PIN_PB10__QSPI1_IO3>; + bias-pull-up; }; }; };

-- 2.25.1

Sergiu Moga

4:22 p.m.

New subject: [PATCH 2/4] ARM: dts: at91: sama7: Align with Linux Devicetree

This patch makes sure that the Devicetree for the sama7 boards are aligned with the Devicetree from Linux. This implies removing the GPIO compatible and replacing it with the PINCTRL one, as well as unifying the SDMMC pinctrl related subnodes under one single subnode.

Signed-off-by: Sergiu Moga sergiu.moga@microchip.com --- arch/arm/dts/at91-sama7g5ek-u-boot.dtsi | 2 +- arch/arm/dts/at91-sama7g5ek.dts | 85 +++++++++++++++---------- arch/arm/dts/sama7g5.dtsi | 16 ++--- 3 files changed, 60 insertions(+), 43 deletions(-)

diff --git a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi index 601386788f..d294ddb54a 100644 --- a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi @@ -28,7 +28,7 @@ u-boot,dm-pre-reloc; };

-&pinctrl { +&pioA { u-boot,dm-pre-reloc; };

diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts index eaba0de3f7..aed84f15a1 100644 --- a/arch/arm/dts/at91-sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -690,46 +690,67 @@ };

pinctrl_sdmmc0_default: sdmmc0_default { - pinmux = <PIN_PA1__SDMMC0_CMD>, - <PIN_PA3__SDMMC0_DAT0>, - <PIN_PA4__SDMMC0_DAT1>, - <PIN_PA5__SDMMC0_DAT2>, - <PIN_PA6__SDMMC0_DAT3>, - <PIN_PA7__SDMMC0_DAT4>, - <PIN_PA8__SDMMC0_DAT5>, - <PIN_PA9__SDMMC0_DAT6>, - <PIN_PA10__SDMMC0_DAT7>, - <PIN_PA0__SDMMC0_CK>, - <PIN_PA2__SDMMC0_RSTN>, - <PIN_PA14__SDMMC0_CD>, - <PIN_PA11__SDMMC0_DS>; + cmd_data { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA3__SDMMC0_DAT0>, + <PIN_PA4__SDMMC0_DAT1>, + <PIN_PA5__SDMMC0_DAT2>, + <PIN_PA6__SDMMC0_DAT3>, + <PIN_PA7__SDMMC0_DAT4>, + <PIN_PA8__SDMMC0_DAT5>, + <PIN_PA9__SDMMC0_DAT6>, + <PIN_PA10__SDMMC0_DAT7>; slew-rate = <0>; bias-pull-up; + }; + + ck_cd_rstn_vddsel { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA2__SDMMC0_RSTN>, + <PIN_PA14__SDMMC0_CD>, + <PIN_PA11__SDMMC0_DS>; + slew-rate = <0>; + bias-pull-up; + }; };

pinctrl_sdmmc1_default: sdmmc1_default { - pinmux = <PIN_PB29__SDMMC1_CMD>, - <PIN_PB31__SDMMC1_DAT0>, - <PIN_PC0__SDMMC1_DAT1>, - <PIN_PC1__SDMMC1_DAT2>, - <PIN_PC2__SDMMC1_DAT3>, - <PIN_PB30__SDMMC1_CK>, - <PIN_PB28__SDMMC1_RSTN>, - <PIN_PC5__SDMMC1_1V8SEL>, - <PIN_PC4__SDMMC1_CD>; - slew-rate = <0>; - bias-pull-up; + cmd_data { + pinmux = <PIN_PB29__SDMMC1_CMD>, + <PIN_PB31__SDMMC1_DAT0>, + <PIN_PC0__SDMMC1_DAT1>, + <PIN_PC1__SDMMC1_DAT2>, + <PIN_PC2__SDMMC1_DAT3>; + slew-rate = <0>; + bias-pull-up; + }; + + ck_cd_rstn_vddsel { + pinmux = <PIN_PB30__SDMMC1_CK>, + <PIN_PB28__SDMMC1_RSTN>, + <PIN_PC5__SDMMC1_1V8SEL>, + <PIN_PC4__SDMMC1_CD>; + slew-rate = <0>; + bias-pull-up; + }; };

pinctrl_sdmmc2_default: sdmmc2_default { - pinmux = <PIN_PD3__SDMMC2_CMD>, - <PIN_PD5__SDMMC2_DAT0>, - <PIN_PD6__SDMMC2_DAT1>, - <PIN_PD7__SDMMC2_DAT2>, - <PIN_PD8__SDMMC2_DAT3>, - <PIN_PD4__SDMMC2_CK>; - slew-rate = <0>; - bias-pull-up; + cmd_data { + pinmux = <PIN_PD3__SDMMC2_CMD>, + <PIN_PD5__SDMMC2_DAT0>, + <PIN_PD6__SDMMC2_DAT1>, + <PIN_PD7__SDMMC2_DAT2>, + <PIN_PD8__SDMMC2_DAT3>; + slew-rate = <0>; + bias-pull-up; + }; + + ck { + pinmux = <PIN_PD4__SDMMC2_CK>; + slew-rate = <0>; + bias-pull-up; + }; };

pinctrl_spdifrx_default: spdifrx_default { diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index 97400dc18e..d38090d7dd 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -187,8 +187,8 @@ reg = <0xe0008000 0x20>; };

- pinctrl: pinctrl@e0014000 { - compatible = "microchip,sama7g5-gpio"; + pioA: pinctrl@e0014000 { + compatible = "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, @@ -196,14 +196,10 @@ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - - pioA: pinctrl_default { - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - compatible = "microchip,sama7g5-pinctrl"; - }; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; };

pmc: pmc@e0018000 {

-- 2.25.1

Sergiu Moga

4:22 p.m.

New subject: [PATCH 3/4] pinctrl: at91-pio4: Bind GPIO driver to the pinctrl DT node

Signed-off-by: Sergiu Moga sergiu.moga@microchip.com --- drivers/gpio/atmel_pio4.c | 2 - drivers/pinctrl/pinctrl-at91-pio4.c | 65 ++++++++++++++++++++++++++--- 2 files changed, 60 insertions(+), 7 deletions(-)

diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index 77a76c1d50..47ed297981 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -350,10 +350,8 @@ static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {

static const struct udevice_id atmel_pio4_ids[] = { { - .compatible = "atmel,sama5d2-gpio", .data = (ulong)&atmel_sama5d2_pioctrl_data, }, { - .compatible = "microchip,sama7g5-gpio", .data = (ulong)&microchip_sama7g5_pioctrl_data, }, {} diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 26fb5d61d5..e434a38f1f 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -9,6 +9,8 @@ #include <common.h> #include <dm.h> #include <asm/global_data.h> +#include <dm/device-internal.h> +#include <dm/lists.h> #include <dm/pinctrl.h> #include <linux/bitops.h> #include <linux/io.h> @@ -28,6 +30,25 @@ struct atmel_pio4_plat { unsigned int slew_rate_support; };

+/* + * Table keeping track of the pinctrl driver's slew rate support and the + * corresponding index into the struct udevice_id of the gpio_atmel_pio4 GPIO + * driver. This has been done in order to align the DT of U-Boot with the DT of + * Linux. In Linux, a phandle from a '-gpio' DT property is linked to the + * pinctrl driver, unlike U-Boot which redirects this phandle to a corresponding + * UCLASS_GPIO driver. Thus, in order to link the two, a hook to the bind method + * of the pinctrl driver in U-Boot has been added. This bind method will attach + * the GPIO driver to the pinctrl DT node using this table. + * @slew_rate_support pinctrl driver's slew rate support + * @gdidx index into the GPIO driver's struct udevide_id + * (needed in order to properly bind with driver_data) + */ + +struct atmel_pinctrl_data { + unsigned int slew_rate_support; + int gdidx; +}; + static const struct pinconf_param conf_params[] = { { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, @@ -181,24 +202,57 @@ const struct pinctrl_ops atmel_pinctrl_ops = { static int atmel_pinctrl_probe(struct udevice *dev) { struct atmel_pio4_plat *plat = dev_get_plat(dev); - ulong priv = dev_get_driver_data(dev); + struct atmel_pinctrl_data *priv = (struct atmel_pinctrl_data *)dev_get_driver_data(dev); fdt_addr_t addr_base;

- dev = dev_get_parent(dev); addr_base = dev_read_addr(dev); if (addr_base == FDT_ADDR_T_NONE) return -EINVAL;

plat->reg_base = (struct atmel_pio4_port *)addr_base; - plat->slew_rate_support = priv; + plat->slew_rate_support = priv->slew_rate_support;

return 0; }

+static int atmel_pinctrl_bind(struct udevice *dev) +{ + struct udevice *g; + struct driver *drv; + ofnode node = dev_ofnode(dev); + struct atmel_pinctrl_data *priv = (struct atmel_pinctrl_data *)dev_get_driver_data(dev); + + if (!CONFIG_IS_ENABLED(ATMEL_PIO4)) + return 0; + + /* Obtain a handle to the GPIO driver */ + drv = lists_driver_lookup_name("gpio_atmel_pio4"); + if (!drv) + return -ENOENT; + + /* + * Bind the GPIO driver to the pinctrl DT node, together + * with its corresponding driver_data. + */ + return device_bind_with_driver_data(dev, drv, drv->name, + drv->of_match[priv->gdidx].data, + node, &g); +} + +static const struct atmel_pinctrl_data atmel_sama5d2_pinctrl_data = { + .gdidx = 0, +}; + +static const struct atmel_pinctrl_data microchip_sama7g5_pinctrl_data = { + .slew_rate_support = 1, + .gdidx = 1, +}; + static const struct udevice_id atmel_pinctrl_match[] = { - { .compatible = "atmel,sama5d2-pinctrl" }, + { .compatible = "atmel,sama5d2-pinctrl", + .data = (ulong)&atmel_sama5d2_pinctrl_data, }, { .compatible = "microchip,sama7g5-pinctrl", - .data = (ulong)1, }, + .data = (ulong)&microchip_sama7g5_pinctrl_data, }, {} };

@@ -206,6 +260,7 @@ U_BOOT_DRIVER(atmel_pinctrl) = { .name = "pinctrl_atmel_pio4", .id = UCLASS_PINCTRL, .of_match = atmel_pinctrl_match, + .bind = atmel_pinctrl_bind, .probe = atmel_pinctrl_probe, .plat_auto = sizeof(struct atmel_pio4_plat), .ops = &atmel_pinctrl_ops,

-- 2.25.1

Sergiu Moga

4:22 p.m.

New subject: [PATCH 4/4] pinctrl: at91-pio4: Add support for pinctrl config subnodes

Previously, in order for the `pinctrl-*` DT node properties to be properly processed, the pinctrl's subnodes were limited to only having the `pinmux` property as well as other additional properties (slew-rate, bias-disable, etc.). Now, with this patch the pinctrl driver is made to work similarly to the one from Linux. It can now distinguish between one subnode and a subnode with multiple subnodes.

Signed-off-by: Sergiu Moga sergiu.moga@microchip.com --- drivers/pinctrl/pinctrl-at91-pio4.c | 73 ++++++++++++++++++++++++----- 1 file changed, 61 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index e434a38f1f..50e3dd449a 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -15,6 +15,7 @@ #include <linux/bitops.h> #include <linux/io.h> #include <linux/err.h> +#include <dm/uclass-internal.h> #include <mach/atmel_pio4.h>

DECLARE_GLOBAL_DATA_PTR; @@ -151,12 +152,11 @@ static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,

#define MAX_PINMUX_ENTRIES 40

-static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config) +static int atmel_process_config_dev(struct udevice *dev, struct udevice *config) { struct atmel_pio4_plat *plat = dev_get_plat(dev); - struct atmel_pio4_port *bank_base; - const void *blob = gd->fdt_blob; int node = dev_of_offset(config); + struct atmel_pio4_port *bank_base; u32 offset, func, bank, line; u32 cells[MAX_PINMUX_ENTRIES]; u32 i, conf; @@ -164,18 +164,17 @@ static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)

conf = atmel_pinctrl_get_pinconf(config, plat);

- count = fdtdec_get_int_array_count(blob, node, "pinmux", + /* + * The only case where this function returns a negative error value + * is when there is no "pinmux" property attached to this node + */ + count = fdtdec_get_int_array_count(gd->fdt_blob, node, "pinmux", cells, ARRAY_SIZE(cells)); - if (count < 0) { - printf("%s: bad pinmux array %d\n", __func__, count); - return -EINVAL; - } + if (count < 0) + return count;

- if (count > MAX_PINMUX_ENTRIES) { - printf("%s: unsupported pinmux array count %d\n", - __func__, count); + if (count > MAX_PINMUX_ENTRIES) return -EINVAL; - }

for (i = 0 ; i < count; i++) { offset = ATMEL_GET_PIN_NO(cells[i]); @@ -195,6 +194,56 @@ static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config) return 0; }

+static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + int node = dev_of_offset(config); + struct udevice *subconfig; + int subnode, subnode_count = 0, ret; + + /* + * If this function returns a negative error code then that means + * that either the "pinmux" property of the node is missing, which is + * the case for pinctrl nodes that do not have all the pins with the + * same configuration and are split in multiple subnodes, or something + * else went wrong and we have to stop. For the latter case, it would + * mean that the node failed even though it has no subnodes. + */ + ret = atmel_process_config_dev(dev, config); + if (!ret) + return ret; + + /* + * If we reach here, it means that the subnode pinctrl's DT has multiple + * subnodes. If it does not, then something else went wrong in the + * previous call to atmel_process_config_dev. + */ + fdt_for_each_subnode(subnode, gd->fdt_blob, node) { + /* Get subnode as an udevice */ + ret = uclass_find_device_by_of_offset(UCLASS_PINCONFIG, subnode, + &subconfig); + if (ret) + return ret; + + /* + * If this time the function returns an error code on a subnode + * then something is totally wrong so abort. + */ + ret = atmel_process_config_dev(dev, subconfig); + if (ret) + return ret; + + subnode_count++; + } + + /* + * If we somehow got here and we do not have any subnodes, abort. + */ + if (!subnode_count) + return -EINVAL; + + return 0; +} + const struct pinctrl_ops atmel_pinctrl_ops = { .set_state = atmel_pinctrl_set_state, };

-- 2.25.1

Eugen.Hristev＠microchip.com

19 Sep 19 Sep

10:21 a.m.

On 9/1/22 5:22 PM, Sergiu Moga wrote:

...

This has been done in order to align the DT of U-Boot with the DT of Linux. In Linux, a phandle from a '-gpio' DT property is linked to the pinctrl driver, a single driver that handles both pinctrl settings and offers GPIO API to callers. On the other hand, U-Boot redirects such phandle to a corresponding UCLASS_GPIO driver, because U-Boot offers two different types of drivers in this case: UCLASS_PINCTRL which handles pin functions and UCLASS_GPIO which handles gpio requests as a gpio provider. Due to this, we have two drivers in Uboot, but the Devicetree has a single node. Thus, just one of the drivers can be probed for the DT node during platform initialization, before relocation.

Our previous solution in U-Boot was to have a different devicetree: the gpio node has a subnode for the pinctrl driver, which is not compliant with Linux ABI. Furthermore, our documentation for this type of nodes mentions no such gpio compatible.

After this patch, we can no longer add nodes with a gpio compatible in the DT. Thus, in order to link the pinctrl driver to the gpio one, a hook to the bind method of the former in U-Boot has been added and the GPIO related compatibles have been removed to avoid conflict when compatibles are enumerated and bound to drivers during platform start before relocation. The bind method will attach the GPIO driver to the pinctrl DT node so that every phandle coming from '-gpio' DT properties will be redirected to a valid driver attached to the pinctrl DT node.

Furthermore, this fixes a GPIO request issue existent on sama7g5, which was caused by the fact that there was no UCLASS_GPIO driver bound to the pioA node label.

To make the two Devicetrees even more similar (the one from Linux and the one from U-Boot), make the pinctrl driver's node support multiple subnodes for its subnode.

Sergiu Moga (4): ARM: dts: at91: sama5: Align with Linux Devicetree ARM: dts: at91: sama7: Align with Linux Devicetree pinctrl: at91-pio4: Bind GPIO driver to the pinctrl DT node pinctrl: at91-pio4: Add support for pinctrl config subnodes

arch/arm/dts/at91-sama5d27_giantboard.dts | 59 +++-- arch/arm/dts/at91-sama5d27_som1_ek.dts | 80 +++---- .../dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi | 6 +- arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 92 ++++---- arch/arm/dts/at91-sama5d2_icp.dts | 134 ++++++------ arch/arm/dts/at91-sama5d2_ptc_ek.dts | 98 ++++----- arch/arm/dts/at91-sama5d2_xplained.dts | 204 +++++++++--------- arch/arm/dts/at91-sama7g5ek-u-boot.dtsi | 2 +- arch/arm/dts/at91-sama7g5ek.dts | 85 +++++--- arch/arm/dts/sama5d2.dtsi | 9 +- arch/arm/dts/sama5d27_som1.dtsi | 94 ++++---- arch/arm/dts/sama5d27_wlsom1.dtsi | 54 +++-- arch/arm/dts/sama7g5.dtsi | 16 +- drivers/gpio/atmel_pio4.c | 2 - drivers/pinctrl/pinctrl-at91-pio4.c | 138 ++++++++++-- 15 files changed, 592 insertions(+), 481 deletions(-)

Applied to u-boot-at91/next , thanks !

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Eugen.Hristev＠microchip.com
Sergiu Moga