This patch adds a helper function that can be used to interpret most "ranges" properties in the device tree.

It reads the n'th range out of a "ranges" array and returns the node's virtual address of the range, the physical address that range starts at and the size of the range.

Signed-off-by: Alexander Graf agraf@suse.de --- common/fdt_support.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fdt_support.h | 2 ++ 2 files changed, 96 insertions(+)

diff --git a/common/fdt_support.c b/common/fdt_support.c index cc0bf76..fcd2523 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1435,3 +1435,97 @@ u64 fdt_get_base_address(void *fdt, int node)

return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0; } + +/* + * Read a property of size <prop_len>. Currently only supports 1 or 2 cells. + */ +static int fdt_read_prop(const fdt32_t *prop, int prop_len, int cell_off, + uint64_t *val, int cells) +{ + const fdt32_t *prop32 = &prop[cell_off]; + const fdt64_t *prop64 = (const fdt64_t *)&prop[cell_off]; + + if ((cell_off + cells) > prop_len) + return -FDT_ERR_NOSPACE; + + switch (cells) { + case 1: + *val = fdt32_to_cpu(*prop32); + break; + case 2: + *val = fdt64_to_cpu(*prop64); + break; + default: + return -FDT_ERR_NOSPACE; + } + + return 0; +} + +/** + * fdt_read_range - Read a node's n'th range property + * + * @fdt: ptr to device tree + * @node: offset of node + * @n: range index + * @child_addr: pointer to storage for the "child address" field + * @addr: pointer to storage for the CPU view translated physical start + * @len: pointer to storage for the range length + * + * Convenience function that reads and interprets a specific range out of + * a number of the "ranges" property array. + */ +int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr, + uint64_t *addr, uint64_t *len) +{ + int pnode = fdt_parent_offset(fdt, node); + const fdt32_t *ranges; + int pacells; + int acells; + int scells; + int ranges_len; + int cell = 0; + int r = 0; + + /* + * The "ranges" property is an array of + * { <child address> <parent address> <size in child address space> } + * + * All 3 elements can span a diffent number of cells. Fetch their size. + */ + pacells = fdt_getprop_u32_default_node(fdt, pnode, 0, "#address-cells", 1); + acells = fdt_getprop_u32_default_node(fdt, node, 0, "#address-cells", 1); + scells = fdt_getprop_u32_default_node(fdt, node, 0, "#size-cells", 1); + + /* Now try to get the ranges property */ + ranges = fdt_getprop(fdt, node, "ranges", &ranges_len); + if (!ranges) + return -FDT_ERR_NOTFOUND; + ranges_len /= sizeof(uint32_t); + + /* Jump to the n'th entry */ + cell = n * (pacells + acells + scells); + + /* Read <child address> */ + if (child_addr) { + r = fdt_read_prop(ranges, ranges_len, cell, child_addr, + acells); + if (r) + return r; + } + cell += acells; + + /* Read <parent address> */ + if (addr) + *addr = fdt_translate_address(fdt, node, ranges + cell); + cell += pacells; + + /* Read <size in child address space> */ + if (len) { + r = fdt_read_prop(ranges, ranges_len, cell, len, scells); + if (r) + return r; + } + + return 0; +} diff --git a/include/fdt_support.h b/include/fdt_support.h index 3e1be57..b28fae6 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -87,6 +87,8 @@ int fdt_add_edid(void *blob, const char *compat, unsigned char *buf); int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr); u64 fdt_get_base_address(void *fdt, int node); +int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr, + uint64_t *addr, uint64_t *len);

enum fdt_status { FDT_STATUS_OKAY,

The DDR mapping function really is just a generic virtual -> physical mapping function. Generalize it so it can support any virtual starting offset and IO maps just the same.

Signed-off-by: Alexander Graf agraf@suse.de

---

v3 -> v4:

- change tlb_map to return unmapped size and get ram/io as enum rather than bool --- arch/powerpc/cpu/mpc85xx/tlb.c | 47 +++++++++++++++++++++++++++------------- arch/powerpc/include/asm/mmu.h | 8 +++++++ 2 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 8748ecd..fed8df9 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -236,20 +236,26 @@ void init_addr_map(void) } #endif

-unsigned int -setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) +uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, + enum tlb_map_type map_type) { int i; unsigned int tlb_size; - unsigned int wimge = MAS2_M; - unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int wimge; + unsigned int perm; unsigned int max_cam, tsize_mask; - u64 size, memsize = (u64)memsize_in_meg << 20;

+ if (map_type == TLB_MAP_RAM) { + perm = MAS3_SX|MAS3_SW|MAS3_SR; + wimge = MAS2_M; #ifdef CONFIG_SYS_PPC_DDR_WIMGE - wimge = CONFIG_SYS_PPC_DDR_WIMGE; + wimge = CONFIG_SYS_PPC_DDR_WIMGE; #endif - size = min(memsize, CONFIG_MAX_MEM_MAPPED); + } else { + perm = MAS3_SW|MAS3_SR; + wimge = MAS2_I|MAS2_G; + } + if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { /* Convert (4^max) kB to (2^max) bytes */ max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10; @@ -261,11 +267,11 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) }

for (i = 0; size && i < 8; i++) { - int ram_tlb_index = find_free_tlbcam(); + int tlb_index = find_free_tlbcam(); u32 camsize = __ilog2_u64(size) & tsize_mask; - u32 align = __ilog2(ram_tlb_address) & tsize_mask; + u32 align = __ilog2(v_addr) & tsize_mask;

- if (ram_tlb_index == -1) + if (tlb_index == -1) break;

if (align == -2) align = max_cam; @@ -277,18 +283,29 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)

tlb_size = camsize - 10;

- set_tlb(1, ram_tlb_address, p_addr, - MAS3_SX|MAS3_SW|MAS3_SR, wimge, - 0, ram_tlb_index, tlb_size, 1); + set_tlb(1, v_addr, p_addr, perm, wimge, + 0, tlb_index, tlb_size, 1);

size -= 1ULL << camsize; - memsize -= 1ULL << camsize; - ram_tlb_address += 1UL << camsize; + v_addr += 1UL << camsize; p_addr += 1UL << camsize; }

+ return size; +} + +unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, + unsigned int memsize_in_meg) +{ + unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + u64 memsize = (u64)memsize_in_meg << 20; + + memsize = min(memsize, CONFIG_MAX_MEM_MAPPED); + memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM); + if (memsize) print_size(memsize, " left unmapped\n"); + return memsize_in_meg; }

diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index cadaeef..5aa916f 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -509,6 +509,14 @@ extern void print_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); extern void clear_ddr_tlbs(unsigned int memsize_in_meg);

+enum tlb_map_type { + TLB_MAP_RAM, + TLB_MAP_IO, +}; + +extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, + enum tlb_map_type map_type); + extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);

#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \

For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one.

It also provides more PCI slots and is supposed to be enumerated by device tree only.

This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration.

Signed-off-by: Alexander Graf agraf@suse.de

---

v1 -> v2:

- Write device tree offset directly into global variable - use r4 rather than r2 for that - access fdt directly from in-memory copy - remove unneeded header includes - clean up pci enumeration - coding style fixes - populate and only use fdt_addr_r - remove unused exported functions - remove unused TLB0 entries - make TLB1 I/O maps non-executable - remove unused defines in board header - make -kernel boot variables more clear - remove TLB0 invalidation - use tlb1.14 for temporary as=1 map - use CONFIG_SYS_MPC85XX_NO_RESETVEC - store fdt pointer in gd through cpu_init_early_f() - replace fixup_tlb1() with dynamic TLB creation hook

v2 -> v3:

- merge dt patches into this one - Document and rename CONFIG_SYS_USE_DYNAMIC_TLBS - remove CONFIG_DDR_SPD - Reduce PCI message to only base address - Map AS=1 fdt behind CCSRBAR - Use CONFIG_SYS_CCSR_DO_NOT_RELOCATE - remove unnecessary ccsr map - s/cell size/cell count/ - add temporary map define - use fdt_get_base_address() to find region - use new APIs - remove myfdt helpers

v3 -> v4:

- use new tlb map syntax - check that tlb map mapped everything - always save/restore r3 for cpu_init_early_f - remove CONFIG_DYNAMIC_CCSRBAR - make init_tlbs weak and remove all init_tlbs_dynamic() cruft - always map fdt to fixed virtual address - fold together AS=1 fdt map functions - use tlb_map_range for CCSR map - search for PCI based on device type rather than compatible - remove unnecessary cast - call get_linear_ram_size directly - override get_tbclk with timebase-frequency fetching code

v4 -> v5:

- remove CONFIG_MPC85xx from header file, it's already defined on the cmdline - use __weak instead of __attribute__((weak)) - use esel parameter in map_fdt_as() - explicitly define start and end of PCI map range --- arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/cpu.c | 5 +- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 8 +- arch/powerpc/cpu/mpc85xx/start.S | 11 + arch/powerpc/cpu/mpc85xx/tlb.c | 2 +- arch/powerpc/include/asm/config_mpc85xx.h | 4 + board/freescale/qemu-ppce500/Makefile | 9 + board/freescale/qemu-ppce500/qemu-ppce500.c | 348 +++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/qemu-ppce500.h | 206 ++++++++++++++++ 10 files changed, 592 insertions(+), 4 deletions(-) create mode 100644 board/freescale/qemu-ppce500/Makefile create mode 100644 board/freescale/qemu-ppce500/qemu-ppce500.c create mode 100644 include/configs/qemu-ppce500.h

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index ef7637a..4094785 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -102,7 +102,9 @@ obj-y += cpu.o obj-y += cpu_init.o obj-y += cpu_init_early.o obj-y += interrupts.o +ifneq ($(CONFIG_QEMU_E500),y) obj-y += speed.o +endif obj-y += tlb.o obj-y += traps.o

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 3e99b07..2c8126c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -272,7 +272,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifndef CONFIG_SYS_FSL_TBCLK_DIV #define CONFIG_SYS_FSL_TBCLK_DIV 8 #endif -unsigned long get_tbclk (void) +__weak unsigned long get_tbclk (void) { unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;

@@ -338,7 +338,8 @@ void mpc85xx_reginfo(void) !defined(CONFIG_SYS_INIT_L2_ADDR) phys_size_t initdram(int board_type) { -#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ + defined(CONFIG_QEMU_E500) return fsl_ddr_sdram_size(); #else return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 993b8b8..998781b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -79,7 +79,7 @@ void setup_ifc(void) #endif

/* We run cpu_init_early_f in AS = 1 */ -void cpu_init_early_f(void) +void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; int i; @@ -102,6 +102,12 @@ void cpu_init_early_f(void) for (i = 0; i < sizeof(gd_t); i++) ((char *)gd)[i] = 0;

+ /* + * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, + * so we need to populate it before it accesses it. + */ + gd->fdt_blob = fdt; + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 691bd3a..6b0380f 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -78,6 +78,13 @@ _start_e500: li r1,MSR_DE mtmsr r1

+ /* + * If we got an ePAPR device tree pointer passed in as r3, we need that + * later in cpu_init_early_f(). Save it to a safe register before we + * clobber it so that we can fetch it from there later. + */ + mr r24, r3 + #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 mfspr r3,SPRN_SVR rlwinm r3,r3,0,0xff @@ -1142,6 +1149,10 @@ _start_cont: mr r1,r3 /* Transfer to SP(r1) */

GET_GOT + + /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */ + mr r3, r24 + bl cpu_init_early_f

/* switch back to AS = 0 */ diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index fed8df9..129ec66 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -24,7 +24,7 @@ void invalidate_tlb(u8 tlb) mtspr(MMUCSR0, 0x2); }

-void init_tlbs(void) +__weak void init_tlbs(void) { int i;

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index df44451..e376783 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -797,6 +797,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125

+#elif defined(CONFIG_QEMU_E500) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 + #else #error Processor type not defined for this platform #endif diff --git a/board/freescale/qemu-ppce500/Makefile b/board/freescale/qemu-ppce500/Makefile new file mode 100644 index 0000000..2d27492 --- /dev/null +++ b/board/freescale/qemu-ppce500/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += qemu-ppce500.o diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c new file mode 100644 index 0000000..3dbb0cf --- /dev/null +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c @@ -0,0 +1,348 @@ +/* + * Copyright 2007,2009-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/fsl_pci.h> +#include <asm/io.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <netdev.h> +#include <fdtdec.h> +#include <errno.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void *get_fdt_virt(void) +{ + return (void *)CONFIG_SYS_TMPVIRT; +} + +static uint64_t get_fdt_phys(void) +{ + return (uint64_t)(uintptr_t)gd->fdt_blob; +} + +static void map_fdt_as(int esel) +{ + u32 mas0, mas1, mas2, mas3, mas7; + uint64_t fdt_phys = get_fdt_phys(); + unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful; + unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful; + + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0); + mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb); + + write_tlb(mas0, mas1, mas2, mas3, mas7); +} + +uint64_t get_phys_ccsrbar_addr_early(void) +{ + void *fdt = get_fdt_virt(); + uint64_t r; + + /* + * To be able to read the FDT we need to create a temporary TLB + * map for it. + */ + map_fdt_as(10); + r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc")); + disable_tlb(10); + + return r; +} + +int board_early_init_f(void) +{ + return 0; +} + +int checkboard(void) +{ + return 0; +} + +static int pci_map_region(void *fdt, int pci_node, int range_id, + phys_size_t *ppaddr, pci_addr_t *pvaddr, + pci_size_t *psize, ulong *pmap_addr) +{ + uint64_t addr; + uint64_t size; + ulong map_addr; + int r; + + r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size); + if (r) + return r; + + if (ppaddr) + *ppaddr = addr; + if (psize) + *psize = size; + + if (!pmap_addr) + return 0; + + map_addr = *pmap_addr; + + /* Align map_addr */ + map_addr += size - 1; + map_addr &= ~(size - 1); + + if (map_addr + size >= CONFIG_SYS_PCI_MAP_END) + return -1; + + /* Map virtual memory for range */ + assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO)); + *pmap_addr = map_addr + size; + + if (pvaddr) + *pvaddr = map_addr; + + return 0; +} + +void pci_init_board(void) +{ + struct pci_controller *pci_hoses; + void *fdt = get_fdt_virt(); + int pci_node = -1; + int pci_num = 0; + int pci_count = 0; + ulong map_addr; + + puts("\n"); + + /* Start MMIO and PIO range maps above RAM */ + map_addr = CONFIG_SYS_PCI_MAP_START; + + /* Count and allocate PCI buses */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + while (pci_node != -FDT_ERR_NOTFOUND) { + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + pci_count++; + } + + if (pci_count) { + pci_hoses = malloc(sizeof(struct pci_controller) * pci_count); + } else { + printf("PCI: disabled\n\n"); + return; + } + + /* Spawn PCI buses based on device tree */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + while (pci_node != -FDT_ERR_NOTFOUND) { + struct fsl_pci_info pci_info = { }; + const fdt32_t *reg; + int r; + + reg = fdt_getprop(fdt, pci_node, "reg", NULL); + pci_info.regs = fdt_translate_address(fdt, pci_node, reg); + + /* Map MMIO range */ + r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL, + &pci_info.mem_size, &map_addr); + if (r) + break; + + /* Map PIO range */ + r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL, + &pci_info.io_size, &map_addr); + if (r) + break; + + /* + * The PCI framework finds virtual addresses for the buses + * through our address map, so tell it the physical addresses. + */ + pci_info.mem_bus = pci_info.mem_phys; + pci_info.io_bus = pci_info.io_phys; + + /* Instantiate */ + pci_info.pci_num = pci_num + 1; + + fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs); + printf("PCI: base address %lx\n", pci_info.regs); + + fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num); + + /* Jump to next PCI node */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + pci_num++; + } + + puts("\n"); +} + +int last_stage_init(void) +{ + void *fdt = get_fdt_virt(); + int len = 0; + const uint64_t *prop; + int chosen; + + chosen = fdt_path_offset(fdt, "/chosen"); + if (chosen < 0) { + printf("Couldn't find /chosen node in fdt\n"); + return -EIO; + } + + /* -kernel boot */ + prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len); + if (prop && (len >= 8)) + setenv_hex("qemu_kernel_addr", *prop); + + /* Give the user a variable for the host fdt */ + setenv_hex("fdt_addr_r", (ulong)fdt); + + return 0; +} + +static uint64_t get_linear_ram_size(void) +{ + void *fdt = get_fdt_virt(); + const void *prop; + int memory; + int len; + + memory = fdt_path_offset(fdt, "/memory"); + prop = fdt_getprop(fdt, memory, "reg", &len); + + if (prop && len >= 16) + return *(uint64_t *)(prop+8); + + panic("Couldn't determine RAM size"); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} +#endif + +void print_laws(void) +{ + /* We don't emulate LAWs yet */ +} + +phys_size_t fixed_sdram(void) +{ + return get_linear_ram_size(); +} + +phys_size_t fsl_ddr_sdram_size(void) +{ + return get_linear_ram_size(); +} + +void init_tlbs(void) +{ + phys_size_t ram_size; + + /* + * Create a temporary AS=1 map for the fdt + * + * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves + * which was only 4k big. This way we don't have to clear any other maps. + */ + map_fdt_as(0); + + /* Fetch RAM size from the fdt */ + ram_size = get_linear_ram_size(); + + /* And remove our fdt map again */ + disable_tlb(0); + + /* Create an internal map of manually created TLB maps */ + init_used_tlb_cams(); + + /* Create a dynamic AS=0 CCSRBAR mapping */ + assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + 1024 * 1024, TLB_MAP_IO)); + + /* Create a RAM map that spans all accessible RAM */ + setup_ddr_tlbs(ram_size >> 20); + + /* Create a map for the TLB */ + assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(), + 1024 * 1024, TLB_MAP_RAM)); +} + +void init_laws(void) +{ + /* We don't emulate LAWs yet */ +} + +static uint32_t get_cpu_freq(void) +{ + void *fdt = get_fdt_virt(); + int cpus_node = fdt_path_offset(fdt, "/cpus"); + int cpu_node = fdt_first_subnode(fdt, cpus_node); + const char *prop = "clock-frequency"; + return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); +} + +void get_sys_info(sys_info_t *sys_info) +{ + int freq = get_cpu_freq(); + + memset(sys_info, 0, sizeof(sys_info_t)); + sys_info->freq_systembus = freq; + sys_info->freq_ddrbus = freq; + sys_info->freq_processor[0] = freq; +} + +int get_clocks (void) +{ + sys_info_t sys_info; + + get_sys_info(&sys_info); + + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + gd->arch.lbc_clk = sys_info.freq_ddrbus; + + return 0; +} + +unsigned long get_tbclk (void) +{ + void *fdt = get_fdt_virt(); + int cpus_node = fdt_path_offset(fdt, "/cpus"); + int cpu_node = fdt_first_subnode(fdt, cpus_node); + const char *prop = "timebase-frequency"; + return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + sys_info_t sys_info; + get_sys_info(&sys_info); + return sys_info.freq_systembus; +} diff --git a/boards.cfg b/boards.cfg index b4203f1..ecf1c17 100644 --- a/boards.cfg +++ b/boards.cfg @@ -963,6 +963,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf agraf@suse.de Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach eibach@gdsys.de Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach eibach@gdsys.de Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach eibach@gdsys.de diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h new file mode 100644 index 0000000..10e014d --- /dev/null +++ b/include/configs/qemu-ppce500.h @@ -0,0 +1,206 @@ +/* + * Copyright 2011-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Corenet DS style board configuration file + */ +#ifndef __QEMU_PPCE500_H +#define __QEMU_PPCE500_H + +#define CONFIG_CMD_REGINFO + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_QEMU_E500 + +#undef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */ + +#define CONFIG_SYS_MPC85XX_NO_RESETVEC + +#define CONFIG_SYS_RAMBOOT + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* Needed to fill the ccsrbar pointer */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* Virtual address to CCSRBAR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +/* Physical address should be a function call */ +#ifndef __ASSEMBLY__ +extern unsigned long long get_phys_ccsrbar_addr_early(void); +#endif +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE + +/* Virtual address range for PCI region maps */ +#define CONFIG_SYS_PCI_MAP_START 0x80000000 +#define CONFIG_SYS_PCI_MAP_END 0xe8000000 + +/* Virtual address to a temporary map if we need it (max 128MB) */ +#define CONFIG_SYS_TMPVIRT 0xe8000000 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 0 + +#define CONFIG_SYS_CLK_FREQ 33000000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_HWCONFIG + +#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +#define CONFIG_LBA48 +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 + +/* + * Environment + */ +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ + +#define CONFIG_LAST_STAGE_INIT + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTCOMMAND \ + "test -n "$qemu_kernel_addr" && bootm $qemu_kernel_addr - $fdt_addr_r\0" + +#endif /* __QEMU_PPCE500_H */