From: Jean-Michel CASAUBON jean-michel.casaubon@csgroup.eu

Remove a stray semicolon in MCR3000 board environment.

Signed-off-by: Jean-Michel CASAUBON jean-michel.casaubon@csgroup.eu Reviewed-by: DUBOIS Hugo hugo.dubois.ext@csgroup.eu Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- board/cssi/mcr3000/mcr3000.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/cssi/mcr3000/mcr3000.env b/board/cssi/mcr3000/mcr3000.env index 372ab09094..380c10c4ce 100644 --- a/board/cssi/mcr3000/mcr3000.env +++ b/board/cssi/mcr3000/mcr3000.env @@ -8,7 +8,7 @@ dhcp_ip=ip=:::::eth0:dhcp console_args=console=ttyCPM0,115200N8 loadkernel=ubi part nand0;ubifsmount ubi0;ubifsload ${loadaddr} /boot/${filename};ubifsumount; ubi detach bootcmd=run flashboot -flashboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;${ofl_args}; run loadkernel; bootm ${loadaddr} +flashboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off ${ofl_args}; run loadkernel; bootm ${loadaddr} tftpboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm ${loadaddr} dhcpboot=dhcp ${loadaddr} ${filename};setenv bootargs ${console_args} ${dhcp_ip} ${ofl_args}; bootm ${loadaddr} update=echo 'Updating ubi image'; if tftp 0x2000 $ubifile; then nand erase.chip; nand write 0x2000 0x00 $filesize; fi

From: Jean-Michel CASAUBON jean-michel.casaubon@csgroup.eu

HUSH shell is not always wanted/desirable.

Add missing braces in environment in order to allow use without HUSH shell.

Signed-off-by: Jean-Michel CASAUBON jean-michel.casaubon@csgroup.eu Cc: DUBOIS Hugo hugo.dubois.ext@csgroup.eu Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- board/cssi/cmpc885/cmpc885.env | 4 ++-- board/cssi/cmpcpro/cmpcpro.env | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/cssi/cmpc885/cmpc885.env b/board/cssi/cmpc885/cmpc885.env index 51ab5ce2cf..570117cd36 100644 --- a/board/cssi/cmpc885/cmpc885.env +++ b/board/cssi/cmpc885/cmpc885.env @@ -2,6 +2,6 @@ loadaddr=0x1a00000 filename=cmpc885.itb console_args=console=ttyCPM0,115200N8 loadkernel=ubi part nand0;ubifsmount ubi0;ubifsload ${loadaddr} /boot/${filename};ubifsumount; ubi detach -flashboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm $loadaddr#$config -tftpboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename};bootm $loadaddr#$config +flashboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm ${loadaddr}#${config} +tftpboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename};bootm ${loadaddr}#${config} update=echo 'Updating ubi image'; if tftp $loadaddr $ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi; diff --git a/board/cssi/cmpcpro/cmpcpro.env b/board/cssi/cmpcpro/cmpcpro.env index 7394b8386e..47b436ff6b 100644 --- a/board/cssi/cmpcpro/cmpcpro.env +++ b/board/cssi/cmpcpro/cmpcpro.env @@ -3,6 +3,6 @@ filename=cmpcpro.itb netdev=eth0 console_args=console=ttyS0,115200N8 loadkernel=ubi part nand0;ubifsmount ubi0; ubifsload ${loadaddr} /boot/${filename}; ubifsumount; ubi detach -flashboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm $loadaddr#$config -tftpboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm $loadaddr#$config +flashboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm ${loadaddr}#${config} +tftpboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm ${loadaddr}#${config} update=echo 'Updating ubi image'; mw.w 90000040 0x000E 1; if tftp $loadaddr $ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi;

From: Hugo Dubois hugo.dubois.ext@csgroup.eu

CMPC885 board can be pluged on a mother board with fibre interface, so fibre interface MAC address must be initialised for that case.

Signed-off-by: Hugo Dubois hugo.dubois.ext@csgroup.eu Reviewed-by: CASAUBON Jean Michel jean-michel.casaubon@csgroup.eu Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- board/cssi/cmpc885/cmpc885.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index e11cfafaa5..49c13056ed 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -114,8 +114,10 @@ static int setup_mac(void) if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0) eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1);

- if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0) + if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0) { eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2); + eth_env_set_enetaddr("eth2addr", din + EE_OFF_MAC2); + }

return 0; }

xfer ops can be passed a NULL input or output buffer. At the time being the driver ignores it and overwrites memory at 0.

Define a dummy buffer and use it when either input or output buffer is NULL. Bail out when both are NULL as it shouldn't.

Also increase MAX_BUFFER len to 32k as the current is pretty low.

Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- drivers/spi/mpc8xx_spi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index 5c8d760935..2aa9c7d5df 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -29,7 +29,7 @@ #define CPM_SPI_BASE_RX CPM_SPI_BASE #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))

-#define MAX_BUFFER 0x104 +#define MAX_BUFFER 0x8000 /* Max possible is 0xffff. We want power of 2 */

struct mpc8xx_priv { spi_t __iomem *spi; @@ -37,6 +37,8 @@ struct mpc8xx_priv { int max_cs; };

+static char dummy_buffer[MAX_BUFFER]; + static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod) { return 0; @@ -154,6 +156,8 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen, int tm; size_t count = (bitlen + 7) / 8;

+ if (!din && !dout) + return -EINVAL; if (count > MAX_BUFFER) return -EINVAL;

@@ -165,12 +169,12 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen, mpc8xx_spi_cs_activate(dev);

/* Setting tx bd status and data length */ - out_be32(&tbdf->cbd_bufaddr, (ulong)dout); + out_be32(&tbdf->cbd_bufaddr, dout ? (ulong)dout : (ulong)dummy_buffer); out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); out_be16(&tbdf->cbd_datlen, count);

/* Setting rx bd status and data length */ - out_be32(&rbdf->cbd_bufaddr, (ulong)din); + out_be32(&rbdf->cbd_bufaddr, din ? (ulong)din : (ulong)dummy_buffer); out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */

MCR3000 board has some components tied to the SPI bus, like the Texas Instruments LM74 temperature sensor.

Add support for SPI bus. The SPI chipselects are a bit special in the way that they are driven by 3 bits in a register of the board's CPLD where the value writen in those bits exclusively activates one of the 7 possible chipselects and value 0 sets all chipselets to inactive.

So add a special GPIO driver that simulates GPIOs for those chipselect.

Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- arch/powerpc/dts/mcr3000.dts | 31 +++++++++ board/cssi/mcr3000/Makefile | 1 + board/cssi/mcr3000/mcr3000.c | 5 ++ board/cssi/mcr3000/mcr3000_gpio.c | 109 ++++++++++++++++++++++++++++++ configs/MCR3000_defconfig | 5 ++ 5 files changed, 151 insertions(+) create mode 100644 board/cssi/mcr3000/mcr3000_gpio.c

diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts index c4d7737bc6..edcd8358d0 100644 --- a/arch/powerpc/dts/mcr3000.dts +++ b/arch/powerpc/dts/mcr3000.dts @@ -26,6 +26,37 @@ timeout-sec = <2>; hw_margin_ms = <1000>; }; + + spi: spi@aa0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8xx-spi"; + }; + }; + + localbus@ff000100 { + compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xff000100 0x40>; // ORx and BRx register + + ranges = <0 0 0x04000000 0x04000000 // BOOT + 1 0 0x00000000 0x04000000 // SDRAM + 2 0 0x08000000 0x04000000 // RAMDP + 3 0 0x0C000000 0x04000000 // NAND + 4 0 0x10000000 0x04000000 // Periphs + 5 0 0x14000000 0x04000000 // FPGA + 6 0 0x18000000 0x04000000 // mezzanine + 7 0 0x1c000000 0x04000000>; // DSP + + csspi: gpio-controller@2 { + #gpio-cells = <2>; + compatible = "s3k,mcr3000-cpld-csspi"; + reg = <4 0x802 2>; + gpio-controller; + }; };

SERIAL: smc@0 { diff --git a/board/cssi/mcr3000/Makefile b/board/cssi/mcr3000/Makefile index 7803016af3..846fd680e9 100644 --- a/board/cssi/mcr3000/Makefile +++ b/board/cssi/mcr3000/Makefile @@ -6,3 +6,4 @@

obj-y += mcr3000.o obj-$(CONFIG_CMD_NAND) += nand.o +obj-$(CONFIG_MPC8XX_SPI) += mcr3000_gpio.o diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c index 8857c9e42c..537d7fa124 100644 --- a/board/cssi/mcr3000/mcr3000.c +++ b/board/cssi/mcr3000/mcr3000.c @@ -116,6 +116,11 @@ int misc_init_r(void) clrbits_be16(&iop->iop_pcpar, 0x4); clrbits_be16(&iop->iop_pcdir, 0x4);

+ /* Activate SPI */ + clrsetbits_be32(&immr->im_cpm.cp_pbpar, 0x1, 0xe); + setbits_be32(&immr->im_cpm.cp_pbdir, 0xf); + clrbits_be32(&immr->im_cpm.cp_pbdat, 0x1); + /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */ if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0) env_set("bootdelay", "60"); diff --git a/board/cssi/mcr3000/mcr3000_gpio.c b/board/cssi/mcr3000/mcr3000_gpio.c new file mode 100644 index 0000000000..2bba14e6e5 --- /dev/null +++ b/board/cssi/mcr3000/mcr3000_gpio.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 CS GROUP France + * Christophe Leroy christophe.leroy@csgroup.eu + */ + +#include <asm/io.h> +#include <dm.h> +#include <mapmem.h> +#include <asm/gpio.h> +#include <malloc.h> + +#include "../common/common.h" + +struct mcr3000_spi_gpio_plat { + ulong addr; +}; + +struct mcr3000_spi_gpio_data { + void __iomem *base; +}; + +static int mcr3000_spi_gpio_set_value(struct udevice *dev, uint gpio, int value) +{ + struct mcr3000_spi_gpio_data *data = dev_get_priv(dev); + + if (value) + clrsetbits_be16(data->base, 7 << 5, (gpio & 7) << 5); + else + clrbits_be16(data->base, 7 << 5); + + return 0; +} + +static int mcr3000_spi_gpio_get_value(struct udevice *dev, uint gpio) +{ + struct mcr3000_spi_gpio_data *data = dev_get_priv(dev); + + return gpio == ((in_be16(data->base) >> 5) & 7); +} + +static int mcr3000_spi_gpio_direction_input(struct udevice *dev, uint gpio) +{ + return 0; +} + +static int mcr3000_spi_gpio_get_function(struct udevice *dev, uint gpio) +{ + return GPIOF_OUTPUT; +} + +static int mcr3000_spi_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct mcr3000_spi_gpio_plat *plat = dev_get_plat(dev); + fdt_addr_t addr; + u32 reg[2]; + + dev_read_u32_array(dev, "reg", reg, 2); + addr = dev_translate_address(dev, reg); + + plat->addr = addr; + + return 0; +} + +static int mcr3000_spi_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mcr3000_spi_gpio_data *data = dev_get_priv(dev); + struct mcr3000_spi_gpio_plat *plat = dev_get_plat(dev); + char name[32], *str; + + data->base = map_sysmem(plat->addr, 2); + + snprintf(name, sizeof(name), "CHIPSELECT@%lx_", plat->addr); + str = strdup(name); + + if (!str) + return -ENOMEM; + + uc_priv->bank_name = str; + uc_priv->gpio_count = 16; + + return 0; +} + +static const struct dm_gpio_ops gpio_mcr3000_spi_ops = { + .get_value = mcr3000_spi_gpio_get_value, + .set_value = mcr3000_spi_gpio_set_value, + .direction_input = mcr3000_spi_gpio_direction_input, + .direction_output = mcr3000_spi_gpio_set_value, + .get_function = mcr3000_spi_gpio_get_function, +}; + +static const struct udevice_id mcr3000_spi_gpio_ids[] = { + { .compatible = "s3k,mcr3000-cpld-csspi"}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mcr3000_spi_gpio) = { + .name = "mcr3000_spi_chipselect", + .id = UCLASS_GPIO, + .ops = &gpio_mcr3000_spi_ops, + .of_to_plat = mcr3000_spi_gpio_ofdata_to_platdata, + .plat_auto = sizeof(struct mcr3000_spi_gpio_plat), + .of_match = mcr3000_spi_gpio_ids, + .probe = mcr3000_spi_gpio_probe, + .priv_auto = sizeof(struct mcr3000_spi_gpio_data), +}; diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 8a88fb445c..ce34c2aa88 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0x4000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="mcr3000" CONFIG_SYS_MONITOR_LEN=327680 CONFIG_SYS_CLK_FREQ=132000000 @@ -91,6 +92,7 @@ CONFIG_SYS_OR6_PRELIM=0xFFFF0908 CONFIG_SYS_BR7_PRELIM_BOOL=y CONFIG_SYS_BR7_PRELIM=0x1C000001 CONFIG_SYS_OR7_PRELIM=0xFFFF810A +CONFIG_MPC8XX_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_MTD=y @@ -102,6 +104,9 @@ CONFIG_SYS_MAX_FLASH_SECT=35 CONFIG_MTD_RAW_NAND=y CONFIG_MPC8XX_FEC=y CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MPC8XX_SPI=y CONFIG_WDT=y CONFIG_WDT_MPC8xxx_BME=y CONFIG_LZMA=y

SDMA configuration register needs to be set up only once and doesn't belong to drivers. Also, the value to be used is different on mpc885.

So do the init in cpu_init_f() with 0x40 for mpc885 and 0x1 for others.

Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- arch/powerpc/cpu/mpc8xx/cpu_init.c | 6 ++++++ drivers/spi/mpc8xx_spi.c | 4 ---- 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index aac4203a6e..d1abe8f00b 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -92,6 +92,12 @@ void cpu_init_f(immap_t __iomem *immr) CONFIG_SYS_PLPRCR); #endif

+ /* Set SDMA configuration register */ + if (IS_ENABLED(CONFIG_MPC885)) + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0040); + else + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); + /* * Memory Controller: */ diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index 2aa9c7d5df..0d142f12e9 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -103,10 +103,6 @@ static int mpc8xx_spi_probe(struct udevice *dev) while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) ;

-/* 5 */ - /* Set SDMA configuration register */ - out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); - /* 6 */ /* Set to big endian. */ out_8(&spi->spi_tfcr, SMC_EB);

On CPM, the RISC core is a lot more efficiant when doing transfers in 16-bits chunks than in 8-bits chunks, but unfortunately the words need to be byte swapped.

So, for large tranfers with an even size, allocate a temporary buffer and byte-swap data before and after transfer.

This change allows setting higher speed for transfer. For instance on an MPC 8xx (CPM1 comms RISC processor), the documentation tells that transfer in byte mode at 1 kbit/s uses 0.200% of CPM load at 25 MHz while a word transfer at the same speed uses 0.032% of CPM load. This means the speed can be 6 times higher in word mode for the same CPM load.

For small transfers, the load reduction is not worth the CPU load required to allocate the temporary buffer, so do it only when data size is over 64 bytes.

Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- drivers/spi/mpc8xx_spi.c | 44 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index a193ac711b..b1abfbf4fc 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -18,6 +18,7 @@

#include <common.h> #include <dm.h> +#include <malloc.h> #include <mpc8xx.h> #include <spi.h> #include <linux/delay.h> @@ -30,6 +31,7 @@ #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))

#define MAX_BUFFER 0x8000 /* Max possible is 0xffff. We want power of 2 */ +#define MIN_HWORD_XFER 64 /* Minimum size for 16 bits transfer */

struct mpc8xx_priv { spi_t __iomem *spi; @@ -149,23 +151,46 @@ static int mpc8xx_spi_xfer_one(struct udevice *dev, size_t count, immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cp = &immr->im_cpm; cbd_t __iomem *tbdf, *rbdf; + void *bufout, *bufin; + u16 spmode_len; int tm;

tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];

+ if (!(count & 1) && count >= MIN_HWORD_XFER) { + spmode_len = SPMODE_LEN(16); + if (dout) { + int i; + + bufout = malloc(count); + for (i = 0; i < count; i += 2) + *(u16 *)(bufout + i) = swab16(*(u16 *)(dout + i)); + } else { + bufout = NULL; + } + if (din) + bufin = malloc(count); + else + bufin = NULL; + } else { + spmode_len = SPMODE_LEN(8); + bufout = (void *)dout; + bufin = din; + } + /* Setting tx bd status and data length */ - out_be32(&tbdf->cbd_bufaddr, dout ? (ulong)dout : (ulong)dummy_buffer); + out_be32(&tbdf->cbd_bufaddr, bufout ? (ulong)bufout : (ulong)dummy_buffer); out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); out_be16(&tbdf->cbd_datlen, count);

/* Setting rx bd status and data length */ - out_be32(&rbdf->cbd_bufaddr, din ? (ulong)din : (ulong)dummy_buffer); + out_be32(&rbdf->cbd_bufaddr, bufin ? (ulong)bufin : (ulong)dummy_buffer); out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */

clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR | - SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8)); + SPMODE_EN | spmode_len | SPMODE_PM(0x8)); out_8(&cp->cp_spim, 0); /* Mask all SPI events */ out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */

@@ -188,6 +213,19 @@ static int mpc8xx_spi_xfer_one(struct udevice *dev, size_t count, if (tm >= 1000) return -ETIMEDOUT;

+ if (!(count & 1) && count > MIN_HWORD_XFER) { + if (dout) + free(bufout); + if (din) { + int i; + + bufout = malloc(count); + for (i = 0; i < count; i += 2) + *(u16 *)(din + i) = swab16(*(u16 *)(bufin + i)); + free(bufin); + } + } + return 0; }

Instead of cross using cross-directory makefile directives, add a Makefile in board/cssi/common/ directory in order to benefit from HAVE_VENDOR_COMMON_LIB logic.

Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- board/cssi/cmpc885/Makefile | 2 +- board/cssi/cmpcpro/Makefile | 2 +- board/cssi/common/Makefile | 8 ++++++++ 3 files changed, 10 insertions(+), 2 deletions(-) create mode 100644 board/cssi/common/Makefile

diff --git a/board/cssi/cmpc885/Makefile b/board/cssi/cmpc885/Makefile index baf9e5ab4f..6c055097cd 100644 --- a/board/cssi/cmpc885/Makefile +++ b/board/cssi/cmpc885/Makefile @@ -5,6 +5,6 @@ # Christophe Leroy christophe.leroy@c-s.fr #

-obj-y += cmpc885.o ../common/common.o +obj-y += cmpc885.o obj-y += sdram.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/cssi/cmpcpro/Makefile b/board/cssi/cmpcpro/Makefile index 73ff451ea1..30837781af 100644 --- a/board/cssi/cmpcpro/Makefile +++ b/board/cssi/cmpcpro/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y += cmpcpro.o nand.o ../common/common.o +obj-y += cmpcpro.o nand.o diff --git a/board/cssi/common/Makefile b/board/cssi/common/Makefile new file mode 100644 index 0000000000..973582639e --- /dev/null +++ b/board/cssi/common/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 CS GROUP France +# Christophe Leroy christophe.leroy@csgroup.eu +# + +obj-$(CONFIG_TARGET_CMPC885) += common.o +obj-$(CONFIG_TARGET_CMPCPRO) += common.o

MCR boards are plugged in racks. The position in the rack can be read in a register.

For MCR3000, that's provided by the FPGA so check it is loaded before reading the address.

For the other boards, the FPGA is loaded by hardware so it can be read inconditionnaly.

Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu --- board/cssi/common/common.c | 6 +++++- board/cssi/mcr3000/mcr3000.c | 7 ++++++- 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c index 6848efd43b..0292a9016e 100644 --- a/board/cssi/common/common.c +++ b/board/cssi/common/common.c @@ -164,7 +164,7 @@ int checkboard_common(void)

void misc_init_r_common(void) { - u8 tmp, far_id; + u8 tmp, far_id, addr; int count = 3;

switch (in_8(ADDR_FPGA_R_BASE)) { @@ -173,6 +173,10 @@ void misc_init_r_common(void) if ((in_8(ADDR_FPGA_R_BASE + 0x31) & FPGA_R_ACQ_AL_FAV) == 0) env_set("bootdelay", "60");

+ addr = in_8(ADDR_FPGA_R_BASE + 0x43); + printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n", + addr, addr >> 7, (addr >> 4) & 7, addr & 15); + env_set("config", CFG_BOARD_MCR3000_2G); env_set("hostname", CFG_BOARD_MCR3000_2G); break; diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c index 15a2d0d946..48e82a902d 100644 --- a/board/cssi/mcr3000/mcr3000.c +++ b/board/cssi/mcr3000/mcr3000.c @@ -167,7 +167,12 @@ int misc_init_r(void) setbits_be32(&immr->im_cpm.cp_pbdir, 0xf); clrbits_be32(&immr->im_cpm.cp_pbdat, 0x1);

- load_fpga(); + if (!load_fpga()) { + u8 addr = in_be16((void *)0x1400009c); + + printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n", + addr, addr >> 7, (addr >> 4) & 7, addr & 15); + }

/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */ if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)