[U-Boot] RFC Pin Configuration Device Tree Bindings for Altera Arria10 SOCFPGA
Altera Arria10 SOCFPGA Pin Configuration Bindings
This document describes device tree bindings required to perform configuration of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to be compact and easy to be consumed only by a SPL running in a small on-chip ram before external memory is available. The Arria10 SOCFPGA does not support dynamic modification of the pin configuration.
Each set of pins is represented by its own subnode. For each subnode, the altr,pinmux-regs data will be written to sequential 32 bit addresses starting at the address in the reg property.
Required properties: - compatible : Must be "altr,arria10-pinmux" for Arria10 SOCFPGA - one subnode for each set of pins to be configured
Required subnode properties: - reg : The start address to write pinmux-data as 32 bit quantities and the number of bytes of registers to be written. - altr,pinmux-regs : Pin configuration data to be written to registers
Example:
pinmux@0xffd07000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,arria10-pinmux"; shared { reg = <0xffd07000 0x000000c0>; altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF>; }; dedicated { reg = <0xffd07200 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0xF 0xF 0xF 0xF 0xF 0xD 0xD>; }; dedicated_cfg { reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; }; };
Hi!
Altera Arria10 SOCFPGA Pin Configuration Bindings
This document describes device tree bindings required to perform configuration of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to be compact and easy to be consumed only by a SPL running in a small on-chip ram before external memory is available. The Arria10 SOCFPGA does not support dynamic modification of the pin configuration.
Each set of pins is represented by its own subnode. For each subnode, the altr,pinmux-regs data will be written to sequential 32 bit addresses starting at the address in the reg property.
These bindings will be incompatible with pin muxing on rest of systems, right?
Do we really want to parse DT in SPL? Should we parse the DT during build for the SPL?
Pavel
Required properties:
- compatible : Must be "altr,arria10-pinmux" for Arria10 SOCFPGA
- one subnode for each set of pins to be configured
Required subnode properties:
- reg : The start address to write pinmux-data as 32 bit quantities and the number of bytes of registers to be written.
- altr,pinmux-regs : Pin configuration data to be written to registers
Example:
pinmux@0xffd07000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,arria10-pinmux"; shared { reg = <0xffd07000 0x000000c0>; altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF>; }; dedicated { reg = <0xffd07200 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0xF 0xF 0xF 0xF 0xF 0xD 0xD>; }; dedicated_cfg { reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; }; };
Hi,
On 3 December 2014 at 06:48, Pavel Machek pavel@ucw.cz wrote:
Hi!
Altera Arria10 SOCFPGA Pin Configuration Bindings
This document describes device tree bindings required to perform configuration of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to be compact and easy to be consumed only by a SPL running in a small on-chip ram before external memory is available. The Arria10 SOCFPGA does not support dynamic modification of the pin configuration.
Each set of pins is represented by its own subnode. For each subnode, the altr,pinmux-regs data will be written to sequential 32 bit addresses starting at the address in the reg property.
These bindings will be incompatible with pin muxing on rest of systems, right?
Do we really want to parse DT in SPL? Should we parse the DT during build for the SPL?
PavelRequired properties:
- compatible : Must be "altr,arria10-pinmux" for Arria10 SOCFPGA
- one subnode for each set of pins to be configured
Required subnode properties:
- reg : The start address to write pinmux-data as 32 bit quantities and the number of bytes of registers to be written.
- altr,pinmux-regs : Pin configuration data to be written to registers
Example:
pinmux@0xffd07000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,arria10-pinmux"; shared { reg = <0xffd07000 0x000000c0>; altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF>; }; dedicated { reg = <0xffd07200 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0xF 0xF 0xF 0xF 0xF 0xD 0xD>; }; dedicated_cfg { reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; }; };
Does this match the kernel? Or does the kernel have no such binding yet?
We can support this in SPL if required.
Regards, Simon
+CC: Matthew Gerlach
Not sure why the original submitter was left on this response.
On 12/3/14, 11:36 AM, Simon Glass wrote:
Hi,
On 3 December 2014 at 06:48, Pavel Machek pavel@ucw.cz wrote:
Hi!
Altera Arria10 SOCFPGA Pin Configuration Bindings
This document describes device tree bindings required to perform configuration of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to be compact and easy to be consumed only by a SPL running in a small on-chip ram before external memory is available. The Arria10 SOCFPGA does not support dynamic modification of the pin configuration.
Each set of pins is represented by its own subnode. For each subnode, the altr,pinmux-regs data will be written to sequential 32 bit addresses starting at the address in the reg property.
These bindings will be incompatible with pin muxing on rest of systems, right?
Do we really want to parse DT in SPL? Should we parse the DT during build for the SPL?
PavelRequired properties:
- compatible : Must be "altr,arria10-pinmux" for Arria10 SOCFPGA
- one subnode for each set of pins to be configured
Required subnode properties:
- reg : The start address to write pinmux-data as 32 bit quantities and the number of bytes of registers to be written.
- altr,pinmux-regs : Pin configuration data to be written to registers
Example:
pinmux@0xffd07000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,arria10-pinmux"; shared { reg = <0xffd07000 0x000000c0>; altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF>; }; dedicated { reg = <0xffd07200 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0xF 0xF 0xF 0xF 0xF 0xD 0xD>; }; dedicated_cfg { reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; }; };
Does this match the kernel? Or does the kernel have no such binding yet?
We can support this in SPL if required.
Regards, Simon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi,
________________________________________ From: sjg@google.com sjg@google.com on behalf of Simon Glass sjg@chromium.org Sent: Wednesday, December 3, 2014 9:36 AM To: Pavel Machek Cc: Matthew Gerlach; u-boot@lists.denx.de Subject: Re: [U-Boot] RFC Pin Configuration Device Tree Bindings for Altera Arria10 SOCFPGA
Hi,
On 3 December 2014 at 06:48, Pavel Machek pavel@ucw.cz wrote:
Hi!
Altera Arria10 SOCFPGA Pin Configuration Bindings
This document describes device tree bindings required to perform configuration of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to be compact and easy to be consumed only by a SPL running in a small on-chip ram before external memory is available. The Arria10 SOCFPGA does not support dynamic modification of the pin configuration.
Each set of pins is represented by its own subnode. For each subnode, the altr,pinmux-regs data will be written to sequential 32 bit addresses starting at the address in the reg property.
These bindings will be incompatible with pin muxing on rest of systems, right?
The pin muxing for the Arria 10 is completely different than the Cyclone5/Arria5 chip family.
Do we really want to parse DT in SPL? Should we parse the DT during build for the SPL?
Pavel
The on-chip ram for the Arria10 is 256k. We are hoping to have fewer SPL binaries and use device trees for configuration.
Required properties:
- compatible : Must be "altr,arria10-pinmux" for Arria10 SOCFPGA
- one subnode for each set of pins to be configured
Required subnode properties:
- reg : The start address to write pinmux-data as 32 bit quantities and the number of bytes of registers to be written.
- altr,pinmux-regs : Pin configuration data to be written to registers
Example:
pinmux@0xffd07000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,arria10-pinmux"; shared { reg = <0xffd07000 0x000000c0>; altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF>; }; dedicated { reg = <0xffd07200 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0xF 0xF 0xF 0xF 0xF 0xD 0xD>; }; dedicated_cfg { reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; }; };
Does this match the kernel? Or does the kernel have no such binding yet?
There are no such bindings in the kernel yet. Dynamic pinmuxing is not supported by the Arria 10; so we don't anticipate the kernel needing pinmux information.
We can support this in SPL if required.
Our prototyping is currently doing some device tree parsing.
Regards, Simon
Hi,
On 3 December 2014 at 09:49, Matthew Gerlach mgerlach@opensource.altera.com wrote:
Hi,
From: sjg@google.com sjg@google.com on behalf of Simon Glass sjg@chromium.org Sent: Wednesday, December 3, 2014 9:36 AM To: Pavel Machek Cc: Matthew Gerlach; u-boot@lists.denx.de Subject: Re: [U-Boot] RFC Pin Configuration Device Tree Bindings for Altera Arria10 SOCFPGA
Hi,
On 3 December 2014 at 06:48, Pavel Machek pavel@ucw.cz wrote:
Hi!
Altera Arria10 SOCFPGA Pin Configuration Bindings
This document describes device tree bindings required to perform configuration of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to be compact and easy to be consumed only by a SPL running in a small on-chip ram before external memory is available. The Arria10 SOCFPGA does not support dynamic modification of the pin configuration.
Each set of pins is represented by its own subnode. For each subnode, the altr,pinmux-regs data will be written to sequential 32 bit addresses starting at the address in the reg property.
These bindings will be incompatible with pin muxing on rest of systems, right?
The pin muxing for the Arria 10 is completely different than the Cyclone5/Arria5 chip family.
Do we really want to parse DT in SPL? Should we parse the DT during build for the SPL?
PavelThe on-chip ram for the Arria10 is 256k. We are hoping to have fewer SPL binaries and use device trees for configuration.
Required properties:
- compatible : Must be "altr,arria10-pinmux" for Arria10 SOCFPGA
- one subnode for each set of pins to be configured
Required subnode properties:
- reg : The start address to write pinmux-data as 32 bit quantities and the number of bytes of registers to be written.
- altr,pinmux-regs : Pin configuration data to be written to registers
Example:
pinmux@0xffd07000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,arria10-pinmux"; shared { reg = <0xffd07000 0x000000c0>;
This doesn't seem to match the address/size-cells stuff immediately above.
altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF>; }; dedicated { reg = <0xffd07200 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0xF 0xF 0xF 0xF 0xF 0xD 0xD>;
For consistency can you use lower-case hex?
}; dedicated_cfg {
Normally use hyphen instead of underscore except for phandles.
reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; };};
Does this match the kernel? Or does the kernel have no such binding yet?
There are no such bindings in the kernel yet. Dynamic pinmuxing is not supported by the Arria 10; so we don't anticipate the kernel needing pinmux information.
OK. Currently device tree files are stored in the kernel, so it might be worth submitting it there one day regardless.
We can support this in SPL if required.
Our prototyping is currently doing some device tree parsing.
Great!
Also I suggest an fdt: tag on this patch. I only saw it by accident.
Regards, Simon
Hi!
altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; };};
Does this match the kernel? Or does the kernel have no such binding yet?
There are no such bindings in the kernel yet. Dynamic pinmuxing is not supported by the Arria 10; so we don't anticipate the kernel needing pinmux information.
OK. Currently device tree files are stored in the kernel, so it might be worth submitting it there one day regardless.
Actually, I believe you should use standard pinmux format. Just because dynamic pinmuxing is not supported now does not mean it will not be supported in Arria 11... And it was already supported in older chipsets (right?).
Pavel
On Wed, 3 Dec 2014, Pavel Machek wrote:
Hi!
altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; };};
Does this match the kernel? Or does the kernel have no such binding yet?
There are no such bindings in the kernel yet. Dynamic pinmuxing is not supported by the Arria 10; so we don't anticipate the kernel needing pinmux information.
OK. Currently device tree files are stored in the kernel, so it might be worth submitting it there one day regardless.
Actually, I believe you should use standard pinmux format. Just because dynamic pinmuxing is not supported now does not mean it will not be supported in Arria 11... And it was already supported in older chipsets (right?).
Pavel
Hi Pavel,
Thanks for the suggestion. I had another look at the pinctlr bindings in the kernel. I think we should be using standard bindings defined in Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for the Arria 10 SOCFPGA.
Matthew Gerlach
-- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
On Thursday, December 04, 2014 at 11:08:32 PM, mgerlach wrote:
On Wed, 3 Dec 2014, Pavel Machek wrote:
Hi!
altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF reg = <0xffd07300 0x00000048>; altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605 0x40605 0x00605 0x40605 0x40605 0x40605 0x10605 0x51010 0x51010 0x51010 0x51010 0x51010 0x03030 0x23030>; }; fpga { reg = <0xffd07400 0x00000044>; altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; };};
Does this match the kernel? Or does the kernel have no such binding yet?
There are no such bindings in the kernel yet. Dynamic pinmuxing is not supported by the Arria 10; so we don't anticipate the kernel needing pinmux information.
OK. Currently device tree files are stored in the kernel, so it might be worth submitting it there one day regardless.
Actually, I believe you should use standard pinmux format. Just because dynamic pinmuxing is not supported now does not mean it will not be supported in Arria 11... And it was already supported in older chipsets (right?).
PavelHi Pavel,
Thanks for the suggestion. I had another look at the pinctlr bindings in the kernel. I think we should be using standard bindings defined in Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for the Arria 10 SOCFPGA.
Thanks for letting me know about the discussion today.
As for the SPL, we agreed that the SPL should parse the DT and do the configuration from the DT. The DT for the SPL might be stripped down in case there was a problem with fitting the full-size DT into the memory.
As for the DT bindings (in general), these should go to the DT mailing list, see http://elinux.org/Device_Tree#Device-tree_Mailing_List . By running those bindings against the DT ML, you will get some kind of a guarantee that their design is sound and these bindings will be somewhat future-proof.
Best regards, Marek Vasut
participants (7)
-
Dinh Nguyen -
Marek Vasut -
Matthew Gerlach -
mgerlach
-
Pavel Machek -
Pavel Machek -
Simon Glass