[PATCH 0/2] Renesas SCIF driver fix & tidy up
I'll shortly be sending an initial patch set adding support for the Renesas RZ/G2L SMARC evaluation board and R9A07G044L SoC. Before dropping those patches I've got a compilation fix and a header tidy up for the SCIF driver.
Paul Barker (2): serial: sh: Fix compile error when lacking HSCIF support serial: sh: Tidy up pre-processor directive indentation
drivers/serial/serial_sh.c | 2 + drivers/serial/serial_sh.h | 84 +++++++++++++++++++------------------- 2 files changed, 44 insertions(+), 42 deletions(-)
If we attempt to compile serial_sh.c for a system which lacks HSCIF support (e.g. R8A7740), we see the following compilation error:
In file included from drivers/serial/serial_sh.c:20: drivers/serial/serial_sh.c: In function ‘sh_serial_init_generic’: drivers/serial/serial_sh.h:429:35: warning: implicit declaration of function ‘sci_HSSRR_out’; did you mean ‘sci_SCSCR_out’? [-Wimplicit-function-declaration] 429 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | ^~~~ drivers/serial/serial_sh.c:62:17: note: in expansion of macro ‘sci_out’ 62 | sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); | ^~~~~~~
To fix this, only try to support access to the HSSRR register for SoCs where it actually exists.
Fixes: bbe36e29ca2c ('serial: sh: Add HSCIF support for R-Car SoC') Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Marek Vasut marek.vasut+renesas@mailbox.org Cc: Simon Glass sjg@chromium.org --- drivers/serial/serial_sh.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 20cda5dbe272..cd9bcf4f0a25 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -58,8 +58,10 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCSPTR, 0x0003); #endif
+#if defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || defined(CONFIG_RCAR_GEN4) if (port->type == PORT_HSCIF) sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); +#endif }
static void
On 8/22/23 20:10, Paul Barker wrote:
If we attempt to compile serial_sh.c for a system which lacks HSCIF support (e.g. R8A7740), we see the following compilation error:
In file included from drivers/serial/serial_sh.c:20: drivers/serial/serial_sh.c: In function ‘sh_serial_init_generic’: drivers/serial/serial_sh.h:429:35: warning: implicit declaration of function ‘sci_HSSRR_out’; did you mean ‘sci_SCSCR_out’? [-Wimplicit-function-declaration] 429 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | ^~~~ drivers/serial/serial_sh.c:62:17: note: in expansion of macro ‘sci_out’ 62 | sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); | ^~~~~~~To fix this, only try to support access to the HSSRR register for SoCs where it actually exists.
Fixes: bbe36e29ca2c ('serial: sh: Add HSCIF support for R-Car SoC') Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Marek Vasut marek.vasut+renesas@mailbox.org Cc: Simon Glass sjg@chromium.org
drivers/serial/serial_sh.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 20cda5dbe272..cd9bcf4f0a25 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -58,8 +58,10 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCSPTR, 0x0003); #endif
+#if defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || defined(CONFIG_RCAR_GEN4)
You can use CONFIG_RCAR_64 instead of GEN3+GEN4 test.
Also, can does
#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_64)
work ?
On 22/08/2023 22:38, Marek Vasut wrote:
On 8/22/23 20:10, Paul Barker wrote:
If we attempt to compile serial_sh.c for a system which lacks HSCIF support (e.g. R8A7740), we see the following compilation error:
In file included from drivers/serial/serial_sh.c:20: drivers/serial/serial_sh.c: In function ‘sh_serial_init_generic’: drivers/serial/serial_sh.h:429:35: warning: implicit declaration of function ‘sci_HSSRR_out’; did you mean ‘sci_SCSCR_out’? [-Wimplicit-function-declaration] 429 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | ^~~~ drivers/serial/serial_sh.c:62:17: note: in expansion of macro ‘sci_out’ 62 | sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); | ^~~~~~~To fix this, only try to support access to the HSSRR register for SoCs where it actually exists.
Fixes: bbe36e29ca2c ('serial: sh: Add HSCIF support for R-Car SoC') Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Marek Vasut marek.vasut+renesas@mailbox.org Cc: Simon Glass sjg@chromium.org
drivers/serial/serial_sh.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 20cda5dbe272..cd9bcf4f0a25 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -58,8 +58,10 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCSPTR, 0x0003); #endif
+#if defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || defined(CONFIG_RCAR_GEN4)
You can use CONFIG_RCAR_64 instead of GEN3+GEN4 test.
I'm going to be sending patches for the RZ/G2L shortly which enables CONFIG_RCAR_64 but lacks HSCIF support. Testing for RCAR gen3/gen4 now will avoid the need to make another change here.
Also, can does
#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_64)
work ?
I'll give this a try with the IS_ENABLED() macros and send over a v2 if it works.
Thanks, Paul
On 8/23/23 08:25, Paul Barker wrote:
On 22/08/2023 22:38, Marek Vasut wrote:
On 8/22/23 20:10, Paul Barker wrote:
If we attempt to compile serial_sh.c for a system which lacks HSCIF support (e.g. R8A7740), we see the following compilation error:
In file included from drivers/serial/serial_sh.c:20: drivers/serial/serial_sh.c: In function ‘sh_serial_init_generic’: drivers/serial/serial_sh.h:429:35: warning: implicit declaration of function ‘sci_HSSRR_out’; did you mean ‘sci_SCSCR_out’? [-Wimplicit-function-declaration] 429 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | ^~~~ drivers/serial/serial_sh.c:62:17: note: in expansion of macro ‘sci_out’ 62 | sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); | ^~~~~~~To fix this, only try to support access to the HSSRR register for SoCs where it actually exists.
Fixes: bbe36e29ca2c ('serial: sh: Add HSCIF support for R-Car SoC') Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Marek Vasut marek.vasut+renesas@mailbox.org Cc: Simon Glass sjg@chromium.org
drivers/serial/serial_sh.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 20cda5dbe272..cd9bcf4f0a25 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -58,8 +58,10 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCSPTR, 0x0003); #endif
+#if defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || defined(CONFIG_RCAR_GEN4)
You can use CONFIG_RCAR_64 instead of GEN3+GEN4 test.
I'm going to be sending patches for the RZ/G2L shortly which enables CONFIG_RCAR_64 but lacks HSCIF support. Testing for RCAR gen3/gen4 now will avoid the need to make another change here.
The G2L has no HSCIF ?
On 23/08/2023 12:22, Marek Vasut wrote:
On 8/23/23 08:25, Paul Barker wrote:
On 22/08/2023 22:38, Marek Vasut wrote:
On 8/22/23 20:10, Paul Barker wrote:
If we attempt to compile serial_sh.c for a system which lacks HSCIF support (e.g. R8A7740), we see the following compilation error:
In file included from drivers/serial/serial_sh.c:20: drivers/serial/serial_sh.c: In function ‘sh_serial_init_generic’: drivers/serial/serial_sh.h:429:35: warning: implicit declaration of function ‘sci_HSSRR_out’; did you mean ‘sci_SCSCR_out’? [-Wimplicit-function-declaration] 429 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | ^~~~ drivers/serial/serial_sh.c:62:17: note: in expansion of macro ‘sci_out’ 62 | sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); | ^~~~~~~To fix this, only try to support access to the HSSRR register for SoCs where it actually exists.
Fixes: bbe36e29ca2c ('serial: sh: Add HSCIF support for R-Car SoC') Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Marek Vasut marek.vasut+renesas@mailbox.org Cc: Simon Glass sjg@chromium.org
drivers/serial/serial_sh.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 20cda5dbe272..cd9bcf4f0a25 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -58,8 +58,10 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCSPTR, 0x0003); #endif
+#if defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || defined(CONFIG_RCAR_GEN4)
You can use CONFIG_RCAR_64 instead of GEN3+GEN4 test.
I'm going to be sending patches for the RZ/G2L shortly which enables CONFIG_RCAR_64 but lacks HSCIF support. Testing for RCAR gen3/gen4 now will avoid the need to make another change here.
The G2L has no HSCIF ?
No, it has SCIF and SCI interfaces but no HSCIF.
Thanks, Paul
On 8/26/23 14:03, Paul Barker wrote:
On 23/08/2023 12:22, Marek Vasut wrote:
On 8/23/23 08:25, Paul Barker wrote:
On 22/08/2023 22:38, Marek Vasut wrote:
On 8/22/23 20:10, Paul Barker wrote:
If we attempt to compile serial_sh.c for a system which lacks HSCIF support (e.g. R8A7740), we see the following compilation error:
In file included from drivers/serial/serial_sh.c:20: drivers/serial/serial_sh.c: In function ‘sh_serial_init_generic’: drivers/serial/serial_sh.h:429:35: warning: implicit declaration of function ‘sci_HSSRR_out’; did you mean ‘sci_SCSCR_out’? [-Wimplicit-function-declaration] 429 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | ^~~~ drivers/serial/serial_sh.c:62:17: note: in expansion of macro ‘sci_out’ 62 | sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); | ^~~~~~~To fix this, only try to support access to the HSSRR register for SoCs where it actually exists.
Fixes: bbe36e29ca2c ('serial: sh: Add HSCIF support for R-Car SoC') Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Cc: Hai Pham hai.pham.ud@renesas.com Cc: Marek Vasut marek.vasut+renesas@mailbox.org Cc: Simon Glass sjg@chromium.org
drivers/serial/serial_sh.c | 2 ++ 1 file changed, 2 insertions(+)diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 20cda5dbe272..cd9bcf4f0a25 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -58,8 +58,10 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCSPTR, 0x0003); #endif
+#if defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || defined(CONFIG_RCAR_GEN4)
You can use CONFIG_RCAR_64 instead of GEN3+GEN4 test.
I'm going to be sending patches for the RZ/G2L shortly which enables CONFIG_RCAR_64 but lacks HSCIF support. Testing for RCAR gen3/gen4 now will avoid the need to make another change here.
The G2L has no HSCIF ?
No, it has SCIF and SCI interfaces but no HSCIF.
Ah, thanks for clarifying.
Let's make the indentation of pre-processor macros and conditionals in serial_sh.h consistent before we add to the confusion with a new SoC.
Signed-off-by: Paul Barker paul.barker.ct@bp.renesas.com Reviewed-by: Biju Das biju.das.jz@bp.renesas.com --- drivers/serial/serial_sh.h | 84 +++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 149ec1fe7397..3109c5a946b9 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -116,9 +116,9 @@ struct uart_port { defined(CONFIG_CPU_SH7751R) || \ defined(CONFIG_CPU_SH7763) || \ defined(CONFIG_CPU_SH7780) -#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ +# define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ #else -#define SCI_CTRL_FLAGS_REIE 0 +# define SCI_CTRL_FLAGS_REIE 0 #endif /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ @@ -174,7 +174,7 @@ struct uart_port { #endif
#ifndef SCIF_ORER -#define SCIF_ORER 0x0000 +# define SCIF_ORER 0x0000 #endif
#define SCxSR_TEND(port)\ @@ -282,45 +282,45 @@ static inline void sci_##name##_out(struct uart_port *port,\ }
#if defined(CONFIG_R8A7740) -#if defined(CONFIG_CPU_SH7721) || \ +# if defined(CONFIG_CPU_SH7721) || \ defined(CONFIG_SH73A0) -#define SCIF_FNS(name, scif_offset, scif_size) \ +# define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) -#elif defined(CONFIG_R8A7740) -#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ +# elif defined(CONFIG_R8A7740) +# define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ sh4_scifb_offset, sh4_scifb_size) \ CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ sh4_scifb_offset, sh4_scifb_size) -#define SCIF_FNS(name, scif_offset, scif_size) \ +# define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) -#else -#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ +# else +# define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ sh4_sci_offset, sh4_sci_size, \ sh3_scif_offset, sh3_scif_size,\ sh4_scif_offset, sh4_scif_size, \ h8_sci_offset, h8_sci_size) \ CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ sh3_scif_offset, sh3_scif_size) -#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ +# define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ sh4_scif_offset, sh4_scif_size) \ CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) -#endif +# endif #elif defined(CONFIG_CPU_SH7723) - #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ - sh4_scif_offset, sh4_scif_size) \ - CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ - sh4_scif_offset, sh4_scif_size) - #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ - CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) +# define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ + sh4_scif_offset, sh4_scif_size) \ + CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ + sh4_scif_offset, sh4_scif_size) +# define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ + CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #else -#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ +# define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ sh4_sci_offset, sh4_sci_size, \ sh3_scif_offset, sh3_scif_size,\ sh4_scif_offset, sh4_scif_size, \ h8_sci_offset, h8_sci_size) \ CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ sh4_scif_offset, sh4_scif_size) -#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ +# define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ sh4_scif_offset, sh4_scif_size) \ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #endif @@ -382,11 +382,11 @@ SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) SCIF_FNS(HSSRR, 0, 0, 0x40, 16) /* HSCIF only */ -#if defined(CFG_SCIF_A) +# if defined(CFG_SCIF_A) SCIF_FNS(SCLSR, 0, 0, 0x14, 16) -#else +# else SCIF_FNS(SCLSR, 0, 0, 0x24, 16) -#endif +# endif #else /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ /* name off sz off sz off sz off sz off sz*/ @@ -397,13 +397,13 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) -#if defined(CONFIG_CPU_SH7780) +# if defined(CONFIG_CPU_SH7780) SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) SCIF_FNS(SCLSR, 0, 0, 0x28, 16) -#elif defined(CONFIG_CPU_SH7763) +# elif defined(CONFIG_CPU_SH7763) SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) @@ -411,16 +411,16 @@ SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) SCIF_FNS(SCLSR, 0, 0, 0x28, 16) -#else +# else
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) -#if defined(CONFIG_CPU_SH7722) +# if defined(CONFIG_CPU_SH7722) SCIF_FNS(SCSPTR, 0, 0, 0, 0) -#else +# else SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) -#endif +# endif SCIF_FNS(SCLSR, 0, 0, 0x24, 16) -#endif +# endif SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) SCIF_FNS(HSSRR, 0, 0, 0x40, 16) /* HSCIF only */ @@ -479,10 +479,10 @@ static inline int sci_rxd_in(struct uart_port *port) */
#if defined(CONFIG_CPU_SH7780) -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) +# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SH7721) || \ defined(CONFIG_R8A7740) -#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SH7723) static inline int scbrr_calc(struct uart_port *port, int bps, int clk) { @@ -491,14 +491,14 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) else return ((clk*2)+16*bps)/(16*bps)-1; } -#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) +# define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) #elif defined(CONFIG_RCAR_GEN2) -#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ - #if defined(CFG_SCIF_A) || defined(CFG_HSCIF) - #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ - #else - #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ - #endif +# define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ +# if defined(CFG_SCIF_A) || defined(CFG_HSCIF) +# define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ +# else +# define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ +# endif #elif defined(CONFIG_RCAR_64) static inline int scbrr_calc(struct uart_port *port, int bps, int clk) { @@ -507,11 +507,11 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) else /* PORT_HSCIF */ return clk / bps / 8 / 2 - 1; /* Internal Clock, Sampling rate = 8 */ } -#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) +# define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) #else /* Generic SH */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif
#ifndef DL_VALUE -#define DL_VALUE(bps, clk) 0 +# define DL_VALUE(bps, clk) 0 #endif
On 8/22/23 20:10, Paul Barker wrote:
Let's make the indentation of pre-processor macros and conditionals in serial_sh.h consistent before we add to the confusion with a new SoC.
What exactly is this patch doing, adding spaces to ifdeffery ?
I would be tempted to say, can we clean up the ifdeffery instead ? It is some hideous mess.
On 22/08/2023 22:40, Marek Vasut wrote:
On 8/22/23 20:10, Paul Barker wrote:
Let's make the indentation of pre-processor macros and conditionals in serial_sh.h consistent before we add to the confusion with a new SoC.
What exactly is this patch doing, adding spaces to ifdeffery ?
I would be tempted to say, can we clean up the ifdeffery instead ? It is some hideous mess.
The header is a mess for sure. I was hoping to make it slightly more easy to follow with this patch.
We can drop this for now if you think it's not a clear improvement. I'll see if I can do some more extensive clean up on this header while I'm adding the RZ/G2L support.
Thanks, Paul
On 8/23/23 08:33, Paul Barker wrote:
On 22/08/2023 22:40, Marek Vasut wrote:
On 8/22/23 20:10, Paul Barker wrote:
Let's make the indentation of pre-processor macros and conditionals in serial_sh.h consistent before we add to the confusion with a new SoC.
What exactly is this patch doing, adding spaces to ifdeffery ?
I would be tempted to say, can we clean up the ifdeffery instead ? It is some hideous mess.
The header is a mess for sure. I was hoping to make it slightly more easy to follow with this patch.
We can drop this for now if you think it's not a clear improvement. I'll see if I can do some more extensive clean up on this header while I'm adding the RZ/G2L support.
If you can give that at least a try, that would be much appreciated.
participants (2)
-
Marek Vasut -
Paul Barker