[U-Boot] [PATCH] This patch adds support for Fujitsu MB86R01 'JADE' SOC
Signed-off-by: Matthias Weisser matthias.weisser@graf-syteco.de --- cpu/arm926ejs/jade/Makefile | 47 +++++++++ cpu/arm926ejs/jade/timer.c | 129 ++++++++++++++++++++++++ include/asm-arm/arch-jade/hardware.h | 31 ++++++ include/asm-arm/arch-jade/jade.h | 182 ++++++++++++++++++++++++++++++++++ 4 files changed, 389 insertions(+), 0 deletions(-) create mode 100755 cpu/arm926ejs/jade/Makefile create mode 100755 cpu/arm926ejs/jade/timer.c create mode 100755 include/asm-arm/arch-jade/hardware.h create mode 100755 include/asm-arm/arch-jade/jade.h
diff --git a/cpu/arm926ejs/jade/Makefile b/cpu/arm926ejs/jade/Makefile new file mode 100755 index 0000000..7da9f40 --- /dev/null +++ b/cpu/arm926ejs/jade/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o +SOBJS = + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/jade/timer.c b/cpu/arm926ejs/jade/timer.c new file mode 100755 index 0000000..59bef84 --- /dev/null +++ b/cpu/arm926ejs/jade/timer.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * + * Matthias Weisser matthias.weisser@graf-syteco.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <div64.h> + +#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_BASE 0xfffe0000 + +#define READ_TIMER (*(volatile ulong *)(TIMER_BASE+4)) +#define TIMER_FREQ (CONFIG_JADE_IOCLK / 16) + +static ulong timestamp; +static ulong lastdec; + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= TIMER_FREQ; + do_div(usec, 1000000); + + return usec; +} + +/* nothing really to do with interrupts, just starts up a counter. */ +int timer_init(void) +{ + *(volatile ulong *)(TIMER_BASE + 0) = TIMER_LOAD_VAL; + *(volatile ulong *)(TIMER_BASE + 8) = 0x86; + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ +unsigned long long get_ticks(void) +{ + ulong now = READ_TIMER; + + if (now <= lastdec) /* normal mode (non roll) */ + /* move stamp forward with absolut diff ticks */ + timestamp += (lastdec - now); + else /* we have rollover of incrementer */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + lastdec = now; + return timestamp; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capture current decrement value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +void udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = usec_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked () - base; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} + + + diff --git a/include/asm-arm/arch-jade/hardware.h b/include/asm-arm/arch-jade/hardware.h new file mode 100755 index 0000000..8546216 --- /dev/null +++ b/include/asm-arm/arch-jade/hardware.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * + * Author : Carsten Schneider, mycable GmbH + * cs@mycable.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <asm/arch/jade.h> + +#endif diff --git a/include/asm-arm/arch-jade/jade.h b/include/asm-arm/arch-jade/jade.h new file mode 100755 index 0000000..0ab96e1 --- /dev/null +++ b/include/asm-arm/arch-jade/jade.h @@ -0,0 +1,182 @@ +/* + * (C) Copyright 2007 + * + * jade definitions + * + * Author : Carsten Schneider, mycable GmbH + * cs@mycable.de + * + * (c) 2009 Graf-Syteco, Matthias Weisser + * matthias.weisser@graf-syteco.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef JADE_H +#define JADE_H + +typedef volatile unsigned int JREG; /* Hardware register definition */ + +/* + * Physical Address Defines + */ +#define JADE_GDC_PHYS_BASE 0xf1fc0000 /* GDC phys */ +#define JADE_GDC_PHYS_DISP_BASE 0xf1fd0000 /* GDC DisplayBase phys */ +#define JADE_CCNT_PHYS_BASE 0xfff42000 /* Chip Control Module */ +#define JADE_CAN0_PHYS_BASE 0xfff54000 /* CAN 0 phys */ +#define JADE_CAN1_PHYS_BASE 0xfff55000 /* CAN 1 phys */ +#define JADE_I2C0_PHYS_BASE 0xfff56000 /* I2C 0 phys */ +#define JADE_I2C1_PHYS_BASE 0xfff57000 /* I2C 1 phys */ +#define JADE_EHCI_PHYS_BASE 0xfff80000 /* EHCI phys */ +#define JADE_OHCI_PHYS_BASE 0xfff81000 /* OHCI phys */ +#define JADE_IRC1_PHYS_BASE 0xfffb0000 /* Jade cascaded Interrupt Controller phys */ +#define JADE_TIMER_PHYS_BASE 0xfffe0000 /* Counter/Timers JADE phys */ +#define JADE_UART0_PHYS_BASE 0xfffe1000 /* UART 0 phys */ +#define JADE_UART1_PHYS_BASE 0xfffe2000 /* UART 1 phys */ +#define JADE_IRCE_PHYS_BASE 0xfffe4000 /* Extended Interrupt Controller */ +#define JADE_CRG_PHYS_BASE 0xfffe7000 /* Clock Reset Generator */ +#define JADE_IRC0_PHYS_BASE 0xfffe8000 /* Jade Interrupt Controller phys */ +#define JADE_GPIO_PHYS_BASE 0xfffe9000 /* GPIO phys */ + + +/* -------- DRAMC_DRIC : (DRAMC Offset: 0x0) DRAM Controller Mode Register -------- */ + +/******************************************************************************** + * REGISTER ADDRESS DEFINITION FOR DRAMC PERIPHERAL * + ********************************************************************************/ +#define JREGC_DRAMC_DRIC ((JREG *) 0xF3000000) /* DRAM Controller Initialization control register */ +#define JREGC_DRAMC_DRIC1 ((JREG *) 0xF3000002) /* DRAM Controller Init control command register 1 */ +#define JREGC_DRAMC_DRIC2 ((JREG *) 0xF3000004) /* DRAM Controller Init control command register 2 */ +#define JREGC_DRAMC_DRCA ((JREG *) 0xF3000006) /* DRAM Controller Address control register */ +#define JREGC_DRAMC_DRCM ((JREG *) 0xF3000008) /* DRAM Controller Modal control register */ +#define JREGC_DRAMC_DRCST1 ((JREG *) 0xF300000A) /* DRAM Controller Timing setting register 1 */ +#define JREGC_DRAMC_DRCST2 ((JREG *) 0xF300000C) /* DRAM Controller Timing setting register 2 */ +#define JREGC_DRAMC_DRCR ((JREG *) 0xF300000E) /* DRAM Controller Refresh control register */ +#define JREGC_DRAMC_DRCS ((JREG *) 0xF3000020) /* DRAM Controller Status control register */ +#define JREGC_DRAMC_DRASR ((JREG *) 0xF3000030) /* DRAM Controller AXI operation setting register */ +#define JREGC_DRAMC_DRIMS1 ((JREG *) 0xF3000042) /* DRAM Controller IF control register 1 */ +#define JREGC_DRAMC_DRIMS2A1 ((JREG *) 0xF3000044) /* DRAM Controller IF control register 2 */ +#define JREGC_DRAMC_DRIMS3A2 ((JREG *) 0xF3000046) /* DRAM Controller IF control register 3 */ +#define JREGC_DRAMC_DRIMS4 ((JREG *) 0xF3000048) /* DRAM Controller IF control register 4 */ +#define JREGC_DRAMC_DRIMS5 ((JREG *) 0xF300004A) /* DRAM Controller IF control register 5 */ +#define JREGC_DRAMC_DRIMS6 ((JREG *) 0xF300004C) /* DRAM Controller IF control register 6 */ +#define JREGC_DRAMC_DRIMS7D1 ((JREG *) 0xF300004E) /* DRAM Controller IF control register 7 */ +#define JREGC_DRAMC_DRIMS8D2 ((JREG *) 0xF3000050) /* DRAM Controller IF control register 8 */ +#define JREGC_DRAMC_DRIMS9T1 ((JREG *) 0xF3000052) /* DRAM Controller IF control register 9 */ +#define JREGC_DRAMC_DRIMSS10T2 ((JREG *) 0xF3000054) /* DRAM Controller IF control register 10 */ +#define JREGC_DRAMC_DROS ((JREG *) 0xF3000060) /* DRAM Controller ODT setting register */ +#define JREGC_DRAMC_DRIBSLI ((JREG *) 0xF3000062) /* DRAM Controller IO LOOPBACK setting register */ +#define JREGC_DRAMC_DRIBSODT1 ((JREG *) 0xF3000064) /* DRAM Controller IO ODT1 setting register */ +#define JREGC_DRAMC_DRIBSOCD ((JREG *) 0xF3000066) /* DRAM Controller IO OCD setting register */ +#define JREGC_DRAMC_DRIBSOCD2 ((JREG *) 0xF3000068) /* DRAM Controller IO OCD2 setting register */ +#define JREGC_DRAMC_DROABA ((JREG *) 0xF3000070) /* DRAM Controller ODT bias self adjustment register */ +#define JREGC_DRAMC_DROBV ((JREG *) 0xF3000080) /* DRAM Controller ODT bias value register */ +#define JREGC_DRAMC_DROBS ((JREG *) 0xF3000084) /* DRAM Controller ODT bias selection register */ +#define JREGC_DRAMC_DROBSR1 ((JREG *) 0xF3000086) /* DRAM Controller ODT bias setting register 1 */ +#define JREGC_DRAMC_DROBSR2 ((JREG *) 0xF3000088) /* DRAM Controller ODT bias setting register 2 */ +#define JREGC_DRAMC_DROBSR3 ((JREG *) 0xF300008A) /* DRAM Controller ODT bias setting register 3 */ +#define JREGC_DRAMC_DROBSR4 ((JREG *) 0xF300008C) /* DRAM Controller ODT bias setting register 4 */ +#define JREGC_DRAMC_DRIMR1 ((JREG *) 0xF3000090) /* DRAM Controller IO monitor register 1 */ +#define JREGC_DRAMC_DRIMR2 ((JREG *) 0xF3000092) /* DRAM Controller IO monitor register 2 */ +#define JREGC_DRAMC_DRIMR3 ((JREG *) 0xF3000094) /* DRAM Controller IO monitor register 3 */ +#define JREGC_DRAMC_DRIMR4 ((JREG *) 0xF3000096) /* DRAM Controller IO monitor register 4 */ +#define JREGC_DRAMC_DROISR1 ((JREG *) 0xF3000098) /* DRAM Controller OCD impedance setting register 1 */ +#define JREGC_DRAMC_DROISR2 ((JREG *) 0xF300009A) /* DRAM Controller OCD impedance setting register 2 */ + + + +/****************************************************************************** + * REGISTER ADDRESS DEFINITION FOR GPIO PERIPHERAL * + ******************************************************************************/ +/* GPIO Port data register */ +#define GPIO_PORT_DATA 0x00 +/* GPIO Data Direction */ +#define GPIO_DIRECTION 0x10 + +/* GPIO Block Defines */ +#define GPIO_BLOCK_0 0x00 +#define GPIO_BLOCK_1 0x04 +#define GPIO_BLOCK_2 0x08 + +/* ------------------------------------------------------------------------ + * JADE Chip Control Module + * ------------------------------------------------------------------------ + */ + +#define CCNT_CGPIO_IST 0x18 /* GPIO interrupt status register */ +#define CCNT_CGPIO_ISTM 0x1c /* GPIO interrupt status mask register */ +#define CCNT_CGPIO_IP 0x20 /* GPIO interrupt polarity setting register */ +#define CCNT_CGPIO_IM 0x24 /* GPIO interrupt mode setting register */ +#define CCNT_CMUX_MD 0x30 /* MultiplexMode setting register */ + +/******************************************************************************** + * REGISTER ADDRESS DEFINITION FOR UART0 PERIPHERAL * + ********************************************************************************/ +#define JREGC_UART0_URT0RFR ((JREG *) 0xFFFE1000) /* UART0 Reception FIFO register */ +#define JREGC_UART0_URT0TFR ((JREG *) 0xFFFE1000) /* UART0 Transmission register */ +#define JREGC_UART0_URT0DLL ((JREG *) 0xFFFE1000) /* UART0 Dividing value */ +#define JREGC_UART0_URT0IER ((JREG *) 0xFFFE1004) /* UART0 DLAB=0: Interrupt enable register */ +#define JREGC_UART0_URT0DLM ((JREG *) 0xFFFE1004) /* UART0 DLAB=1: Dividing value (upper byte) */ +#define JREGC_UART0_URT0IIR ((JREG *) 0xFFFE1008) /* UART0 Interrupt ID register (read only) */ +#define JREGC_UART0_URT0FCR ((JREG *) 0xFFFE1008) /* UART0 FIFO control register (write only) */ +#define JREGC_UART0_URT0LCR ((JREG *) 0xFFFE100C) /* UART0 Line control register */ +#define JREGC_UART0_URT0MCR ((JREG *) 0xFFFE1010) /* UART0 Modem control register */ +#define JREGC_UART0_URT0LSR ((JREG *) 0xFFFE1014) /* UART0 Line status register */ +#define JREGC_UART0_URT0MSR ((JREG *) 0xFFFE1018) /* UART0 Modem status register */ +#define JREGC_UART0_URT0SCR ((JREG *) 0xFFFE101C) /* UART0 Scratch register (At DLAB=0) */ + +/******************************************************************************** + * REGISTER ADDRESS DEFINITION FOR UART1 PERIPHERAL * + ********************************************************************************/ +#define JREGC_UART1_URT1RFR ((JREG *) 0xFFFE2000) /* UART1 Reception FIFO register */ +#define JREGC_UART1_URT1TFR ((JREG *) 0xFFFE2000) /* UART1 Transmission register */ +#define JREGC_UART1_URT1DLL ((JREG *) 0xFFFE2000) /* UART1 Dividing value */ +#define JREGC_UART1_URT1IER ((JREG *) 0xFFFE2004) /* UART1 DLAB=0: Interrupt enable register */ +#define JREGC_UART1_URT1DLM ((JREG *) 0xFFFE2004) /* UART1 DLAB=1: Dividing value (upper byte) */ +#define JREGC_UART1_URT1IIR ((JREG *) 0xFFFE2008) /* UART1 Interrupt ID register (read only) */ +#define JREGC_UART1_URT1FCR ((JREG *) 0xFFFE2008) /* UART1 FIFO control register (write only) */ +#define JREGC_UART1_URT1LCR ((JREG *) 0xFFFE200C) /* UART1 Line control register */ +#define JREGC_UART1_URT1MCR ((JREG *) 0xFFFE2010) /* UART1 Modem control register */ +#define JREGC_UART1_URT1LSR ((JREG *) 0xFFFE2014) /* UART1 Line status register */ +#define JREGC_UART1_URT1MSR ((JREG *) 0xFFFE2018) /* UART1 Modem status register */ +#define JREGC_UART1_URT1SCR ((JREG *) 0xFFFE201C) /* UART1 Scratch register (At DLAB=0) */ + +/******************************************************************************** + * REGISTER ADDRESS DEFINITION FOR CLOCK/RESET INTERFACE * + ********************************************************************************/ +#define JREGC_CRG_CRPR ((JREG *) 0xFFFE7000) /* CRG PLL control register */ +#define JREGC_CRG_CRWR ((JREG *) 0xFFFE7008) /* CRG Watchdog timer control register */ +#define JREGC_CRG_CRSR ((JREG *) 0xFFFE700C) /* CRG Reset/standby control register */ +#define JREGC_CRG_CRDA ((JREG *) 0xFFFE7010) /* CRG Clock divider control register A */ +#define JREGC_CRG_CRDB ((JREG *) 0xFFFE7014) /* CRG Clock divider control register B */ +#define JREGC_CRG_CRHA ((JREG *) 0xFFFE7018) /* CRG (AHB(A) bus) bus clock gate control register */ +#define JREGC_CRG_CRPA ((JREG *) 0xFFFE701C) /* CRG (APB(A) bus) bus clock gate control register */ +#define JREGC_CRG_CRPB ((JREG *) 0xFFFE7020) /* CRG (APB(B) bus) bus clock gate control register */ +#define JREGC_CRG_CRHB ((JREG *) 0xFFFE7024) /* CRG (AHB(B) bus) bus clock gate control register */ +#define JREGC_CRG_CRAM ((JREG *) 0xFFFE7028) /* CRG ARM core clock gate control register */ + +/******************************************************************************** + * REGISTER BASE ADDRESS DEFINITION FOR PERIPHERAL * + ********************************************************************************/ +#define JREGC_BASE_DRAM ((JREGPS_DRAMC) 0xF3000000) /* (DRAMC) Base Address */ +#define JREGC_BASE_GPIO ((JREGPS_GPIO) 0xFFFE9000) /* (GPIO) Base Address */ +#define JREGC_BASE_UART0 ((JREGPS_UART0) 0xFFFE1000) /* (UART0) Base Address */ +#define JREGC_BASE_UART1 ((JREGPS_UART1) 0xFFFE2000) /* (UART1) Base Address */ + +#endif /* jade_H */
Signed-off-by: Matthias Weisser matthias.weisser@graf-syteco.de --- drivers/video/jadegdc.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 205 insertions(+), 0 deletions(-) create mode 100755 drivers/video/jadegdc.c
diff --git a/drivers/video/jadegdc.c b/drivers/video/jadegdc.c new file mode 100755 index 0000000..88b71b7 --- /dev/null +++ b/drivers/video/jadegdc.c @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2007 + * DENX Software Engineering, Anatolij Gustschin, agust@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * jade.c - Graphic interface for Fujitsu Jade integrated graphic + * controller. Derived from mb862xx.c + */ + +#include <common.h> + +#if defined(CONFIG_VIDEO_JADEGDC) + +#include <malloc.h> +#include <asm/io.h> +#include <video_fb.h> +#include "videomodes.h" + +#if defined(CONFIG_POST) +#include <post.h> +#endif + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define GDC_HOST_BASE 0xF1FC0000 +#define GDC_DSP0_BASE 0xF1FD0000 +#define GDC_DSP1_BASE 0xF1FD2000 + +/* + * Graphic Device + */ +GraphicDevice jadegdc; + +void *video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&jadegdc; + struct ctfb_res_modes var_mode[2]; + unsigned long * vid; + unsigned long div; + unsigned long dspBase[2]; + char *penv; + int bpp; + int i, j; + + memset (pGD, 0, sizeof (GraphicDevice)); + + dspBase[0] = GDC_DSP0_BASE; + dspBase[1] = GDC_DSP1_BASE; + + /* Preliminary init of the onboard graphic controller, + retrieve base address */ + if ((pGD->frameAdrs = GDC_HOST_BASE) == 0) { + printf ("Controller not found!\n"); + return (NULL); + } + + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + vid = (unsigned long *)pGD->frameAdrs; + + for(i = 0; i < 2; i++) + { + char varName[32]; + u32 dcm1, dcm2, dcm3; + u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; + u8 hsw, vsw; + u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; + u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; + + sprintf(varName, "gs_dsp_%d_param", i); + + if(NULL == (penv = getenv (varName))) + if(NULL == (penv = getenv ("videomode"))) + continue; + + bpp = 0; + bpp = video_get_params (&var_mode[i], penv); + + if(0 == bpp){ + var_mode[i].xres = 640; + var_mode[i].yres = 480; + var_mode[i].pixclock = 39721; /* 25MHz */ + var_mode[i].left_margin = 48; + var_mode[i].right_margin = 16; + var_mode[i].upper_margin = 33; + var_mode[i].lower_margin = 10; + var_mode[i].hsync_len = 96; + var_mode[i].vsync_len = 2; + var_mode[i].sync = 0; + var_mode[i].vmode = 0; + } + + for(j = 0; j < var_mode[i].xres * var_mode[i].yres / 2; j++) + { + *vid++ = 0xFFFFFFFF; + } + + pGD->winSizeX = var_mode[i].xres; + pGD->winSizeY = var_mode[i].yres; + + /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ + div = 660000 / (1000000000L / var_mode[i].pixclock); + if(div > 64) + div = 64; + + dcm1 = div << 8; + dcm2 = 0x00000000; + dcm3 = 0x00000000; + + htp = var_mode[i].left_margin + var_mode[i].xres + var_mode[i].hsync_len + var_mode[i].right_margin; + hdp = var_mode[i].xres; + hdb = var_mode[i].xres; + hsp = var_mode[i].xres + var_mode[i].right_margin; + hsw = var_mode[i].hsync_len; + + vsw = var_mode[i].vsync_len; + vtr = var_mode[i].upper_margin + var_mode[i].yres + var_mode[i].vsync_len + var_mode[i].lower_margin; + vsp = var_mode[i].yres + var_mode[i].lower_margin; + vdp = var_mode[i].yres; + + l2m = ( (var_mode[i].yres-1) << ( 0)) | + (((var_mode[i].xres * 2)/64) << (16)) | + ( (1) << (31)); + + l2em = (1<<0) | (1 <<1); + + l2oa0 = pGD->frameAdrs; + l2da0 = pGD->frameAdrs; + l2oa1 = pGD->frameAdrs; + l2da1 = pGD->frameAdrs; + l2dx = 0; + l2dy = 0; + l2wx = 0; + l2wy = 0; + l2ww = var_mode[i].xres; + l2wh = var_mode[i].yres - 1; + + writel(dcm1, dspBase[i] + 0x100); + writel(dcm2, dspBase[i] + 0x104); + writel(dcm3, dspBase[i] + 0x108); + + writew(htp, dspBase[i] + 0x006); + writew(hdp, dspBase[i] + 0x008); + writew(hdb, dspBase[i] + 0x00A); + writew(hsp, dspBase[i] + 0x00C); + writeb(hsw, dspBase[i] + 0x00E); + + writeb(vsw, dspBase[i] + 0x00F); + writew(vtr, dspBase[i] + 0x012); + writew(vsp, dspBase[i] + 0x014); + writew(vdp, dspBase[i] + 0x016); + + writel( l2m, dspBase[i] + 0x040); + writel( l2em, dspBase[i] + 0x130); + writel(l2oa0, dspBase[i] + 0x044); + writel(l2da0, dspBase[i] + 0x048); + writel(l2oa1, dspBase[i] + 0x04C); + writel(l2da1, dspBase[i] + 0x050); + writew( l2dx, dspBase[i] + 0x054); + writew( l2dy, dspBase[i] + 0x056); + writew( l2wx, dspBase[i] + 0x134); + writew( l2wy, dspBase[i] + 0x136); + writew( l2ww, dspBase[i] + 0x138); + writew( l2wh, dspBase[i] + 0x13A); + + writel(dcm1 | (1<<18) | (1<<31), dspBase[i] + 0x100); + } + + return pGD; +} + +/* + * Set a RGB color in the LUT + */ +void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b) +{ + +} + +#endif /* CONFIG_VIDEO_JADEGDC */
Signed-off-by: Matthias Weisser matthias.weisser@graf-syteco.de --- drivers/video/cfb_console.c | 12 ++++++++++-- 1 files changed, 10 insertions(+), 2 deletions(-) mode change 100644 => 100755 drivers/video/cfb_console.c
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c old mode 100644 new mode 100755 index bcafb27..15b99cb --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -314,7 +314,7 @@ void console_cursor (int state); #else #define SWAP16(x) (x) #define SWAP32(x) (x) -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) || defined (CONFIG_VIDEO_JADEGDC) #define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) #else #define SHORTSWAP32(x) (x) @@ -1188,9 +1188,17 @@ static void *video_logo (void) ulong addr;
if ((s = getenv ("splashimage")) != NULL) { + int x = 0, y = 0; + addr = simple_strtoul (s, NULL, 16);
- if (video_display_bitmap (addr, 0, 0) == 0) { + if ((s = strchr (s, ' ')) != NULL) { + x = simple_strtoul (s + 1, NULL, 0); + if ((s = strchr (s + 1, ' ')) != NULL) + y = simple_strtoul (s + 1, NULL, 0); + } + + if (video_display_bitmap (addr, x, y) == 0) { return ((void *) (video_fb_address)); } }
Signed-off-by: Matthias Weisser matthias.weisser@graf-syteco.de --- MAINTAINERS | 3 + MAKEALL | 1 + Makefile | 7 + board/syteco/jadecpu/Makefile | 55 ++++++ board/syteco/jadecpu/config.mk | 1 + board/syteco/jadecpu/jadecpu.c | 99 ++++++++++ board/syteco/jadecpu/lowlevel_init.S | 337 ++++++++++++++++++++++++++++++++++ include/configs/jadecpu.h | 173 +++++++++++++++++ tools/Makefile | 3 + tools/logos/syteco.bmp | Bin 0 -> 12278 bytes 10 files changed, 679 insertions(+), 0 deletions(-) mode change 100644 => 100755 MAINTAINERS mode change 100644 => 100755 Makefile create mode 100755 board/syteco/jadecpu/Makefile create mode 100755 board/syteco/jadecpu/config.mk create mode 100755 board/syteco/jadecpu/jadecpu.c create mode 100755 board/syteco/jadecpu/lowlevel_init.S create mode 100755 include/configs/jadecpu.h mode change 100644 => 100755 tools/Makefile create mode 100755 tools/logos/syteco.bmp
diff --git a/MAINTAINERS b/MAINTAINERS old mode 100644 new mode 100755 index 9379c7e..c2e0223 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -671,6 +671,9 @@ Sergey Lapin slapin@ossfans.org
afeb9260 ARM926EJS (AT91SAM9260 SoC)
+Matthias Weisser matthias.weisser@graf-syteco.de + + jadecpu ARM926EJS (MB86R01 'Jade' SoC) -------------------------------------------------------------------------
Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index f4599d6..841c3d6 100755 --- a/MAKEALL +++ b/MAKEALL @@ -533,6 +533,7 @@ LIST_ARM9=" \ davinci_sffsdr \ davinci_sonata \ davinci_dm355evm \ + jadecpu \ "
######################################################################### diff --git a/Makefile b/Makefile old mode 100644 new mode 100755 index bcc81c9..ef19740 --- a/Makefile +++ b/Makefile @@ -2785,6 +2785,13 @@ at91sam9rlek_config : unconfig pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
+######################################################################### +## ARM926EJ-S Systems from multiple vendors +######################################################################### + +jadecpu_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs jadecpu syteco jade + ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile new file mode 100755 index 0000000..87d2234 --- /dev/null +++ b/board/syteco/jadecpu/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop stelian.pop@leadtechdesign.com +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += jadecpu.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk new file mode 100755 index 0000000..c661f0b --- /dev/null +++ b/board/syteco/jadecpu/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x46000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c new file mode 100755 index 0000000..533d44b --- /dev/null +++ b/board/syteco/jadecpu/jadecpu.c @@ -0,0 +1,99 @@ +/* + * (c) 2009 Graf-Syteco, Matthias Weisser + * matthias.weisser@graf-syteco.de + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider cs@mycable.de, Alexander Bigga ab@mycable.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/jade.h> + +DECLARE_GLOBAL_DATA_PTR; + +void multiplex_group_init(void); +void gpio_init(void); + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + /* arch number of Versatile Board */ + gd->bd->bi_arch_number = 0/*MACH_TYPE_GSJADECPU*/; + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x47000000; + + gd->flags = 0; + + icache_enable (); + + /* set Multiplex Group */ + multiplex_group_init(); + + /* init GPIOs */ + gpio_init(); + + return 0; +} + +int misc_init_r (void) +{ + setenv("verify", "n"); + return (0); +} + +/* + * DRAM configuration + */ +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + + return 0; +} + +/* + * Initial the Pin Multiplex Groups + */ +void multiplex_group_init(void) +{ + +} + +void gpio_init(void) +{ + +} + diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S new file mode 100755 index 0000000..727eda5 --- /dev/null +++ b/board/syteco/jadecpu/lowlevel_init.S @@ -0,0 +1,337 @@ +/* + * Board specific setup info + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider cs@mycable.de, Alexander Bigga ab@mycable.de + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider cs@mycable.de, Alexander Bigga ab@mycable.de + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, philippe.robin@arm.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software/* you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation/* either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY/* without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program/* if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: +/*------------------------------------------------------------------------------*/ +/* Initialize Clock Reset Generator (CRG) */ +/*------------------------------------------------------------------------------*/ + + ldr r0, =0xfffe7000 /* CRG base address */ + + /* Not change the initial value that is set by external pin.*/ +1: ldr r2, [r0, #0x00] /* Wait for PLLREADY */ + tst r2, #0x00000100 + beq 1b + + /* Set clock gate control */ + ldr r1, =0x0000ffff /* Open */ + str r1, [r0, #0x18] /* CRHA: AHB clock */ + ldr r1, =0x0000ffff /* Open */ + str r1, [r0, #0x1c] /* CRPA: APB-A clock */ + ldr r1, =0xfffffffe /* Close */ + str r1, [r0, #0x20] /* CRPA: APB-B clock */ + ldr r1, =0x0000ffff /* Open */ + str r1, [r0, #0x24] /* CRHB: ExtAHB clock */ + ldr r1, =0xffffffef /* Open ARM926EJ-S only */ + str r1, [r0, #0x28] /* CRAM: ARM core clock */ + +/*------------------------------------------------------------------------------*/ +/* Initialize External Bus Interface */ +/*------------------------------------------------------------------------------*/ +#define MEMC_BASE 0xfffc0000 + + ldr r0, =MEMC_BASE /* MEMC base address */ + + /* SRAM/flash _mode_ registers (XCS4 is set by external pin) + XCS0: Ethernet Controller + XCS2: not used (?) + XCS4: Flash + */ + ldr r1, =0x00000001 /* XCS0: 16bit */ + str r1, [r0, #0x00] + ldr r1, =0x00000001 /* XCS2: 16bit */ + str r1, [r0, #0x08] + ldr r1, =0x00000021 /* XCS4: 16bit, */ + str r1, [r0, #0x10] + + /* SRAM/flash _timing_ registers (HCLK=83.3/80MHz) */ + ldr r1, =0x055ff00f /* XCS0: */ + str r1, [r0, #0x20] + ldr r1, =0x03061008 /* XCS2: not used */ + str r1, [r0, #0x28] + ldr r1, =0x03061804 /* XCS4: FLASH ROM, reviewed by ab@mycable.de */ + str r1, [r0, #0x30] + + /* SRAM/flash _area_ registers (address of XCS4 is set by external pin) */ + ldr r1, =0x00000020 + str r1, [r0, #0x40] + ldr r1, =0x00000050 /* XCS2: 0x05000000/2MB */ + str r1, [r0, #0x48] + ldr r1, =0x001f0000 /* XCS4: 32 MB */ + str r1, [r0, #0x50] + +/*------------------------------------------------------------------------------*/ +/* GPIO Settings */ +/*------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- */ +/* Initialize DDR2 Controller */ +/*----------------------------------------------------------------------------- */ +#define CCNT_BASE 0xfff42000 +#define CDEBUG1 0xec + +#define DDR2C_BASE 0xf3000000 +#define DRIC 0x00 +#define DRIC1 0x02 +#define DRIC2 0x04 +#define DRCA 0x06 +#define DRCM 0x08 +#define DRCST1 0x0a +#define DRCST2 0x0c +#define DRCR 0x0e +#define DRCF 0x20 +#define DRASR 0x30 +#define DRIMS 0x50 +#define DROS 0x60 +#define DRIBSLI 0x62 +#define DRIBSODT1 0x64 +#define DRIBSOCD 0x66 +#define DRIBSOCD2 0x68 +#define DROABA 0x70 +#define DROBV 0x80 +#define DROBS 0x84 +#define DROBSR1 0x86 +#define DROBSR2 0x88 +#define DROBSR3 0x8a +#define DROBSR4 0x8c +#define DRIMR1 0x90 +#define DRIMR2 0x92 +#define DRIMR3 0x94 +#define DRIMR4 0x96 +#define DROISR1 0x98 +#define DROISR2 0x9a + + .macro wait, count + mov r4, #\count +3: + subs r4, r4, #0x1 + bne 3b + + .endm + + /* Wait for PLL LOCK up time or more */ + wait 20 + + /* ----------------------- */ + /* (2) Initialize DDRIF */ + /* ----------------------- */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0x5555 + strh r1, [r0, #DRIMS] + + /* ----------------------- */ + /* (3) Wait for 20MCKPs(120nsec) or more */ + /* ----------------------- */ + wait 20 + + /* ----------------------- */ + /* (4) IRESET/IUSRRST release */ + /* ----------------------- */ + ldr r0, =CCNT_BASE /* CCNT base address */ + ldr r1, =0x00000002 + str r1, [r0, #CDEBUG1] + + /* ----------------------- */ + /* (5) Wait for 20MCKPs(120nsec) or more */ + /* ----------------------- */ + wait 20 + + /* ----------------------- */ + /* (6) IDLLRST release */ + /* ----------------------- */ + ldr r0, =CCNT_BASE /* CCNT base address */ + ldr r1, =0x00000003 + str r1, [r0, #CDEBUG1] + + /* ----------------------- */ + /* (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) */ + /* ----------------------- */ + wait 33536 + + /* ----------------------- */ + /* (9) MCKE ON */ + /* ----------------------- */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0x003f + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 + strh r1, [r0, #DRIC2] + ldr r1, =0xc124 /* 512Mbit DDR2SDRAM x 2 */ + strh r1, [r0, #DRCA] + ldr r1, =0xc000 + strh r1, [r0, #DRIC] + + /* ----------------------- */ + /* (10) Initialize SDRAM */ + /* ----------------------- */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0xc001 /* NOP Command */ + strh r1, [r0, #DRIC] + + wait 67 /* 400ns wait */ + + ldr r1, =0x0017 /* PALL Command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0400 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0006 /* EMR(2) command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0007 /* EMR(3) command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0005 /* EMR(1) command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 /* Extended Mode Register 1 clear*/ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0004 /* MRS command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0532 /* Mode Register */ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + wait 200 + + ldr r1, =0x0017 /* PALL command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0400 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x000f /* REF command 1 */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 /* (changed) */ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + wait 18 /* 105ns wait */ + + ldr r1, =0x0004 /* MRS command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0432 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + wait 200 /* MRS to OCD: 200clock */ + + ldr r1, =0x0005 /* EMR(1) command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0380 /* Extended Mode Register 1 set OCD */ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0005 /* EMR(1) command */ + strh r1, [r0, #DRIC1] + /* ldr r1, =0x0044 */ + ldr r1, =0x0002 /* Extended Mode Register 1 set reduced strength */ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0032 /* Set BT, AL, CL, BL */ + strh r1, [r0, #DRCM] + + ldr r1, =0x3418 /* Set tRCD, tRAS, tRP, tRC */ + strh r1, [r0, #DRCST1] + + /* ldr r1, =0x2e22 */ /* Set tRFC, tRRD, tWR */ + ldr r1, =0x6e32 + strh r1, [r0, #DRCST2] + + /* ldr r1, =0x0051 */ /* Set CNTL, REF_CNT*/ + ldr r1, =0x0141 /* (changed) */ + strh r1, [r0, #DRCR] + + ldr r1, =0x0002 /* Set Address FIFO (8 steps) */ + strh r1, [r0, #DRCF] + + ldr r1, =0x0001 /* Enable AXI Cache */ + strh r1, [r0, #DRASR] + + /* ----------------------- */ + /* (11) ODT setting */ + /* ----------------------- */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0x0001 + strh r1, [r0, #DROBS] + ldr r1, =0x0103 /* ODT auto adjustment on */ + strh r1, [r0, #DROABA] + ldr r1, =0x003F /* Set ODT to on 50/100 Ohm */ + strh r1, [r0, #DRIBSODT1] + + /* ----------------------- */ + /* (12) Shift to ODTCONT ON (SDRAM side) and DDR2C usual operation mode */ + /* ----------------------- */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0x0001 + strh r1, [r0, #DROS] + ldr r1, =0x4000 + strh r1, [r0, #DRIC] + + mov pc, lr + +/*------------------------------------------------------------------------------*/ +/* Reset CPU by writing SWRSTREQ to CRSR-register */ +/*------------------------------------------------------------------------------*/ +.globl reset_cpu +reset_cpu: + ldr r0, =0xfffe7000/* CRG Base address */ + + ldr r2, =0x00000002 /* SWRSTREQ */ + str r2, [r0, #0x0c] + +_loop_forever: + b _loop_forever + diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h new file mode 100755 index 0000000..7350f7b --- /dev/null +++ b/include/configs/jadecpu.h @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2007-2008 + * Matthias Weisser matthias.weisser@graf-syteco.de + * + * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_JADE_IOCLK (41500000) +#define CONFIG_SYS_TIMERBASE 0xfffe0000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ethaddr=66:15:00:87:02:00\0" \ + "ipaddr=192.168.1.105\0" \ + "serverip=192.168.1.19\0" \ + "bootcmd=tftpboot 0x40100000 jade.ifs; go 0x40100000\0" \ + "" +*/ + +/* + * Hardware drivers + */ + +/* + * Serial + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_JADE_IOCLK +#define CONFIG_SYS_NS16550_COM1 0xfffe1000 +#define CONFIG_SYS_NS16550_COM2 0xfffe2000 + +#define CONFIG_CONS_INDEX 1 + +/* + * Ethernet + */ +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_BASE 0x02000000 +#define CONFIG_DRIVER_SMC911X_16_BIT + +/* + * Video + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_JADEGDC +#define CONFIG_CFB_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_LOGO +#define VIDEO_KBD_INIT_FCT 0 +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc +#define CONSOLE_BG_COL 0xFF +#define CONSOLE_FG_COL 0x00 + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_IMI 1 +#define CONFIG_CMD_ELF 1 +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_BMP 1 +//#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 /* Start address of flash */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ + +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) /* 256k for uboot */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +//#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM + (512*1024) +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM + PHYS_SDRAM_SIZE + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "jade> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_BOOTDELAY 2 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif /* __CONFIG_H */ + diff --git a/tools/Makefile b/tools/Makefile old mode 100644 new mode 100755 index 43c284c..456e9dd --- a/tools/Makefile +++ b/tools/Makefile @@ -125,6 +125,9 @@ endif ifeq ($(VENDOR),ronetix) LOGO_BMP= logos/ronetix.bmp endif +ifeq ($(VENDOR),syteco) +LOGO_BMP= logos/syteco.bmp +endif
# now $(obj) is defined SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) diff --git a/tools/logos/syteco.bmp b/tools/logos/syteco.bmp new file mode 100755 index 0000000000000000000000000000000000000000..141ee8e10edd85caa52b9501e3a4381b81fe772d GIT binary patch literal 12278 zcmeI0TdvbE5Qg2PNJwmiH{MtP??`Ncopb>#s;lC)jN^<mx5VSvEtQTf72hWQzx=+$ zhaW%xehW+behuL(l>Wf)7yK^a^U@yw`TZsRu;KA|g!}yt)yLX&3%A>CEstzCFdP^T zd`t(f&J=<Se1cz6Vz2%xn8}kC7#8>(XPCrZWxxz)aQVUR*)s#%*H9UWBXrEA1QO&t zYstvm(XSvSGDIqb%bIEx@j1x-j~>EAlo=D;a@~oAc7b6ib0rJDLd@MXyUuWw7M5lh zfih3b_~Yq<Q0mM4sm&RQGEdX7KJAq(ZPTPs8d(~qNu#u~oQ5$_npsY+84IPE<=mPv zQ97`kn5KBBu^pKzRr@FeV}ujV0E-%key8+JPwjR%PSg-fL+v?Zuuzm~N*8k07B$EL zgOci{u%n!(&w*xPvQV*M3>M{ZnIT6kFp5Q@?7&zo5+*A-3K2%KXp{&O|B7Qh)*L|? zpC$*w76J<5c_x@E8fJ%u!)!vHl9NR{v&%xA@eq(0pD%ivp1}fG^iANr-ANEg*UW!q z5!3Wi7BY`!(b&_ei5$V^gNKdw934IaoiAk}Vud1NtB)*p`12iK3IL=Vr3MQz1&YHL z?g!T5(G$}<te52r@ir{UnfLG|IrA<o(V5;X`SwN+d0eDBdHS-))l0rbu^5}`5<7SE zRg$sjdj!8hEd8L`mjx~<>uXXIGz-iLz0M#^oeMge`4T14zy+4)zzCKVrZ7jqYdS;U zK)-geMY1HAGK&er_EJ$=1t^vU#=&C1z*A)XDyd=veR|!7ux30g3PzkUMQIhlSTc-@ zMZgG@*7F4qsH=~K!AO*L798Qkj$n(W{oIW!FU?{FOAaOLb{j}7ih~CEHp_s~Z*R(> z0tFpD&{ka*OeKq?NOh&;XfR-ESl~bKOcsZ-5uyjHVwp@9L&w#mVCq;V!xxvX86;tv zS@1$`sudaqOe;&gcN7#4x;acE%W?(k1=GfoP<lDj#DXX-Fy!*w!m^>X!E6i4`vtgM zK%4GqiqZ>a!!mBRTo7yU$TR*rpd^+A%JbZc6eD%0s`up(SQ{|tgv^IC(h;nGKxaB^ J$T5U;;2&8xIXwUX
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Dear Matthias,
Thanks for this patch, some comments however. Please use short patch subject, e.g. "[PATCH] Add support for splash screen positioning" is enough. And than please add more descriptive patch commit message above your "Signed-off-by" line. In this commit message you can shortly explain how it is done (e.g. what you mean with "adding by adding").
This is a new feature and also we should document it in the README where the original "splashimage" environment variable is documented. But if this feature will be documented, we also have to support it in other places, it is used in "common/lcd.c". Also please see other comments below.
Matthias Weisser wrote:
Signed-off-by: Matthias Weisser matthias.weisser@graf-syteco.de
drivers/video/cfb_console.c | 12 ++++++++++-- 1 files changed, 10 insertions(+), 2 deletions(-) mode change 100644 => 100755 drivers/video/cfb_console.c
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c old mode 100644 new mode 100755 index bcafb27..15b99cb --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -314,7 +314,7 @@ void console_cursor (int state); #else #define SWAP16(x) (x) #define SWAP32(x) (x) -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) || defined (CONFIG_VIDEO_JADEGDC)
Here you added CONFIG_VIDEO_JADEGDC case. Please do this in your other patch where you add support for JADE GDC. This patch addresses extension of "splashimage" and should do only this logical change.
#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) #else #define SHORTSWAP32(x) (x) @@ -1188,9 +1188,17 @@ static void *video_logo (void) ulong addr;
if ((s = getenv ("splashimage")) != NULL) {
int x = 0, y = 0;
----^^^^^^^^^^^^ please remove tabs in the empty line above.
addr = simple_strtoul (s, NULL, 16);
if (video_display_bitmap (addr, 0, 0) == 0) {
if ((s = strchr (s, ' ')) != NULL) {x = simple_strtoul (s + 1, NULL, 0);if ((s = strchr (s + 1, ' ')) != NULL)
------------------------------------------------------------^^^^ remove trailing white space here, please.
y = simple_strtoul (s + 1, NULL, 0);}
-----^^^^^^^^^^^ please remove tabs here, too.
if (video_display_bitmap (addr, x, y) == 0) { return ((void *) (video_fb_address));
Please fix and resubmit, thanks! Anatolij
Dear Matthias,
Thanks for this patch! Please see some comments/issues below which we should resolve before committing the driver.
Matthias Weisser wrote:
Signed-off-by: Matthias Weisser matthias.weisser@graf-syteco.de
drivers/video/jadegdc.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 205 insertions(+), 0 deletions(-) create mode 100755 drivers/video/jadegdc.c
diff --git a/drivers/video/jadegdc.c b/drivers/video/jadegdc.c new file mode 100755 index 0000000..88b71b7 --- /dev/null +++ b/drivers/video/jadegdc.c @@ -0,0 +1,205 @@ +/*
- (C) Copyright 2007
- DENX Software Engineering, Anatolij Gustschin, agust@denx.de
Please use your copyright here, as this driver for JADE GDC is mostly your work.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-----------------------------------------------------------^^^^^ please replace tab by space here.
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/*
- jade.c - Graphic interface for Fujitsu Jade integrated graphic
------------------------------------------------------------------^^^^^ and remove trailing white space here.
- controller. Derived from mb862xx.c
same here, trailing white space in the line above, please remove.
- */
+#include <common.h>
+#if defined(CONFIG_VIDEO_JADEGDC)
drop this ifdef and add "COBJS-$(CONFIG_VIDEO_JADEGDC) += jadegdc.o" line to drivers/video/Makefile instead.
+#include <malloc.h> +#include <asm/io.h> +#include <video_fb.h> +#include "videomodes.h"
+#if defined(CONFIG_POST) +#include <post.h> +#endif
I think, this CONFIG_POST ifdef is not needed here, please remove it. Or am I missing something?
+/*
- 4MB (at the end of system RAM)
- */
+#define VIDEO_MEM_SIZE 0x400000
+#define GDC_HOST_BASE 0xF1FC0000 +#define GDC_DSP0_BASE 0xF1FD0000 +#define GDC_DSP1_BASE 0xF1FD2000
+/*
- Graphic Device
- */
+GraphicDevice jadegdc;
+void *video_hw_init (void) +{
- GraphicDevice *pGD = (GraphicDevice *)&jadegdc;
- struct ctfb_res_modes var_mode[2];
- unsigned long * vid;
- unsigned long div;
- unsigned long dspBase[2];
- char *penv;
- int bpp;
- int i, j;
----^^^ please remove tab in the line above.
- memset (pGD, 0, sizeof (GraphicDevice));
same here, remove tab.
- dspBase[0] = GDC_DSP0_BASE;
- dspBase[1] = GDC_DSP1_BASE;
----^^^ same here.
- /* Preliminary init of the onboard graphic controller,
retrieve base address */- if ((pGD->frameAdrs = GDC_HOST_BASE) == 0) {
printf ("Controller not found!\n");return (NULL);- }
please replace above 4 lines by
pGD->frameAdrs = GDC_HOST_BASE;
and for multi line comments we now use following style
/* * Multi line * comment */
please use it here too.
- pGD->gdfIndex = GDF_15BIT_555RGB;
- pGD->gdfBytesPP = 2;
- pGD->memSize = VIDEO_MEM_SIZE;
- pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
- vid = (unsigned long *)pGD->frameAdrs;
remove tabs in empty lines above, please.
- for(i = 0; i < 2; i++)
- {
please use the following coding style:
for (i = 0; i < 2; i++) {
char varName[32];u32 dcm1, dcm2, dcm3;u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;u8 hsw, vsw;u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
-----^^^^^^^^^^^^ tabs again, please drop.
sprintf(varName, "gs_dsp_%d_param", i);
please add a space between function name and open parenthesis as you seem to use this style in other places too. Use either
function (...); or function(...);
style throughout the file an do not intermix.
if(NULL == (penv = getenv (varName)))if(NULL == (penv = getenv ("videomode")))continue;
please add a space between if and open parenthesis and remove tabs in the line above if statement.
bpp = 0;bpp = video_get_params (&var_mode[i], penv);
------^^^ please remove.
if(0 == bpp){
if (bpp == 0) {
var_mode[i].xres = 640;var_mode[i].yres = 480;var_mode[i].pixclock = 39721; /* 25MHz */var_mode[i].left_margin = 48;var_mode[i].right_margin = 16;var_mode[i].upper_margin = 33;var_mode[i].lower_margin = 10;var_mode[i].hsync_len = 96;var_mode[i].vsync_len = 2;var_mode[i].sync = 0;var_mode[i].vmode = 0;}
------^^^^^ please remove.
for(j = 0; j < var_mode[i].xres * var_mode[i].yres / 2; j++){*vid++ = 0xFFFFFFFF;}
fix the coding style here, please:
for (...) one line statement;
for (...) { statement1; statement2; ... }
tabs here, too, please check for tabs in empty lines throughout the file and remove them.
pGD->winSizeX = var_mode[i].xres;pGD->winSizeY = var_mode[i].yres;/* LCD base clock is ~ 660MHZ. We do calculations in kHz */div = 660000 / (1000000000L / var_mode[i].pixclock);if(div > 64)div = 64;
please add space between if and open parenthesis.
dcm1 = div << 8;dcm2 = 0x00000000;dcm3 = 0x00000000;htp = var_mode[i].left_margin + var_mode[i].xres + var_mode[i].hsync_len + var_mode[i].right_margin;
line to long, max. 80 chars allowed.
hdp = var_mode[i].xres;hdb = var_mode[i].xres;hsp = var_mode[i].xres + var_mode[i].right_margin;hsw = var_mode[i].hsync_len;vsw = var_mode[i].vsync_len;vtr = var_mode[i].upper_margin + var_mode[i].yres + var_mode[i].vsync_len + var_mode[i].lower_margin;
here too.
vsp = var_mode[i].yres + var_mode[i].lower_margin;vdp = var_mode[i].yres;
remove trailing white space in the line above.
l2m = ( (var_mode[i].yres-1) << ( 0)) |(((var_mode[i].xres * 2)/64) << (16)) |( (1) << (31));l2em = (1<<0) | (1 <<1);
please add spaces around "<<", "-", "/" in the lines above. Also use this coding style elsewhere in the file.
l2oa0 = pGD->frameAdrs;l2da0 = pGD->frameAdrs;l2oa1 = pGD->frameAdrs;l2da1 = pGD->frameAdrs;l2dx = 0;l2dy = 0;l2wx = 0;l2wy = 0;
trailing white space in 4 lines above, please remove.
l2ww = var_mode[i].xres;l2wh = var_mode[i].yres - 1;writel(dcm1, dspBase[i] + 0x100);writel(dcm2, dspBase[i] + 0x104);writel(dcm3, dspBase[i] + 0x108);writew(htp, dspBase[i] + 0x006);
trailing white space in the line above.
writew(hdp, dspBase[i] + 0x008);writew(hdb, dspBase[i] + 0x00A);writew(hsp, dspBase[i] + 0x00C);writeb(hsw, dspBase[i] + 0x00E);writeb(vsw, dspBase[i] + 0x00F);writew(vtr, dspBase[i] + 0x012);writew(vsp, dspBase[i] + 0x014);writew(vdp, dspBase[i] + 0x016);writel( l2m, dspBase[i] + 0x040);writel( l2em, dspBase[i] + 0x130);writel(l2oa0, dspBase[i] + 0x044);writel(l2da0, dspBase[i] + 0x048);writel(l2oa1, dspBase[i] + 0x04C);writel(l2da1, dspBase[i] + 0x050);writew( l2dx, dspBase[i] + 0x054);writew( l2dy, dspBase[i] + 0x056);writew( l2wx, dspBase[i] + 0x134);writew( l2wy, dspBase[i] + 0x136);writew( l2ww, dspBase[i] + 0x138);writew( l2wh, dspBase[i] + 0x13A);writel(dcm1 | (1<<18) | (1<<31), dspBase[i] + 0x100);- }
- return pGD;
+}
+/*
- Set a RGB color in the LUT
- */
+void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b)
line too long, please fix.
+{
+}
+#endif /* CONFIG_VIDEO_JADEGDC */
We also should use macros for register offsets, I think. Can we coordinate efforts for fixing this in mb862xx driver also? I know that mb862xx driver has similar style issues and I'm willing to fix them soon. For new patches the policy is to resolve issues before inclusion.
Thanks, Anatolij
Anatolij Gustschin agust@denx.de schrieb am 01.07.2009 um 15:40:
Dear Matthias,
Thanks for this patch! Please see some comments/issues below which
we
should resolve before committing the driver.
First of all thanks for your detailed comments. I fix them all before resending the patch. Please see some additional comments at some points.
if(0 == bpp){if (bpp == 0) {
The spaces are OK but why turn around the comparison? I always use this style to prevent from unwanted assignments. Well, GCC warns about assignments in ifs and as u-boot is GCC only I can do that.
We also should use macros for register offsets, I think. Can we coordinate efforts for fixing this in mb862xx driver also?
As the graphic controller in the jade soc is only a slight evolution of the coral graphic chip (additional display output/video input) I think
we may even merge the two drivers into one with some #ifdefs to deal with the differences.
When I started to implement the driver I decided against that idea because I don't have any hardware here to test the "non-jade" case.
But a common include file with the register offsets seems to be a good idea to me.
Thanks for your time, Matthias
------------------------------------ Amtsgericht Freiburg HRA 602707 Ust. ID-Nr.: DE232464428
Geschäftsführer: Dipl. Ing. (FH) Martin Graf Dipl. Ing. (FH) David Graf Dipl. Inf. Fabian Graf
Komplementärin: GRAF-SYTECO Verwaltungs-GmbH Amtsgericht Freiburg HRB 602868 ------------------------------------
Matthias Weisser wrote:
Anatolij Gustschin agust@denx.de schrieb am 01.07.2009 um 15:40:
Dear Matthias,
Thanks for this patch! Please see some comments/issues below which
we
should resolve before committing the driver.
First of all thanks for your detailed comments. I fix them all before resending the patch. Please see some additional comments at some points.
if(0 == bpp){if (bpp == 0) {
The spaces are OK but why turn around the comparison? I always use this style to prevent from unwanted assignments. Well, GCC warns about assignments in ifs and as u-boot is GCC only I can do that.
it is a matter of personal preference. "if (0 == bpp) {" is OK for me, too.
We also should use macros for register offsets, I think. Can we coordinate efforts for fixing this in mb862xx driver also?
As the graphic controller in the jade soc is only a slight evolution of the coral graphic chip (additional display output/video input) I think
we may even merge the two drivers into one with some #ifdefs to deal with the differences.
When I started to implement the driver I decided against that idea because I don't have any hardware here to test the "non-jade" case.
if you want to use the existing driver, it shouldn't be too complicated. To use the mb862xx driver you can implement "board_video_init()" in your board code in which you initialize both display controllers, set "GraphicDevice mb862xx" structure fields winSizeX, etc. and return the video RAM base. Then additionally implement "board_get_regs()" in your board code, e.g.
#include <mb862xx.h>
static const gdc_regs init_regs [] = { {0, 0} }
const gdc_regs *board_get_regs (void) { return init_regs; }
and define CONFIG_VIDEO_MB862xx in the board config file.
see e.g. the appropriate code in "board/lwmon5/lwmon5.c". It does the display controller initialization differently and therefore my suggestion to do the display controller init in custom "board_video_init()".
We have to fix some register access macros in the mb862xx driver for JADE and it should work. I can try to provide a patch for this fix in mb862xx.c.
But a common include file with the register offsets seems to be a good idea to me.
I'will prepare a list of register offset defines for "include/mb862xx.h" and send a patch so that you can use them in your code.
Thanks, Anatolij
Dear Anatolij & Matthias,
in message 4A4C7D73.1080502@denx.de you wrote:
if(0 == bpp){if (bpp == 0) {
The spaces are OK but why turn around the comparison? I always use
Because "0 == bpp" is ugly.
this style to prevent from unwanted assignments. Well, GCC warns about assignments in ifs and as u-boot is GCC only I can do that.
it is a matter of personal preference. "if (0 == bpp) {" is OK for me, too.
NAK for me. Matthias, please do as Anatolij suggested.
Best regards,
Wolfgang Denk
Anatolij Gustschin wrote:
But a common include file with the register offsets seems to be a good idea to me.
I'will prepare a list of register offset defines for "include/mb862xx.h" and send a patch so that you can use them in your code.
now the patch is out: http://lists.denx.de/pipermail/u-boot/2009-July/055582.html
you can use the register offsets from "include/mb862xx.h" in your code for JADE SOC.
Thanks, Anatolij
Dear Matthias Weisser,
In message 1246368064-4957-1-git-send-email-matthias.weisser@graf-syteco.de you wrote:
Signed-off-by: Matthias Weisser matthias.weisser@graf-syteco.de
cpu/arm926ejs/jade/Makefile | 47 +++++++++ cpu/arm926ejs/jade/timer.c | 129 ++++++++++++++++++++++++ include/asm-arm/arch-jade/hardware.h | 31 ++++++ include/asm-arm/arch-jade/jade.h | 182 ++++++++++++++++++++++++++++++++++ 4 files changed, 389 insertions(+), 0 deletions(-) create mode 100755 cpu/arm926ejs/jade/Makefile create mode 100755 cpu/arm926ejs/jade/timer.c create mode 100755 include/asm-arm/arch-jade/hardware.h create mode 100755 include/asm-arm/arch-jade/jade.h
Entries to MAKEALL and MAINTAINERS are missing.
diff --git a/include/asm-arm/arch-jade/jade.h b/include/asm-arm/arch-jade/jade.h new file mode 100755 index 0000000..0ab96e1 --- /dev/null +++ b/include/asm-arm/arch-jade/jade.h
...
+typedef volatile unsigned int JREG; /* Hardware register definition */
You don't need this. We don't use register accesses, but I/O accessor functions.
+/*
- Physical Address Defines
- */
+#define JADE_GDC_PHYS_BASE 0xf1fc0000 /* GDC phys */ +#define JADE_GDC_PHYS_DISP_BASE 0xf1fd0000 /* GDC DisplayBase phys */ +#define JADE_CCNT_PHYS_BASE 0xfff42000 /* Chip Control Module */ +#define JADE_CAN0_PHYS_BASE 0xfff54000 /* CAN 0 phys */ +#define JADE_CAN1_PHYS_BASE 0xfff55000 /* CAN 1 phys */ +#define JADE_I2C0_PHYS_BASE 0xfff56000 /* I2C 0 phys */ +#define JADE_I2C1_PHYS_BASE 0xfff57000 /* I2C 1 phys */ +#define JADE_EHCI_PHYS_BASE 0xfff80000 /* EHCI phys */ +#define JADE_OHCI_PHYS_BASE 0xfff81000 /* OHCI phys */ +#define JADE_IRC1_PHYS_BASE 0xfffb0000 /* Jade cascaded Interrupt Controller phys */ +#define JADE_TIMER_PHYS_BASE 0xfffe0000 /* Counter/Timers JADE phys */ +#define JADE_UART0_PHYS_BASE 0xfffe1000 /* UART 0 phys */ +#define JADE_UART1_PHYS_BASE 0xfffe2000 /* UART 1 phys */ +#define JADE_IRCE_PHYS_BASE 0xfffe4000 /* Extended Interrupt Controller */ +#define JADE_CRG_PHYS_BASE 0xfffe7000 /* Clock Reset Generator */ +#define JADE_IRC0_PHYS_BASE 0xfffe8000 /* Jade Interrupt Controller phys */ +#define JADE_GPIO_PHYS_BASE 0xfffe9000 /* GPIO phys */
+/* -------- DRAMC_DRIC : (DRAMC Offset: 0x0) DRAM Controller Mode Register -------- */
+/********************************************************************************
REGISTER ADDRESS DEFINITION FOR DRAMC PERIPHERAL *- ********************************************************************************/
+#define JREGC_DRAMC_DRIC ((JREG *) 0xF3000000) /* DRAM Controller Initialization control register */ +#define JREGC_DRAMC_DRIC1 ((JREG *) 0xF3000002) /* DRAM Controller Init control command register 1 */ +#define JREGC_DRAMC_DRIC2 ((JREG *) 0xF3000004) /* DRAM Controller Init control command register 2 */ +#define JREGC_DRAMC_DRCA ((JREG *) 0xF3000006) /* DRAM Controller Address control register */ +#define JREGC_DRAMC_DRCM ((JREG *) 0xF3000008) /* DRAM Controller Modal control register */ +#define JREGC_DRAMC_DRCST1 ((JREG *) 0xF300000A) /* DRAM Controller Timing setting register 1 */ +#define JREGC_DRAMC_DRCST2 ((JREG *) 0xF300000C) /* DRAM Controller Timing setting register 2 */ +#define JREGC_DRAMC_DRCR ((JREG *) 0xF300000E) /* DRAM Controller Refresh control register */ +#define JREGC_DRAMC_DRCS ((JREG *) 0xF3000020) /* DRAM Controller Status control register */ +#define JREGC_DRAMC_DRASR ((JREG *) 0xF3000030) /* DRAM Controller AXI operation setting register */ +#define JREGC_DRAMC_DRIMS1 ((JREG *) 0xF3000042) /* DRAM Controller IF control register 1 */
...
NAK.
We don't allow such a base address + offset approach.
Please define C structs for the peripherals, and use I/O accessors.
Best regards,
Wolfgang Denk
participants (4)
-
Anatolij Gustschin -
Matthias Weisser -
Matthias Weisser
-
Wolfgang Denk