Add nds32 architecture with generic cpu core support. Add nds32 architecture with n1213s cpu core support.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- arch/nds32/config.mk | 32 +++ arch/nds32/cpu/Makefile | 52 ++++ arch/nds32/cpu/config.mk | 28 ++ arch/nds32/cpu/cpu.c | 171 ++++++++++++ arch/nds32/cpu/interrupts.c | 293 +++++++++++++++++++++ arch/nds32/cpu/lowlevel_init.S | 192 ++++++++++++++ arch/nds32/cpu/n1213s/Makefile | 53 ++++ arch/nds32/cpu/n1213s/ag101/Makefile | 50 ++++ arch/nds32/cpu/n1213s/ag101/cpu.c | 171 ++++++++++++ arch/nds32/cpu/n1213s/config.mk | 28 ++ arch/nds32/cpu/n1213s/interrupts.c | 27 ++ arch/nds32/cpu/n1213s/lowlevel_init.S | 27 ++ arch/nds32/cpu/n1213s/start.S | 27 ++ arch/nds32/cpu/start.S | 456 +++++++++++++++++++++++++++++++++ arch/nds32/cpu/u-boot.lds | 67 +++++ 15 files changed, 1674 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/config.mk create mode 100644 arch/nds32/cpu/Makefile create mode 100644 arch/nds32/cpu/config.mk create mode 100644 arch/nds32/cpu/cpu.c create mode 100644 arch/nds32/cpu/interrupts.c create mode 100644 arch/nds32/cpu/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213s/Makefile create mode 100644 arch/nds32/cpu/n1213s/ag101/Makefile create mode 100644 arch/nds32/cpu/n1213s/ag101/cpu.c create mode 100644 arch/nds32/cpu/n1213s/config.mk create mode 100644 arch/nds32/cpu/n1213s/interrupts.c create mode 100644 arch/nds32/cpu/n1213s/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213s/start.S create mode 100644 arch/nds32/cpu/start.S create mode 100644 arch/nds32/cpu/u-boot.lds

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk new file mode 100644 index 0000000..e88e516 --- /dev/null +++ b/arch/nds32/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2006 +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +CROSS_COMPILE ?= nds32le-linux- + +STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common +PLATFORM_CPPFLAGS += -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-8 diff --git a/arch/nds32/cpu/Makefile b/arch/nds32/cpu/Makefile new file mode 100644 index 0000000..7eee48c --- /dev/null +++ b/arch/nds32/cpu/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2006 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = interrupts.o cpu.o +SOBJS = lowlevel_init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/nds32/cpu/config.mk b/arch/nds32/cpu/config.mk new file mode 100644 index 0000000..316332e --- /dev/null +++ b/arch/nds32/cpu/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, gj@denx.de +# +# Copyright (C) 2006 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += diff --git a/arch/nds32/cpu/cpu.c b/arch/nds32/cpu/cpu.c new file mode 100644 index 0000000..d8fc5cf --- /dev/null +++ b/arch/nds32/cpu/cpu.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include <asm/andesboot.h> +#include <command.h> + +/* it makes no sense to use the caches if the MMU also isn't used */ +void cpu_init(void) +{ + /* + * setup up stack if necessary + */ + _andesboot_real_end = _andesboot_end + CONFIG_STACKSIZE; +} + +void cleanup_before_linux(void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ + +#ifdef CONFIG_MMU + unsigned long i; +#endif + + disable_interrupts(); + +#ifdef CONFIG_MMU + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); + + /* flush I/D-cache */ + invalidate_icac(); + invalidate_dcac(); +#endif + +} + + +void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + extern void reset_cpu(ulong addr); + + disable_interrupts(); +// reset_cpu(0); FIXME: -by Shawn, currently no ROM loader at addr 0 + reset_cpu(TEXT_BASE); //reset to the base addr of andesboot + /*NOTREACHED*/ +} + + +void flush_cache (unsigned long dummy1, unsigned long dummy2) +{ +/* + unsigned long u32IfRun = 0; + + if(u32IfRun) return; + u32IfRun = 1; + + reset_cpu((unsigned long)flush_cache); + return; +*/ +} + + +void icache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "ori $p0, $p0, 0x01 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +void icache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "li $p1, ~0x01 \n\t" + "and $p0, $p0, $p1 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +int icache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "andi %0, $p0, 0x01 \n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} + +void dcache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "ori $p0, $p0, 0x02 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +void dcache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "li $p1, ~0x02 \n\t" + "and $p0, $p0, $p1 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +int dcache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "andi %0, $p0, 0x02 \n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} diff --git a/arch/nds32/cpu/interrupts.c b/arch/nds32/cpu/interrupts.c new file mode 100644 index 0000000..89a2cd6 --- /dev/null +++ b/arch/nds32/cpu/interrupts.c @@ -0,0 +1,293 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/andesboot.h> + +//#include <board/AndesTech/include/porting.h> +#include "../../../board/AndesTech/include/porting.h" +#undef INTERRUPT_MODE + +#include <asm/ptregs.h> + +extern void reset_cpu(ulong addr); + +int GIE_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $psw \n\t" + "andi %0, %0, 0x1 \n\t" + : "=r" (ret) + : + : "memory" + ); + return ret; +} + + +#ifdef CONFIG_USE_INTERRUPT +/* enable interrupts */ +void enable_interrupts (void) +{ + __asm__ __volatile__("setgie.e"); +} + + +/* + * disable interrupts + * Return TRUE if GIE is enabled before we disable it. + */ +int disable_interrupts (void) +{ + int GIE_OriStatus; + + GIE_OriStatus = GIE_status(); + + __asm__ __volatile__("setgie.d"); + + return GIE_OriStatus; +} +#endif + + +void bad_mode(void) +{ + panic("Resetting CPU ...\n"); + reset_cpu(0); +} + +void show_regs(struct pt_regs * regs) +{ + const char *processor_modes[]= + { "USER", "SuperUser" , "HyperVisor" }; + + printf("\n"); + printf("pc : [<%08lx>] sp: [<%08lx>]\n" + "ra : %08lx gp : %08lx fp : %08lx\n", + regs->PC, regs->SP, regs->RA, regs->GP, regs->FP); + printf("D1H: %081x D1L: %08lx D0H: %081x D0L: %08lx\n", + regs->D1HI, regs->D1LO, regs->D0HI, regs->D0LO); + printf("r27: %081x r26: %08lx r25: %08lx r24: %08lx\n", + regs->R27, regs->R26, regs->R25, regs->R24); + printf("r23: %081x r22: %08lx r21: %08lx r20: %08lx\n", + regs->R23, regs->R22, regs->R21, regs->R20); + printf("r19: %081x r18: %08lx r17: %08lx r16: %08lx\n", + regs->R19, regs->R18, regs->R17, regs->R16); + printf("r15: %081x r14: %08lx r13: %08lx r12: %08lx\n", + regs->R15, regs->R14, regs->R13, regs->R12); + printf("r11: %081x r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->R11, regs->R10, regs->R9, regs->R8); + printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->R7, regs->R6, regs->R5, regs->R4); + printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->R3, regs->R2, regs->R1, regs->R0); + printf(" Interrupts %s Mode %s\n", + interrupts_enabled(regs) ? "on" : "off", + processor_modes[processor_mode(regs)]); +} + +void do_interruption(struct pt_regs *pt_regs, int EVIC_num) +{ + const char *interruption_type[]= + { "Reset", "TLB Fill", "TLB Not Present", "TLB Misc", + "VLPT Miss", "Cache Parity Error", "Debug", + "General Exception", "External Interrupt" }; + + printf("%s\n", interruption_type[EVIC_num]); + show_regs(pt_regs); + bad_mode(); +} + +/* + * functions copy from flib (timer.c) + */ +typedef struct +{ + UINT32 Tm1En:1; // Timer1 enable bit + UINT32 Tm1Clock:1; // Timer1 clock source (0: PCLK, 1: EXT1CLK) + UINT32 Tm1OfEn:1; // Timer1 over flow interrupt enable bit + UINT32 Tm2En:1; + UINT32 Tm2Clock:1; + UINT32 Tm2OfEn:1; + UINT32 Tm3En:1; + UINT32 Tm3Clock:1; + UINT32 Tm3OfEn:1; + UINT32 Tm1UpDown:1; + UINT32 Tm2UpDown:1; + UINT32 Tm3UpDown:1; + + UINT32 Reserved; +}fLib_TimerControl; + + +typedef struct +{ + UINT32 TimerValue; + UINT32 TimerLoad; + UINT32 TimerMatch1; + UINT32 TimerMatch2; +}fLib_TimerReg; + + +/* + * TimerBase[0] is a NULL entry + */ +fLib_TimerReg *TimerBase[] ={0, (fLib_TimerReg *) NDS32_COMMON_TIMER1_BASE, + (fLib_TimerReg *) NDS32_COMMON_TIMER2_BASE,(fLib_TimerReg *)NDS32_COMMON_TIMER3_BASE}; + +#define TIMER_LOAD_VAL 0x80000000 + +/* + * warning: + * timer = 1, 2, 3 + */ +UINT32 Read_Timer_Counter(UINT32 timer) +{ + volatile fLib_TimerReg *Timer = TimerBase[timer]; + + return Timer->TimerValue; +} + +void Set_Timer_AutoReloadValue(UINT32 timer, UINT32 value) +{ + volatile fLib_TimerReg *Timer = TimerBase[timer]; + + Timer->TimerLoad = value; +} + +static ulong timestamp; +static ulong lastdec; + +int interrupt_init (void) +{ + volatile fLib_TimerControl *TimerControl=(fLib_TimerControl *)(NDS32_COMMON_CT_BASE + TIMER_CR); + + TimerControl->Tm1UpDown = 0; // Set timer1 to down count + TimerControl->Tm2UpDown = 0; // Set timer2 to down count + TimerControl->Tm3UpDown = 0; // Set timer3 to down count + + TimerControl->Tm1En = 1; // enable timer 1 + TimerControl->Tm1Clock = 0; + TimerControl->Tm1OfEn = 0; // over flow interrupt disable + + TimerControl->Tm2En = 0; // disable timer 2 + TimerControl->Tm3En = 0; // disable timer 3 + + Set_Timer_AutoReloadValue(1, TIMER_LOAD_VAL); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer (ulong base) +{ + return (get_timer_masked() / CONFIG_SYS_HZ) - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + ulong tmo; + + tmo = usec * (CONFIG_SYS_HZ / 1000000); + //tmo *= CONFIG_SYS_HZ; + //tmo /= 1000; + + tmo += get_timer(0); + + while(get_timer_masked() < tmo) + { + /*NOP*/; + } +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = Read_Timer_Counter(1); + timestamp = 0; +} + +/* + * 1. get timestamp + * 2. lastdec = now + */ +ulong get_timer_masked(void) +{ + ulong now = Read_Timer_Counter(1);; + + if (lastdec >= now) + { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + + +void udelay_masked(unsigned long usec) +{ + ulong tmo; + + tmo = usec / 1000; + tmo *= CONFIG_SYS_HZ; + tmo /= 1000; + + reset_timer_masked(); + + while(get_timer_masked() < tmo) + { + /*NOP*/; + } +} + diff --git a/arch/nds32/cpu/lowlevel_init.S b/arch/nds32/cpu/lowlevel_init.S new file mode 100644 index 0000000..50c3ff1 --- /dev/null +++ b/arch/nds32/cpu/lowlevel_init.S @@ -0,0 +1,192 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.text + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + jal mem_init + jal remap + jal uart_init + + ret $r10 + +mem_init: + move $r11, $lp + li $r0, 0x90200004 + li $r1, 0x00151151 + swi $r1, [$r0] + + li $r0, 0x90100018 + li $r1, 0x100b0000 + swi $r1, [$r0] + li $r0, 0x98100030 + lwi $r1, [$r0] + li $r2, 0x00010000 + or $r1, $r1, $r2 + swi $r1, [$r0] +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + lwi $r1, [$r0] + li $r2, 0x00e00000 + or $r1, $r1, $r2 + swi $r1, [$r0] + li $r0, 0x98100028 + lwi $r1, [$r0] + li $r2, 0x00000010 + or $r1, $r1, $r2 + swi $r1, [$r0] + li $r0, 0x9810004c + lwi $r1, [$r0] + li $r2, 0x0007f000 + or $r1, $r1, $r2 + swi $r1, [$r0] +#endif + li $r0, 0x90300000 + li $r1, 0x00011312 + swi $r1, [$r0] + li $r1, 0x00480180 + swi $r1, [$r0+0x4] + li $r1, 0x00002326 + swi $r1, [$r0+0x8] + li $r1, 0x00000010 + swi $r1, [$r0+0xc] +1: + lwi $r1, [$r0+0xc] + andi $r1, $r1, 0x1c + bnez $r1, 1b + + li $r1, 0x00000004 + swi $r1, [$r0+0xc] +2: + lwi $r1, [$r0+0xc] + bnez $r1, 2b + + li $r1, 0x00000008 + swi $r1, [$r0+0xc] +3: + lwi $r1, [$r0+0xc] + bnez $r1, 3b + + move $lp, $r11 + ret + +remap: + move $r11, $lp +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + bal 2f +relo_base: + move $r0, $lp +#else +relo_base: + mfusr $r0, $pc +#endif + + /* relocation, copy ROM code to SDRAM(current is at 0x10000000) */ + li $r4, 0x10000000 + li $r5, 0x0 + la $r1, relo_base + sub $r2, $r0, $r1 + sethi $r6, hi20(andesboot_end) + ori $r6, $r6, lo12(andesboot_end) + add $r6, $r6, $r2 +1: + lwi $r7, [$r5] + swi $r7, [$r4] + addi $r5, $r5, #4 + addi $r4, $r4, #4 + blt $r5, $r6, 1b + + /* Remapping */ + li $r0, 0x90300000 + li $r1, 0x00001100 + swi $r1, [$r0+0x10] + li $r1, 0x0 + swi $r1, [$r0+0x14] + swi $r1, [$r0+0x18] + swi $r1, [$r0+0x1c] + li $r1, 0x00001000 + swi $r1, [$r0+0x10] + + li $r0, 0x90100088 + lwi $r1, [$r0] + ori $r1, $r1, 0x1 + swi $r1, [$r0] + + li $r0, 0x90200000 +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + li $r1, 0x10400062 + swi $r1, [$r0+0x8] + li $r1, 0x000ff3ff + swi $r1, [$r0+0xc] +#else + li $r1, 0x10400062 + swi $r1, [$r0] +#endif + + move $lp, $r11 +2: + ret + +uart_init: +#! 1. fLib_SetSerialMode(DebugSerialPort, SERIAL_MDR_UART); + li $r0, #0x99600000 !; CPE_UART4_BASE = 0x99600000 + lwi $r1, [$r0+#0x20] !; mdr = mdr = inw(CPE_UART4_BASE + SERIAL_MDR) + li $r2, #0xfffffffc !; mdr &= ~(0x3) ; SERIAL_MDR_MODE_SEL = 0x3 + and $r1, $r1, $r2 + swi $r1, [$r0+#0x20] !; outw(CPE_UART4_BASE + SERIAL_MDR, mdr | mode); +#! 2. fLib_SerialInit(DebugSerialPort, (int)DEFAULT_HOST_BAUD, PARITY_NONE, 0, 8); +#! dgbserialport = 0x99600000; baud = (UART_CLOCK / 614400) = 24; PARITY_NONE = 0; num = 0; len = 8; + li $r0, #0x99600000 !;lcr = inw(port + SERIAL_LCR) & ~SERIAL_LCR_DLAB; SERIAL_LCR = 0x0c + lwi $r1, [$r0+#0x0c] + li $r2, #0xffffff7f !; SERIAL_LCR_DLAB = 0x80 + and $r1, $r1, $r2 + li $r2, #0x80 !; outw(port + SERIAL_LCR,SERIAL_LCR_DLAB); + swi $r2, [$r0+#0x0c] + li $r2, #0 !; outw(port + SERIAL_DLM, ((baudrate & 0xf00) >> 8)); + swi $r2, [$r0+#0x4] +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + li $r2, #60 !; outw(port + SERIAL_DLL, (baudrate & 0xff)); +#else + li $r2, #24 !; outw(port + SERIAL_DLL, (baudrate & 0xff)); +#endif + swi $r2, [$r0+#0x0] + andi $r1, $r1, #0xc0 !; lcr &= 0xc0; + li $r2, #3 !; len-=5; + or $r1, $r1, $r2 !; lcr|=len; + swi $r1, [$r0+#0x0c] !; outw(port+SERIAL_LCR,lcr); +#! 3. fLib_SetSerialFifoCtrl(DebugSerialPort, 0, 0, ENABLE(1), ENABLE(1)); + li $r0, #0x99600000 + li $r1, #0x7 !; fcr = 0x7 + swi $r1, [$r0+#0x8] !; SERIAL_FCR = 0x08; outw(port+SERIAL_FCR,fcr); + + ret + +.globl show_led +show_led: + li $r8, 0x902ffffc ! 0x902ffffc + swi $r7, [$r8] + ret +#endif diff --git a/arch/nds32/cpu/n1213s/Makefile b/arch/nds32/cpu/n1213s/Makefile new file mode 100644 index 0000000..1cc3731 --- /dev/null +++ b/arch/nds32/cpu/n1213s/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2006 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = interrupts.o +SOBJS = lowlevel_init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + sed -e "s/start.o/$(CPU)/start.o/" ../u-boot.lds > ./u-boot.lds + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/nds32/cpu/n1213s/ag101/Makefile b/arch/nds32/cpu/n1213s/ag101/Makefile new file mode 100644 index 0000000..65ccf94 --- /dev/null +++ b/arch/nds32/cpu/n1213s/ag101/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# Copyright (C) 2006 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = cpu.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/nds32/cpu/n1213s/ag101/cpu.c b/arch/nds32/cpu/n1213s/ag101/cpu.c new file mode 100644 index 0000000..d8fc5cf --- /dev/null +++ b/arch/nds32/cpu/n1213s/ag101/cpu.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include <asm/andesboot.h> +#include <command.h> + +/* it makes no sense to use the caches if the MMU also isn't used */ +void cpu_init(void) +{ + /* + * setup up stack if necessary + */ + _andesboot_real_end = _andesboot_end + CONFIG_STACKSIZE; +} + +void cleanup_before_linux(void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ + +#ifdef CONFIG_MMU + unsigned long i; +#endif + + disable_interrupts(); + +#ifdef CONFIG_MMU + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); + + /* flush I/D-cache */ + invalidate_icac(); + invalidate_dcac(); +#endif + +} + + +void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + extern void reset_cpu(ulong addr); + + disable_interrupts(); +// reset_cpu(0); FIXME: -by Shawn, currently no ROM loader at addr 0 + reset_cpu(TEXT_BASE); //reset to the base addr of andesboot + /*NOTREACHED*/ +} + + +void flush_cache (unsigned long dummy1, unsigned long dummy2) +{ +/* + unsigned long u32IfRun = 0; + + if(u32IfRun) return; + u32IfRun = 1; + + reset_cpu((unsigned long)flush_cache); + return; +*/ +} + + +void icache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "ori $p0, $p0, 0x01 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +void icache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "li $p1, ~0x01 \n\t" + "and $p0, $p0, $p1 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +int icache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "andi %0, $p0, 0x01 \n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} + +void dcache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "ori $p0, $p0, 0x02 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +void dcache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "li $p1, ~0x02 \n\t" + "and $p0, $p0, $p1 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +int dcache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "andi %0, $p0, 0x02 \n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} diff --git a/arch/nds32/cpu/n1213s/config.mk b/arch/nds32/cpu/n1213s/config.mk new file mode 100644 index 0000000..316332e --- /dev/null +++ b/arch/nds32/cpu/n1213s/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, gj@denx.de +# +# Copyright (C) 2006 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += diff --git a/arch/nds32/cpu/n1213s/interrupts.c b/arch/nds32/cpu/n1213s/interrupts.c new file mode 100644 index 0000000..a115a72 --- /dev/null +++ b/arch/nds32/cpu/n1213s/interrupts.c @@ -0,0 +1,27 @@ +/* + * Andesboot - Startup Code for Whitiger core + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Macpaul macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "../interrupts.c" + diff --git a/arch/nds32/cpu/n1213s/lowlevel_init.S b/arch/nds32/cpu/n1213s/lowlevel_init.S new file mode 100644 index 0000000..26e0727 --- /dev/null +++ b/arch/nds32/cpu/n1213s/lowlevel_init.S @@ -0,0 +1,27 @@ +/* + * Andesboot - Startup Code for Whitiger core + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Macpaul macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "../lowlevel_init.S" + diff --git a/arch/nds32/cpu/n1213s/start.S b/arch/nds32/cpu/n1213s/start.S new file mode 100644 index 0000000..e93d048 --- /dev/null +++ b/arch/nds32/cpu/n1213s/start.S @@ -0,0 +1,27 @@ +/* + * Andesboot - Startup Code for Whitiger core + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Macpaul macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "../start.S" + diff --git a/arch/nds32/cpu/start.S b/arch/nds32/cpu/start.S new file mode 100644 index 0000000..12cd30f --- /dev/null +++ b/arch/nds32/cpu/start.S @@ -0,0 +1,456 @@ +/* + * Andesboot - Startup Code for Whitiger core + * + * Copyright (c) 2001 Marius Gröger mag@sysgo.de + * Copyright (c) 2002 Alex Züpke azu@sysgo.de + * Copyright (c) 2002 Gary Jennejohn gj@denx.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin nobuhiro@andestech.com + * Copyright (C) 2010 Macpaul macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <version.h> +#include <nds32_common.h> + +#if defined(CONFIG_AG101) +#include <./configs/ag101.h> +#endif + +!======================================================================== +! Jump vector table for EVIC mode +!======================================================================== + +#define ENA_DCAC 2UL +#define DIS_DCAC ~ENA_DCAC +#define ICAC_MEM_kbfISET (0x07) ! I Cache sets per way +#define ICAC_MEM_kbfIWAY (0x07<<3) ! I cache ways +#define ICAC_MEM_kbfISZ (0x07<<6) ! I cache line size +#define DCAC_MEM_kbfDSET (0x07) ! D Cache sets per way +#define DCAC_MEM_kbfDWAY (0x07<<3) ! D cache ways +#define DCAC_MEM_kbfDSZ (0x07<<6) ! D cache line size + +#define psw $ir0 +#define EIT_INTR_PSW $ir1 // interruption $PSW +#define EIT_PREV_IPSW $ir2 // previous ... +#define EIT_IVB $ir3 // intr vector base address +#define EIT_EVA $ir4 // MMU related Exception Virtual Address register +#define EIT_PREV_EVA $ir5 // previous $eva +#define EIT_ITYPE $ir6 // interruption type +#define EIT_PREV_ITYPE $ir7 // prev intr type +#define EIT_MACH_ERR $ir8 // machine error log +#define EIT_INTR_PC $ir9 // Interruption PC +#define EIT_PREV_IPC $ir10 // previous $IPC +#define EIT_OVL_INTR_PC $ir11 // overflow interruption PC +#define EIT_PREV_P0 $ir12 // prev $P0 +#define EIT_PREV_P1 $ir13 // prev $p1 +#define CR_ICAC_MEM $cr1 // Insn cache/memory config register +#define CR_DCAC_MEM $cr2 // Data cache/memory config register +#define MR_CAC_CTL $mr8 + + +.globl _start + +_start: b reset + b TLB_fill + b TLB_not_present + b TLB_misc + b TLB_VLPT_miss + b cache_parity_error + b debug + b general_exception + b internal_interrupt ! H0I + b internal_interrupt ! H1I + b internal_interrupt ! H2I + b internal_interrupt ! H3I + b internal_interrupt ! H4I + b internal_interrupt ! H5I + + .balign 16 + + +!======================================================================== +! Andesboot Startup Code (reset vector) +! +! 1. bootstrap +! 1.1 reset - start of Andesboot +! 1.2 to superuser mode - as is when reset +! 1.3 Turn off watchdog timer +! 2. Do critical init when reboot (not from mem) +! 3. Relocate andesboot to ram +! 4. Setup stack +! 5. Jump to second stage (start_andesboot) +!======================================================================== + +! Note: TEXT_BASE is defined by the (board-dependent) linker script +_TEXT_BASE: + .word TEXT_BASE + +.globl _andesboot_start +_andesboot_start: + .word _start + +! Note: andesboot_end is defined by the (board-dependent) linker script +.globl _andesboot_end +_andesboot_end: + .word andesboot_end + +! _andesboot_real_end is the first usable RAM address behind Andesboot +! and the various stacks +.globl _andesboot_real_end +_andesboot_real_end: + .word 0x0badc0de + + +!============================================= +! The bootstrap code of Andesboot +!============================================= + +reset: + +load_lli: +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + jal load_lowlevel_init + jral $p0 +#endif + + ! Set the Whitiger core to superuser mode + ! According to spec, it is already when reset + +#define WD_CR 0xC +#define WdEnable 0x1 + + ! Turn off the watchdog, according to Faraday FTWDT010 spec + li $p0, (NDS32_COMMON_WATCHDOG_BASE+WD_CR) ! Get the address of the WD CR + lwi $p1, [$p0] ! Get the WD configuration + andi $p1, $p1, 0x1f ! Wipe out useless bits + li $r0, ~WdEnable + and $p1, $p1, $r0 ! Set WD disable + sw $p1, [$p0] ! Write back to WD CR + + ! Disable Interrupts by clear GIE in $PSW reg + setgie.d + +! Do CPU critical regs init only at reboot, not when booting from ram +#ifdef CONFIG_INIT_CRITICAL + bal cpu_init_crit ! Do CPU critical regs init +#endif +.align 2 +relocate: + ! relocate andesboot to RAM + jal 2f + !la $r0, _start ! $r0 = source start address + !l.w $r2, _andesboot_start ! Andesboot start address + !l.w $r3, _andesboot_end ! Andesboot end address + !sub $r2, $r3, $r2 ! $r2 = size of Andesboot + !l.w $r1, _TEXT_BASE ! $r1 = destination start address + move $r0, $lp + la $p0, _start + la $p1, relocate+4 + sub $p0, $p1, $p0 + sub $r0, $r0, $p0 + + la $p0, _andesboot_end + sub $p0, $p0, $p1 + move $r3, $lp + lw $r3, [$r3+$p0] ! _andesboot_end + addi $p0, $p0, -4 + move $r2, $lp + lw $r2, [$r2+$p0] ! _andesboot_start + sub $r2, $r3, $r2 + addi $p0, $p0, -4 + move $r1, $lp + lw $r1, [$r1+$p0] ! _TEXT_BASE + + ! $r0 = source address + ! $r1 = destination address + ! $r2 = size to copy +copy_loop: + lmw.bim $r3, [$r0], $r10 + smw.bim $r3, [$r1], $r10 + addi $r2, $r2, -32 + bgez $r2, copy_loop + + ! Set up the stack + l.w $p0, _andesboot_end ! Defined by the board linker script + li $p1, CONFIG_STACKSIZE ! (128*1024) defined in config.h + add $sp, $p0, $p1 + + bal fLib_InitBSSMemory + + ! Jump to start_andesboot (2nd phase) + l.w $p0, __start_andesboot + br $p0 + +__start_andesboot: .word start_andesboot + + + +!========================================================================= +! Initialize CPU critical registers +! +! 1. Setup control registers +! 1.1 Mask all IRQs +! 1.2 Flush cache and TLB +! 1.3 Disable MMU and cache +! 2. Setup memory timing +!========================================================================= + + +cpu_init_crit: + !push ra + move $r0, $lp + ! Disable Interrupts by clear GIE in $PSW reg + setgie.d + + ! Flush caches and TLB + + ! Invalidate caches + bal invalidate_icac + bal invalidate_dcac + + ! Flush TLB + mfsr $p0, $MMU_CFG + andi $p0, $p0, 0x3 ! MMPS + li $p1, 0x2 ! TLB MMU + bne $p0, $p1, 1f + tlbop FlushAll ! Flush TLB + +1: + ! Disable MMU, Dcache + ! Whitiger is MMU disabled when reset + ! Disable the D$ + mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg + li $p1, DIS_DCAC + and $p0, $p0, $p1 ! Set DC_EN bit + mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg + isb + + ! RAM is initialized in the dram_init()(board/nds32/cpe.c) + ! Remove the memsetup.S in the board directory. + !pop ra + + move $lp, $r0 +2: + ret + +fLib_InitBSSMemory: + smw.adm $r4, [$sp], $r6, #0x1 + + la $r4, __bss_start + la $r5, __bss_end + move $r6, #0 +1: + swi.p $r6, [$r4], #4 + blt $r4, $r5, 1b ! Check if done.. + + lmw.bim $r4, [$sp], $r6, #0x1 + ret + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +load_lowlevel_init: + la $r6, lowlevel_init + la $r7, load_lli + 4 + sub $p0, $r6, $r7 + add $p0, $p0, $lp +ret +#endif + +!======================================================= +! Invalidate I$ +!======================================================= +invalidate_icac: + mfsr $t0, CR_ICAC_MEM ! read $cr1(I CAC/MEM cfg. reg.) configuration + andi $p0, $t0, ICAC_MEM_kbfISZ ! Get the ISZ field + beqz $p0, end_flush_icache ! if $p0=0, then no I CAC existed + srli $p0, $p0, 6 ! get $p0 the index of I$ block + addi $t1, $p0, 2 ! $t1= bit width of I cache line size(ISZ) + li $t4, 1 + sll $t5, $t4, $t1 ! get $t5 cache line size + andi $p1, $t0, ICAC_MEM_kbfISET! get the ISET field + addi $t2, $p1, 6 ! $t2= bit width of ISET + andi $p1, $t0, ICAC_MEM_kbfIWAY! get bitfield of Iway + srli $p1, $p1, 3 + addi $p1, $p1, 1 ! then $p1 is I way number + add $t3, $t2, $t1 ! SHIFT + sll $p1, $p1, $t3 ! GET the total cache size +ICAC_LOOP: + sub $p1, $p1, $t5 + cctl $p1, L1I_IX_INVAL + bnez $p1, ICAC_LOOP +end_flush_icache: + ret +!======================================================= +! Invalidate D$ +!======================================================= +invalidate_dcac: + mfsr $t0, CR_DCAC_MEM ! read $cr2(D CAC/MEM cfg. reg.) configuration + andi $p0, $t0, DCAC_MEM_kbfDSZ ! Get the DSZ field + beqz $p0, end_flush_dcache ! if $p0=0, then no D CAC existed + srli $p0, $p0, 6 ! get $p0 the index of D$ block + addi $t1, $p0, 2 ! $t1= bit width of D cache line size(DSZ) + li $t4, 1 + sll $t5, $t4, $t1 ! get $t5 cache line size + andi $p1, $t0, DCAC_MEM_kbfDSET! get the DSET field + addi $t2, $p1, 6 ! $t2= bit width of DSET + andi $p1, $t0, DCAC_MEM_kbfDWAY! get bitfield of D way + srli $p1, $p1, 3 + addi $p1, $p1, 1 ! then $p1 is D way number + add $t3, $t2, $t1 ! SHIFT + sll $p1, $p1, $t3 ! GET the total cache size +DCAC_LOOP: + sub $p1, $p1, $t5 + cctl $p1, L1D_IX_INVAL + bnez $p1, DCAC_LOOP +end_flush_dcache: + ret + +!======================================================================== +! Interrupt handling +!======================================================================== + +/* + * exception handlers + */ + .align 5 + + .macro SAVE_ALL + ! FIXME: Other way to get PC? + ! FIXME: Update according to the newest spec!! +1: la $r28, 1 + push $r28 + mfsr $r28, psw ! $psw + push $r28 + mfsr $r28, EIT_EVA ! $ir1 $EVA + push $r28 + mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE + push $r28 + mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error + push $r28 + mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW + push $r28 + mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW + push $r28 + mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA + push $r28 + mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE + push $r28 + mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC + push $r28 + mfsr $r28, EIT_PREV_IPC ! $ir10 prev Interruption PC + push $r28 + mfsr $r28, EIT_OVL_INTR_PC ! $ir11:OVerflowed interruption PC + push $r28 + mfusr $r28, $d1.lo + push $r28 + mfusr $r28, $d1.hi + push $r28 + mfusr $r28, $d0.lo + push $r28 + mfusr $r28, $d0.hi + push $r28 + pushm $r0,$r30 // we will also store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp + addi $sp, $sp, -4 ! make room for implicit pt_regs parameters + .endm + + .align 5 +TLB_fill: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 1 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_not_present: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 2 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_misc: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 3 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_VLPT_miss: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 4 ! Determine interruption type + bal do_interruption + + .align 5 +cache_parity_error: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 5 ! Determine interruption type + bal do_interruption + + .align 5 +debug: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 6 ! Determine interruption type + bal do_interruption + + .align 5 +general_exception: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 7 ! Determine interruption type + bal do_interruption + + + .align 5 +internal_interrupt: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 8 ! Determine interruption type + bal do_interruption + + .align 5 + +!=========================================== +!void reset_cpu(ulong addr); +! $r0: input address to jump to +!=========================================== +.globl reset_cpu +reset_cpu: +! No need to disable MMU because we never enable it! + + bal invalidate_icac + bal invalidate_dcac + mfsr $p0, $MMU_CFG + andi $p0, $p0, 0x3 ! MMPS + li $p1, 0x2 ! TLB MMU + bne $p0, $p1, 1f + tlbop FlushAll ! Flush TLB +1: + mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg + li $p1, DIS_DCAC + and $p0, $p0, $p1 ! Clear the DC_EN bit + mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg + br $r0 ! Jump to the input address + diff --git a/arch/nds32/cpu/u-boot.lds b/arch/nds32/cpu/u-boot.lds new file mode 100644 index 0000000..e74bb0f --- /dev/null +++ b/arch/nds32/cpu/u-boot.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32") +OUTPUT_ARCH(nds32) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/nds32/cpu/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + . = ALIGN(4); + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + + andesboot_end = .; + + . = 0x02000000; + .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) } +}

Add nds32 architecture with include header files support.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- arch/nds32/include/asm/andesboot.h | 224 +++++++++++++++++++++ arch/nds32/include/asm/atomic.h | 121 ++++++++++++ arch/nds32/include/asm/bitops.h | 148 ++++++++++++++ arch/nds32/include/asm/byteorder.h | 36 ++++ arch/nds32/include/asm/config.h | 24 +++ arch/nds32/include/asm/global_data.h | 84 ++++++++ arch/nds32/include/asm/io.h | 352 ++++++++++++++++++++++++++++++++++ arch/nds32/include/asm/memory.h | 141 ++++++++++++++ arch/nds32/include/asm/posix_types.h | 85 ++++++++ arch/nds32/include/asm/processor.h | 145 ++++++++++++++ arch/nds32/include/asm/ptrace.h | 51 +++++ arch/nds32/include/asm/ptregs.h | 83 ++++++++ arch/nds32/include/asm/setup.h | 274 ++++++++++++++++++++++++++ arch/nds32/include/asm/string.h | 57 ++++++ arch/nds32/include/asm/types.h | 84 ++++++++ arch/nds32/include/asm/u-boot.h | 72 +++++++ arch/nds32/include/asm/unaligned.h | 35 ++++ 17 files changed, 2016 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/include/asm/andesboot.h create mode 100644 arch/nds32/include/asm/atomic.h create mode 100644 arch/nds32/include/asm/bitops.h create mode 100644 arch/nds32/include/asm/byteorder.h create mode 100644 arch/nds32/include/asm/config.h create mode 100644 arch/nds32/include/asm/global_data.h create mode 100644 arch/nds32/include/asm/io.h create mode 100644 arch/nds32/include/asm/memory.h create mode 100644 arch/nds32/include/asm/posix_types.h create mode 100644 arch/nds32/include/asm/processor.h create mode 100644 arch/nds32/include/asm/ptrace.h create mode 100644 arch/nds32/include/asm/ptregs.h create mode 100644 arch/nds32/include/asm/setup.h create mode 100644 arch/nds32/include/asm/string.h create mode 100644 arch/nds32/include/asm/types.h create mode 100644 arch/nds32/include/asm/u-boot.h create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/andesboot.h b/arch/nds32/include/asm/andesboot.h new file mode 100644 index 0000000..d177099 --- /dev/null +++ b/arch/nds32/include/asm/andesboot.h @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ANDESBOOT_H_ +#define _ANDESBOOT_H_ 1 + +#undef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ +#include <config.h> +#include <asm/types.h> +#include <asm/u-boot.h> +#include <stdarg.h> +#include <common.h> +#include <flash.h> +#include <image.h> + +#ifdef DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#else +#define debug(fmt,args...) +#endif + +/* + * The environment storages is simply a list of '\0'-terminated + * "name=value" strings, the end of the list marked by a double '\0'. + * New entries are always added at the end. Deleting an entry shifts + * the remaining entries to the front. Replacing an entry is a + * combination of deleting the old and adding the new value. + * + * The environment is preceeded by a 32 bit CRC over the data part. + */ + +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +/* common/crc32.c */ +//uint32_t crc32 (uint32_t, const unsigned char *, uint); +//uint32_t crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len); + +/* + * Don't define some stuff private to andesboot target code + */ +#ifndef HOST_TOOLS + +/* board/.../env.c */ +int board_env_getchar(bd_t * bd, int index, uchar *c); +int board_env_save (bd_t * bd, env_t *data, int size); +int board_env_copy (bd_t * bd, env_t *data, int size); +uchar * board_env_getaddr(bd_t * bd, int index); + +/* + * Function Prototypes + */ +void hang (void); +void start_andesboot (void); +void main_loop (void); +int run_command (const char *cmd, int flag); +int readline (const char *const prompt); +void reset_cmd_timeout(void); + +/* board/.../... */ +int board_init(bd_t *); +int dram_init(bd_t *bd); + +/* common/display_options.c */ +void display_banner(bd_t *bd); +void display_dram_config(bd_t *bd); +void display_flash_config(ulong size); + +/* common/cmd_nvedit.c */ +//int env_init (void); +void env_relocate (void); +char *getenv (char *); +int setenv (char *, char *); + +/* $(CPU)/serial.c */ +int serial_init (void); +void serial_setbrg(void); +void serial_putc (const char); +void serial_puts (const char *); +void serial_addr (unsigned int); +int serial_getc (void); +int serial_tstc (void); + +/* common/string.c */ +char * strcpy (char * dest,const char *src); +char * strncpy (char * dest,const char *src, size_t count); +size_t strlen (const char *); +size_t strnlen (const char * s, size_t count); +int strncmp (const char * cs, const char * ct, size_t count); +int strcmp (const char * cs, const char * ct); +void * memcpy (void * dest, const void *src, size_t count); +int memcmp (const void * dest, const void *src, size_t count); +void * memset (void * s, int c, size_t count); + +void * memmove (void * dest, const void *src, size_t count); +char * strchr (const char * s, int c); + +/* common/vsprintf.c */ +ulong simple_strtoul (const char *cp,char **endp,unsigned int base); +long simple_strtol (const char *cp,char **endp,unsigned int base); +void panic (const char *fmt, ...); +int sprintf (char * buf, const char *fmt, ...); +int vsprintf (char *buf, const char *fmt, va_list args); + +void udelay (unsigned long); + +int ctrlc (void); +int had_ctrlc (void); +void clear_ctrlc (void); +int disable_ctrlc (int); + +int console_assign (int file, char *devname); + +/* */ +int icache_status (void); +void icache_enable (void); +void icache_disable(void); +int dcache_status (void); +void dcache_enable (void); +void dcache_disable(void); + +/* common/cmd_bootm.c */ +void print_image_hdr (image_header_t *hdr); + +/* cpu/.../interrupt.c */ +void enable_interrupts (void); +int disable_interrupts (void); +int interrupt_init (void); +void reset_timer (void); +ulong get_timer (ulong base); +void set_timer (ulong t); +void reset_timer_masked (void); +ulong get_timer_masked (void); +void udelay_masked (unsigned long usec); + +/* cpu/.../cpu.c */ +void cpu_init(void); +void cleanup_before_linux(void); + +extern ulong load_addr; + +/* for the following variables, see start.S */ +extern ulong _andesboot_start; /* code start */ +extern ulong _andesboot_end; /* code end */ +extern ulong _andesboot_real_end; /* first usable RAM address */ + +/* + * STDIO based functions (can always be used) + */ + +/* serial stuff */ +void serial_printf (const char *fmt, ...); + +/* stdin */ +int getc(void); +int tstc(void); + +/* stdout */ +void putc(const char c); +void puts(const char *s); +void printf(const char *fmt, ...); + +/* stderr */ +#define eputc(c) fputc(stderr, c) +#define eputs(s) fputs(stderr, s) +#define eprintf(fmt,args...) fprintf(stderr,fmt ,##args) + +/* + * FILE based functions (can only be used AFTER relocation!) + */ + +#define stdin 0 +#define stdout 1 +#define stderr 2 +#define MAX_FILES 3 + +void fprintf(int file, const char *fmt, ...); +void fputs(int file, const char *s); +void fputc(int file, const char c); +int ftstc(int file); +int fgetc(int file); + +/* Byte swapping stuff */ +#define SWAP16(x) ((((x) & 0xff) << 8) | ((x) >> 8)) +#define SWAP16c(x) ((((x) & 0xff) << 8) | ((x) >> 8)) +#define SWAP32(x) ( \ + (((x) >> 24) & 0x000000ff) | \ + (((x) >> 8) & 0x0000ff00) | \ + (((x) << 8) & 0x00ff0000) | \ + (((x) << 24) & 0xff000000) ) + +#endif /* HOST_TOOLS */ + +#endif /* _ANDESBOOT_H_ */ diff --git a/arch/nds32/include/asm/atomic.h b/arch/nds32/include/asm/atomic.h new file mode 100644 index 0000000..dede681 --- /dev/null +++ b/arch/nds32/include/asm/atomic.h @@ -0,0 +1,121 @@ +/* + * linux/include/asm-nds32/atomic.h + * + * Copyright (c) 1996 Russell King. + * Copyright (C) 2006 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 13-04-1997 RMK Made functions atomic! + * 07-12-1997 RMK Upgraded for v2.1. + * 26-08-1998 PJB Added #ifdef __KERNEL__ + */ + +/* + * CAUTION: + * - do not implement for NDS32 Arch yet. + */ + +#if 0 +#ifndef __ASM_NDS_ATOMIC_H +#define __ASM_NDS_ATOMIC_H +#include <linux/config.h> + +#ifdef CONFIG_SMP +#error SMP not supported +#endif + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#ifdef __KERNEL__ +//#include <asm/proc/system.h> + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v,i) (((v)->counter) = (i)) + +static inline void atomic_add(int i, volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic_dec(volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + +static inline int atomic_dec_and_test(volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val -= 1; + local_irq_restore(flags); + + return val == 0; +} + +static inline int atomic_add_negative(int i, volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val += i; + local_irq_restore(flags); + + return val < 0; +} + +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long flags; + + local_irq_save(flags); + *addr &= ~mask; + local_irq_restore(flags); +} + +/* Atomic operations are already serializing on ARM */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#endif +#endif +#endif // 0 diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h new file mode 100644 index 0000000..a31532c --- /dev/null +++ b/arch/nds32/include/asm/bitops.h @@ -0,0 +1,148 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + * + * Please note that the code in this file should never be included + * from user space. Many of these are not implemented in assembler + * since they would be too costly. Also, they require priviledged + * instructions (which are not available from user mode) to ensure + * that they are atomic. + */ + +#ifndef __ASM_NDS_BITOPS_H +#define __ASM_NDS_BITOPS_H + +#ifdef __KERNEL__ + +#define smp_mb__before_clear_bit() do { } while (0) +#define smp_mb__after_clear_bit() do { } while (0) + +/* + * Function prototypes to keep gcc -Wall happy. + */ +extern void set_bit(int nr, volatile void * addr); + +static inline void __set_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); +} + +extern void clear_bit(int nr, volatile void * addr); + +static inline void __clear_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); +} + +extern void change_bit(int nr, volatile void * addr); + +static inline void __change_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); +} + +extern int test_and_set_bit(int nr, volatile void * addr); + +static inline int __test_and_set_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval | mask; + return oldval & mask; +} + +extern int test_and_clear_bit(int nr, volatile void * addr); + +static inline int __test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; + return oldval & mask; +} + +extern int test_and_change_bit(int nr, volatile void * addr); + +static inline int __test_and_change_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; + return oldval & mask; +} + +extern int find_first_zero_bit(void * addr, unsigned size); +extern int find_next_zero_bit(void * addr, int size, int offset); + +/* + * This routine doesn't need to be atomic. + */ +static inline int test_bit(int nr, const void * addr) +{ + return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); +} + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) +{ + int k; + + word = ~word; + k = 31; + if (word & 0x0000ffff) { k -= 16; word <<= 16; } + if (word & 0x00ff0000) { k -= 8; word <<= 8; } + if (word & 0x0f000000) { k -= 4; word <<= 4; } + if (word & 0x30000000) { k -= 2; word <<= 2; } + if (word & 0x40000000) { k -= 1; } + return k; +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +/* redefined in include/linux/bitops.h */ +//#define ffs(x) generic_ffs(x) + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#define ext2_set_bit test_and_set_bit +#define ext2_clear_bit test_and_clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_NDS_BITOPS_H */ diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h new file mode 100644 index 0000000..d41c5fa --- /dev/null +++ b/arch/nds32/include/asm/byteorder.h @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ + +#ifndef __ASM_NDS_BYTEORDER_H +#define __ASM_NDS_BYTEORDER_H + +#include <asm/types.h> + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __NDSEB__ +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h new file mode 100644 index 0000000..0826f29 --- /dev/null +++ b/arch/nds32/include/asm/config.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h new file mode 100644 index 0000000..f87f36d --- /dev/null +++ b/arch/nds32/include/asm/global_data.h @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - so far no one uses the macros defined in this head file. + **************************************************************/ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long fb_base; /* base address of frame buffer */ +#ifdef CONFIG_VFD + unsigned char vfd_type; /* display type */ +#endif +#if 0 + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long bus_clk; + unsigned long ram_size; /* RAM size */ + unsigned long reset_status; /* reset status register at boot */ +#endif + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#if 0 +//extern gd_t *global_data; +//#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data +extern volatile gd_t g_gd; +#define DECLARE_GLOBAL_DATA_PTR static volatile gd_t *gd = &g_gd +#else +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("$r8") +#endif + +#endif /* __ASM_GBL_DATA_H */ diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h new file mode 100644 index 0000000..8a78263 --- /dev/null +++ b/arch/nds32/include/asm/io.h @@ -0,0 +1,352 @@ +/* + * linux/include/asm-nds/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_NDS_IO_H +#define __ASM_NDS_IO_H + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc... include asm/io.h + **************************************************************/ + +#ifdef __KERNEL__ + +#include <linux/types.h> +#include <asm/byteorder.h> +#include <asm/memory.h> +#if 0 /* XXX###XXX */ +#include <asm/arch/hardware.h> +#endif /* XXX###XXX */ + +static inline void sync(void) +{ +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) __arch_putb(v,a) +#define __raw_writew(v,a) __arch_putw(v,a) +#define __raw_writel(v,a) __arch_putl(v,a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +#define writeb(v,a) __arch_putb(v,a) +#define writew(v,a) __arch_putw(v,a) +#define writel(v,a) __arch_putl(v,a) + +#define readb(a) __arch_getb(a) +#define readw(a) __arch_getw(a) +#define readl(a) __arch_getl(a) + + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) +#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) +#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) + +#define __raw_base_readb(base,off) __arch_base_getb(base,off) +#define __raw_base_readw(base,off) __arch_base_getw(base,off) +#define __raw_base_readl(base,off) __arch_base_getl(base,off) + +/* + * Now, pick up the machine-defined IO definitions + */ +#if 0 /* XXX###XXX */ +#include <asm/arch/io.h> +#endif /* XXX###XXX */ + +/* + * IO port access primitives + * ------------------------- + * + * The ARM doesn't have special IO access instructions; all IO is memory + * mapped. Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerious + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v,p) __raw_writeb(v,__io(p)) +#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p,d,l) __raw_writesb(__io(p),d,l) +#define outsw(p,d,l) __raw_writesw(__io(p),d,l) +#define outsl(p,d,l) __raw_writesl(__io(p),d,l) + +#define insb(p,d,l) __raw_readsb(__io(p),d,l) +#define insw(p,d,l) __raw_readsw(__io(p),d,l) +#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#endif + +#define outb_p(val,port) outb((val),(port)) +#define outw_p(val,port) outw((val),(port)) +#define outl_p(val,port) outl((val),(port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. If you want a + * physical address, use __ioremap instead. + */ +extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); +extern void __iounmap(void *addr); + +/* + * Generic ioremap support. + * + * Define: + * iomem_valid_addr(off,size) + * iomem_to_phys(off) + */ +#ifdef iomem_valid_addr +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret; \ + }) + +#define __arch_iounmap __iounmap +#endif + +#define ioremap(off,sz) __arch_ioremap((off),(sz),0) +#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) +#define iounmap(_addr) __arch_iounmap(_addr) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +extern void __readwrite_bug(const char *fn); + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) +#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) + +#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) +#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) +#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) + +#define eth_io_copy_and_sum(s,c,l,b) \ + eth_copy_and_sum((s),__mem_pci(c),(l),(b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#elif !defined(readb) + +#define readb(addr) (__readwrite_bug("readb"),0) +#define readw(addr) (__readwrite_bug("readw"),0) +#define readl(addr) (__readwrite_bug("readl"),0) +#define writeb(v,addr) __readwrite_bug("writeb") +#define writew(v,addr) __readwrite_bug("writew") +#define writel(v,addr) __readwrite_bug("writel") + +#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") + +#define check_signature(io,sig,len) (0) + +#endif /* __mem_pci */ + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) +#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + eth_copy_and_sum((a),__mem_isa(b),(c),(d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) +#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") +#define isa_writew(val,addr) __readwrite_bug("isa_writew") +#define isa_writel(val,addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io,sig,len) (0) + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ +#endif /* __ASM_NDS_IO_H */ + diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h new file mode 100644 index 0000000..141721c --- /dev/null +++ b/arch/nds32/include/asm/memory.h @@ -0,0 +1,141 @@ +/* + * linux/include/asm-arm/memory.h + * + * Copyright (C) 2000-2002 Russell King + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: this file should not be included by non-asm/.h files + */ +#ifndef __ASM_NDS_MEMORY_H +#define __ASM_NDS_MEMORY_H + +#if 0 /* XXX###XXX */ + +#include <linux/config.h> +#include <asm/arch/memory.h> + +/* + * PFNs are used to describe any physical page; this means + * PFN 0 == physical address 0. + * + * This is the PFN of the first RAM page in the kernel + * direct-mapped view. We assume this is the first page + * of RAM in the mem_map as well. + */ +#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) + +/* + * These are *only* valid on the kernel direct mapped RAM memory. + */ +static inline unsigned long virt_to_phys(void *x) +{ + return __virt_to_phys((unsigned long)(x)); +} + +static inline void *phys_to_virt(unsigned long x) +{ + return (void *)(__phys_to_virt((unsigned long)(x))); +} + +#define __pa(x) __virt_to_phys((unsigned long)(x)) +#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) + +/* + * Virtual <-> DMA view memory address translations + * Again, these are *only* valid on the kernel direct mapped RAM + * memory. Use of these is *depreciated*. + */ +#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) +#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) + +/* + * Conversion between a struct page and a physical address. + * + * Note: when converting an unknown physical address to a + * struct page, the resulting pointer must be validated + * using VALID_PAGE(). It must return an invalid struct page + * for any physical address not corresponding to a system + * RAM address. + * + * page_to_pfn(page) convert a struct page * to a PFN number + * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * + * pfn_valid(pfn) indicates whether a PFN number is valid + * + * virt_to_page(k) convert a _valid_ virtual address to struct page * + * virt_addr_valid(k) indicates whether a virtual address is valid + */ +#ifndef CONFIG_DISCONTIGMEM + +#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) +#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) +#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) + +#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) +#define virt_addr_valid(kaddr) ((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory) + +#define PHYS_TO_NID(addr) (0) + +#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) + +#else + +/* + * This is more complex. We have a set of mem_map arrays spread + * around in memory. + */ +#define page_to_pfn(page) \ + (((page) - page_zone(page)->zone_mem_map) \ + + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT)) + +#define pfn_to_page(pfn) \ + (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) + +#define pfn_valid(pfn) \ + ({ \ + unsigned int node = PFN_TO_NID(pfn); \ + struct pglist_data *nd = NODE_DATA(node); \ + ((node < NR_NODES) && \ + ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\ + }) + +#define virt_to_page(kaddr) \ + (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) + +#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < NR_NODES) + +/* + * Common discontigmem stuff. + * PHYS_TO_NID is used by the ARM kernel/setup.c + */ +#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) + +/* + * 2.4 compatibility + * + * VALID_PAGE returns a non-zero value if given page pointer is valid. + * This assumes all node's mem_maps are stored within the node they + * refer to. This is actually inherently buggy. + */ +#define VALID_PAGE(page) \ +({ unsigned int node = KVADDR_TO_NID(page); \ + ((node < NR_NODES) && \ + ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \ +}) + +#endif + +/* + * We should really eliminate virt_to_bus() here - it's depreciated. + */ +#define page_to_bus(page) (virt_to_bus(page_address(page))) + +#endif /* XXX###XXX */ + +#endif /* __ASM_NDS_MEMORY_H */ diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h new file mode 100644 index 0000000..285538b --- /dev/null +++ b/arch/nds32/include/asm/posix_types.h @@ -0,0 +1,85 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 05-03-2010 Modified for arch NDS32 + */ +#ifndef __ARCH_NDS_POSIX_TYPES_H +#define __ARCH_NDS_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) + +#endif + +#endif // __ARCH_NDS_POSIX_TYPES_H + diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h new file mode 100644 index 0000000..f5b7470 --- /dev/null +++ b/arch/nds32/include/asm/processor.h @@ -0,0 +1,145 @@ +/* + * linux/include/asm-arm/processor.h + * + * Copyright (C) 1995-2002 Russell King + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_NDS_PROCESSOR_H +#define __ASM_NDS_PROCESSOR_H +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - so far some files include /asm/processor.h, but + * no one uses the macros defined in this head file. + **************************************************************/ +#if 0 +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#define FP_SIZE 35 + +struct fp_hard_struct { + unsigned int save[FP_SIZE]; /* as yet undefined */ +}; + +struct fp_soft_struct { + unsigned int save[FP_SIZE]; /* undefined information */ +}; + +union fp_state { + struct fp_hard_struct hard; + struct fp_soft_struct soft; +}; + +typedef unsigned long mm_segment_t; /* domain register */ + +#ifdef __KERNEL__ + +#define EISA_bus 0 +#define MCA_bus 0 +#define MCA_bus__is_a_macro + +#include <asm/atomic.h> +#include <asm/ptrace.h> +#if 0 /* XXX###XXX */ +#include <asm/arch/memory.h> +#endif /* XXX###XXX */ +#include <asm/proc/processor.h> +#include <asm/types.h> + +union debug_insn { + u32 arm; + u16 thumb; +}; + +struct debug_entry { + u32 address; + union debug_insn insn; +}; + +struct debug_info { + int nsaved; + struct debug_entry bp[2]; +}; + +struct thread_struct { + atomic_t refcount; + /* fault info */ + unsigned long address; + unsigned long trap_no; + unsigned long error_code; + /* floating point */ + union fp_state fpstate; + /* debugging */ + struct debug_info debug; + /* context info */ + struct context_save_struct *save; + EXTRA_THREAD_STRUCT +}; + +#define INIT_THREAD { \ + refcount: ATOMIC_INIT(1), \ + EXTRA_THREAD_STRUCT_INIT \ +} + +/* + * Return saved PC of a blocked thread. + */ +static inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + return t->save ? pc_pointer(t->save->pc) : 0; +} + +static inline unsigned long thread_saved_fp(struct thread_struct *t) +{ + return t->save ? t->save->fp : 0; +} + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +extern void release_thread(struct task_struct *); + +/* Copy and release all segment info associated with a VM */ +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define THREAD_SIZE (8192) + +extern struct task_struct *alloc_task_struct(void); +extern void __free_task_struct(struct task_struct *); +#define get_task_struct(p) atomic_inc(&(p)->thread.refcount) +#define free_task_struct(p) \ + do { \ + if (atomic_dec_and_test(&(p)->thread.refcount)) \ + __free_task_struct((p)); \ + } while (0) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +#define cpu_relax() barrier() + +/* + * Create a new kernel thread + */ +extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +#endif + +#endif /* __ASM_ARM_PROCESSOR_H */ +#endif diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h new file mode 100644 index 0000000..098b843 --- /dev/null +++ b/arch/nds32/include/asm/ptrace.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - included in common.h + **************************************************************/ + +#if 0 +#ifndef __ASM_NDS_PTRACE_H +#define __ASM_NDS_PTRACE_H + +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 + +#define PTRACE_SETOPTIONS 21 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +#include <asm/proc/ptrace.h> + +#ifndef __ASSEMBLY__ +#define pc_pointer(v) \ + ((v) & ~PCMASK) + +#define instruction_pointer(regs) \ + (pc_pointer((regs)->ARM_pc)) + +#ifdef __KERNEL__ +extern void show_regs(struct pt_regs *); + +#define predicate(x) (x & 0xf0000000) +#define PREDICATE_ALWAYS 0xe0000000 + +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_NDS_PTRACE_H */ +#endif diff --git a/arch/nds32/include/asm/ptregs.h b/arch/nds32/include/asm/ptregs.h new file mode 100644 index 0000000..5cb5521 --- /dev/null +++ b/arch/nds32/include/asm/ptregs.h @@ -0,0 +1,83 @@ +/* + * linux/include/asm-arm/proc-armv/ptrace.h + * + * Copyright (C) 1996-1999 Russell King + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PTREGS_H +#define __PTREGS_H + +#define USR_MODE 0x00 +#define SU_MODE 0x01 +#define HV_MODE 0x10 +#define MODE_MASK (0x03<<3) +#define GIE_BIT 0x01 + +#ifndef __ASSEMBLY__ + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long uregs[39]; +}; + +#define PTREGS(reg) [reg] +#define R0 uregs[1] // R0 +#define R1 uregs[2] +#define R2 uregs[3] +#define R3 uregs[4] +#define R4 uregs[5] +#define R5 uregs[6] +#define R6 uregs[7] +#define R7 uregs[8] +#define R8 uregs[9] +#define R9 uregs[10] +#define R10 uregs[11] +#define R11 uregs[12] +#define R12 uregs[13] +#define R13 uregs[14] +#define R14 uregs[15] +#define R15 uregs[16] +#define R16 uregs[17] +#define R17 uregs[18] +#define R18 uregs[19] +#define R19 uregs[20] +#define R20 uregs[21] +#define R21 uregs[22] +#define R22 uregs[23] +#define R23 uregs[24] +#define R24 uregs[25] +#define R25 uregs[26] +#define R26 uregs[27] +#define R27 uregs[28] +#define FP uregs[29] //R28 +#define GP uregs[30] //R29 +#define RA uregs[31] //R30 +#define SP uregs[32] //R31 +#define D0HI uregs[33] +#define D0LO uregs[34] +#define D1HI uregs[35] +#define D1LO uregs[36] +#define PSW uregs[37] //IR0 +#define PC uregs[38] //PC + + +#define processor_mode(regs) \ + (((regs)->PSW & MODE_MASK)>>3) + +#define interrupts_enabled(regs) \ + ((regs)->PSW & GIE_BIT) + +#endif /* __ASSEMBLY__ */ + +#endif + diff --git a/arch/nds32/include/asm/setup.h b/arch/nds32/include/asm/setup.h new file mode 100644 index 0000000..f8b044b --- /dev/null +++ b/arch/nds32/include/asm/setup.h @@ -0,0 +1,274 @@ +/* + * linux/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See linux/Documentation/arm/Setup + * for more info. + * + * NOTE: + * This file contains two ways to pass information from the boot + * loader to the kernel. The old struct param_struct is deprecated, + * but it will be kept in the kernel for 5 years from now + * (2001). This will allow boot loaders to convert to the new struct + * tag way. + */ + +#ifndef __ASM_NDS_SETUP_H +#define __ASM_NDS_SETUP_H + +/* + * Usage: + * - do not go blindly adding fields, add them at the end + * - when adding fields, don't rely on the address until + * a patch from me has been released + * - unused fields should be zero (for future expansion) + * - this structure is relatively short-lived - only + * guaranteed to contain useful data in setup_arch() + */ +#define COMMAND_LINE_SIZE 1024 + +/* This is the old deprecated way to pass parameters to the kernel */ +struct param_struct { + union { + struct { + unsigned long page_size; /* 0 */ + unsigned long nr_pages; /* 4 */ + unsigned long ramdisk_size; /* 8 */ + unsigned long flags; /* 12 */ +#define FLAG_READONLY 1 +#define FLAG_RDLOAD 4 +#define FLAG_RDPROMPT 8 + unsigned long rootdev; /* 16 */ + unsigned long video_num_cols; /* 20 */ + unsigned long video_num_rows; /* 24 */ + unsigned long video_x; /* 28 */ + unsigned long video_y; /* 32 */ + unsigned long memc_control_reg; /* 36 */ + unsigned char sounddefault; /* 40 */ + unsigned char adfsdrives; /* 41 */ + unsigned char bytes_per_char_h; /* 42 */ + unsigned char bytes_per_char_v; /* 43 */ + unsigned long pages_in_bank[4]; /* 44 */ + unsigned long pages_in_vram; /* 60 */ + unsigned long initrd_start; /* 64 */ + unsigned long initrd_size; /* 68 */ + unsigned long rd_start; /* 72 */ + unsigned long system_rev; /* 76 */ + unsigned long system_serial_low; /* 80 */ + unsigned long system_serial_high; /* 84 */ + unsigned long mem_fclk_21285; /* 88 */ + } s; + char unused[256]; + } u1; + union { + char paths[8][128]; + struct { + unsigned long magic; + char n[1024 - sizeof(unsigned long)]; + } s; + } u2; + char commandline[COMMAND_LINE_SIZE]; +}; + + + +/* + * The new way of passing information: a list of tagged entries + */ + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; /* bit 0 = read-only */ + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + u32 size; + u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + u8 x; + u8 y; + u16 video_page; + u8 video_mode; + u8 video_cols; + u16 video_ega_bx; + u8 video_lines; + u8 video_isvga; + u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RDIMG 0x54410004 + +struct tag_mem_range { + u32 addr; + u32 size; + struct tag_mem_range * next; +}; + +struct tag_ramdisk { + u32 flags; /* bit 0 = load, bit 1 = prompt */ + u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* describes where the compressed ramdisk image lives */ +#define ATAG_INITRD 0x54410005 + +struct tag_initrd { + u32 start; /* physical start address */ + u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + u32 low; + u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + u16 lfb_width; + u16 lfb_height; + u16 lfb_depth; + u16 lfb_linelength; + u32 lfb_base; + u32 lfb_size; + u8 red_size; + u8 red_pos; + u8 green_size; + u8 green_pos; + u8 blue_size; + u8 blue_pos; + u8 rsvd_size; + u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* acorn RiscPC specific information */ +#define ATAG_ACORN 0x41000101 + +struct tag_acorn { + u32 memc_control_reg; + u32 vram_pages; + u8 sounddefault; + u8 adfsdrives; +}; + +/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ +#define ATAG_MEMCLK 0x41000402 + +struct tag_memclk { + u32 fmemclk; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + struct tag_mem_range mem_range; + /* + * Acorn specific + */ + struct tag_acorn acorn; + + /* + * DC21285 specific + */ + struct tag_memclk memclk; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(const struct tag *); +}; + +#define __tag __attribute__((unused, __section__(".taglist"))) +#define __tagtable(tag, fn) \ +static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +/* + * Memory map description + */ +#define NR_BANKS 8 + +struct meminfo { + int nr_banks; + unsigned long end; + struct { + unsigned long start; + unsigned long size; + int node; + } bank[NR_BANKS]; +}; + +extern struct meminfo meminfo; + +#endif diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h new file mode 100644 index 0000000..5a8a7ed --- /dev/null +++ b/arch/nds32/include/asm/string.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_NDS_STRING_H +#define __ASM_NDS_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#if 0 +extern void __memzero(void *ptr, __kernel_size_t n); + +#define memset(p,v,n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p),(n)); \ + else \ + memset((p),(v),(n)); \ + } \ + (p); \ + }) + +#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) +#else +extern void memzero(void *ptr, __kernel_size_t n); +#endif + +#endif // __ASM_NDS_STRING_H diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h new file mode 100644 index 0000000..b3d7c61 --- /dev/null +++ b/arch/nds32/include/asm/types.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_NDS_TYPES_H +#define __ASM_NDS_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/*typedef unsigned long ulong;*/ /* in /linux/types.h */ +/*typedef unsigned short ushort;*//* in /linux/types.h */ +/*typedef unsigned char uchar;*/ /* in common.h */ + +/* in /linux/types.h */ +/* +typedef unsigned int uint32_t; +typedef unsigned short uint16_t; +typedef unsigned char uint8_t; +*/ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/*typedef unsigned int uint; */ /* in /linux/types.h */ + +typedef volatile unsigned char vuchar; +typedef volatile unsigned long vulong; +typedef volatile unsigned short vushort; + +/* both of the following 2 types are defined in Posix_types.h [Hill_20090306]*/ +/*typedef long time_t;*/ +/*typedef long suseconds_t;*/ + +#include <stddef.h> + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h new file mode 100644 index 0000000..c5deda8 --- /dev/null +++ b/arch/nds32/include/asm/u-boot.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +#include <environment.h> + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + + env_t *bi_env; + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + + struct /* RAM configuration */ + { + unsigned long start; + unsigned long size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; + + struct bd_info_ext bi_ext; /* board specific extension */ +} bd_t; + +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h new file mode 100644 index 0000000..3524d06 --- /dev/null +++ b/arch/nds32/include/asm/unaligned.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef _ASM_NDS_UNALIGNED_H +#define _ASM_NDS_UNALIGNED_H + +#include <compiler.h> +/* + * Select endianness + */ +//#if defined(__NDSEL__) +#ifndef __NDSEB__ +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +//#elif defined(__NDSEB__) +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +//#else +//#error invalid endian +#endif /* __NDSEB__ */ + +#include <asm/byteorder.h> + +#include <linux/unaligned/le_byteshift.h> +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> + +#endif /* _ASM_NDS_UNALIGNED_H */

Add nds32 based board adp-ag101 support.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- board/AndesTech/adp-ag101/Makefile | 60 ++++++++++++++ board/AndesTech/adp-ag101/adp-ag101.c | 144 +++++++++++++++++++++++++++++++++ board/AndesTech/adp-ag101/config.mk | 46 +++++++++++ 3 files changed, 250 insertions(+), 0 deletions(-) create mode 100644 board/AndesTech/adp-ag101/Makefile create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c create mode 100644 board/AndesTech/adp-ag101/config.mk

diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile new file mode 100644 index 0000000..53d8592 --- /dev/null +++ b/board/AndesTech/adp-ag101/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH <www.elinos.com> +# Marius Groeger mgroeger@sysgo.de +# +# Copyright (C) 2006 Andes Technology Corporation +# Shawn Lin, Andes Tech Crop. nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +OBJS-y += adp-ag101.o ../common/serial.o ../common/flib_serial.o \ + ../common/flash.o ../common/flib_flash.o ../common/env.o +OBJS-$(CONFIG_DRIVER_FTMAC100) += ../common/ftmac100.o +OBJS-$(CONFIG_DRIVER_FTPCI100) += ../common/ftpci100.o +OBJS-$(CONFIG_DRIVER_FOTG2xx) += ../common/fotg2xx.o + +SOBJS := +OBJS := $(OBJS-y) + +all: $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c new file mode 100644 index 0000000..8e56999 --- /dev/null +++ b/board/AndesTech/adp-ag101/adp-ag101.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/andesboot.h> +//#include <porting.h> +#include "../include/porting.h" + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init(bd_t *bd) +{ +#ifdef not_complete_yet + /* Activate LED flasher */ + IO_LEDFLSH = 0x40; +#endif /* end_of_not */ + + /* arch number MACH_TYPE_EDB7312 */ + bd->bi_arch_number = 91; + + /* location of boot parameters */ + bd->bi_boot_params = 0x400; + + return 1; +} + +/* + * bank_num ==> setting the config of which bank (0, 1st, 2nd, ..) + * data_width ==> the width of the SDRAM module on the bank + * sdram_size ==> the size of each module + * bus_width ==> the width of data bus + * bank_size ==> the total memory size of the bank (should be equal as "sdram_size * how many modules") + */ +#define SDRAM_MODULE_WIDTH_4 0 +#define SDRAM_MODULE_WIDTH_8 (1<<12) +#define SDRAM_MODULE_WIDTH_16 (2<<12) +#define SDRAM_MODULE_WIDTH_32 (3<<12) + + +// 16M bit, 64M bit,... +#define SDRAM_MODULE_SIZE_16M 0 +#define SDRAM_MODULE_SIZE_64M (1<<8) +#define SDRAM_MODULE_SIZE_128M (2<<8) +#define SDRAM_MODULE_SIZE_256M (3<<8) + +#define SDRAM_BUS_WIDTH_8 0 +#define SDRAM_BUS_WIDTH_16 (1<<4) +#define SDRAM_BUS_WIDTH_32 (2<<4) + +// 1M byte, 2M byte,... +#define SDRAM_BANK_SIZE_1M 0 +#define SDRAM_BANK_SIZE_2M 1 +#define SDRAM_BANK_SIZE_4M 2 +#define SDRAM_BANK_SIZE_8M 3 +#define SDRAM_BANK_SIZE_16M 4 +#define SDRAM_BANK_SIZE_32M 5 +#define SDRAM_BANK_SIZE_64M 6 +#define SDRAM_BANK_SIZE_128M 7 +#define SDRAM_BANK_SIZE_256M 8 + + +#define NDS32_COMMON_BANK_REG_BASE 0x0c + +void sdram_config(int bank_num, u32 bank_base, int data_width, int sdram_size, int bus_width, int bank_size) +{ + u32 config_reg_val; + + config_reg_val = (1UL<<28) | (bank_base>>4)&0x0fff0000 | data_width | sdram_size | bus_width | bank_size; + + cpe_outl( NDS32_COMMON_SDRAMC_BASE + NDS32_COMMON_BANK_REG_BASE + bank_num*4, config_reg_val); +} + +int dram_init(bd_t *bd) +{ +#ifdef not_complete_yet + // initialize the base address of SDRAM + sdram_config( 0, 0x0, SDRAM_MODULE_WIDTH_8, SDRAM_MODULE_SIZE_64M, SDRAM_BUS_WIDTH_32, SDRAM_BANK_SIZE_32M); + sdram_config( 1, 0x02000000, SDRAM_MODULE_WIDTH_8, SDRAM_MODULE_SIZE_64M, SDRAM_BUS_WIDTH_32, SDRAM_BANK_SIZE_32M); + sdram_config( 2, 0x04000000, SDRAM_MODULE_WIDTH_8, SDRAM_MODULE_SIZE_64M, SDRAM_BUS_WIDTH_32, SDRAM_BANK_SIZE_32M); + sdram_config( 3, 0x06000000, SDRAM_MODULE_WIDTH_8, SDRAM_MODULE_SIZE_64M, SDRAM_BUS_WIDTH_32, SDRAM_BANK_SIZE_32M); +#endif /* end_of_not */ + + int i; + u32 config_reg_ptr; + u32 config_reg_val; + u32 phys_sdram_size = 0; + + /* for convinence, we assume there is only one bank in total. + * (boot_ini will put all sdram at the continues address with the beginning is 0) + */ + for (i=0; i<8; ++i) + { + config_reg_ptr = NDS32_COMMON_SDRAMC_BASE + NDS32_COMMON_BANK_REG_BASE + i*4; + config_reg_val = cpe_inl(config_reg_ptr); + + if ( (config_reg_val & 0x10000000) == 0) + { + continue; + } + + switch (config_reg_val & 0x0f) + { + case SDRAM_BANK_SIZE_1M: phys_sdram_size += 0x100000; break; + case SDRAM_BANK_SIZE_2M: phys_sdram_size += 0x200000; break; + case SDRAM_BANK_SIZE_4M: phys_sdram_size += 0x400000; break; + case SDRAM_BANK_SIZE_8M: phys_sdram_size += 0x800000; break; + case SDRAM_BANK_SIZE_16M: phys_sdram_size += 0x1000000; break; + case SDRAM_BANK_SIZE_32M: phys_sdram_size += 0x2000000; break; + case SDRAM_BANK_SIZE_64M: phys_sdram_size += 0x4000000; break; + case SDRAM_BANK_SIZE_128M: phys_sdram_size += 0x8000000; break; + case SDRAM_BANK_SIZE_256M: phys_sdram_size += 0x10000000; break; + } + } + bd->bi_dram[0].start = PHYS_SDRAM_0; + bd->bi_dram[0].size = phys_sdram_size; + + return phys_sdram_size; +} diff --git a/board/AndesTech/adp-ag101/config.mk b/board/AndesTech/adp-ag101/config.mk new file mode 100644 index 0000000..16bf578 --- /dev/null +++ b/board/AndesTech/adp-ag101/config.mk @@ -0,0 +1,46 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, gj@denx.de +# David Mueller, ELSOFT AG, d.mueller@elsoft.ch +# +# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# +# Copyright (C) 2006 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# SMDK2410 has 1 bank of 32 MB DRAM +# +# 3000'0000 to 3200'0000 +# +# Linux-Kernel is expected to be at 3000'0000, entry 3000'0000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 31F0'0000 +# +# download areas is 3100'0000 + +PLATFORM_RELFLAGS += -gdwarf-2 +TEXT_BASE = 0x03200000 +LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds +EXTERN_LIB += $(shell $(CC) -print-file-name=include)/../static/el/libgcc.a

Add nds32 based common board related support.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- board/AndesTech/common/env.c | 138 ++++++ board/AndesTech/common/flash.c | 621 +++++++++++++++++++++++++++ board/AndesTech/common/flib_flash.c | 721 ++++++++++++++++++++++++++++++++ board/AndesTech/common/flib_serial.c | 373 +++++++++++++++++ board/AndesTech/common/fotg2xx.c | 60 +++ board/AndesTech/common/ftmac100.c | 766 ++++++++++++++++++++++++++++++++++ board/AndesTech/common/ftpci100.c | 712 +++++++++++++++++++++++++++++++ board/AndesTech/common/serial.c | 141 +++++++ 8 files changed, 3532 insertions(+), 0 deletions(-) create mode 100644 board/AndesTech/common/env.c create mode 100644 board/AndesTech/common/flash.c create mode 100644 board/AndesTech/common/flib_flash.c create mode 100644 board/AndesTech/common/flib_serial.c create mode 100644 board/AndesTech/common/fotg2xx.c create mode 100644 board/AndesTech/common/ftmac100.c create mode 100644 board/AndesTech/common/ftpci100.c create mode 100644 board/AndesTech/common/serial.c

diff --git a/board/AndesTech/common/env.c b/board/AndesTech/common/env.c new file mode 100644 index 0000000..55e2b66 --- /dev/null +++ b/board/AndesTech/common/env.c @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/andesboot.h> + +static int check_crc(bd_t *bd) +{ + /* need to calculate crc? */ + if (bd->bi_ext.env_crc_valid == 0) + { + env_t *env = (env_t *)CONFIG_ENV_ADDR; + + if (crc32(0, env->data, sizeof(env->data)) == env->crc) + bd->bi_ext.env_crc_valid = 1; + else + bd->bi_ext.env_crc_valid = -1; + } + return bd->bi_ext.env_crc_valid > 0; +} + + +/* + * save environment buffer back to flash + * returns -1 on error, 0 if ok + */ +int board_env_save(bd_t *bd, env_t *env, int size) +{ + int rc; + ulong start_addr, end_addr; + + +//no CONFIG_ENV_ADDR_REDUND +#if CONFIG_ENV_SIZE > CONFIG_ENV_SECT_SIZE /* modified: <= to >, by Hill, 20090313 */ +#error Make sure that CONFIG_ENV_SIZE <= CONFIG_ENV_SECT_SIZE +#endif + + start_addr = CONFIG_ENV_ADDR; + end_addr = start_addr + CONFIG_ENV_SIZE - 1; + + rc = flash_sect_protect(0, CONFIG_ENV_ADDR, end_addr); + if (rc < 0) + return rc; + + rc = flash_sect_erase(start_addr, end_addr); + if (rc < 0) { + flash_sect_protect(1, start_addr, end_addr); + flash_perror(rc); + return rc; + } + + printf("Saving Environment to Flash..."); + rc = flash_write((uchar*)env, start_addr, size); + if (rc < 0) + flash_perror(rc); + else + printf("done.\n"); + + (void)flash_sect_protect(1, start_addr, end_addr); + + return 0; +} + +/* + * copy environment to memory + * returns -1 on error, 0 if ok + */ +int board_env_copy(bd_t *bd, env_t *data, int size) +{ + env_t *env = (env_t *)CONFIG_ENV_ADDR; + + if (check_crc(bd)) { + memcpy(data, env, sizeof(env_t)); + return 0; + } + + return -1; +} + +/* + * try to read env character at offset #index + * + * called before the environment is copied to ram + * returns -1 on error, 0 if ok + */ +int board_env_getchar(bd_t * bd, int index, uchar *c) +{ + env_t *env = (env_t *)CONFIG_ENV_ADDR; + + /* check environment crc */ + if (index < sizeof(env->data) && check_crc(bd)) { + *c = env->data[index]; + return 0; + } + + return -1; +} + +/* + * try to read env character at offset #index + * + * called before the environment is copied to ram + * returns -1 on error, 0 if ok + */ +uchar *board_env_getaddr(bd_t * bd, int index) +{ + env_t *env = (env_t *)CONFIG_ENV_ADDR; + + /* check environment crc */ + if (index < sizeof(env->data) && check_crc(bd)) + return &env->data[index]; + + return 0; +} diff --git a/board/AndesTech/common/flash.c b/board/AndesTech/common/flash.c new file mode 100644 index 0000000..4dc68c9 --- /dev/null +++ b/board/AndesTech/common/flash.c @@ -0,0 +1,621 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/andesboot.h> +#include "../include/porting.h" +#include "../include/flib_flash.h" +//#include <flash.h> +//#include <andes.h> + +ulong myflush(void); + +#define FLASH_BANK_SIZE 0x800000 +#define MAIN_SECT_SIZE 0x20000 +#define PARAM_SECT_SIZE 0x4000 + +#define MX_SECTOR_COUNT 19 +#define SST39VF080_SECTOR_COUNT 256 +#define SST39VF016_SECTOR_COUNT 512 + +/* puzzle magic for lart + * data_*_flash are def'd in flashasm.S + */ + +extern u32 data_from_flash(u32); +extern u32 data_to_flash(u32); + +#define PUZZLE_FROM_FLASH(x) (x) +#define PUZZLE_TO_FLASH(x) (x) + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + + +#define CMD_IDENTIFY 0x90909090 +#define CMD_ERASE_SETUP 0x20202020 +#define CMD_ERASE_CONFIRM 0xD0D0D0D0 +#define CMD_PROGRAM 0x40404040 +#define CMD_RESUME 0xD0D0D0D0 +#define CMD_SUSPEND 0xB0B0B0B0 +#define CMD_STATUS_READ 0x70707070 +#define CMD_STATUS_RESET 0x50505050 + +#define BIT_BUSY 0x80808080 +#define BIT_ERASE_SUSPEND 0x40404040 +#define BIT_ERASE_ERROR 0x20202020 +#define BIT_PROGRAM_ERROR 0x10101010 +#define BIT_VPP_RANGE_ERROR 0x08080808 +#define BIT_PROGRAM_SUSPEND 0x04040404 +#define BIT_PROTECT_ERROR 0x02020202 +#define BIT_UNDEFINED 0x01010101 + +#define BIT_SEQUENCE_ERROR 0x30303030 +#define BIT_TIMEOUT 0x80000000 + + +// -------------------------------------------------------------------- +// In bytes +// -------------------------------------------------------------------- +#define SRAM_BANK_SIZE_32K 0xb0 +#define SRAM_BANK_SIZE_64K 0xc0 +#define SRAM_BANK_SIZE_128K 0xd0 +#define SRAM_BANK_SIZE_256K 0xe0 +#define SRAM_BANK_SIZE_512K 0xf0 +#define SRAM_BANK_SIZE_1M 0x00 +#define SRAM_BANK_SIZE_2M 0x10 +#define SRAM_BANK_SIZE_4M 0x20 +#define SRAM_BANK_SIZE_8M 0x30 +#define SRAM_BANK_SIZE_16M 0x40 +#define SRAM_BANK_SIZE_32M 0x50 + + +#define SRAM_BUS_WIDTH_8 0 +#define SRAM_BUS_WIDTH_16 1 +#define SRAM_BUS_WIDTH_32 2 + +#define K (1024) + + // pleaase change the timing parameter for different SRAM type +#define TIMING_PARAMETER (STMC_BANK_TM_AST3|STMC_BANK_TM_CTW3|STMC_BANK_TM_AT1_F|STMC_BANK_TM_AT2_3|STMC_BANK_TM_WTC3|STMC_BANK_TM_AHT3|STMC_BANK_TM_TRNA_F) + +// -------------------------------------------------------------------- +// setting the config of ROM/flash/sram +// write_protect: 1 ==> write protect, 0 ==> should be readable/writable +// bank_base: ==> only the last 24 bits is affect +// -------------------------------------------------------------------- +void sram_config(int bank_num, u32 bank_base, int write_protect, int bank_type, int bank_size, int bus_width) { + u32 config_reg_val; + + config_reg_val = (1UL<<28) | (bank_base & 0x0fffffff) | ((write_protect&0x01)<<11) | bank_type | bank_size | bus_width; + + cpe_outl( NDS32_COMMON_SRAMC_BASE + bank_num*8, config_reg_val); +} + + +void sram_disable(int bank_num) { + cpe_outl( NDS32_COMMON_SRAMC_BASE + bank_num*8, cpe_inl( NDS32_COMMON_SRAMC_BASE + bank_num*8) & 0x0fffffff ); +} + +void sram_set_timing(int bank_num, unsigned long timing) { + cpe_outl( NDS32_COMMON_SRAMC_BASE + bank_num*8 + 4, timing ); +} + +void mx_flash_init(void) +{ + int j; + + flash_info[0].flash_id = (MX_MANUFACT & FLASH_VENDMASK) | (MX_ID_29LV008B & FLASH_TYPEMASK); + flash_info[0].size = 0x400000; + flash_info[0].sector_count = MX_SECTOR_COUNT; + memset(flash_info[0].protect, 0, MX_SECTOR_COUNT); + + for (j=0; j<flash_info[0].sector_count; ++j) + { + if (j==0) { + flash_info[0].start[j] = PHYS_FLASH_1; + } else if (j==1 || j==2) { + flash_info[0].start[j] = PHYS_FLASH_1 + 64*K + 32*K*(j-1); + } else if (j==3) { + flash_info[0].start[j] = PHYS_FLASH_1 + 128*K; + } else { + flash_info[0].start[j] = PHYS_FLASH_1 + 256*K + 256*K*(j-4); + } + } +} + +void sst39vf080_flash_init(void) +{ + int j; + + flash_info[0].flash_id = + (SST_MANUFACT & FLASH_VENDMASK) | (SST_ID_39VF080 & FLASH_TYPEMASK); + flash_info[0].size = 0x400000; + flash_info[0].sector_count = SST39VF080_SECTOR_COUNT; + memset(flash_info[0].protect, 0, SST39VF080_SECTOR_COUNT); + + for (j=0; j<flash_info[0].sector_count; ++j) { + flash_info[0].start[j] = PHYS_FLASH_1 + 16*K*j; + } +} + +void sst39vf016_flash_init(void) +{ + int j; + + flash_info[0].flash_id = + (SST_MANUFACT & FLASH_VENDMASK) | (SST_ID_39VF016 & FLASH_TYPEMASK); + flash_info[0].size = 0x800000; + flash_info[0].sector_count = SST39VF016_SECTOR_COUNT; + memset(flash_info[0].protect, 0, SST39VF016_SECTOR_COUNT); + + for (j=0; j<flash_info[0].sector_count; ++j) { + flash_info[0].start[j] = PHYS_FLASH_1 + 16*K*j; + } +} + +/* add by Charles Tsai */ +void intel_mx_flash_init(void) +{ + int j; + + flash_info[0].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_E28F128 & FLASH_TYPEMASK); + flash_info[0].size = INTEL_E28F128_SIZE*2; /* 32 MB */ + flash_info[0].sector_count = (INTEL_E28F128_SIZE*2)/0x40000; + + //memset(flash_info[0].protect, 0, (INTEL_E28F128_SIZE*2)/0x40000); // <- bug + memset(flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); + + for (j=0; j<flash_info[0].sector_count; ++j) + { + flash_info[0].start[j] = PHYS_FLASH_1 + 256*K*j; /* sector size=256K */ + } +} +/* end add */ + +/*----------------------------------------------------------------------- + */ +//added by ivan +#define FLASH_BANK CONFIG_FLASH_BANK // 1 + +ulong flash_init(void) +{ + unsigned int DDI1=0; + unsigned int DDI2=0; + int i=0; + + //added by ivan wang + sram_config(FLASH_BANK, CONFIG_FLASH_BASE, 0, 0, SRAM_BANK_SIZE_4M, SRAM_BUS_WIDTH_32); + //sram_config(FLASH_BANK, CONFIG_FLASH_BASE, 0, 0, SRAM_BANK_SIZE_8M, SRAM_BUS_WIDTH_32); + + sram_set_timing(FLASH_BANK, TIMING_PARAMETER); + for(i=1;i<7;i++) // modify by Charles Tsai, bank 0 can't be disabled + if(i!=FLASH_BANK) + sram_disable(i); + +// fLib_Flash_Reset(PHYS_FLASH_1, FLASH_FOUR); + fLib_Flash_ReadID(MX_Type, PHYS_FLASH_1, FLASH_FOUR, &DDI1, &DDI2); + //printf("DDI1 = %x, DDI2 = %x\n", DDI1, DDI2); + if (DDI1 == 0xc2c2c2c2 && DDI2 == 0x37373737) // ©ô§» flash + { + fLib_Flash_Reset(PHYS_FLASH_1, FLASH_FOUR); + mx_flash_init(); + } else { + fLib_Flash_Reset(PHYS_FLASH_1, FLASH_FOUR); + fLib_Flash_ReadID(SST_Type, PHYS_FLASH_1, FLASH_FOUR, &DDI1, &DDI2); + fLib_Flash_Reset(PHYS_FLASH_1, FLASH_FOUR); + //printf("DDI1 = %x, DDI2 = %x\n", DDI1, DDI2); + if (DDI1 == 0xbfbfbfbf && DDI2 == 0xd8d8d8d8) { + sst39vf080_flash_init(); + } else if(DDI1 == 0xbfbfbfbf && DDI2 == 0xd9d9d9d9) { + sram_config(FLASH_BANK, CONFIG_FLASH_BASE, 0, 0, SRAM_BANK_SIZE_8M, SRAM_BUS_WIDTH_32); + sst39vf016_flash_init(); + } else { + /* add by Charles Tsai */ + sram_set_timing(FLASH_BANK, TIMING_PARAMETER); + sram_config(FLASH_BANK, CONFIG_FLASH_BASE, 0, 0, SRAM_BANK_SIZE_32M, SRAM_BUS_WIDTH_32); + fLib_Flash_Reset(PHYS_FLASH_1, FLASH_FOUR); + fLib_Flash_ReadID(Intel_Type, PHYS_FLASH_1, FLASH_FOUR, &DDI1, &DDI2); + fLib_Flash_Reset(PHYS_FLASH_1, FLASH_FOUR); + printf(" ID1:%x, ID2:%x \n", DDI1, DDI2); + if ( (DDI1 == 0x00890089) && (DDI2 == 0x00180018)) { + printf("Find Intel flash\n"); + intel_mx_flash_init(); + } else + printf("can not found any flash\n"); + /* end add */ + } + } + +#ifdef not_complete_yet + /* + * Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_FLASH_BASE, + CONFIG_FLASH_BASE + _armboot_end - _armboot_start, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, + &flash_info[0]); +#endif /* end_of_not */ + + return flash_info[0].size; +} + +/* + * + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (MX_MANUFACT & FLASH_VENDMASK): + printf("Macronix: "); + break; + + case (SST_MANUFACT & FLASH_VENDMASK): + printf("SST: "); + break; + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf("Intel: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (MX_ID_29LV008B & FLASH_TYPEMASK): + printf("4x 29LV008B(8Mbit)\n"); + break; + + case (SST_ID_39VF080 & FLASH_TYPEMASK): + printf("4x 39VF080(8Mbit)\n"); + break; + + case (SST_ID_39VF016 & FLASH_TYPEMASK): + printf("4x 39VF016(16Mbit)\n"); + break; + case (INTEL_ID_E28F128&FLASH_TYPEMASK): + printf("2x E28F128(128Mbit)\n"); + break; + default: + printf("Unknown Chip Type: %x\n", info->flash_id & FLASH_TYPEMASK); + goto Done; + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: +; //This is because new version of GCC doesn't take label at the end of the compound statement. +} + +/* + * + */ + +int flash_error (ulong code) +{ + /* Check bit patterns */ + /* SR.7=0 is busy, SR.7=1 is ready */ + /* all other flags indicate error on 1 */ + /* SR.0 is undefined */ + /* Timeout is our faked flag */ + + /* sequence is described in Intel 290644-005 document */ + + /* check Timeout */ + if (code & BIT_TIMEOUT) { + printf ("Timeout\n"); + return ERR_TIMOUT; + } + + /* check Busy, SR.7 */ + if (~code & BIT_BUSY) { + printf ("Busy\n"); + return ERR_PROG_ERROR; + } + + /* check Vpp low, SR.3 */ + if (code & BIT_VPP_RANGE_ERROR) { + printf ("Vpp range error\n"); + return ERR_PROG_ERROR; + } + + /* check Device Protect Error, SR.1 */ + if (code & BIT_PROTECT_ERROR) { + printf ("Device protect error\n"); + return ERR_PROG_ERROR; + } + + /* check Command Seq Error, SR.4 & SR.5 */ + if (code & BIT_SEQUENCE_ERROR) { + printf ("Command seqence error\n"); + return ERR_PROG_ERROR; + } + + /* check Block Erase Error, SR.5 */ + if (code & BIT_ERASE_ERROR) { + printf ("Block erase error\n"); + return ERR_PROG_ERROR; + } + + /* check Program Error, SR.4 */ + if (code & BIT_PROGRAM_ERROR) { + printf ("Program error\n"); + return ERR_PROG_ERROR; + } + + /* check Block Erase Suspended, SR.6 */ + if (code & BIT_ERASE_SUSPEND) { + printf ("Block erase suspended\n"); + return ERR_PROG_ERROR; + } + + /* check Program Suspended, SR.2 */ + if (code & BIT_PROGRAM_SUSPEND) { + printf ("Program suspended\n"); + return ERR_PROG_ERROR; + } + + /* OK, no error */ + return ERR_OK; +} + + +// -------------------------------------------------------------------- +// erase the sectors between s_first to s_last +// -------------------------------------------------------------------- +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int iflag, cflag, prot, sect; + int rc = ERR_OK; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) { + return ERR_UNKNOWN_FLASH_TYPE; + } + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != (MX_MANUFACT & FLASH_VENDMASK) && + (info->flash_id & FLASH_VENDMASK) != (SST_MANUFACT & FLASH_VENDMASK) ) { + if((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + // if there exist any sector was protected between s_first to s_last, than return error + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status(); + icache_disable(); + + iflag = disable_interrupts(); + /* add by Charles Tsai */ + //fLib_Flash_ChipErase(Intel_Type, info->start[0], FLASH_FOUR); + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) + { + int start_addr; + int end_addr; + printf("Erasing sector %2d ... ", sect); + + if((info->flash_id & FLASH_VENDMASK) == (MX_MANUFACT&FLASH_VENDMASK) ) { + fLib_Flash_SectorErase(MX_Type, info->start[0], + FLASH_FOUR, (info->start[sect]-info->start[0])/4); + } else if((info->flash_id & FLASH_VENDMASK) == (SST_MANUFACT&FLASH_VENDMASK) ) { + fLib_Flash_SectorErase(SST_Type, info->start[0], FLASH_FOUR, (info->start[sect]-info->start[0])/4); + } + else if((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT&FLASH_VENDMASK) ) { + /* modify by Charles Tsai for test */ + fLib_Flash_ChipErase(Intel_Type, info->start[sect], FLASH_FOUR); + fLib_Flash_Reset(PHYS_FLASH_1, FLASH_FOUR); + } else { + printf("unknown flash type\n"); + return ERR_UNKNOWN_FLASH_TYPE; + } + + reset_timer_masked(); + start_addr = info->start[sect]; + if (sect < flash_info[0].sector_count-1) { + end_addr = info->start[sect+1]; + } else { + end_addr = info->start[0] + info->size; + } + for (; start_addr < end_addr; start_addr+=4) { + for (; *(unsigned long *)start_addr != 0xffffffff; ) { + if (get_timer_masked() > CONFIG_FLASH_ERASE_TOUT) { + printf("fail:0x%x\n",start_addr); + return ERR_PROG_ERROR; + } + } + } + + printf("ok.\n"); + } + + if (ctrlc()) + printf("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/* + * Copy memory to flash + */ +// -------------------------------------------------------------------- +// return +// ERR_OK ==> without error +// less than 0 ==> error code +// -------------------------------------------------------------------- +volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile ulong new_data; + int flash_type; + + if ( (info->flash_id & FLASH_VENDMASK) == (MX_MANUFACT & FLASH_VENDMASK) ) { + flash_type = MX_Type; + } else if( (info->flash_id & FLASH_VENDMASK) == (SST_MANUFACT & FLASH_VENDMASK) ) { + flash_type = SST_Type; + } else if( (info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK) ) { + /* modify by charles Tsai only for test */ + flash_type = Intel_Type; + } else { + printf("unknown flash type\n"); + return ERR_UNKNOWN_FLASH_TYPE; + } + + fLib_Flash_ProgramWord(flash_type, info->start[0], dest, data); + fLib_Flash_ReadWord(dest, &new_data); + + if (new_data != data) { + printf("addr: %x write error: should %x ==> result %x\n", dest, data, new_data); + return ERR_PROG_ERROR; + } + + return ERR_OK; +} + +/*--------------------------------------------------------------------- + * Copy memory to flash. + */ +// -------------------------------------------------------------------- +// src ==> source address +// addr ==> destination address +// return +// ERR_OK ==> without error +// less than 0 ==> error code +// -------------------------------------------------------------------- +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + for (; i<4 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((vulong*)src); + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + src += 4; + wp += 4; + cnt -= 4; + if((cnt&0xfff)==0x0) + printf("."); + } + printf("\n"); + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + return write_word(info, wp, data); + +} diff --git a/board/AndesTech/common/flib_flash.c b/board/AndesTech/common/flib_flash.c new file mode 100644 index 0000000..826b3bb --- /dev/null +++ b/board/AndesTech/common/flib_flash.c @@ -0,0 +1,721 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ +* Copyright Faraday Technology Corp 2002-2003. All rights reserved. * +*-----------------------------------------------------------------------* +* Name:flash.c * +* Description: Flash library routine * +* Author: Fred Chien * +* Date: 2002/03/01 * +* Version:1.0 * +*-----------------------------------------------------------------------* +************************************************************************/ + +#include "../include/porting.h" +#include "../include/flib_flash.h" +//#include <flash.h> + +/* add by Charles Tsai */ +void Do_Delay(unsigned count); +/* end add */ +void Check_Toggle_Ready(unsigned char *Dst); +void Check_Toggle_ReadyHalfWord(unsigned short *Dst); +void Check_Toggle_ReadyWord(unsigned *Dst); + +void fLib_Flash_ReadID(unsigned flash_type, unsigned base, unsigned BusWidth, unsigned* DDI1, unsigned* DDI2) +{ + if (flash_type == MX_Type) + { + switch(BusWidth) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base+0x555,0xaa); + cpe_outb(base+0x2aa,0x55); + cpe_outb(base+0x555,0x90); + Check_Toggle_Ready(base+0x00); + *DDI1 = cpe_inb(base+0x00); + + cpe_outb(base+0x555,0xaa); + cpe_outb(base+0x2aa,0x55); + cpe_outb(base+0x555,0x90); + Check_Toggle_Ready(base+0x01); + *DDI2 = cpe_inb(base+0x01); + break; + + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base+0x555*2,0xaaaa); + cpe_outw(base+0x2aa*2,0x5555); + cpe_outw(base+0x555*2,0x9090); + Check_Toggle_ReadyHalfWord(base+0x00); + *DDI1 = cpe_inw(base+0x00); + + cpe_outw(base+0x555*2,0xaaaa); + cpe_outw(base+0x2aa*2,0x5555); + cpe_outw(base+0x555*2,0x9090); + Check_Toggle_ReadyHalfWord(base+0x02); + *DDI2 = cpe_inw(base+0x02); + break; + + case FLASH_FOUR:// four 32 bit + cpe_outl(base+0x555*4,0xaaaaaaaa); // 0x1554 + cpe_outl(base+0x2aa*4,0x55555555); // 0xaa8 + cpe_outl(base+0x555*4,0x90909090); + Check_Toggle_ReadyWord(base+0x00); + *DDI1 = cpe_inl(base+0x00); + + cpe_outl(base+0x555*4,0xaaaaaaaa); + cpe_outl(base+0x2aa*4,0x55555555); + cpe_outl(base+0x555*4,0x90909090); + Check_Toggle_ReadyWord(base+0x04); + *DDI2 = cpe_inl(base+0x04); + break; + } + } + + if (flash_type == SST_Type) + { + switch(BusWidth) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base+0x5555,0xaa); + cpe_outb(base+0x2aaa,0x55); + cpe_outb(base+0x5555,0x90); + Check_Toggle_Ready(base+0x00); + *DDI1 = cpe_inb(base+0x00); + + cpe_outb(base+0x5555,0xaa); + cpe_outb(base+0x2aaa,0x55); + cpe_outb(base+0x5555,0x90); + Check_Toggle_Ready(base+0x00); + *DDI2 = cpe_inb(base+0x01); + break; + + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base+0x5555*2,0xaaaa); + cpe_outw(base+0x2aaa*2,0x5555); + cpe_outw(base+0x5555*2,0x9090); + Check_Toggle_ReadyHalfWord(base+0x00); + *DDI1 = cpe_inw(base+0x00); + + cpe_outw(base+0x5555*2,0xaaaa); + cpe_outw(base+0x2aaa*2,0x5555); + cpe_outw(base+0x5555*2,0x9090); + Check_Toggle_ReadyHalfWord(base+0x02); + *DDI2 = cpe_inw(base+0x02); + break; + + case FLASH_FOUR:// four 32 bit + cpe_outl(base+0x5555*4,0xaaaaaaaa); + cpe_outl(base+0x2aaa*4,0x55555555); + cpe_outl(base+0x5555*4,0x90909090); + Check_Toggle_ReadyWord(base+0x00); + *DDI1 = cpe_inl(base+0x00); + + cpe_outl(base+0x5555*4,0xaaaaaaaa); + cpe_outl(base+0x2aaa*4,0x55555555); + cpe_outl(base+0x5555*4,0x90909090); + Check_Toggle_ReadyWord(base+0x04); + *DDI2 = cpe_inl(base+0x04); + break; + } + } + /* add by Charles Tsai */ + if (flash_type == Intel_Type) + { + switch(BusWidth) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base+0x100,0x90); + *DDI1 = cpe_inb(base+0x00); + *DDI2 = cpe_inb(base+0x01); + cpe_outb(base+0x100,0xff); + break; + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base+0x100,0x9090); + *DDI1 = cpe_inw(base+0x00); + *DDI2 = cpe_inw(base+0x02); + cpe_outw(base+0x100,0xffff); + break; + case FLASH_FOUR:// four 32 bit + cpe_outl(base+0x100,0x00900090); + *DDI1 = cpe_inl(base+0x00); + *DDI2 = cpe_inl(base+0x04); + cpe_outl(base+0x100,0x00ff00ff); + break; + } + } + /* end add */ + + +} + +void fLib_Flash_Reset(unsigned base, unsigned BusWidth) +{ + switch(BusWidth) + { + case FLASH_SINGLE: + cpe_outb(base,0xf0); + break; + case FLASH_DOUBLE: + cpe_outw(base,0xf0f0); + break; + case FLASH_FOUR: + //cpe_outl(base,0xf0f0f0f0); + cpe_outl(base+0x100,0x00ff00ff); /* modify by Charles Tsai */ + break; + } +} + +void fLib_Flash_ChipErase(unsigned flash_type, unsigned base, unsigned BusWidth) +{ + unsigned data; + + if (flash_type == MX_Type) + { + switch(BusWidth) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base+0x555,0xaa); + cpe_outb(base+0x2aa,0x55); + cpe_outb(base+0x555,0x80); + cpe_outb(base+0x555,0xaa); + cpe_outb(base+0x2aa,0x55); + cpe_outb(base+0x555,0x10); + break; + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base+0x555*2,0xaaaa); + cpe_outw(base+0x2aa*2,0x5555); + cpe_outw(base+0x555*2,0x8080); + cpe_outw(base+0x555*2,0xaaaa); + cpe_outw(base+0x2aa*2,0x5555); + cpe_outw(base+0x555*2,0x1010); + break; + case FLASH_FOUR:// four 32 bit + cpe_outl(base+0x555*4,0xaaaaaaaa); + cpe_outl(base+0x2aa*4,0x55555555); + cpe_outl(base+0x555*4,0x80808080); + cpe_outl(base+0x555*4,0xaaaaaaaa); + cpe_outl(base+0x2aa*4,0x55555555); + cpe_outl(base+0x555*4,0x10101010); + break; + } + } + + if (flash_type == SST_Type) + { + switch(flash_type) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base+0x5555,0xaa); + cpe_outb(base+0x2aaa,0x55); + cpe_outb(base+0x5555,0x80); + cpe_outb(base+0x5555,0xaa); + cpe_outb(base+0x2aaa,0x55); + cpe_outb(base+0x5555,0x10); + break; + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base+0x5555*2,0xaaaa); + cpe_outw(base+0x2aaa*2,0x5555); + cpe_outw(base+0x5555*2,0x8080); + cpe_outw(base+0x5555*2,0xaaaa); + cpe_outw(base+0x2aaa*2,0x5555); + cpe_outw(base+0x5555*2,0x1010); + break; + case FLASH_FOUR:// four 32 bit + cpe_outl(base+0x5555*4,0xaaaaaaaa); + cpe_outl(base+0x2aaa*4,0x55555555); + cpe_outl(base+0x5555*4,0x80808080); + cpe_outl(base+0x5555*4,0xaaaaaaaa); + cpe_outl(base+0x2aaa*4,0x55555555); + cpe_outl(base+0x5555*4,0x10101010); + break; + } + } + + /* add by Charles Tsai */ + if (flash_type == Intel_Type) + { + // Only erase the first sector + switch(BusWidth) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base,0x20); + cpe_outb(base,0xd0); + cpe_outb(base,0xff); + + // read status register + //Do_Delay(0xffff); + cpe_outb(base,0x70); + data = cpe_inb(base); + + while (data != 0x80) { + //Do_Delay(0xffff); + cpe_outb(base,0x70); + data=cpe_inb(base); + } + cpe_outb(base,0xff); + + break; + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base,0x2020); + cpe_outw(base,0xd0d0); + cpe_outw(base,0xffff); + + // read status register + //Do_Delay(0xffff); + cpe_outw(base,0x7070); + data = cpe_inw(base); + + while (data != 0x8080) { + //Do_Delay(0xffff); + cpe_outw(base,0x7070); + data=cpe_inl(base); + } + cpe_outw(base,0xffff); + + break; + + case FLASH_FOUR:// four 32 bit + cpe_outl(base,0x00200020);Do_Delay(0x30000); + cpe_outl(base,0x00d000d0);Do_Delay(0x30000); + cpe_outl(base,0x00ff00ff);Do_Delay(0x30000); + + // read status register + Do_Delay(0x100000); + cpe_outl(base,0x00700070); + data = cpe_inl(base); + //ivan wang + while (data != 0x00800080) { + //while ( (data&0xff) != 0x80) { + //Do_Delay(0xffff); + cpe_outl(base,0x00700070); + data=cpe_inl(base); + } + cpe_outl(base,0x00ff00ff); + break; + } + } + + /* end add */ +} + +void fLib_Flash_SectorErase(unsigned flash_type, unsigned base, unsigned BusWidth, unsigned sector) { + unsigned data; + + if (flash_type == MX_Type) { + switch(BusWidth) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base+0x555,0xaa); + cpe_outb(base+0x2aa,0x55); + cpe_outb(base+0x555,0x80); + cpe_outb(base+0x555,0xaa); + cpe_outb(base+0x2aa,0x55); + cpe_outb(base+sector,0x30); + break; + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base+0x555*2,0xaaaa); + cpe_outw(base+0x2aa*2,0x5555); + cpe_outw(base+0x555*2,0x8080); + cpe_outw(base+0x555*2,0xaaaa); + cpe_outw(base+0x2aa*2,0x5555); + cpe_outw(base+sector*2,0x3030); + break; + case FLASH_FOUR:// four 32 bit + cpe_outl(base+0x555*4,0xaaaaaaaa); + cpe_outl(base+0x2aa*4,0x55555555); + cpe_outl(base+0x555*4,0x80808080); + cpe_outl(base+0x555*4,0xaaaaaaaa); + cpe_outl(base+0x2aa*4,0x55555555); + cpe_outl(base+sector*4,0x30303030); + break; + } + } + + if (flash_type == SST_Type) { + switch(BusWidth) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base+0x5555,0xaa); + cpe_outb(base+0x2aaa,0x55); + cpe_outb(base+0x5555,0x80); + cpe_outb(base+0x5555,0xaa); + cpe_outb(base+0x2aaa,0x55); + cpe_outb(base+sector,0x30); + break; + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base+0x5555*2,0xaaaa); + cpe_outw(base+0x2aaa*2,0x5555); + cpe_outw(base+0x5555*2,0x8080); + cpe_outw(base+0x5555*2,0xaaaa); + cpe_outw(base+0x2aaa*2,0x5555); + cpe_outw(base+sector*2,0x3030); + break; + case FLASH_FOUR:// four 32 bit + cpe_outl(base+0x5555*4,0xaaaaaaaa); + cpe_outl(base+0x2aaa*4,0x55555555); + cpe_outl(base+0x5555*4,0x80808080); + cpe_outl(base+0x5555*4,0xaaaaaaaa); + cpe_outl(base+0x2aaa*4,0x55555555); + cpe_outl(base+sector*4,0x30303030); + break; + } + } + + /* add by Charles Tsai */ + if (flash_type == Intel_Type) { + switch(BusWidth) + { + case FLASH_SINGLE: // 8 bit + cpe_outb(base+sector,0x20); + cpe_outb(base+sector,0xd0); + + // read status register + //Do_Delay(0xff); + cpe_outb(base,0x70); + data = cpe_inb(base); + + while (data != 0x80) { + //Do_Delay(0xff); + cpe_outb(base,0x70); + data=cpe_inb(base); + } + cpe_outb(base,0xff); + break; + + case FLASH_DOUBLE: // double 16 bit + cpe_outw(base+sector,0x2020); + cpe_outw(base+sector,0xd0d0); + + // read status register + //Do_Delay(0xff); + cpe_outw(base,0x7070); + data = cpe_inw(base); + + while (data != 0x8080) { + //Do_Delay(0xff); + cpe_outw(base,0x7070); + data=cpe_inw(base); + } + cpe_outw(base,0xffff); + + break; + case FLASH_FOUR:// four 32 bit + cpe_outl(base+sector,0x00200020); + cpe_outl(base+sector,0x00d000d0); + + // read status register + //Do_Delay(0xff); + cpe_outl(base,0x00700070); + data = cpe_inl(base); +//ivan + while (data != 0x00800080) { + //while ((data&0xff) != 0x80) { + //Do_Delay(0xff); + cpe_outl(base,0x00700070); + data=cpe_inl(base); + } + cpe_outl(base,0x00ff00ff); + + break; + } + } + /* end add */ + +} + +// this function only use in FLASH_SINGLE +void fLib_Flash_ProgramByte(unsigned flash_type, unsigned base, unsigned address, unsigned char data) { + volatile unsigned int s_reg = 0; /* add by Charles Tsai */ + + if (flash_type == MX_Type) + { + cpe_outb(base+0x555,0xaa); + cpe_outb(base+0x2aa,0x55); + cpe_outb(base+0x555,0xa0); + cpe_outb(address,data); + + Check_Toggle_Ready((unsigned char *)address); + } + + if (flash_type == SST_Type) + { + cpe_outb(base+0x5555,0xaa); + cpe_outb(base+0x2aaa,0x55); + cpe_outb(base+0x5555,0xa0); + cpe_outb(address,data); + + Check_Toggle_Ready((unsigned char *)address); + } + + /* add by Charles Tsai */ + if (flash_type == Intel_Type) + { + cpe_outb(base,0x40); + cpe_outb(address,data); + + //Do_Delay(0xff); + cpe_outb(base,0x70); + s_reg=cpe_inb(base); + +//ivan +// while (s_reg != 0x80) { + while ((s_reg&0xff) != 0x80) { + //Do_Delay(0xff); + cpe_outb(base,0x70); + s_reg=cpe_inb(base); + } + + cpe_outl(base,0x00ff00ff); + } + /* end add */ +} +/************************************************************************/ +/* PROCEDURE: Check_Toggle_Ready */ +/* */ +/* During the internal program cycle, any consecutive read operation */ +/* on DQ6 will produce alternating 0's and 1's (i.e. toggling between */ +/* 0 and 1). When the program cycle is completed, DQ6 of the data will */ +/* stop toggling. After the DQ6 data bit stops toggling, the device is */ +/* ready for next operation. */ +/* */ +/* Input: */ +/* Dst must already be set-up by the caller */ +/* */ +/* Output: */ +/* None */ +/************************************************************************/ + +void Check_Toggle_Ready (unsigned char *Dst) +{ + unsigned char Loop = 1; + unsigned char PreData; + unsigned char CurrData; + long long TimeOut = 0; + + PreData = *Dst; + PreData = PreData & 0x40; + while ((TimeOut< 0x07FFFFFF) && (Loop)) { + CurrData = *Dst; + CurrData = CurrData & 0x40; + if (PreData == CurrData) + Loop = 0; /* ready to exit the while loop */ + PreData = CurrData; + TimeOut++; + } +} + +// this function only use in FLASH_DOUBLE +void fLib_Flash_ProgramHalfWord(unsigned flash_type, unsigned base, unsigned address, unsigned short data) +{ + volatile unsigned int s_reg = 0; + + if (flash_type == MX_Type) { + cpe_outw(base+0x555*2,0xaaaa); + cpe_outw(base+0x2aa*2,0x5555); + cpe_outw(base+0x555*2,0xa0a0); + cpe_outw(address,data); + Check_Toggle_ReadyHalfWord((unsigned short *) (address)); + } + + if (flash_type == SST_Type) { + + cpe_outw(base+0x5555*2,0xaaaa); + cpe_outw(base+0x2aaa*2,0x5555); + cpe_outw(base+0x5555*2,0xa0a0); + cpe_outw(address,data); + + Check_Toggle_ReadyHalfWord((unsigned short *) (address)); + } + + /* add by Charles Tsai */ + if (flash_type == Intel_Type) { + cpe_outw(base,0x4040); + cpe_outw(address,data); + + //Do_Delay(0xff); + cpe_outw(base,0x7070); + s_reg=cpe_inw(base); +//ivan +// while (s_reg != 0x8080) { + while ((s_reg&0xff) != 0x80) { + //Do_Delay(0xff); + cpe_outw(base,0x7070); + s_reg=cpe_inw(base); + } + + cpe_outw(base,0xffff); + } + /* end add */ +} + +void Check_Toggle_ReadyHalfWord(unsigned short *Dst) +{ + unsigned char Loop = 1; + short PreData; + short CurrData; + long long TimeOut = 0; + + PreData = *Dst; + PreData = PreData & 0x4040; + while ((TimeOut< 0x07FFFFFF) && (Loop)) { + CurrData = *Dst; + CurrData = CurrData & 0x4040; + if (PreData == CurrData) + Loop = 0; /* ready to exit the while loop */ + PreData = CurrData; + TimeOut++; + } +} + +// this function only use in FLASH_FOUR +void fLib_Flash_ProgramWord(unsigned flash_type, unsigned base, unsigned address, unsigned data) +{ + volatile unsigned int s_reg = 0; + + if (flash_type == MX_Type) { + cpe_outl(base+0x555*4,0xaaaaaaaa); + cpe_outl(base+0x2aa*4,0x55555555); + cpe_outl(base+0x555*4,0xa0a0a0a0); + cpe_outl(address,data); + + Check_Toggle_ReadyWord((unsigned *) (address)); + } + + if (flash_type == SST_Type) { + cpe_outl(base+0x5555*4,0xaaaaaaaa); + cpe_outl(base+0x2aaa*4,0x55555555); + cpe_outl(base+0x5555*4,0xa0a0a0a0); + + cpe_outl(address,data); + + Check_Toggle_ReadyWord((unsigned *) (address)); + } + + /* add by Charles Tsai */ + if (flash_type == Intel_Type) + { + cpe_outl(base,0x00400040); + cpe_outl(address,data); + + //Do_Delay(0xf); + cpe_outl(base,0x00700070); + s_reg=cpe_inl(base); + +//ivan + while (s_reg != 0x00800080) { + //while ((s_reg&0xff) != 0x80) { + //Do_Delay(0xf); + cpe_outl(base,0x00700070); + s_reg=cpe_inl(base); + } + + cpe_outl(base,0x00ff00ff); + } + /* end add */ +} + +void Check_Toggle_ReadyWord(unsigned *Dst) +{ + unsigned char Loop = 2; + unsigned PreData; + unsigned CurrData; + long long TimeOut = 0; + + + PreData = *Dst; + PreData = PreData & 0x40404040; + while (Loop) { + CurrData = *Dst; + CurrData = CurrData & 0x40404040; + if (PreData == CurrData) + Loop--; /* ready to exit the while loop */ + PreData = CurrData; + TimeOut++; + } + +} + +int Check_Toggle_ReadyWord1(unsigned base, unsigned programmed_Data, unsigned *Dst) +{ + unsigned loopCounter; + unsigned TimeOutFlag; + unsigned ProgramOkFlag; + unsigned read_Data; + unsigned return_status; + unsigned i; + + loopCounter = 0; + TimeOutFlag = 0; + ProgramOkFlag = 1; + + + while(1) { + read_Data = *Dst; + if (read_Data == programmed_Data) { + return_status = PROGRAM_OK; + break; + } + + // delay + for (i = 0; i < FLASH_PROGRAM_DELAY_CYCLE; i++); + + if (loopCounter >= FLASH_PROGRAM_LOOP_COUNTER) { + return_status = PROGRAM_NOT_OK; + break; + } + + loopCounter++; + }// end of while + + return return_status; +} + +void fLib_Flash_ReadWord(unsigned address, unsigned* data) +{ + *data = cpe_inl(address); +} + +void fLib_Flash_ReadHalfWord(unsigned address, unsigned short* data) +{ + *data = cpe_inw(address); +} + +void fLib_Flash_ReadByte(unsigned address, unsigned char* data) +{ + *data = cpe_inb(address); +} + + +void Do_Delay(unsigned count) +{ + unsigned i; + + for ( i = count; i>0; i--); +} diff --git a/board/AndesTech/common/flib_serial.c b/board/AndesTech/common/flib_serial.c new file mode 100644 index 0000000..2b3df24 --- /dev/null +++ b/board/AndesTech/common/flib_serial.c @@ -0,0 +1,373 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ +* Copyright Faraday Technology Corp 2002-2003. All rights reserved. * +*-----------------------------------------------------------------------* +* Name:serial.c * +* Description: serial library routine * +* Author: Fred Chien * +************************************************************************/ + +#include <nds32_common.h> +#include "../include/symbol.h" +#include "../include/serial.h" +#include "../include/porting.h" + +#define outw cpe_outl +#define inw cpe_inl + +void LED_ShowHex(UINT32 u32HexValue) +{ + cpe_outl(NDS32_COMMON_DBG_ALPHA, u32HexValue); +} + +UINT64 fLib_CurrentT1Tick() +{ + return 0; +} + +#ifdef not_complete_yet +UINT32 DebugSerialPort = NDS32_COMMON_UART1_BASE; +UINT32 SystemSerialPort = NDS32_COMMON_UART2_BASE; +#endif /* end_of_not */ + +void fLib_SetSerialMode(UINT32 port, UINT32 mode) +{ + UINT32 mdr; + + mdr = inw(port + SERIAL_MDR); + mdr &= ~SERIAL_MDR_MODE_SEL; + outw(port + SERIAL_MDR, mdr | mode); +} + + +void fLib_EnableIRMode(UINT32 port, UINT32 TxEnable, UINT32 RxEnable) +{ + UINT32 acr; + + acr = inw(port + SERIAL_ACR); + acr &= ~(SERIAL_ACR_TXENABLE | SERIAL_ACR_RXENABLE); + if(TxEnable) + acr |= SERIAL_ACR_TXENABLE; + if(RxEnable) + acr |= SERIAL_ACR_RXENABLE; + outw(port + SERIAL_ACR, acr); +} + +/*****************************************************************************/ + +void fLib_SerialInit(UINT32 port, UINT32 baudrate, UINT32 parity,UINT32 num,UINT32 len) +{ + UINT32 lcr; + + lcr = inw(port + SERIAL_LCR) & ~SERIAL_LCR_DLAB; + /* Set DLAB=1 */ + outw(port + SERIAL_LCR,SERIAL_LCR_DLAB); + /* Set baud rate */ + outw(port + SERIAL_DLM, ((baudrate & 0xf00) >> 8)); + outw(port + SERIAL_DLL, (baudrate & 0xff)); + + //clear orignal parity setting + lcr &= 0xc0; + + switch (parity) + { + case PARITY_NONE: + //do nothing + break; + case PARITY_ODD: + lcr|=SERIAL_LCR_ODD; + break; + case PARITY_EVEN: + lcr|=SERIAL_LCR_EVEN; + break; + case PARITY_MARK: + lcr|=(SERIAL_LCR_STICKPARITY|SERIAL_LCR_ODD); + break; + case PARITY_SPACE: + lcr|=(SERIAL_LCR_STICKPARITY|SERIAL_LCR_EVEN); + break; + + default: + break; + } + + if(num==2) + lcr|=SERIAL_LCR_STOP; + + len-=5; + + lcr|=len; + + outw(port+SERIAL_LCR,lcr); +} + + +void fLib_SetSerialLoopback(UINT32 port, UINT32 onoff) +{ + UINT32 temp; + + temp=inw(port+SERIAL_MCR); + if(onoff==ON) + temp|=SERIAL_MCR_LPBK; + else + temp&=~(SERIAL_MCR_LPBK); + + outw(port+SERIAL_MCR,temp); +} + +void fLib_SetSerialFifoCtrl(UINT32 port, UINT32 level, UINT32 resettx, UINT32 resetrx) +{ + UINT8 fcr = 0; + + fcr |= SERIAL_FCR_FE; + + switch(level) + { + case 4: + fcr|=0x40; + break; + case 8: + fcr|=0x80; + break; + case 14: + fcr|=0xc0; + break; + default: + break; + } + + if(resettx) + fcr|=SERIAL_FCR_TXFR; + + if(resetrx) + fcr|=SERIAL_FCR_RXFR; + + outw(port+SERIAL_FCR,fcr); +} + + +void fLib_DisableSerialFifo(UINT32 port) +{ + outw(port+SERIAL_FCR,0); +} + + +void fLib_SetSerialInt(UINT32 port, UINT32 IntMask) +{ + outw(port + SERIAL_IER, IntMask); +} + + +char fLib_GetSerialChar(UINT32 port) +{ + char Ch; + UINT32 status; + + do + { + status=inw(port+SERIAL_LSR); + } + while (!((status & SERIAL_LSR_DR)==SERIAL_LSR_DR)); // wait until Rx ready + Ch = inw(port + SERIAL_RBR); + return (Ch); +} + +void fLib_PutSerialChar(UINT32 port, char Ch) +{ + UINT32 status; + + do + { + status=inw(port+SERIAL_LSR); + } while (!((status & SERIAL_LSR_THRE)==SERIAL_LSR_THRE)); // wait until Tx ready + outw(port + SERIAL_THR,Ch); +} + +void fLib_PutSerialStr(UINT32 port, char *Str) +{ + char *cp; + + for(cp = Str; *cp != 0; cp++) + fLib_PutSerialChar(port, *cp); +} + +void fLib_Modem_waitcall(UINT32 port) +{ + fLib_PutSerialStr(port, "ATS0=2\r"); +} + +void fLib_Modem_call(UINT32 port, char *tel) +{ + fLib_PutSerialStr(port, "ATDT"); + fLib_PutSerialStr(port, tel); + fLib_PutSerialStr(port, "\r"); +} + +int fLib_Modem_getchar(UINT32 port,int TIMEOUT) +{ + UINT64 start_time, middle_time, dead_time; + UINT32 status; + INT8 ch; + UINT32 n=0; + + start_time = fLib_CurrentT1Tick(); + dead_time = start_time + TIMEOUT; + + do + { + if(n>1000) + { + middle_time = fLib_CurrentT1Tick(); + if (middle_time > dead_time) + return 0x100; + } + status = inw(port + SERIAL_LSR); + n++; + }while (!((status & SERIAL_LSR_DR)==SERIAL_LSR_DR)); + + ch = inw(port + SERIAL_RBR); + return (ch); +} + +BOOL fLib_Modem_putchar(UINT32 port, INT8 Ch) +{ + UINT64 start_time, middle_time, dead_time; + UINT32 status; + UINT32 n=0; + + start_time = fLib_CurrentT1Tick(); + dead_time = start_time + 5; + + do + { + if(n>1000) + { + middle_time = fLib_CurrentT1Tick(); + if (middle_time > dead_time) + return FALSE; + } + status = inw(port + SERIAL_LSR); + n++; + } while (!((status & SERIAL_LSR_THRE)==SERIAL_LSR_THRE)); + + outw(port + SERIAL_THR, Ch); + + return TRUE; +} + +void fLib_EnableSerialInt(UINT32 port, UINT32 mode) +{ +UINT32 data; + + data = inw(port + SERIAL_IER); + outw(port + SERIAL_IER, data | mode); +} + + +void fLib_DisableSerialInt(UINT32 port, UINT32 mode) +{ +UINT32 data; + + data = inw(port + SERIAL_IER); + mode = data & (~mode); + outw(port + SERIAL_IER, mode); +} + +UINT32 fLib_SerialIntIdentification(UINT32 port) +{ + return inw(port + SERIAL_IIR); +} + +void fLib_SetSerialLineBreak(UINT32 port) +{ +UINT32 data; + + data = inw(port + SERIAL_LCR); + outw(port + SERIAL_LCR, data | SERIAL_LCR_SETBREAK); +} + +void fLib_SetSerialLoopBack(UINT32 port,UINT32 onoff) +{ +UINT32 temp; + + temp = inw(port+SERIAL_MCR); + if(onoff == ON) + temp |= SERIAL_MCR_LPBK; + else + temp &= ~(SERIAL_MCR_LPBK); + + outw(port+SERIAL_MCR,temp); +} + +void fLib_SerialRequestToSend(UINT32 port) +{ +UINT32 data; + + data = inw(port + SERIAL_MCR); + outw(port + SERIAL_MCR, data | SERIAL_MCR_RTS); +} + +void fLib_SerialStopToSend(UINT32 port) +{ +UINT32 data; + + data = inw(port + SERIAL_MCR); + data &= ~(SERIAL_MCR_RTS); + outw(port + SERIAL_MCR, data); +} + +void fLib_SerialDataTerminalReady(UINT32 port) +{ +UINT32 data; + + data = inw(port + SERIAL_MCR); + outw(port + SERIAL_MCR, data | SERIAL_MCR_DTR); +} + +void fLib_SerialDataTerminalNotReady(UINT32 port) +{ +UINT32 data; + + data = inw(port + SERIAL_MCR); + data &= ~(SERIAL_MCR_DTR); + outw(port + SERIAL_MCR, data); +} + +UINT32 fLib_ReadSerialLineStatus(UINT32 port) +{ + return inw(port + SERIAL_LSR); +} + +UINT32 fLib_ReadSerialModemStatus(UINT32 port) +{ + return inw(port + SERIAL_MSR); +} +// End of file - serial.c + diff --git a/board/AndesTech/common/fotg2xx.c b/board/AndesTech/common/fotg2xx.c new file mode 100644 index 0000000..8fa6c9c --- /dev/null +++ b/board/AndesTech/common/fotg2xx.c @@ -0,0 +1,60 @@ +/* + * FOTG2xx (Host Controller Driver) for USB on the Andes. + * + * Copyright (C) 2009 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * IMPORTANT NOTES + * 1 - you MUST define LITTLEENDIAN in the configuration file for the + * board or this driver will NOT work! + * 2 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include <common.h> +#include <usb.h> + +#if defined(CONFIG_CMD_USB) && !defined(CONFIG_PCI_OHCI) && !defined(CONFIG_USB_OHCI_NEW) + +int usb_lowlevel_init(void) +{ +} + +int usb_lowlevel_stop(void) +{ +} + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len) +{ +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len,struct devrequest *setup) +{ +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ +} + + +#endif // CONFIG_CMD_USB diff --git a/board/AndesTech/common/ftmac100.c b/board/AndesTech/common/ftmac100.c new file mode 100644 index 0000000..825031d --- /dev/null +++ b/board/AndesTech/common/ftmac100.c @@ -0,0 +1,766 @@ +/* + * Copyright (C) 2009 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +// -------------------------------------------------------------------- +// lmc83: modified from smc91111.c (2002-11-29) +// -------------------------------------------------------------------- + + +#include <common.h> +#include <asm/andesboot.h> +#include <malloc.h> +#include <command.h> +#include "../include/porting.h" +#include "../include/ftmac100.h" +#include <net.h> + + +#ifdef CONFIG_DRIVER_FTMAC100 + +// Use power-down feature of the chip +#define POWER_DOWN 0 + +static unsigned char ftmac100_mac_addr[] = {0x00, 0x41, 0x71, 0x99, 0x00, 0x00}; + +static const char version[] = + "Faraday FTMAC100 Driver, (Linux Kernel 2.4) 10/18/02 - by Faraday\n"; + +#define inl(addr) (*((volatile u32 *)(addr))) +#define inw(addr) (*((volatile u16 *)(addr))) +#define outl(value, addr) (*((volatile u32 *)(addr)) = value) +#define outb(value, addr) (*((volatile u8 *)(addr)) = value) + +struct net_device dev_eth0; +int tx_rx_cnt = 0; +/* + * + * Configuration options, for the experienced user to change. + * + */ +/* + * DEBUGGING LEVELS + * + * 0 for normal operation + * 1 for slightly more details + * >2 for various levels of increasingly useless information + * 2 for interrupt tracking, status flags + * 3 for packet info + * 4 for complete packet dumps + */ + +#define DO_PRINT(args...) printk(args) + +//#define FTMAC100_DEBUG 5 // Must be defined in makefile + +#if (FTMAC100_DEBUG > 2 ) +#define PRINTK3(args...) DO_PRINT(args) +#else +#define PRINTK3(args...) +#endif + +#if FTMAC100_DEBUG > 1 +#define PRINTK2(args...) DO_PRINT(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef FTMAC100_DEBUG +#define PRINTK(args...) DO_PRINT(args) +#else +#define PRINTK(args...) +#endif + + +///#define FTMAC100_TIMER + +/* + * + * The internal workings of the driver. If you are changing anything + * here with the SMC stuff, you should have the datasheet and know + * what you are doing. + * + */ +#define CARDNAME "FTMAC100" + +#ifdef FTMAC100_TIMER + static struct timer_list ftmac100_timer; +#endif + +#define ETH_ZLEN 60 + +#ifdef CONFIG_SMC_USE_32_BIT +#define USE_32_BIT +#else +#undef USE_32_BIT +#endif +/* + * + * The driver can be entered at any of the following entry points. + * + */ + +extern int eth_init(bd_t *bd); +extern void eth_halt(void); +extern int eth_rx(void); +extern int eth_send(volatile void *packet, int length); + + +int initialized = 0; +/* + * This is called by register_netdev(). It is responsible for + * checking the portlist for the FTMAC100 series chipset. If it finds + * one, then it will initialize the device, find the hardware information, + * and sets up the appropriate device parameters. + * NOTE: Interrupts are *OFF* when this procedure is called. + * + * NB:This shouldn't be static since it is referred to externally. + */ +int ftmac100_init(struct net_device *dev); + +/* + * This is called by unregister_netdev(). It is responsible for + * cleaning up before the driver is finally unregistered and discarded. + */ +void ftmac100_destructor(struct net_device *dev); + +/* + * The kernel calls this function when someone wants to use the net_device, + * typically 'ifconfig ethX up'. + */ +static int ftmac100_open(struct net_device *dev); + + +/* + * This is called by the kernel in response to 'ifconfig ethX down'. It + * is responsible for cleaning up everything that the open routine + * does, and maybe putting the card into a powerdown state. + */ +static int ftmac100_close(struct net_device *dev); + + +/* + * This is a separate procedure to handle the receipt of a packet, to + * leave the interrupt code looking slightly cleaner + */ +inline static int ftmac100_rcv( struct net_device *dev ); + + + +/* + * Internal routines + */ + + + +/* + * A rather simple routine to print out a packet for debugging purposes. + */ +#if FTMAC100_DEBUG > 2 +static void print_packet( byte *, int ); +#endif + + + + +/* this does a soft reset on the device */ +static void ftmac100_reset( struct net_device *dev ); + +/* Enable Interrupts, Receive, and Transmit */ +static void ftmac100_enable( struct net_device *dev ); + +/* this puts the device in an inactive state */ +static void ftmac100_shutdown( unsigned int ioaddr ); + +/* + * Routines to Read and Write the PHY Registers across the + * MII Management Interface + */ + +void print_mac(unsigned char *); + +void put_mac(int base, unsigned char *mac_addr) +{ + int val; + + val = ((u32)mac_addr[0])<<8 | (u32)mac_addr[1]; + outl(val, base + MAC_MADR_REG); + val = ((((u32)mac_addr[2])<<24)&0xff000000) | + ((((u32)mac_addr[3])<<16)&0xff0000) | + ((((u32)mac_addr[4])<<8)&0xff00) | + ((((u32)mac_addr[5])<<0)&0xff); + outl(val, base + MAC_LADR_REG); +} + +void get_mac(int base, unsigned char *mac_addr) +{ + int val; + val = inl(base + MAC_MADR_REG); + mac_addr[0] = (val>>8)&0xff; + mac_addr[1] = val&0xff; + val = inl(base + MAC_LADR_REG); + mac_addr[2] = (val>>24)&0xff; + mac_addr[3] = (val>>16)&0xff; + mac_addr[4] = (val>>8)&0xff; + mac_addr[5] = val&0xff; +} + +/* + * Print the Ethernet address + */ +void print_mac(unsigned char *mac_addr) +{ + int i; + + DO_PRINT("ADDR: "); + for (i = 0; i < 5; i++) + { + DO_PRINT("%2.2x:", mac_addr[i] ); + } + DO_PRINT("%2.2x \n", mac_addr[5] ); +} + + + + +#ifdef FTMAC100_TIMER +static void ftmac100_timer_func(unsigned long dummy) +{ + struct net_device *dev = (struct net_device *)ftmac100_timer.data; + struct ftmac100_local *lp = (struct ftmac100_local *)dev->priv; + int i; + int rxdma_own = 0; + + DO_PRINT("lp->rx_idx = %d\n", lp->rx_idx); + for (i=0; i<RXDES_NUM; ++i) + { + rxdma_own += lp->rx_descs[i].RXDMA_OWN; + DO_PRINT("%d ", lp->rx_descs[i].RXDMA_OWN); + if (i%10==9) + { + DO_PRINT("\n"); + } + } + DO_PRINT("\n"); + + mod_timer(&ftmac100_timer, jiffies + FTMAC100_STROBE_TIME); +} + +#endif + +/* + * Function: ftmac100_reset( struct device* dev ) + * Purpose: + * This sets the SMC91111 chip to its normal state, hopefully from whatever + * mess that any other DOS driver has put it in. + * + * Maybe I should reset more registers to defaults in here? SOFTRST should + * do that for me. + * + * Method: + * 1. send a SOFT RESET + * 2. wait for it to finish + * 3. enable autorelease mode + * 4. reset the memory management unit + * 5. clear all interrupts + */ +static void ftmac100_reset( struct net_device* dev ) +{ + //struct ftmac100_local *lp = (struct ftmac100_local *)dev->priv; + unsigned int ioaddr = dev->base_addr; + + PRINTK2("%s:ftmac100_reset\n", dev->name); + + outl( SW_RST_bit, ioaddr + MACCR_REG ); + +#ifdef not_complete_yet + /* Setup for fast accesses if requested */ + /* If the card/system can't handle it then there will */ + /* be no recovery except for a hard reset or power cycle */ + if (dev->dma) { + outw( inw( ioaddr + CONFIG_REG ) | CONFIG_NO_WAIT, ioaddr + CONFIG_REG ); + } +#endif /* end_of_not */ + + /* this should pause enough for the chip to be happy */ + for (; (inl( ioaddr + MACCR_REG ) & SW_RST_bit) != 0; ) { + mdelay(10); + PRINTK3("RESET: reset not complete yet\n" ); + } + + /* Disable all interrupts */ + outl( 0, ioaddr + IMR_REG ); +} + + +/* + * Function: ftmac100_enable + * Purpose: let the chip talk to the outside work + * Method: + * 1. Enable the transmitter + * 2. Enable the receiver + * 3. Enable interrupts + */ +static void ftmac100_enable( struct net_device *dev ) +{ + unsigned int ioaddr = dev->base_addr; + int i; + struct ftmac100_local *lp = (struct ftmac100_local *)dev->priv; + + PRINTK2("%s:ftmac100_enable\n", dev->name); + + for (i=0; i<RXDES_NUM; ++i) { + lp->rx_descs[i].RXDMA_OWN = OWNBY_FTMAC100; // owned by FTMAC100 + } + lp->rx_idx = 0; + + for (i=0; i<TXDES_NUM; ++i) { + lp->tx_descs[i].TXDMA_OWN = OWNBY_SOFTWARE; // owned by software + } + lp->tx_idx = 0; + + + /* set the MAC address */ + put_mac(ioaddr, dev->dev_addr); + + outl( lp->rx_descs_dma, ioaddr + RXR_BADR_REG); + outl( lp->tx_descs_dma, ioaddr + TXR_BADR_REG); + outl( 0x00001010, ioaddr + ITC_REG); // this value is recommend by document + ///outl( 0x0, ioaddr + ITC_REG); + ///outl( (1UL<<TXPOLL_CNT)|(1UL<<RXPOLL_CNT), ioaddr + APTC_REG); + outl( (0UL<<TXPOLL_CNT)|(0x1<<RXPOLL_CNT), ioaddr + APTC_REG); + outl( 0x1df, ioaddr + DBLAC_REG ); // this value is recommend by document + outl( inl(FCR_REG)|0x1, ioaddr + FCR_REG ); // enable flow control + outl( inl(BPR_REG)|0x1, ioaddr + BPR_REG ); // enable back pressure register + + /* now, enable interrupts */ + outl ( + PHYSTS_CHG_bit | + AHB_ERR_bit | +/// RPKT_LOST_bit | +/// RPKT_SAV_bit | +/// XPKT_LOST_bit | +/// XPKT_OK_bit | +/// NOTXBUF_bit | +/// XPKT_FINISH_bit | +/// NORXBUF_bit | + RPKT_FINISH_bit + ,ioaddr + IMR_REG + ); + + /// enable trans/recv,... + outl(lp->maccr_val, ioaddr + MACCR_REG ); + +#ifdef FTMAC100_TIMER + /// waiting to do: šâ­Ó¥H€Wªººôžô¥d + init_timer(&ftmac100_timer); + ftmac100_timer.function = ftmac100_timer_func; + ftmac100_timer.data = (unsigned long)dev; + mod_timer(&ftmac100_timer, jiffies + FTMAC100_STROBE_TIME); +#endif +} + +/* + * Function: ftmac100_shutdown + * Purpose: closes down the SMC91xxx chip. + * Method: + * 1. zero the interrupt mask + * 2. clear the enable receive flag + * 3. clear the enable xmit flags + * + * TODO: + * (1) maybe utilize power down mode. + * Why not yet? Because while the chip will go into power down mode, + * the manual says that it will wake up in response to any I/O requests + * in the register space. Empirical results do not show this working. + */ +static void ftmac100_shutdown( unsigned int ioaddr ) +{ + /// ³]©w interrupt mask register + outl( 0, ioaddr + IMR_REG ); + + /// enable trans/recv,... + outl( 0, ioaddr + MACCR_REG ); +} + + + +static int ftmac100_send_packet( void *packet, int length, struct net_device *dev ) +{ + struct ftmac100_local *lp = (struct ftmac100_local *)dev->priv; + unsigned int ioaddr = dev->base_addr; + volatile TX_DESC *cur_desc; + + + PRINTK3("%s:ftmac100_wait_to_send_packet\n", dev->name); + cur_desc = &lp->tx_descs[lp->tx_idx]; + + /* there is no empty transmit descriptor */ + for (; cur_desc->TXDMA_OWN != OWNBY_SOFTWARE; ) + { + DO_PRINT("Transmitting busy\n"); + udelay(10); + } + length = ETH_ZLEN < length ? length : ETH_ZLEN; + length = length > TX_BUF_SIZE ? TX_BUF_SIZE : length; + +#if FTMAC100_DEBUG > 2 +/// DO_PRINT("Transmitting Packet\n"); +/// print_packet( packet, length ); +#endif + /* waiting to do: slice data into many segments*/ + memcpy((char *)cur_desc->VIR_TXBUF_BADR, packet, length); + + cur_desc->TXBUF_Size = length; + cur_desc->LTS = 1; + cur_desc->FTS = 1; + cur_desc->TX2FIC = 0; + cur_desc->TXIC = 0; + cur_desc->TXDMA_OWN = OWNBY_FTMAC100; + outl( 0xffffffff, ioaddr + TXPD_REG); + lp->tx_idx = (lp->tx_idx + 1) % TXDES_NUM; + + + return length; +} + +/* + * smc_destructor( struct net_device * dev ) + * Input parameters: + * dev, pointer to the device structure + * + * Output: + * None. + */ +void ftmac100_destructor(struct net_device *dev) +{ + PRINTK3("%s:ftmac100_destructor\n", dev->name); +} + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc .. + * + */ +static int ftmac100_open(struct net_device *dev) +{ + unsigned int ioaddr = dev->base_addr; + + PRINTK2("%s:ftmac100_open\n", dev->name); + +#ifdef MODULE + MOD_INC_USE_COUNT; +#endif + + /* reset the hardware */ + ftmac100_reset( dev ); + ftmac100_enable( dev ); + + /* set the MAC address */ + put_mac(ioaddr, dev->dev_addr); + + return 0; +} + +#ifdef USE_32_BIT +void +insl32(r,b,l) +{ + int __i ; + dword *__b2; + + __b2 = (dword *) b; + for (__i = 0; __i < l; __i++) { + *(__b2 + __i) = *(dword *)(r+0x10000300); + } +} +#endif + +/* + * ftmac100_rcv - receive a packet from the card + * + * There is ( at least ) a packet waiting to be read from + * chip-memory. + * + * o Read the status + * o If an error, record it + * o otherwise, read in the packet + */ +static int ftmac100_rcv(struct net_device *dev) +{ + struct ftmac100_local *lp = (struct ftmac100_local *)dev->priv; + int packet_length; + volatile RX_DESC *cur_desc; + int cpy_length; + int start_idx; + int seg_length; + int rcv_cnt; + + ///PRINTK3("%s:ftmac100_rcv\n", dev->name); + for (rcv_cnt=0; rcv_cnt<1; ++rcv_cnt) { + packet_length = 0; + start_idx = lp->rx_idx; + + for (; (cur_desc = &lp->rx_descs[lp->rx_idx])->RXDMA_OWN==0; ) { + lp->rx_idx = (lp->rx_idx+1)%RXDES_NUM; + if (cur_desc->FRS) { + if (cur_desc->RX_ERR || cur_desc->CRC_ERR || cur_desc->FTL || cur_desc->RUNT || cur_desc->RX_ODD_NB) { + cur_desc->RXDMA_OWN = 1; // this frame has been processed, return this to hardware + return 0; + } + packet_length = cur_desc->ReceiveFrameLength; // normal frame + } + + // packet's last frame + if ( cur_desc->LRS ) { + break; + } + } + + if (packet_length>0) // received one packet + { + byte * data; + + data = NetRxPackets[0]; + cpy_length = 0; + for (; start_idx!=lp->rx_idx; start_idx=(start_idx+1)%RXDES_NUM) { + seg_length = min(packet_length - cpy_length, RX_BUF_SIZE); + memcpy(data+cpy_length, (char *)lp->rx_descs[start_idx].VIR_RXBUF_BADR, seg_length); + cpy_length += seg_length; + lp->rx_descs[start_idx].RXDMA_OWN = 1; // this frame has been processed, return this to hardware + } + NetReceive(NetRxPackets[0], packet_length); +#if FTMAC100_DEBUG > 4 + DO_PRINT("Receiving Packet\n"); + print_packet( data, packet_length ); +#endif + return packet_length; + } + } + return 0; +} + + + +/* + * ftmac100_close + * + * this makes the board clean up everything that it can + * and not talk to the outside world. Caused by + * an 'ifconfig ethX down' + * + */ +static int ftmac100_close(struct net_device *dev) +{ + //netif_stop_queue(dev); + //dev->start = 0; + + PRINTK2("%s:ftmac100_close\n", dev->name); + + /* clear everything */ + ftmac100_shutdown( dev->base_addr ); + + /* Update the statistics here. */ +#ifdef MODULE + MOD_DEC_USE_COUNT; +#endif + + return 0; +} + + +/* PHY CONTROL AND CONFIGURATION */ + + + +#if FTMAC100_DEBUG > 2 +static void print_packet( byte * buf, int length ) +{ +#if 1 +#if FTMAC100_DEBUG > 3 + int i; + int remainder; + int lines; +#endif + + DO_PRINT("Packet of length %d \n", length ); + +#if FTMAC100_DEBUG > 3 + lines = length / 16; + remainder = length % 16; + + for ( i = 0; i < lines ; i ++ ) { + int cur; + + for ( cur = 0; cur < 8; cur ++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + DO_PRINT("%02x%02x ", a, b ); + } + DO_PRINT("\n"); + } + for ( i = 0; i < remainder/2 ; i++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + DO_PRINT("%02x%02x ", a, b ); + } + DO_PRINT("\n"); +#endif +#endif +} +#endif + + +void ftmac100_ringbuf_alloc(struct ftmac100_local *lp) +{ + int i; + + lp->rx_descs = kmalloc( sizeof(RX_DESC)*(RXDES_NUM+1), GFP_DMA|GFP_KERNEL ); + if (lp->rx_descs == NULL) { + DO_PRINT("Receive Ring Buffer allocation error\n"); + BUG(); + } + lp->rx_descs = (RX_DESC *)((int)(((char *)lp->rx_descs)+sizeof(RX_DESC)-1)&0xfffffff0); + lp->rx_descs_dma = virt_to_phys(lp->rx_descs); + memset(lp->rx_descs, 0, sizeof(RX_DESC)*RXDES_NUM); + + + lp->rx_buf = kmalloc( RX_BUF_SIZE*RXDES_NUM, GFP_DMA|GFP_KERNEL ); + if (lp->rx_buf == NULL || (( (u32)lp->rx_buf % 4)!=0)) { + DO_PRINT("Receive Ring Buffer allocation error, lp->rx_buf = %x\n", lp->rx_buf); + BUG(); + } + lp->rx_buf_dma = virt_to_phys(lp->rx_buf); + + + for (i=0; i<RXDES_NUM; ++i) { + lp->rx_descs[i].RXBUF_Size = RX_BUF_SIZE; + lp->rx_descs[i].EDOTR = 0; // not last descriptor + lp->rx_descs[i].RXBUF_BADR = lp->rx_buf_dma+RX_BUF_SIZE*i; + lp->rx_descs[i].VIR_RXBUF_BADR = virt_to_phys( lp->rx_descs[i].RXBUF_BADR ); + } + lp->rx_descs[RXDES_NUM-1].EDOTR = 1; // is last descriptor + + + lp->tx_descs = kmalloc( sizeof(TX_DESC)*(TXDES_NUM+1), GFP_DMA|GFP_KERNEL ); + if (lp->tx_descs == NULL) { + DO_PRINT("Transmit Ring Buffer allocation error\n"); + BUG(); + } + lp->tx_descs = (TX_DESC *)((int)(((char *)lp->tx_descs)+sizeof(TX_DESC)-1)&0xfffffff0); + lp->tx_descs_dma = virt_to_phys(lp->tx_descs); + memset(lp->tx_descs, 0, sizeof(TX_DESC)*TXDES_NUM); + + lp->tx_buf = kmalloc( TX_BUF_SIZE*TXDES_NUM, GFP_DMA|GFP_KERNEL ); + if (lp->tx_buf == NULL || (( (u32)lp->tx_buf % 4)!=0)) { + DO_PRINT("Transmit Ring Buffer allocation error\n"); + BUG(); + } + lp->tx_buf_dma = virt_to_phys(lp->tx_buf); + + for (i=0; i<TXDES_NUM; ++i) { + lp->tx_descs[i].EDOTR = 0; // not last descriptor + lp->tx_descs[i].TXBUF_BADR = lp->tx_buf_dma+TX_BUF_SIZE*i; + lp->tx_descs[i].VIR_TXBUF_BADR = virt_to_phys( lp->tx_descs[i].TXBUF_BADR ); + } + lp->tx_descs[TXDES_NUM-1].EDOTR = 1; // is last descriptor + PRINTK("lp->rx_descs = %x, lp->rx_rx_descs_dma = %x\n", lp->rx_descs, lp->rx_descs_dma); + PRINTK("lp->rx_buf = %x, lp->rx_buf_dma = %x\n", lp->rx_buf, lp->rx_buf_dma); + PRINTK("lp->tx_descs = %x, lp->tx_rx_descs_dma = %x\n", lp->tx_descs, lp->tx_descs_dma); + PRINTK("lp->tx_buf = %x, lp->tx_buf_dma = %x\n", lp->tx_buf, lp->tx_buf_dma); +} + +//added by ivan +void ahb_init() +{ +#ifdef CONFIG_ADP_AG101_110_PLATFORM + *(unsigned int *)0x90100040=0x96700000; +#endif +} + +int eth_init(bd_t *bd) +{ + struct ftmac100_local *lp; + int i; + + ahb_init(); + + if (initialized == 0) + { + initialized = 1; + + dev_eth0.base_addr = NDS32_COMMON_FTMAC100_BASE; + /* Initialize the private structure. */ + dev_eth0.priv = (void *)malloc(sizeof(struct ftmac100_local)); + if (dev_eth0.priv == NULL) + { + DO_PRINT("out of memory\n"); + return 0; + } + + + /* initialize ftmac100_local */ + memset(dev_eth0.priv, 0, sizeof(struct ftmac100_local)); + strcpy(dev_eth0.name, "eth0"); + lp = (struct ftmac100_local *)dev_eth0.priv; + lp->maccr_val = FULLDUP_bit | CRC_APD_bit | MDC_SEL_bit | RCV_EN_bit | XMT_EN_bit | RDMA_EN_bit | XDMA_EN_bit; + ///lp->maccr_val = FULLDUP_bit | CRC_APD_bit | MDC_SEL_bit | RCV_EN_bit | RDMA_EN_bit ; // receive only + + ftmac100_ringbuf_alloc(lp); + } + if (memcmp(bd->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) + get_mac(NDS32_COMMON_FTMAC100_BASE, bd->bi_enetaddr); + else + put_mac(NDS32_COMMON_FTMAC100_BASE, bd->bi_enetaddr); + for (i=0; i<6; ++i) + dev_eth0.dev_addr[i] = bd->bi_enetaddr[i]; + print_mac(bd->bi_enetaddr); + ftmac100_open(&dev_eth0); + + return 0; +} + +void eth_halt() +{ + if (initialized == 1) { + ftmac100_close(&dev_eth0); + } +} + +int eth_rx() +{ + return ftmac100_rcv(&dev_eth0); +} + +int eth_send(volatile void *packet, int length) +{ + return ftmac100_send_packet(packet, length, &dev_eth0); +} + +void ftmac100_dummy() +{ + printf("enter ftmac100_dummy\n"); +} +#endif diff --git a/board/AndesTech/common/ftpci100.c b/board/AndesTech/common/ftpci100.c new file mode 100644 index 0000000..b117d3c --- /dev/null +++ b/board/AndesTech/common/ftpci100.c @@ -0,0 +1,712 @@ +/* + * Copyright (C) 2005 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * filename: ftpci100.c + * description: the low-level code for FTPCI100 AHB-PCI Bridge, + * implement to meet the u-boot/driver/pci/pci.c. + * + * history: + * - 2009.04.02, move the code from bootrom to u-boot (Hill). + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ftpci100.h> +#include <common.h> +#include <asm/andesboot.h> +#include <malloc.h> +#include <command.h> + +#if defined(CONFIG_CMD_PCI) && defined (CONFIG_DRIVER_FTPCI100) + +/* + * register IOs + */ +typedef struct +{ + volatile unsigned int offset[4096]; /* 4K * 4 = SZ_16K */ +} __regbase32; + +typedef struct +{ + volatile unsigned short offset[4096]; /* 4K * 2 = SZ_8K */ +} __regbase16; + +typedef struct +{ + volatile unsigned char offset[4096]; /* 4K * 1 = SZ_4K */ +} __regbase8; + +#define REG32(a) ((__regbase32 *)((a)&~4095))->offset[((a)&4095)>>2] +#define REG16(a) ((__regbase16 *)((a)&~4095))->offset[((a)&4095)>>1] +#define REG8(a) ((__regbase8 *)((a)&~4095))->offset[((a)&4095)>>0] + +#define inb(a) REG8(a) +#define inhw(a) REG16(a) +#define inw(a) REG32(a) + +#define outb(a,v) (REG8(a) = (unsigned char)(v)) +#define outhw(a,v) (REG16(a) = (unsigned short)(v)) +#define outw(a,v) (REG32(a) = (unsigned int)(v)) + +static struct pci_controller sg_PCIHost; //[PCI_MAX_BUS_NUM]; +/* + * static members + */ +static UINT32 flib_ReadPCICfgSpaceWord(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg); +static UINT16 flib_ReadPCICfgSpaceHalfWord(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg); +static UINT8 flib_ReadPCICfgSpaceByte(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg); +static void flib_WritePCICfgSpaceWord(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg, UINT32 dt); +static void flib_WritePCICfgSpaceHalfWord(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg, UINT16 dt); +static void flib_WritePCICfgSpaceByte(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg, UINT8 dt); + +static UINT32 sg_PCIRegBase; +static PCIResourceMapStruct sg_PCIRscMap_s; +static PCIBridgeDMAResourceMapStruct sg_PCI_Bridge_DMA_s; + + +static void flib_PCI_INT_Init(void) +{ +#if 0 + unsigned int u32i, *pu32; + + pu32 = (unsigned int*)PCI_CARD_MEM_BASE; + + printf("test start \r\n"); + for(u32i=0; u32i<0x1000; u32i++) + pu32[u32i] = u32i; + for(u32i=0; u32i<0x1000; u32i++) + if(pu32[u32i] != u32i) + printf("err: %08Xh W:%04Xh R:%04Xh \r\n", &pu32[u32i], u32i, pu32[u32i]); + printf("test finish \r\n"); +#endif +#if 0 + PCIBridgeINTPollingIndex=0; +//opened by Howard@2007-4-23 + fLib_CloseInt(FIQ_PCI); + //Ext_CloseInt(FIQ_PCI); + + +#ifdef PCI_INT_USE_ACTIVE_H +//opened by Howard@2007-4-23 + fLib_SetIntTrig(FIQ_PCI,LEVEL,H_ACTIVE); + //Ext_SetIntTrig(FIQ_PCI,LEVEL,H_ACTIVE); + +#else +//opened by Howard@2007-4-23 + fLib_SetIntTrig(FIQ_PCI,LEVEL,L_ACTIVE); + //Ext_SetIntTrig(FIQ_PCI,LEVEL,L_ACTIVE); +#endif +//opened by Howard@2007-4-23 + fLib_ConnectInt(FIQ_PCI, (PrHandler)flib_PCI_IntHandler); + //Ext_ConnectInt(FIQ_PCI, (PrHandler)flib_PCI_IntHandler); +//opened by Howard@2007-4-23 + fLib_EnableInt(FIQ_PCI); + //Ext_EnableInt(FIQ_PCI); +#endif +} + + +static void InitPCIBridge(UINT32 RegBase) +{ + UINT32 u32TestValue1; + + // 1.Set the PCI Reg Base + sg_PCIRegBase = RegBase; + + // 2.disable the Interrupt Mask (INTA/INTB/INTC/INTD) + outw(NDS32_COMMON_PCI_IO_BASE+PCI_CONFIG_ADDR_REG ,(PCI_BRIDGE_CFG_SPACE_CONTROL|0x80000000)); + u32TestValue1 = inw(NDS32_COMMON_PCI_IO_BASE+PCI_CONFIG_DATA_REG); + +#if 0 + u32TestValue1 |= PCI_ENABLE_INTA_INTB_INTC_INTD; +#else + u32TestValue1 &= ~PCI_ALL_INTs_MASK; // disable INTs +#endif + outw(NDS32_COMMON_PCI_IO_BASE+PCI_CONFIG_ADDR_REG, (PCI_BRIDGE_CFG_SPACE_CONTROL|0x80000000)); + outw(NDS32_COMMON_PCI_IO_BASE+PCI_CONFIG_DATA_REG, u32TestValue1); + + // 3.Init PCI Bridge INT (do nothing) + flib_PCI_INT_Init(); + +} + + + +/* + * * Function Name: flib_PCIBridgeMemoryRequest + * * Description: 1.Fix mem for the DMA (PCI.h) + * 2.Set the PCI Bridge Configuration Space + */ +static void flib_PCIBridgeMemoryRequest(void) +{ + PCIDeviceIDStruct PCIDeviceID; + + sg_PCI_Bridge_DMA_s.PCI_DMA_Base_Address = PCI_BRIDGE_DMA_START_ADDRESS; + PCIDeviceID.BusNum = PCIDeviceID.DevNum = PCIDeviceID.FunNum = 0x00; + flib_WritePCICfgSpaceWord(PCIDeviceID, PCI_BRIDGE_CFG_SPACE_MEM1_BA, + PCI_BRIDGE_DMA_START_SIZE_VALUE); + + sg_PCI_Bridge_DMA_s.PCI_DMA_Start_Pointer = (UINT8*)PCI_BRIDGE_DMA_START_ADDRESS; + sg_PCI_Bridge_DMA_s.PCI_DMA_Size_Remain = PCI_BRIDGE_DMA_SIZE*1024*1024; +} + + +void flib_DisablePCIDevice(PCIDeviceIDStruct PCIDeviceID) +{ + UINT32 CMDType; + PCIDeviceID.RegNum = PCI_CSH_COMMAND_REG; + CMDType = flib_ReadPCICfgSpaceByte(PCIDeviceID, PCI_CSH_COMMAND_REG); + flib_WritePCICfgSpaceByte(PCIDeviceID, PCI_CSH_COMMAND_REG, CMDType & ~(UINT32)(PCI_CMD_IO_ENABLE|PCI_CMD_MEM_ENABLE)); +} + + +void flib_EnablePCIDevice(PCIDeviceIDStruct PCIDeviceID) +{ + UINT32 CMDType; + PCIDeviceID.RegNum = PCI_CSH_COMMAND_REG; + CMDType = flib_ReadPCICfgSpaceByte(PCIDeviceID, PCI_CSH_COMMAND_REG); + flib_WritePCICfgSpaceByte(PCIDeviceID, PCI_CSH_COMMAND_REG, CMDType | PCI_CMD_IO_ENABLE | PCI_CMD_MEM_ENABLE); +} + + +void flib_SetPCIMaster(PCIDeviceIDStruct PCIDeviceID) +{ + UINT32 CMDType; + PCIDeviceID.RegNum = PCI_CSH_COMMAND_REG; + CMDType = flib_ReadPCICfgSpaceByte(PCIDeviceID, PCI_CSH_COMMAND_REG); + flib_WritePCICfgSpaceByte(PCIDeviceID, PCI_CSH_COMMAND_REG, CMDType | PCI_CMD_BUS_MASTER_ENABLE); +} + + +/* + * * Function Name: flib_AssignPCIResource + * * Description: It will assign the PCI Device resource of the: + * 1.IO Resourse + * 2.Mem Resource + */ +void flib_AssignPCIResource +( + PCIDeviceIDStruct PCIDeviceID , UINT32 *PciMemStart, UINT32 *PciIoStart +) +{ + UINT32 lw, i, j, Reg, BaseAddrReg, BaseSize; + UINT32 dwAlignmentSize; + + for (i = 0 ; i < PCI_MAX_BAR_NUM ; i++) + { + Reg = PCI_CSH_BASE_ADDR_REG + (i * 4); + flib_WritePCICfgSpaceWord(PCIDeviceID, Reg, 0xFFFFFFFF); + lw = flib_ReadPCICfgSpaceWord(PCIDeviceID, Reg); + print_pci("%08Xh \r\n", lw); + + if ((lw == 0) || ((lw & 0xffffffff) == 0xffffffff)) + { + continue; + } + else + { + if ((lw & 0x01) != 0x00) /* it's IO base */ + { + print_pci("it's IO base\n\r");//Howard@2007-4-23 + lw >>= 2; + for (j=2; j < 32; j++) + { + if ((lw & 0x01) == 0x01) // Harry@Dec.30.2006 + break; + lw >>= 1; + } + BaseSize = 1 << j; + if (BaseSize>=PCI_IO_SPACE_ALIGNMENT) + dwAlignmentSize=BaseSize; + else dwAlignmentSize=PCI_IO_SPACE_ALIGNMENT; + + if ((*PciIoStart % dwAlignmentSize) != 0) + *PciIoStart = ((*PciIoStart / dwAlignmentSize) + 1) * dwAlignmentSize; + + BaseAddrReg = *PciIoStart; + *PciIoStart += BaseSize; + flib_WritePCICfgSpaceWord(PCIDeviceID, Reg, BaseAddrReg); + print_pci(" B:%02u.D:%02u.F:%02u Reg:%08Xh BaseAddrReg:%08Xh\r\n", + PCIDeviceID.BusNum, PCIDeviceID.DevNum, PCIDeviceID.FunNum, Reg, BaseAddrReg); + } + else if ((lw & 0x01) != 0x01) /* it's Memory base */ + { + print_pci("it's Memory base\n\r");//Howard@2007-4-23 + lw >>= 4; + for (j=4; j < 32; j++) + { + if ((lw & 0x01) == 0x01) // Harry@Dec.30.2006 + break; + lw >>= 1; + } + BaseSize = 1 << j; + + if (BaseSize>=PCI_MEM_SPACE_ALIGNMENT) + dwAlignmentSize=BaseSize; + else dwAlignmentSize=PCI_MEM_SPACE_ALIGNMENT; + + if ((*PciMemStart % dwAlignmentSize) != 0) + *PciMemStart = ((*PciMemStart / dwAlignmentSize) + 1) * dwAlignmentSize; + + BaseAddrReg = *PciMemStart; + flib_WritePCICfgSpaceWord(PCIDeviceID, Reg, BaseAddrReg); + print_pci(" B:%02u.D:%02u.F:%02u Reg:%08Xh BaseAddrReg:%08Xh\r\n", + PCIDeviceID.BusNum, PCIDeviceID.DevNum, PCIDeviceID.FunNum, Reg, BaseAddrReg); + + *PciMemStart += BaseSize; + } + } + } +} + +BOOL flib_FindNextPCIDevice(PCIDeviceIDStruct CurrDevID,PCIDeviceIDStruct *NextDevID) +{ + UINT16 VendorID; + UINT8 HeaderType; + + /* read vendor id to check whether this PCI device exists or not */ + VendorID = flib_ReadPCICfgSpaceHalfWord(CurrDevID, PCI_CSH_VENDOR_ID_REG); + if ((VendorID != 0x0) && (VendorID != 0xFFFF)) + { + //This device is exist, then it will get the counter of the Dev number and Fun number + printf("\r\n+ FindNextPCIDev, B:%02u.D:%02u.F:%02u VID: %04Xh \r\n", + CurrDevID.BusNum, CurrDevID.DevNum, CurrDevID.FunNum, VendorID); + + //1.To determine single_function/multi_function + HeaderType = flib_ReadPCICfgSpaceByte(CurrDevID, PCI_CSH_HEADER_TYPE_REG); + /* the bit 7 of header type is 1, it it multi function device */ + if (HeaderType & PCI_HEADER_TYPE_MULTI_FUNCTION) + { + printf("multi-func \r\n"); + CurrDevID.FunNum++; + if (CurrDevID.FunNum >= PCI_MAX_FUNCTION_NUM) + CurrDevID.DevNum++; + } + else + { + printf("single-func \r\n"); + CurrDevID.DevNum++; + CurrDevID.FunNum = 0; + } + + printf("\r\n- FindNextPCIDev, B:%02u.D:%02u.F:%02u VID: %04Xh \r\n", + CurrDevID.BusNum, CurrDevID.DevNum, CurrDevID.FunNum, VendorID); + + } + else + { + //printf("%s[Ln.%u] invalid Vendor ID: %04Xh /r/n", __FILE__, __LINE__, VendorID); + /* if this PCI device does not exist, find PCI device from the beginning */ + CurrDevID.BusNum = 0; + CurrDevID.DevNum = 0; + CurrDevID.FunNum = 0; + } + + for (;CurrDevID.BusNum < PCI_MAX_BUS_NUM; CurrDevID.BusNum++, CurrDevID.DevNum=0) + for (;CurrDevID.DevNum < PCI_MAX_DEVICE_NUM; CurrDevID.DevNum++, CurrDevID.FunNum=0) + for (;CurrDevID.FunNum < PCI_MAX_FUNCTION_NUM; CurrDevID.FunNum++) + { + VendorID = flib_ReadPCICfgSpaceHalfWord(CurrDevID, PCI_CSH_VENDOR_ID_REG); + + if ((VendorID != 0x0) && (VendorID != 0xFFFF)) + { + *NextDevID = CurrDevID; + return TRUE; + } + } + + return FALSE; +} + + + +static void flib_AssignPCIResource_hill(void) +{ + PCIDeviceIDStruct CurrDevID_st; + UINT16 VendorID; + UINT8 HeaderType; + + CurrDevID_st.BusNum = 0; + CurrDevID_st.DevNum = 1; + CurrDevID_st.FunNum = 0; + + /* read vendor id to check whether this PCI device exists or not */ + for (;CurrDevID_st.BusNum < PCI_MAX_BUS_NUM; CurrDevID_st.BusNum++, CurrDevID_st.DevNum=0) + for (;CurrDevID_st.DevNum < PCI_MAX_DEVICE_NUM; CurrDevID_st.DevNum++, CurrDevID_st.FunNum=0) + for (;CurrDevID_st.FunNum < PCI_MAX_FUNCTION_NUM; CurrDevID_st.FunNum++) + { + VendorID = flib_ReadPCICfgSpaceHalfWord(CurrDevID_st, PCI_CSH_VENDOR_ID_REG); + if ((VendorID != 0x0) && (VendorID != 0xFFFF)) + { + flib_DisablePCIDevice(CurrDevID_st); + print_pci("\r\n B:%02u.D:%02u.F:%02u VID: %04Xh \r\n", + CurrDevID_st.BusNum, CurrDevID_st.DevNum, CurrDevID_st.FunNum, VendorID); + flib_AssignPCIResource(CurrDevID_st, + &sg_PCIRscMap_s.PciMem0Addr, &sg_PCIRscMap_s.PciIOAddr); + + flib_EnablePCIDevice(CurrDevID_st); + flib_SetPCIMaster(CurrDevID_st); + } + } + +} + + +// scan device and print the Vendor ID / Device ID +static void flib_scan_device(void) +{ + UINT16 u16VendorID, u16DevID; + PCIDeviceIDStruct CurrDevID; + UINT8 u8HeadType; + + for(CurrDevID.BusNum=0; CurrDevID.BusNum < PCI_MAX_BUS_NUM; CurrDevID.BusNum++) + for (CurrDevID.DevNum=0; CurrDevID.DevNum < PCI_MAX_DEVICE_NUM; CurrDevID.DevNum++) + for (CurrDevID.FunNum=0;CurrDevID.FunNum < PCI_MAX_FUNCTION_NUM; CurrDevID.FunNum++) + { + u16VendorID = flib_ReadPCICfgSpaceHalfWord(CurrDevID, PCI_CSH_VENDOR_ID_REG); + u16DevID = flib_ReadPCICfgSpaceHalfWord(CurrDevID, PCI_CSH_DEVICE_ID_REG); + u8HeadType = flib_ReadPCICfgSpaceByte(CurrDevID, PCI_CSH_HEADER_TYPE_REG); + + if(0 == u16VendorID) + printf("VID == 0 \r\n"); + else if(0xFFFF != u16DevID) + { + printf("Bus: %02Xh Dev: %02Xh Func: %02Xh \r\n", + CurrDevID.BusNum, CurrDevID.DevNum, CurrDevID.FunNum); + printf(" VID: %04Xh DevID: %04Xh %s\r\n", u16VendorID, u16DevID, + (u8HeadType&0x80)?"Multi-Fun":"Single-Fun"); + } + } +} + +static void flib_PCI_InitPCIDevice(void) +{ + PCIDeviceIDStruct PCIDeviceID; + + // 1.Init InitPCIBridge + InitPCIBridge(NDS32_COMMON_PCI_IO_BASE); + + // 2.Set start Address of the I/O and Mem + sg_PCIRscMap_s.PciIOAddr=PCI_CARD_IO_BASE; + sg_PCIRscMap_s.PciMem0Addr=PCI_CARD_MEM_BASE; + +#if 0 + // 3.Reserve Mem for DMA, write Base/Size to the PCI Bridge Configuration Space + flib_PCIBridgeMemoryRequest(); + + // 4.Assign the Resource & Enable PCI DEVICE & Start PCI Device + PCIDeviceID.BusNum = PCIDeviceID.DevNum = PCIDeviceID.FunNum = 0; + // device 0 has been assigned resource in step.3. + while(flib_FindNextPCIDevice(PCIDeviceID, &PCIDeviceID)) + { + flib_AssignPCIResource(PCIDeviceID, &sg_PCIRscMap_s.PciMem0Addr, &sg_PCIRscMap_s.PciIOAddr); + flib_EnablePCIDevice(PCIDeviceID); + flib_SetPCIMaster(PCIDeviceID); + } +#else + PCIDeviceID.BusNum = 0; + PCIDeviceID.DevNum = 0; + PCIDeviceID.FunNum = 0; + flib_WritePCICfgSpaceWord(PCIDeviceID, PCI_BRIDGE_CFG_SPACE_MEM1_BA, + PCI_INBOUND_MEM_BASE & (~0xFFF0000) | PCI_INBOUND_MEM_256MB); + print_pci("%X \r\n", PCI_INBOUND_MEM_BASE & (~0xFFF0000) | PCI_INBOUND_MEM_256MB); + + //flib_scan_device(); + flib_AssignPCIResource_hill(); +#endif +} + +static UINT32 flib_ReadPCICfgSpaceWord(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg) +{ + PCIDeviceID.RegNum = Reg; + PCIDeviceID.Enable = 1; + outw(sg_PCIRegBase + PCI_CONFIG_ADDR_REG, *(UINT32 *)((void *)&PCIDeviceID)); // Harry@Dec.30.2006 + return inw(sg_PCIRegBase+PCI_CONFIG_DATA_REG); +} + +static UINT16 flib_ReadPCICfgSpaceHalfWord(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg) +{ + UINT32 lw; + + lw = flib_ReadPCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc)); + switch(Reg % 4) + { + case 0: + case 1: + lw &= 0x0000FFFF; + break; + case 2: + case 3: + lw &= 0xFFFF0000; + lw = lw >> 16; + break; + } + + return (UINT16)lw; +} + + +static UINT8 flib_ReadPCICfgSpaceByte(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg) +{ + UINT32 lw; + + lw = flib_ReadPCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc)); + switch(Reg % 4) + { + case 0: + lw &= 0x000000FF; + break; + case 1: + lw &= 0x0000FF00; + lw = lw >> 8; + break; + case 2: + lw &= 0x00FF0000; + lw = lw >> 16; + break; + case 3: + lw &= 0xFF000000; + lw = lw >> 24; + break; + } + + return (UINT8)lw; +} + +static void flib_WritePCICfgSpaceWord(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg, UINT32 dt) +{ + PCIDeviceID.RegNum = Reg; + PCIDeviceID.Enable = 1; + + outw(sg_PCIRegBase + PCI_CONFIG_ADDR_REG, *(UINT32 *)((void *)&PCIDeviceID)); + outw(sg_PCIRegBase + PCI_CONFIG_DATA_REG, dt); +} + +static void flib_WritePCICfgSpaceHalfWord(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg, UINT16 dt) +{ + UINT32 lw; + + lw = flib_ReadPCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc)); + switch(Reg % 4) + { + case 0: + case 1: + lw &= 0xFFFF0000; + lw += dt; + flib_WritePCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc), lw); + break; + case 2: + case 3: + lw &= 0x0000FFFF; + lw += (UINT32)(((UINT32)dt) << 16); + flib_WritePCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc), lw); + break; + } +} + +static void flib_WritePCICfgSpaceByte(PCIDeviceIDStruct PCIDeviceID, UINT32 Reg, UINT8 dt) +{ + UINT32 lw; + + lw = flib_ReadPCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc)); + switch(Reg % 4) + { + case 0: + lw &= 0xFFFFFF00; + lw += dt; + flib_WritePCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc), lw); + break; + case 1: + lw &= 0xFFFF00FF; + lw += (UINT32)(((UINT32)dt) << 8); + flib_WritePCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc), lw); + break; + case 2: + lw &= 0xFF00FFFF; + lw += (UINT32)(((UINT32)dt) << 16); + flib_WritePCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc), lw); + break; + case 3: + lw &= 0x00FFFFFF; + lw += (UINT32)(((UINT32)dt) << 24); + flib_WritePCICfgSpaceWord(PCIDeviceID, (Reg&0xfffffffc), lw); + break; + } +} + +int flib_read_byte(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, u8 *pu8Dat) +{ + PCIDeviceIDStruct DevId; + + DevId.BusNum = PCI_BUS(PciDev); + DevId.DevNum= PCI_DEV(PciDev); + DevId.FunNum = PCI_FUNC(PciDev); + *pu8Dat = flib_ReadPCICfgSpaceByte(DevId, where); + return 0; +} + +int flib_read_word(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, u16 *pu16Dat) +{ + PCIDeviceIDStruct DevId; + + DevId.BusNum = PCI_BUS(PciDev); + DevId.DevNum= PCI_DEV(PciDev); + DevId.FunNum = PCI_FUNC(PciDev); + *pu16Dat = flib_ReadPCICfgSpaceHalfWord(DevId, where); + return 0; +} + +int flib_read_dword(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, u32 *pu32Dat) +{ + PCIDeviceIDStruct DevId; + + DevId.BusNum = PCI_BUS(PciDev); + DevId.DevNum= PCI_DEV(PciDev); + DevId.FunNum = PCI_FUNC(PciDev); + *pu32Dat = flib_ReadPCICfgSpaceWord(DevId, where); + return 0; +} + +int flib_write_byte(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, u8 u8Dat) +{ + PCIDeviceIDStruct DevId; + + DevId.BusNum = PCI_BUS(PciDev); + DevId.DevNum= PCI_DEV(PciDev); + DevId.FunNum = PCI_FUNC(PciDev); + flib_WritePCICfgSpaceByte(DevId, where, u8Dat); + return 0; +} + +int flib_write_word(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, u16 u16Dat) +{ + PCIDeviceIDStruct DevId; + + DevId.BusNum = PCI_BUS(PciDev); + DevId.DevNum= PCI_DEV(PciDev); + DevId.FunNum = PCI_FUNC(PciDev); + flib_WritePCICfgSpaceHalfWord(DevId, where, u16Dat); + return 0; +} + +int flib_write_dword(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, u32 u32Dat) +{ + PCIDeviceIDStruct DevId; + + DevId.BusNum = PCI_BUS(PciDev); + DevId.DevNum= PCI_DEV(PciDev); + DevId.FunNum = PCI_FUNC(PciDev); + flib_WritePCICfgSpaceWord(DevId, where, u32Dat); + return 0; +} + +/* + * exposed APIs + */ + +// low-level init routine, called by /drivers/pci/pci.c - pci_init. +void pci_init_board(void) +{ + struct pci_controller *host = &sg_PCIHost; + + flib_PCI_InitPCIDevice(); + + memset(host, 0, sizeof(struct pci_controller)); + + /* + * Register the hose + */ + host->first_busno = 0; + host->last_busno = 0xff; + + /*pci_setup_indirect(host, + (sg_PCIRegBase + PCI_CONFIG_ADDR_REG), + (sg_PCIRegBase + PCI_CONFIG_DATA_REG)); + */ + +#if 0 + /* System memory space */ + pci_set_region (host->regions + 0, + AP1000_SYS_MEM_START, AP1000_SYS_MEM_START, + AP1000_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + /* PCI Memory space */ + pci_set_region (host->regions + 1, + PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE, + PSII_PCI_MEM_SIZE, PCI_REGION_MEM); + + host->region_count = 2; +#else + #if 0 + /* PCI memory space */ + pci_set_region(host->regions + 1, + PCI_CARD_MEM_BASE, + PCI_CARD_MEM_BASE, + PCI_CARD_MEM_TOTAL_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(host->regions + 2, + PCI_CARD_IO_BASE, + PCI_CARD_IO_BASE, + 0x100000-0x1000, + PCI_REGION_IO); + + host->region_count = 2; + #else + /* System space */ + pci_set_region(host->regions + 0, + PCI_BRIDGE_DMA_START_ADDRESS, + PCI_BRIDGE_DMA_START_ADDRESS, + PCI_BRIDGE_DMA_START_SIZE_VALUE - PCI_BRIDGE_DMA_START_ADDRESS, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + /* PCI memory space */ + pci_set_region(host->regions + 1, + PCI_CARD_MEM_BASE, + PCI_CARD_MEM_BASE, + PCI_CARD_MEM_TOTAL_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(host->regions + 2, + PCI_CARD_IO_BASE, + PCI_CARD_IO_BASE, + 0x100000-0x1000, + PCI_REGION_IO); + + host->region_count = 3; +#endif +#endif + + /* No IO Memory space - for now */ + pci_set_ops (host, + flib_read_byte, flib_read_word, flib_read_dword, + flib_write_byte, flib_write_word, flib_write_dword); + + pci_register_hose (host); + + host->last_busno = pci_hose_scan (host); +} + +#endif diff --git a/board/AndesTech/common/serial.c b/board/AndesTech/common/serial.c new file mode 100644 index 0000000..ebd6c52 --- /dev/null +++ b/board/AndesTech/common/serial.c @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * Copyright (C) 2009 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <asm/andesboot.h> +#include <asm/global_data.h> +#include "../include/symbol.h" +#include "../include/porting.h" +#include "../include/serial.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * librarys copy from flib + */ + +#ifdef CONFIG_SERIAL1 + UINT32 DebugSerialPort = NDS32_COMMON_UART1_BASE; +#elif CONFIG_SERIAL2 + UINT32 DebugSerialPort = NDS32_COMMON_UART2_BASE; +#else + #error "Bad: you didn't configure serial ..." +#endif + + +unsigned int br[] = {1562, 780, 390, 194, 32, 15}; +void serial_setbrg(void) +{ + unsigned int reg = 0; + + if (gd->baudrate == 9600) + { + reg = NDS32_COMMON_BAUD_9600; + } + else if (gd->baudrate == 19200) + { + reg = NDS32_COMMON_BAUD_19200; + } + else if (gd->baudrate == 38400) + { + reg = NDS32_COMMON_BAUD_38400; + } + else if (gd->baudrate == 57600) + { + reg = NDS32_COMMON_BAUD_57600; + } +#if (SYS_CLK == 22118400) + else if (gd->baudrate == 115200) + { + reg = NDS32_COMMON_BAUD_115200; + } +#endif + else + { + hang(); + } + fLib_SetSerialMode( DebugSerialPort, SERIAL_MDR_UART ); + fLib_SerialInit( DebugSerialPort, reg, PARITY_NONE, 0, 8 ); + fLib_SetSerialFifoCtrl(DebugSerialPort, 1, ENABLE, ENABLE); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init(void) +{ + const char *baudrate; + + gd->baudrate = CONFIG_BAUDRATE; + if ((baudrate = getenv("baudrate")) != 0) + { + //printf("serial_init> baudrate: %s \n", baudrate); + gd->baudrate = simple_strtoul(baudrate, NULL, 10); + } + //serial_setbrg(); + + return 0; +} + + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc(void) +{ + return fLib_GetSerialChar( DebugSerialPort ); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc(const char c) +{ + + if(c == '\n') + serial_putc('\r'); + fLib_PutSerialChar( DebugSerialPort, c ); + + /* If \n, also do \r */ +// if(c == '\n') +// serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc(void) +{ + return ( cpe_inl( DebugSerialPort + SERIAL_LSR ) & SERIAL_LSR_DR ) == SERIAL_LSR_DR; +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +}

Add nds32 based board with include header files support.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- board/AndesTech/include/andes.h | 51 ++ board/AndesTech/include/chipset.h | 852 ++++++++++++++++++++++++++++++++++ board/AndesTech/include/flib_flash.h | 87 ++++ board/AndesTech/include/ftmac100.h | 257 ++++++++++ board/AndesTech/include/ftpci100.h | 238 ++++++++++ board/AndesTech/include/porting.h | 60 +++ board/AndesTech/include/serial.h | 175 +++++++ board/AndesTech/include/symbol.h | 107 +++++ 8 files changed, 1827 insertions(+), 0 deletions(-) create mode 100644 board/AndesTech/include/andes.h create mode 100644 board/AndesTech/include/chipset.h create mode 100644 board/AndesTech/include/flib_flash.h create mode 100644 board/AndesTech/include/ftmac100.h create mode 100644 board/AndesTech/include/ftpci100.h create mode 100644 board/AndesTech/include/porting.h create mode 100644 board/AndesTech/include/serial.h create mode 100644 board/AndesTech/include/symbol.h

diff --git a/board/AndesTech/include/andes.h b/board/AndesTech/include/andes.h new file mode 100644 index 0000000..1ab103b --- /dev/null +++ b/board/AndesTech/include/andes.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * define version number + */ +#define VERSION_MAJOR_NUM 0 +#define VERSION_MINOR_NUM 16 +#define VERSION_CLOCK SYSTEM_CLOCK + +/* + * define platform + */ +#define CONFIG_ADP_AG101_120_PLATFORM +//#define CONFIG_ADP_AG101_110_PLATFORM + +/* + * define system clock + */ +//#define SYSTEM_CLOCK 16000000 //16.000000 MHz +//#define SYSTEM_CLOCK 18432000 //18.432000 MHz +//#define SYSTEM_CLOCK 22118400 //22.118400 MHz +#define SYSTEM_CLOCK 83000000 //83.000000 MHz +//#define SYSTEM_CLOCK 33000000 //83.000000 MHz +//#define SYSTEM_CLOCK 36864000 //36.864000 MHz + +/* + * define flash bank + */ +#define CONFIG_FLASH_BANK 1 //bank 0,1,2,3,4,5,6,7 diff --git a/board/AndesTech/include/chipset.h b/board/AndesTech/include/chipset.h new file mode 100644 index 0000000..c5cbf04 --- /dev/null +++ b/board/AndesTech/include/chipset.h @@ -0,0 +1,852 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef CHIPSET_H +#define CHIPSET_H + +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/*********************************************************************** + * Copyright Faraday Technology Corp 2002-2003. All rights reserved. * + *---------------------------------------------------------------------* + * Name:cpe.s * + * Description: ADP_AG101 board specfic define * + * Author: Fred Chien * + *********************************************************************** + */ + +/* + * ADP_AG101 address map; + * + * +========================================== + * 0x00000000 | ROM + * | + * 0x00080000 |========================================== + * | SRAM + * |========================================== + * 0x10000000 | SDRAM + * 0x8FFFFFFF | + * |========================================== + * 0x90000000 |Controller's reg + * | + * |0x90100000 Arbiter/Decoder + * |0x90200000 SRAM controller reg + * |0x902ffffc Debug Numberic LED + * |0x90900000 SDRAM controller reg + * |0x90400000 DMA controller reg + * |0x90500000 AHB2APB bridge + * |0x90600000 Reserved + * |0x91000000-91F00000 DMA0-DMA15 Device; + * |0x92400000 DSP + * |0x92500000 Reserved + * |0x96500000 LCD + * |0x96600000 Bluetooth + * |0x96700000 MAC + * |0x96800000 PCI + * |0x96900000 USB2.0 host + * |0x98000000-9AFFFFFF APB Device; + * | + * 0x98000000 |========================================== + * | APB Device's Reg + * | + * |0x98000000 Reserved + * |0x98100000 Power Managemnet + * |0x98200000 UART1 + * |0x98300000 UART2/IrDA + * |0x98400000 Timer + * |0x98500000 Watchdog Timer + * |0x98600000 RTC + * |0x98700000 GPIO + * |0x98800000 INTC + * |0x98900000 UART3 + * |0x98A00000 I2C + * |0x98B00000 SSP1 + * |0x98C00000 USB Device + * |0x98D00000 Compact Flash + * |0x98E00000 Secure Digital + * |0x98F00000 SMC + * |0x99000000 MS + * |0x99100000 SCI + * |0x99200000 ECP/EPP + * |0x99300000 KBC + * |0x99400000 I2S + * |0x99500000 AC97 + * |0x99600000 SSP2 + * |0x99700000 Mouse + * |0x9AFFFFFF Reserved + * | + * +========================================== + */ + +/* ------------------------------------------------------------------------------- + * ADP_AG101 system registers + * ------------------------------------------------------------------------------- + * ------------------------------------------------------------------------------- + * Decoder definitions + * ------------------------------------------------------------------------------- + */ + +#define AHB_SLAVE0_REG 0x00 +#define AHB_SLAVE1_REG 0x04 +#define AHB_SLAVE2_REG 0x08 +#define AHB_SLAVE3_REG 0x0c +#define AHB_SLAVE4_REG 0x10 +#define AHB_SLAVE5_REG 0x14 +#define AHB_SLAVE6_REG 0x18 +#define AHB_SLAVE7_REG 0x1c +#define AHB_SLAVE8_REG 0x20 +#define AHB_SLAVE9_REG 0x24 +#define AHB_SLAVE10_REG 0x28 + +#define ADP_AG101_PRIORITY_REG 0x80 +#define ADP_AG101_DEFAULT_MASTER_REG 0x84 +#define ADP_AG101_REMAP_REG 0x88 + +/* ------------------------------------------------------------------------------- + * SRAM definitions + * ------------------------------------------------------------------------------- + */ + +#define SRAM_CONFIG0 0x00 +#define SRAM_TIME0 0x04 +#define SRAM_CONFIG1 0x08 +#define SRAM_TIME1 0x0C +#define SRAM_CONFIG2 0x10 +#define SRAM_TIME2 0x14 +#define SRAM_CONFIG3 0x18 +#define SRAM_TIME3 0x1C +#define SRAM_CONFIG4 0x20 +#define SRAM_TIME4 0x24 +#define SRAM_CONFIG5 0x28 +#define SRAM_TIME5 0x2C +#define SRAM_CONFIG6 0x30 +#define SRAM_TIME6 0x34 +#define SRAM_CONFIG7 0x38 +#define SRAM_TIME7 0x3C +#define SRAM_SHADOW 0x40 +#define SRAM_PARITY 0x44 + +/* SRAM bank config register */ + +#define SRAMBANK_ENABLE (1<<28) + + +#define SRAMBNK_WPROT 0x800 /* write protect */ + +#define SRAMBNK_TYPE1 0x400 /* synchrous */ +#define SRAMBNK_TYPE2 0x200 /* burst rom or pipeline depend on type 1 */ +#define SRAMBNK_TYPE3 0x100 /* write latency enable */ + +/* bank size */ +#define SRAM_BNKSIZE_32K 0xb0 +#define SRAM_BNKSIZE_64K 0xc0 +#define SRAM_BNKSIZE_128K 0xd0 +#define SRAM_BNKSIZE_256K 0xe0 +#define SRAM_BNKSIZE_512K 0xf0 +#define SRAM_BNKSIZE_1M 0x00 +#define SRAM_BNKSIZE_2M 0x10 +#define SRAM_BNKSIZE_4M 0x20 +#define SRAM_BNKSIZE_8M 0x30 +#define SRAM_BNKSIZE_16M 0x40 +#define SRAM_BNKSIZE_32M 0x50 + + +/* bus width */ +#define SRAM_BNKMBW_8 0x0 +#define SRAM_BNKMBW_16 0x1 +#define SRAM_BNKMBW_32 0x2 + + +/* Timing parameter register */ + +#define SRAM_RBE 0x100000 /* read byte enable */ +#define SRAM_AST1 0x40000 /* address setup time */ +#define SRAM_AST2 0x80000 +#define SRAM_AST3 0xc0000 +#define SRAM_CTW1 0x10000 /* chp select to write enable delay */ +#define SRAM_CTW2 0x20000 /* chp select to write enable delay */ +#define SRAM_CTW3 0x30000 /* chp select to write enable delay */ + + + + +/* ------------------------------------------------------------------------------- + * SDRAM definitions + * ------------------------------------------------------------------------------- + */ + + + +#define SDRAM_TIME0 0x00 +#define SDRAM_TIME1 0x04 +#define SDRAM_CONFIG 0x08 + +#define SDRAM_EXTBANK0 0x0C +#define SDRAM_EXTBANK1 0x10 +#define SDRAM_EXTBANK2 0x14 +#define SDRAM_EXTBANK3 0x18 +#define SDRAM_EXTBANK4 0x1C +#define SDRAM_EXTBANK5 0x20 +#define SDRAM_EXTBANK6 0x24 +#define SDRAM_EXTBANK7 0x28 + +#define SDRAM_Arbiter 0x34 + +/* Timing Parameter 0 + * Active to precharge cycle + */ +#define SDRAM_TRAS_1 0x100000 +#define SDRAM_TRAS_2 0x200000 +#define SDRAM_TRAS_3 0x300000 +#define SDRAM_TRAS_4 0x400000 +#define SDRAM_TRAS_5 0x500000 +#define SDRAM_TRAS_6 0x600000 +#define SDRAM_TRAS_7 0x700000 +#define SDRAM_TRAS_8 0x800000 + +/* Precharge cycle */ +#define SDRAM_TRP_1 0x010000 +#define SDRAM_TRP_2 0x020000 +#define SDRAM_TRP_3 0x030000 +#define SDRAM_TRP_4 0x040000 +#define SDRAM_TRP_5 0x050000 +#define SDRAM_TRP_6 0x060000 +#define SDRAM_TRP_7 0x070000 +#define SDRAM_TRP_8 0x080000 + +/* RAS to CAS delay */ +#define SDRAM_TRCD_1 0x001000 +#define SDRAM_TRCD_2 0x002000 +#define SDRAM_TRCD_3 0x003000 +#define SDRAM_TRCD_4 0x004000 +#define SDRAM_TRCD_5 0x005000 +#define SDRAM_TRCD_6 0x006000 +#define SDRAM_TRCD_7 0x007000 + +/* Auto refresh cycle */ +#define SDRAM_TRF_1 0x000100 +#define SDRAM_TRF_2 0x000200 +#define SDRAM_TRF_3 0x000300 +#define SDRAM_TRF_4 0x000400 +#define SDRAM_TRF_5 0x000500 +#define SDRAM_TRF_6 0x000600 +#define SDRAM_TRF_7 0x000700 +#define SDRAM_TRF_8 0x000800 + +/* Write recovery time */ +#define SDRAM_TWR_1 0x000010 +#define SDRAM_TWR_2 0x000020 +#define SDRAM_TWR_3 0x000030 + +/* CAS latency */ +#define SDRAM_TCL_1 0x1 +#define SDRAM_TCL_2 0x2 +#define SDRAM_TCL_3 0x3 + + +/* Timing Parameter 1 */ + +/* Initial precharge times */ +#define SDRAM_INIPREC_1 0x100000 +#define SDRAM_INIPREC_2 0x200000 +#define SDRAM_INIPREC_3 0x300000 +#define SDRAM_INIPREC_4 0x400000 +#define SDRAM_INIPREC_5 0x500000 +#define SDRAM_INIPREC_6 0x600000 +#define SDRAM_INIPREC_7 0x700000 +#define SDRAM_INIPREC_8 0x800000 + + +/* Initial refresh times */ +#define SDRAM_INIREFT_1 0x10000 +#define SDRAM_INIREFT_2 0x20000 +#define SDRAM_INIREFT_3 0x30000 +#define SDRAM_INIREFT_4 0x40000 +#define SDRAM_INIREFT_5 0x50000 +#define SDRAM_INIREFT_6 0x60000 +#define SDRAM_INIREFT_7 0x70000 +#define SDRAM_INIREFT_8 0x80000 + +/* Config reguister */ +#define ADP_AG101_REFRESH_TYPE 0x20 /* refresh type */ +#define ADP_AG101_IPREC 0x10 /* initial precharge flag */ +#define ADP_AG101_IREF 0x8 /* Initial refresh flag */ +#define ADP_AG101_ISMR 0x4 /* Start set mode register */ +#define ADP_AG101_PWDN 0x2 /* Power down mode */ +#define ADP_AG101_SREF 0x1 /* Self refresh mode when power down */ + +/* External Bank Register define */ + +/* data width */ +#define SDRAM_DDW4 (0x0 <<12) +#define SDRAM_DDW8 (0x1 <<12) +#define SDRAM_DDW16 (0x2 <<12) +#define SDRAM_DDW32 (0x3 <<12) + +/* module size (bits) */ +#define SDRAM_DSZ_16M (0x00<<8) +#define SDRAM_DSZ_64M (0x1<<8) +#define SDRAM_DSZ_128M (0x2<<8) +#define SDRAM_DSZ_256M (0x3<<8) + +/* Bus data width */ +#define SDRAM_BNK_WIDTH8 (0x0 <<4) +#define SDRAM_BNK_WIDTH16 (0x1 <<4) +#define SDRAM_BNK_WIDTH32 (0x2 <<4) + +/* Bank size */ +#define SDRAM_BNK_SIZE_1M 0x0 +#define SDRAM_BNK_SIZE_2M 0x1 +#define SDRAM_BNK_SIZE_4M 0x2 +#define SDRAM_BNK_SIZE_8M 0x3 +#define SDRAM_BNK_SIZE_16M 0x4 +#define SDRAM_BNK_SIZE_32M 0x5 +#define SDRAM_BNK_SIZE_64M 0x6 +#define SDRAM_BNK_SIZE_128M 0x7 +#define SDRAM_BNK_SIZE_256M 0x8 + +/* ------------------------------------------------------------------------------- + * AHB2APB Bridge definitions + * ------------------------------------------------------------------------------- + */ + +#define ADP_AG101_APB_BASE 0x90500000 + +#define APB_SLAVE0_REG 0x0 +#define APB_SLAVE1_REG 0x4 +#define APB_SLAVE2_REG 0x8 +#define APB_SLAVE3_REG 0xc +#define APB_SLAVE4_REG 0x10 +#define APB_SLAVE5_REG 0x14 +#define APB_SLAVE6_REG 0x18 +#define APB_SLAVE7_REG 0x1c +#define APB_SLAVE8_REG 0x20 +#define APB_SLAVE9_REG 0x24 +#define APB_SLAVE10_REG 0x28 +#define APB_SLAVE11_REG 0x2c +#define APB_SLAVE12_REG 0x30 +#define APB_SLAVE13_REG 0x34 +#define APB_SLAVE14_REG 0x38 +#define APB_SLAVE15_REG 0x3c +#define APB_SLAVE16_REG 0x40 +#define APB_SLAVE17_REG 0x44 +#define APB_SLAVE18_REG 0x48 +#define APB_SLAVE19_REG 0x4c + +#define APB_DMA_SRC_A 0x80 +#define APB_DMA_DEST_A 0x84 +#define APB_DMA_CYCLE_A 0x88 +#define APB_DMA_CMD_A 0x8c +#define APB_DMA_SRC_B 0x90 +#define APB_DMA_DEST_B 0x94 +#define APB_DMA_CYCLE_B 0x98 +#define APB_DMA_CMD_B 0x9c +#define APB_DMA_SRC_C 0xa0 +#define APB_DMA_DEST_C 0xa4 +#define APB_DMA_CYCLE_C 0xa8 +#define APB_DMA_CMD_C 0xac +#define APB_DMA_SRC_D 0xb0 +#define APB_DMA_DEST_D 0xb4 +#define APB_DMA_CYCLE_D 0xb8 +#define APB_DMA_CMD_D 0xbc + + +/* ------------------------------------------------------------------------------- + * APB Device definitions + * ------------------------------------------------------------------------------- + */ + +/* ------------------------------------------------------------------------------- + * Timer definitions + * ------------------------------------------------------------------------------- + */ + +#define TIMER1_COUNT 0x0 +#define TIMER1_LOAD 0x4 +#define TIMER1_MATCH1 0x8 +#define TIMER1_MATCH2 0xC +#define TIMER2_COUNT 0x10 +#define TIMER2_LOAD 0x14 +#define TIMER2_MATCH1 0x18 +#define TIMER2_MATCH2 0x1C +#define TIMER3_COUNT 0x20 +#define TIMER3_LOAD 0x24 +#define TIMER3_MATCH1 0x28 +#define TIMER3_MATCH2 0x2C +#define TIMER_CR 0x30 + +#define PCLK 0 +#define EXTCLK 1 + +/* ------------------------------------------------------------------------------- + * GPIO definitions + * ------------------------------------------------------------------------------- + */ + +#define GPIO_DOUT_OFFSET 0x0 +#define GPIO_DIN_OFFSET 0X4 +#define GPIO_PINOUT_OFFSET 0x8 +#define GPIO_PIN_BYPASS 0XC +#define GPIO_DATASET 0X10 +#define GPIO_DATACLR 0X14 +#define GPIO_INT_ENABLE 0X20 +#define GPIO_INT_SOURCE 0X24 +#define GPIO_INT_STATUS 0X28 +#define GPIO_INT_CLEAR 0X2C +#define GPIO_INT_MODE 0X30 +#define GPIO_INT_BOUNCEENABLE 0X3C +#define GPIO_INT_PRESCALE 0X40 + +#define GPIO_NUM 32 +#define GPIO_EDGE 0 +#define GPIO_LEVEL 1 +#define SINGLE 0 +#define BOTH 1 + +/* ------------------------------------------------------------------------------- + * LED definitions + * ------------------------------------------------------------------------------- + */ + +#define LED_ON 0 +#define LED_OFF 1 +#define NUM_OF_LEDS 16 +#define DBG_LEDS (ADP_AG101_GPIO_BASE + GPIO_DOUT_OFFSET) +#define LED_BASE DBG_LEDS + + +/* ------------------------------------------------------------------------------- + * Keyboard Mouse Interface (KMI) definitions + * ------------------------------------------------------------------------------- + */ + +#define MOUSE_ENABLE 0xF4 + +#define KEYPAD_INT 0x04 +#define KEYBOARD_TXINT 0x02 +#define KEYBOARD_RXINT 0x01 + +#define CLR_KEYPAD_INT 0x400 +#define CLR_KEYBOARD_TXINT 0x40 +#define CLR_KEYBOARD_RXINT 0x80 + + +/* ------------------------------------------------------------------------------- + * Interrupt Controllers + * ------------------------------------------------------------------------------- + */ + + +#define IRQ_SOURCE 0 +#define IRQ_MASK 0x04 +#define IRQ_CLEAR 0x08 +#define IRQ_MODE 0x0c +#define IRQ_LEVEL 0x10 +#define IRQ_STATUS 0x14 + +#define FIQ_SOURCE 0x20 +#define FIQ_MASK 0x24 +#define FIQ_CLEAR 0x28 +#define FIQ_MODE 0x2c +#define FIQ_LEVEL 0x30 +#define FIQ_STATUS 0x34 + + +/* ADP_AG101 IRQ numbers definition */ + + +#define EXT_IRQ7 25 +#define EXT_IRQ6 24 +#define EXT_IRQ5 23 +#define EXT_IRQ4 22 +#define EXT_IRQ3 21 +#define EXT_IRQ2 20 +#define EXT_IRQ1 19 +//#define EXT_IRQ0 18 +#define IRQ_EXT 18 //old define + +#define IRQ_RTCALARM 17 +#define IRQ_WATCHDOG 16 +#define IRQ_TIMER3 15 +#define IRQ_TIMER2 14 +#define IRQ_GPIO 13 +#define IRQ_SMMC 12 + +//#define IRQ_UART2 26 //new define +#define IRQ_UART2 11 //old define +//#define IRQ_RESERVE 11 //new define + +#define IRQ_UART1 10 +#define IRQ_MOUSE 9 +#define IRQ_SSP2 8 +#define IRQ_AC97 7 +#define IRQ_I2S 6 +#define IRQ_SDC 5 +#define IRQ_KBD 4 +#define IRQ_I2C 3 +#define IRQ_SSP1 2 +#define IRQ_CFC_DMA 1 +#define IRQ_CFC_CD 0 + + +/* ADP_AG101 FIQ number definition */ + +#define FIQ_OFFSET 32 + +#define EXT_FIQ8 (8+FIQ_OFFSET) +#define EXT_FIQ7 (7+FIQ_OFFSET) +#define EXT_FIQ6 (6+FIQ_OFFSET) +#define EXT_FIQ5 (5+FIQ_OFFSET) + +//#define FIQ_IRDA2 (9+FIQ_OFFSET) //New define +#define FIQ_IRDA2 (5+FIQ_OFFSET) //old define + +#define FIQ_IRDA1 (4+FIQ_OFFSET) +#define FIQ_DMA (3+FIQ_OFFSET) +#define FIQ_LCD (2+FIQ_OFFSET) +#define FIQ_TIMER1 (1+FIQ_OFFSET) +#define FIQ_RTCSEC (0+FIQ_OFFSET) + + +/* Interrupt bit positions */ + +#define MAXIRQNUM 31//18 +#define MAXFIQNUM 31//4 +#define NR_IRQS (MAXIRQNUM + 1) +#define NR_FIQS (MAXFIQNUM + 1) + +#define LEVEL 0 +#define EDGE 1 + +#define H_ACTIVE 0 +#define L_ACTIVE 1 + + +/* -------------------------------------------------------------------------- + * SSP Controllers + * -------------------------------------------------------------------------- + */ + + +#define I2S_RX_FIFO_OVER_RUN_INT (0x1) +#define I2S_TX_FIFO_UNDER_RUN_INT (0x2) +#define I2S_RX_FIFO_THRSD_INT (0x4) +#define I2S_TX_FIFO_THRSD_INT (0x8) + +#define I2S_RX_DMA_ENABLE (0x10) +#define I2S_TX_DMA_ENABLE (0x20) + +#define I2S_FSDIST_00 (0x0) +#define I2S_FSDIST_01 (0x1 << 8) +#define I2S_FSDIST_10 (0x2 << 8) +#define I2S_FSDIST_11 (0x3 << 8) + +#define SSP_CONTROL0 0x0 +#define SSP_CONTROL1 0x4 +#define SSP_CONTROL2 0x8 +#define SSP_STATUS 0xC +#define SSP_INT_CONTROL 0X10 +#define SSP_INT_STATUS 0x14 +#define SSP_DATA 0x18 + +/* Control register 0 */ + +#define SSP_FFMT_TI 0x0 +#define SSP_FFMT_MOTOR 0x1 +#define SSP_FFMT_NS 0x2 +#define SSP_FFMT_PHILP 0x3 +#define SSP_FFMT_INTEL 0x4 + +#define SSP_FSDIST 0x1 +#define SSP_LBM 0x1 /* loopback mode */ +#define SSP_LSB 0x1 /* LSB first */ +#define SSP_FSPO_LOW 0x1 /* Frame sync atcive low */ +#define SSP_DATAPAD 0x1 /* data padding in front of serial data */ + +#define SSP_OPM_MSST 0x3 /* Master stereo mode */ +#define SSP_OPM_MSMO 0x2 /* Master mono mode */ +#define SSP_OPM_SLST 0x1 /* Slave stereo mode */ +#define SSP_OPM_SLMO 0x0 /* Slave mono mode */ + +#define SSP_SCLKPO_HIGH 0x1 /* SCLK Remain HIGH */ +#define SSP_SCLKPO_LOW 0x0 /* SCLK Remain LOW */ +#define SSP_SCLKPH_HALFCLK 0x1 /* Half CLK cycle */ +#define SSP_SCLKPH_ONECLK 0x0 /* One CLK cycle */ + + +/* Control Register 1 */ + +#define SSP_PDL 0x00000000 /* paddinf data length */ +#define SSP_SDL 0x7 /* Serial data length(actual data length-1) */ +#define SSP_CLKDIV 0xf /* clk divider */ + +/* Control Register 2 */ + +#define SSP_ACCRST 0x1 /* AC-Link Cold Reset Enable */ +#define SSP_ACWRST 0x1 /* AC-Link Warm Reset Enable */ +#define SSP_TXFCLR 0x1 /* TX FIFO Clear */ +#define SSP_RXFCLR 0x1 /* RX FIFO Clear */ +#define SSP_TXDOE 0x1 /* TX Data Output Enable */ +#define SSP_SSPEN 0x1 /* SSP Enable */ + +/* Status register + */ +#define SSP_TFVE 0x1f000 /* Tx FIFO Valid Entries */ +#define SSP_RFVE 0x1f0 /* Rx FIFO Valid Entries */ + +#define SSP_BUSY 0x4 /* Busy for recv or tx */ +#define SSP_TFNF 0x2 /* TX FIFO Not Full */ +#define SSP_RFF 0x1 /* RX FIFO Full */ + + +/* Interrupr Control register */ +#define SSP_TXDMAEN 0x20 /* TX DMA Enable */ +#define SSP_RXDMAEN 0x10 /* RX DMA Enable */ +#define SSP_TFIEN 0x8 /* TX FIFO Int Enable */ +#define SSP_RFIEN 0x4 /* RX FIFO Int Enable */ +#define SSP_TFURIEN 0x2 /* TX FIFO Underrun int enable */ +#define SSP_RFURIEN 0x1 /* RX FIFO Underrun int enable */ + +/* Interrupt Status register */ +#define SSP_TFTHI 0x8 /* TX FIFO Threshold Interrupt */ +#define SSP_RFTHI 0x4 /* RX FIFO Threshold Interrupt */ +#define TFURI 0x2 /* TX FIFO Underrun interrupt */ +#define RFURI 0x1 /* RX FIFO Underrun interrupt */ + +#define MAX_SSP 0x4 /* ssp device number(include AC97 and I2S) */ + + +/* ------------------------------------------------------------------------------- + * I2C Controllers + * ------------------------------------------------------------------------------- + */ + + +/* I2C Control register */ + + +#define I2C_ALIEN 0x2000 /* Arbitration lose */ +#define I2C_SAMIEN 0x1000 /* slave address match */ +#define I2C_STOPIEN 0x800 /* stop condition */ +#define I2C_BERRIEN 0x400 /* non ACK response */ +#define I2C_DRIEN 0x200 /* data receive */ +#define I2C_DTIEN 0x100 /* data transmit */ +#define I2C_TBEN 0x80 /* transfer byte enable */ +#define I2C_ACKNAK 0x40 /* ack sent */ +#define I2C_STOP 0x20 /* stop */ +#define I2C_START 0x10 /* start */ +#define I2C_GCEN 0x8 /* general call */ +#define I2C_SCLEN 0x4 /* enable clock */ +#define I2C_I2CEN 0x2 /* enable I2C */ +#define I2C_I2CRST 0x1 /* reset I2C */ +#define I2C_ENABLE (I2C_ALIEN|I2C_SAMIEN|I2C_STOPIEN|I2C_BERRIEN|I2C_DRIEN|I2C_DTIEN|I2C_SCLEN|I2C_I2CEN) + + +/* I2C Status Register */ + +#define I2C_CLRAL 0x400 +#define I2C_CLRGC 0x200 +#define I2C_CLRSAM 0x100 +#define I2C_CLRSTOP 0x80 +#define I2C_CLRBERR 0x40 +#define I2C_DR 0x20 +#define I2C_DT 0x10 +#define I2C_BB 0x8 +#define I2C_BUSY 0x4 +#define I2C_ACK 0x2 +#define I2C_RW 0x1 + + +/* I2C clock divided register */ + +#define I2C_CLKCOUNT 0x3ff + + +/* I2C slave address register */ + +#define I2C_EN10 0x80000000 /* 10-bit address slave mode */ +#define I2C_SARMSB 0x380 /* mask for SAR msb when EN10=1 */ +#define I2C_SARLSB 0x7f /* mask for SAR lsb */ + +/* Bus Monitor Register */ + +#define I2C_SCL 0x2 +#define I2C_SDA 0x1 + +/* ------------------------------------------------------------------------------- + * DMA Controllers + * ------------------------------------------------------------------------------- + */ + +#define ADP_AG101_DMA_BASE 0x90400000 + + /* registers */ +#define DMA_INT 0x0 +#define DMA_INT_TC 0x4 +#define DMA_INT_TC_CLR 0x8 +#define DMA_INT_ERR 0xC +#define DMA_INT_ERR_CLR 0x10 +#define DMA_TC 0x14 +#define DMA_ERR 0x18 +#define DMA_CH_EN 0x1C +#define DMA_CH_BUSY 0x20 +#define DMA_CSR 0x24 +#define DMA_SYNC 0x28 + +#define DMA_C0_DevRegBase 0x40 +#define DMA_C0_DevDtBase 0x80 + +#define DMA_CH_CFG_REG_OFFSET 0x20 +#define DMA_C0_CSR 0x100 +#define DMA_C0_CFG 0x104 +#define DMA_C0_SrcAddr 0x108 +#define DMA_C0_DstAddr 0x10C +#define DMA_C0_LLP 0x110 +#define DMA_C0_SIZE 0x114 + +/* bit mapping of main configuration status register(CSR) */ +#define DMA_CSR_M1ENDIAN 0x00000004 +#define DMA_CSR_M0ENDIAN 0x00000002 +#define DMA_CSR_DMACEN 0x00000001 + +/* bit mapping of channel control register */ +#define DMA_CSR_TC_MSK 0x80000000 +#define DMA_CSR_CHPRJ_HIGHEST 0x00C00000 +#define DMA_CSR_CHPRJ_2ND 0x00800000 +#define DMA_CSR_CHPRJ_3RD 0x00400000 +#define DMA_CSR_PRTO3 0x00200000 +#define DMA_CSR_PRTO2 0x00100000 +#define DMA_CSR_PRTO1 0x00080000 +#define DMA_CSR_SRC_BURST_SIZE_1 0x00000000 +#define DMA_CSR_SRC_BURST_SIZE_4 0x00010000 +#define DMA_CSR_SRC_BURST_SIZE_8 0x00020000 +#define DMA_CSR_SRC_BURST_SIZE_16 0x00030000 +#define DMA_CSR_SRC_BURST_SIZE_32 0x00040000 +#define DMA_CSR_SRC_BURST_SIZE_64 0x00050000 +#define DMA_CSR_SRC_BURST_SIZE_128 0x00060000 +#define DMA_CSR_SRC_BURST_SIZE_256 0x00070000 + +#define DMA_CSR_ABT 0x00008000 +#define DMA_CSR_SRC_WIDTH_8 0x00000000 +#define DMA_CSR_SRC_WIDTH_16 0x00000800 +#define DMA_CSR_SRC_WIDTH_32 0x00001000 + +#define DMA_CSR_DST_WIDTH_8 0x00000000 +#define DMA_CSR_DST_WIDTH_16 0x00000100 +#define DMA_CSR_DST_WIDTH_32 0x00000200 + +#define DMA_CSR_MODE_NORMAL 0x00000000 +#define DMA_CSR_MODE_HANDSHAKE 0x00000080 + +#define DMA_CSR_SRC_INCREMENT 0x00000000 +#define DMA_CSR_SRC_DECREMENT 0x00000020 +#define DMA_CSR_SRC_FIX 0x00000040 + +#define DMA_CSR_DST_INCREMENT 0x00000000 +#define DMA_CSR_DST_DECREMENT 0x00000008 +#define DMA_CSR_DST_FIX 0x00000010 + +#define DMA_CSR_SRC_SEL 0x00000004 +#define DMA_CSR_DST_SEL 0x00000002 +#define DMA_CSR_CH_ENABLE 0x00000001 + + +#define DMA_MAX_SIZE 0x10000 + + +/* ----------------------------------------------------------------------- + * STMC Controllers + * ----------------------------------------------------------------------- + */ + +#define STMC_BANK_WRITE_PROTECT (0x1 << 11) // bit 11 + +#define STMC_BANK_TYPE1_ASYNC (0x0) // bit 10 +#define STMC_BANK_TYPE1_SYNC (0x1 << 10) // bit 10 + +#define STMC_BANK_TYPE2_ASYNC (0x0) // bit 9 +#define STMC_BANK_TYPE2_BURST_ROM (0x1 << 9) // bit 9 +#define STMC_BANK_TYPE2_NON_PIPE (0x0) // bit 9 +#define STMC_BANK_TYPE2_PIPE (0x1 << 9) // bit 9 + +#define STMC_BANK_TYPE3_LATE_WRITE_D (0x0) // bit 8 +#define STMC_BANK_TYPE3_LATE_WRITE_E (0x1 << 8) // bit 8 + +#define STMC_BANK_TM_AST0 (0x0) +#define STMC_BANK_TM_AST1 (0x01 << 18) // bit 18-19 +#define STMC_BANK_TM_AST2 (0x02 << 18) // bit 18-19 +#define STMC_BANK_TM_AST3 (0x03 << 18) // bit 18-19 + +#define STMC_BANK_TM_CTW1 (0x01 << 16) // bit 16-17 +#define STMC_BANK_TM_CTW2 (0x02 << 16) // bit 16-17 +#define STMC_BANK_TM_CTW3 (0x03 << 16) // bit 16-17 + +#define STMC_BANK_TM_AT1_1 (0x01 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_2 (0x02 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_3 (0x03 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_4 (0x04 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_5 (0x05 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_6 (0x06 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_7 (0x07 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_8 (0x08 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_9 (0x09 << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_A (0x0A << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_B (0x0B << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_C (0x0C << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_D (0x0D << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_E (0x0E << 12) // bit 12-15 +#define STMC_BANK_TM_AT1_F (0x0F << 12) // bit 12-15 + +#define STMC_BANK_TM_AT2_1 (0x01 << 8) // bit 9-8 +#define STMC_BANK_TM_AT2_2 (0x02 << 8) // bit 9-8 +#define STMC_BANK_TM_AT2_3 (0x03 << 8) // bit 9-8 + +#define STMC_BANK_TM_WTC1 (0x01 << 6) // bit 7-6 +#define STMC_BANK_TM_WTC2 (0x02 << 6) // bit 7-6 +#define STMC_BANK_TM_WTC3 (0x03 << 6) // bit 7-6 + +#define STMC_BANK_TM_AHT1 (0x01 << 4) // bit 5-4 +#define STMC_BANK_TM_AHT2 (0x02 << 4) // bit 5-4 +#define STMC_BANK_TM_AHT3 (0x03 << 4) // bit 5-4 + +#define STMC_BANK_TM_TRNA_1 (0x01) // bit 3-0 +#define STMC_BANK_TM_TRNA_2 (0x02) // bit 3-0 +#define STMC_BANK_TM_TRNA_3 (0x03) // bit 3-0 +#define STMC_BANK_TM_TRNA_4 (0x04) // bit 3-0 +#define STMC_BANK_TM_TRNA_5 (0x05) // bit 3-0 +#define STMC_BANK_TM_TRNA_6 (0x06) // bit 3-0 +#define STMC_BANK_TM_TRNA_7 (0x07) // bit 3-0 +#define STMC_BANK_TM_TRNA_8 (0x08) // bit 3-0 +#define STMC_BANK_TM_TRNA_9 (0x09) // bit 3-0 +#define STMC_BANK_TM_TRNA_A (0x0A) // bit 3-0 +#define STMC_BANK_TM_TRNA_B (0x0B) // bit 3-0 +#define STMC_BANK_TM_TRNA_C (0x0C) // bit 3-0 +#define STMC_BANK_TM_TRNA_D (0x0D) // bit 3-0 +#define STMC_BANK_TM_TRNA_E (0x0E) // bit 3-0 +#define STMC_BANK_TM_TRNA_F (0x0F) // bit 3-0 + +/* END */ + +#endif diff --git a/board/AndesTech/include/flib_flash.h b/board/AndesTech/include/flib_flash.h new file mode 100644 index 0000000..5a1b206 --- /dev/null +++ b/board/AndesTech/include/flib_flash.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*************************************************************************** +* Copyright Faraday Technology Corp 2002-2003. All rights reserved. * +*--------------------------------------------------------------------------* +* Name:symbol.h * +* Description: Faraday code library define * +* Author: Fred Chien * +* Date: 2002/03/01 * +* Version:1.0 * +*--------------------------------------------------------------------------* +***************************************************************************/ + +#ifndef __ADP_AG101_FLASH_H +#define __ADP_AG101_FLASH_H + +/* + * macronix flash + */ +#define MX_MANUFACT 0x00c20000 // macronix's manufacture id + +/* + * device id + */ +#define MX_ID_29LV008T 0x3e +#define MX_ID_29LV008B 0x37 +#define MX_ID_26F128J3T 0x89 + +/* + * SST flash + */ +#define SST_MANUFACT 0x00bf0000 // SST's manufacture id + +/* + * device id + */ +#define SST_ID_39VF080 0xd8 +#define SST_ID_39VF016 0xd9 + +/* + * Intel flash + */ +#define INTEL_MANUFACT 0x00890000 +#define INTEL_ID_E28F128 0x18 + +#define INTEL_E28F128_SIZE (0x1000000) +#define INTEL_E28F128_SEC_SIZE (0x20000) + +#define FLASH_SINGLE (0x00) +#define FLASH_DOUBLE (0x01) +#define FLASH_FOUR (0x02) + +#define MX_Type (0x01) +#define SST_Type (0x02) +#define Intel_Type (0x03) + +#define PROGRAM_OK (1) +#define PROGRAM_NOT_OK (-2) +#define FLASH_PROGRAM_DELAY_CYCLE (50) +#define FLASH_PROGRAM_LOOP_COUNTER (100) + +#endif diff --git a/board/AndesTech/include/ftmac100.h b/board/AndesTech/include/ftmac100.h new file mode 100644 index 0000000..9b6efc9 --- /dev/null +++ b/board/AndesTech/include/ftmac100.h @@ -0,0 +1,257 @@ +// -------------------------------------------------------------------- +// lmc83: modified from smc91111.h (2002-11-29) +// -------------------------------------------------------------------- + +#ifndef FTMAC100_H +#define FTMAC100_H + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; + +// -------------------------------------------------------------------- +// structure for andesboot +// -------------------------------------------------------------------- + +#define ANDESBOOT +#ifdef ANDESBOOT + + #define MAX_ADDR_LEN 6 + #define IFNAMSIZ 16 + #define printk printf + #define mdelay udelay + #define spin_lock_irq + #define min(a, b) (((a) < (b)) ? (a) : (b)) + #define kmalloc(a, b) malloc(a) + #define BUG() printf("faultal error\n"); for (;;) + #define virt_to_phys(a) (unsigned int)(a) + + struct net_device + { + void *priv; + unsigned long base_addr; + int irq; + unsigned char dev_addr[MAX_ADDR_LEN]; /* hw address */ + char name[IFNAMSIZ]; + + }; + + struct net_device_stats + { + unsigned long multicast; + }; + + typedef int spinlock_t; + +#endif + +// -------------------------------------------------------------------- +// FTMAC100 hardware related defenition +// -------------------------------------------------------------------- +#ifdef CONFIG_ADP_AG101_110_PLATFORM +#define NDS32_COMMON_FTMAC100_BASE 0x96700000 +#else +#ifdef CONFIG_ADP_AG101_120_PLATFORM +#define NDS32_COMMON_FTMAC100_BASE 0x90900000 +#endif +#endif + + +#define ISR_REG 0x00 // interrups status register +#define IMR_REG 0x04 // interrupt maks register +#define MAC_MADR_REG 0x08 // MAC address (Most significant) +#define MAC_LADR_REG 0x0c // MAC address (Least significant) + +#define MAHT0_REG 0x10 // Multicast Address Hash Table 0 register +#define MAHT1_REG 0x14 // Multicast Address Hash Table 1 register +#define TXPD_REG 0x18 // Transmit Poll Demand register +#define RXPD_REG 0x1c // Receive Poll Demand register +#define TXR_BADR_REG 0x20 // Transmit Ring Base Address register +#define RXR_BADR_REG 0x24 // Receive Ring Base Address register +#define ITC_REG 0x28 // interrupt timer control register +#define APTC_REG 0x2c // Automatic Polling Timer control register +#define DBLAC_REG 0x30 // DMA Burst Length and Arbitration control register + + + +#define MACCR_REG 0x88 // MAC control register +#define MACSR_REG 0x8c // MAC status register +#define PHYCR_REG 0x90 // PHY control register +#define PHYWDATA_REG 0x94 // PHY Write Data register +#define FCR_REG 0x98 // Flow Control register +#define BPR_REG 0x9c // back pressure register +#define WOLCR_REG 0xa0 // Wake-On-Lan control register +#define WOLSR_REG 0xa4 // Wake-On-Lan status register +#define WFCRC_REG 0xa8 // Wake-up Frame CRC register +#define WFBM1_REG 0xb0 // wake-up frame byte mask 1st double word register +#define WFBM2_REG 0xb4 // wake-up frame byte mask 2nd double word register +#define WFBM3_REG 0xb8 // wake-up frame byte mask 3rd double word register +#define WFBM4_REG 0xbc // wake-up frame byte mask 4th double word register +#define TM_REG 0xcc // test mode register + + + +// -------------------------------------------------------------------- +// ISR_REG and IMR_REG related +// -------------------------------------------------------------------- +#define PHYSTS_CHG_bit (1UL<<9) +#define AHB_ERR_bit (1UL<<8) +#define RPKT_LOST_bit (1UL<<7) +#define RPKT_SAV_bit (1UL<<6) +#define XPKT_LOST_bit (1UL<<5) +#define XPKT_OK_bit (1UL<<4) +#define NOTXBUF_bit (1UL<<3) +#define XPKT_FINISH_bit (1UL<<2) +#define NORXBUF_bit (1UL<<1) +#define RPKT_FINISH_bit (1UL<<0) + + +// -------------------------------------------------------------------- +// APTC_REG related +// -------------------------------------------------------------------- +typedef struct +{ + u32 RXPOLL_CNT:4; + u32 RXPOLL_TIME_SEL:1; + u32 Reserved1:3; + u32 TXPOLL_CNT:4; + u32 TXPOLL_TIME_SEL:1; + u32 Reserved2:19; +}FTMAC100_APTCR_Status; + + +// -------------------------------------------------------------------- +// MACCR_REG related +// -------------------------------------------------------------------- +#define RX_BROADPKT_bit (1UL<<17) // Receiving broadcast packet +#define RX_MULTIPKT_bit (1UL<<16) // receiving multicast packet +#define FULLDUP_bit (1UL<<15) // full duplex +#define CRC_APD_bit (1UL<<14) // append crc to transmit packet +#define MDC_SEL_bit (1UL<<13) // set MDC as TX_CK/10 +#define RCV_ALL_bit (1UL<<12) // not check incoming packet's destination address +#define RX_FTL_bit (1UL<<11) // Store incoming packet even its length is great than 1518 byte +#define RX_RUNT_bit (1UL<<10) // Store incoming packet even its length is les than 64 byte +#define HT_MULTI_EN_bit (1UL<<9) +#define RCV_EN_bit (1UL<<8) // receiver enable +#define XMT_EN_bit (1UL<<5) // transmitter enable +#define CRC_DIS_bit (1UL<<4) +#define LOOP_EN_bit (1UL<<3) // Internal loop-back +#define SW_RST_bit (1UL<<2) // software reset/ +#define RDMA_EN_bit (1UL<<1) // enable DMA receiving channel +#define XDMA_EN_bit (1UL<<0) // enable DMA transmitting channel + + +// -------------------------------------------------------------------- +// Receive Ring descriptor structure +// -------------------------------------------------------------------- +typedef struct +{ + // RXDES0 + u32 ReceiveFrameLength:11; //0~10 + u32 Reserved1:5; //11~15 + u32 MULTICAST:1; //16 + u32 BROARDCAST:1; //17 + u32 RX_ERR:1; //18 + u32 CRC_ERR:1; //19 + u32 FTL:1; + u32 RUNT:1; + u32 RX_ODD_NB:1; + u32 Reserved2:5; + u32 LRS:1; + u32 FRS:1; + u32 Reserved3:1; + u32 RXDMA_OWN:1; // 1 ==> owned by FTMAC100, 0 ==> owned by software + + // RXDES1 + u32 RXBUF_Size:11; + u32 Reserved:20; + u32 EDOTR:1; + + // RXDES2 + u32 RXBUF_BADR; + + u32 VIR_RXBUF_BADR; // not defined, we use it for maintaining the virtual address of receiving buffer + +} RX_DESC; + + +typedef struct +{ + // TXDES0 + u32 TXPKT_LATECOL:1; + u32 TXPKT_EXSCOL:1; + u32 Reserved1:29; + u32 TXDMA_OWN:1; + + // TXDES1 + u32 TXBUF_Size:11; + u32 Reserved2:16; + u32 LTS:1; + u32 FTS:1; + u32 TX2FIC:1; + u32 TXIC:1; + u32 EDOTR:1; + + // RXDES2 + u32 TXBUF_BADR; + + u32 VIR_TXBUF_BADR; // Reserved, we use it for maintaining the virtual address of receiving buffer + +} TX_DESC; + + +// waiting to do: +#define TXPOLL_CNT 8 +#define RXPOLL_CNT 0 + +#define OWNBY_SOFTWARE 0 +#define OWNBY_FTMAC100 1 + +// -------------------------------------------------------------------- +// driver related definition +// -------------------------------------------------------------------- +#define RXDES_NUM 64 // we defined 32 descriptors for receiving packets +#define RX_BUF_SIZE 128 // each receiving buffer is 512 bytes +#define TXDES_NUM 8 +#define TX_BUF_SIZE 2048 + + +/* store this information for the driver.. */ +struct ftmac100_local { + + // these are things that the kernel wants me to keep, so users + // can find out semi-useless statistics of how well the card is + // performing + struct net_device_stats stats; + + // Set to true during the auto-negotiation sequence + int autoneg_active; + + // Address of our PHY port + u32 phyaddr; + + // Type of PHY + u32 phytype; + + // Last contents of PHY Register 18 + u32 lastPhy18; + + spinlock_t lock; + volatile RX_DESC *rx_descs; // receive ring base address + u32 rx_descs_dma; // receive ring physical base address + char *rx_buf; // receive buffer cpu address + int rx_buf_dma; // receive buffer physical address + int rx_idx; // current receive descriptor + + volatile TX_DESC *tx_descs; + u32 tx_descs_dma; + char *tx_buf; + int tx_buf_dma; + int tx_idx; + + int maccr_val; +}; + +#define FTMAC100_STROBE_TIME (20*HZ) + +#endif /* FTMAC100_H */ diff --git a/board/AndesTech/include/ftpci100.h b/board/AndesTech/include/ftpci100.h new file mode 100644 index 0000000..ee98791 --- /dev/null +++ b/board/AndesTech/include/ftpci100.h @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PCI_H__ +#define __PCI_H__ 1 + +#include <porting.h> +#include <pci.h> + +/* Condition Definition */ +#define DEBUG_INFO_ENABLE 0x00 +//#define USE_IDSELECT_1234 0x00 + +/* Slot Definition */ +#ifdef USE_IDSELECT_1234 + #define SLOT_1 0x01 + #define SLOT_2 0x02 + #define SLOT_3 0x03 + #define SLOT_4 0x04 +#else + #define SLOT_1 0x08 + #define SLOT_2 0x09 + #define SLOT_3 0x0A + #define SLOT_4 0x0B +#endif + + +#define PCI_BASE_CLASS_MASS_STORAGE 1 +#define PCI_BASE_CLASS_NETWORK 2 +#define PCI_BASE_CLASS_DISPLAY 3 +#define PCI_BASE_CLASS_MULTIMEDIA 4 +#define PCI_BASE_CLASS_MEMORY 5 +#define PCI_BASE_CLASS_BRIDGE 6 +#define PCI_BASE_CLASS_SIMPLE_COMMUNICATION 7 +#define PCI_BASE_CLASS_BASE_SYS_PERIPHERAL 8 +#define PCI_BASE_CLASS_INPUT 9 +#define PCI_BASE_CLASS_DOCK_STATION 10 +#define PCI_BASE_CLASS_PROCESSOR 11 +#define PCI_BASE_CLASS_SERIAL 12 + +/* 7.Alignment Constants */ +#define PCI_MEM_SPACE_ALIGNMENT 0x10 +#define PCI_IO_SPACE_ALIGNMENT 0x4 + + + +/* + * PCI Configuration Space Structures + */ +typedef struct +{ + /* offset 0x00 */ + UINT32 VendorID:16; + UINT32 DeviceID:16; + /* offset 0x04 */ + UINT32 Command:16; + UINT32 Status:16; + /* offset 0x08 */ + UINT32 RevisionID:8; + UINT32 ClassCode:24; + /* offset 0x0c */ + UINT32 CacheLineSize:8; + UINT32 LatencyTimer:8; + UINT32 HeaderType:8; + UINT32 BIST:8; + /* offset 0x10 - 0x24*/ + UINT32 BaseAddrReg[6]; + /* offset 0x28 */ + UINT32 CardbusCISPointer; + /* offset 0x2c */ + UINT32 SubsystemVendorID:16; + UINT32 SubsystemID:16; + /* offset 0x30 */ + UINT32 ExpansionROMBaseAddr; + /* offset 0x34-0x38 */ + UINT32 Reserved[2]; + /* offset 0x3c */ + UINT32 IntLine:8; + UINT32 IntPin:8; + UINT32 MinGnt:8; + UINT32 MaxLat:8; +} PCIConfigSpaceStruct; + + + +/* + * u-boot header info for the Faraday FTPCI100 AHB-PCI Bridge. + * + * History: + * 2009.04.13 Init - Hill + */ + +#define PCI_DEBUG_INFO 0 + +#if PCI_DEBUG_INFO +#define print_pci(format, arg...) printf("PCI DBG INFO: \r\n " format "\n", ## arg) +#else +#define print_pci(format, arg...) do {} while (0) +#endif + +//ivan modified +#define ADP_AG101_PCI_IO_BASE 0x90c00000 // ~1MB +#define ADP_AG101_PCI_MEM_BASE 0xa0000000 // ~256MB + +#define PCI_CARD_IO_BASE (ADP_AG101_PCI_IO_BASE+0x1000)//0x90c00100 +#define PCI_CARD_MEM_BASE ADP_AG101_PCI_MEM_BASE// ADP_AG101_PCI_MEM_BASE +#define PCI_CARD_MEM_TOTAL_SIZE 0x10000000 + +#define PCI_BRIDGE_REGISTER_IO 0x00 +#define PCI_BRIDGE_REGISTER_AHB_PROTECTION 0x04 +#define PCI_BRIDGE_REGISTER_PCI_CONTROL_REGISTER 0x08 +#define PCI_BRIDGE_REGISTER_ERREN 0x0C +#define PCI_BRIDGE_REGISTER_SOFT_RESET 0x10 +#define PCI_BRIDGE_REGISTER_ENABLE_64BIT 0x14 +#define PCI_BRIDGE_REGISTER_HIGHT_32BIT_ABR 0x18 +#define PCI_CONFIG_ADDR_REG 0x28 +#define PCI_CONFIG_DATA_REG 0x2C + +#define PCI_BRIDGE_CFG_SPACE_CONTROL 0x4C +#define PCI_BRIDGE_CFG_INTABCD_STATUS 0x4F +#define PCI_BRIDGE_CFG_INTMASK 0x4E +#define PCI_BRIDGE_CFG_SPACE_MEM1_BA 0x80000050 +#define PCI_BRIDGE_CFG_SPACE_MEM2_BA 0x80000054 +#define PCI_BRIDGE_CFG_SPACE_MEM3_BA 0x80000058 + +#define PCI_ENABLE_INTA_INTB_INTC_INTD 0x03C00000 +#define PCI_ALL_INTs_MASK 0x0FFF0000 +#define PCI_BRIDGE_MAX_INT_NUMBER 0x04 +#define PCI_DMA_MEM_REQUEST_FAIL 0xFFFFFFFF +#define PCI_DMA_DEFAULT_SIZE 0x00 + +/* disable INTs in u-boot */ +#define PCI_INT_USE_ACTIVE_H 0x01 //After 12/01/2002-->Use Active High + +#define PCI_BRIDGE_DMA_START_ADDRESS 0x02000000 //0x05000000 +#define PCI_BRIDGE_DMA_SIZE 0x10 //16M (SIZE) +#define PCI_BRIDGE_DMA_START_SIZE_VALUE 0x02040000 //4=> 16M (SIZE)0x05040000 +#define PCI_BRIDGE_DMA_START_SIZE_256MB 0x02080000 //8=>256M (SIZE)0x05040000 + +#define PCI_INBOUND_MEM_BASE 0 // DRAM Base Address +#define PCI_INBOUND_MEM_1MB (0<<16) +#define PCI_INBOUND_MEM_2MB (1<<16) +#define PCI_INBOUND_MEM_4MB (2<<16) +#define PCI_INBOUND_MEM_8MB (3<<16) +#define PCI_INBOUND_MEM_16MB (4<<16) +#define PCI_INBOUND_MEM_32MB (5<<16) +#define PCI_INBOUND_MEM_64MB (6<<16) +#define PCI_INBOUND_MEM_128MB (7<<16) +#define PCI_INBOUND_MEM_256MB (8<<16) +#define PCI_INBOUND_MEM_512MB (9<<16) +#define PCI_INBOUND_MEM_1GB (0xA<<16) + +/* Configuration Space Header offset*/ +#define PCI_CSH_VENDOR_ID_REG 0x00 +#define PCI_CSH_DEVICE_ID_REG 0x02 +#define PCI_CSH_COMMAND_REG 0x04 +#define PCI_CSH_STATUS_REG 0x06 +#define PCI_CSH_REVISION_CLASS_REG 0x08 +#define PCI_CSH_CACHE_LINE_SIZE_REG 0x0C +#define PCI_CSH_LATENCY_TIMER_REG 0x0D +#define PCI_CSH_HEADER_TYPE_REG 0x0E +#define PCI_CSH_BIST_REG 0x0F +#define PCI_CSH_BASE_ADDR_REG 0x10 + +#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 + +/* PCI command status register bit mapping */ +#define PCI_CMD_IO_ENABLE 0x00000001 +#define PCI_CMD_MEM_ENABLE 0x00000002 +#define PCI_CMD_BUS_MASTER_ENABLE 0x00000004 + +#define PCI_MAX_DEVICE_TYPE_NUM 0x13 +#define PCI_MAX_BAR_NUM 0x06 +#define PCI_MAX_BUS_NUM 0x03 // 256 +#define PCI_MAX_DEVICE_NUM 0x10 // 32 +#define PCI_MAX_FUNCTION_NUM 0x04 // 8 +#define PCI_MAX_REG_NUM 0x3c + +/* + * PCI Configuration Address Structures + */ + +typedef struct { + UINT32 RegNum:8; + UINT32 FunNum:3; + UINT32 DevNum:5; + UINT32 BusNum:8; + UINT32 Always0:7; + UINT32 Enable:1; +} PCIDeviceIDStruct; + + +typedef struct { + UINT32 PciIOAddr; + UINT32 PciMem0Addr; + UINT32 PciMem1Addr; +} PCIResourceMapStruct; + +typedef struct { + UINT8 *PCI_DMA_Start_Pointer; + UINT32 PCI_DMA_Size_Remain; + UINT32 PCI_DMA_Base_Address; +} PCIBridgeDMAResourceMapStruct; + +/* + * exposed APIs + */ +void pci_init_board(void); + +int flib_read_byte(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned char *pu8Dat); +int flib_read_word(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned short *pu16Dat); +int flib_read_dword(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned long *pu32Dat); +int flib_write_byte(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned char u8Dat); +int flib_write_word(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned short u16Dat); +int flib_write_dword(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned long u32Dat); + +#endif diff --git a/board/AndesTech/include/porting.h b/board/AndesTech/include/porting.h new file mode 100644 index 0000000..c2bd151 --- /dev/null +++ b/board/AndesTech/include/porting.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ADP_AG101_PORTING +#define __ADP_AG101_PORTING + +#include <asm/types.h> +//#include <adp-ag101.h> +#include "chipset.h" +#include "symbol.h" + +/* + * "1 word" in armboot ==> 2 bytes + * "1 word" in nds32 architecture ==> 4 bytes, + * When we should take care the follows when we port code to armboot + * inw" (nds32) should be replaced by "inl"; + * "outw" (nds32) should be replaced by "outl" + */ + +#ifndef u32 + #define u32 unsigned long +#endif + +#ifndef u16 + #define u16 unsigned short +#endif + +#ifndef u8 + #define u8 unsigned char +#endif + +#define cpe_inl(addr) (*((volatile u32 *)(addr))) +#define cpe_inw(addr) (*((volatile u16 *)(addr))) +#define cpe_inb(addr) (*((volatile u8 *)(addr))) +#define cpe_outl(addr, value) (*((volatile u32 *)(addr)) = value) +#define cpe_outw(addr, value) (*((volatile u16 *)(addr)) = value) +#define cpe_outb(addr, value) (*((volatile u8 *)(addr)) = value) + +#endif diff --git a/board/AndesTech/include/serial.h b/board/AndesTech/include/serial.h new file mode 100644 index 0000000..5382c1b --- /dev/null +++ b/board/AndesTech/include/serial.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ADP_AG101_SERIAL_H +#define __ADP_AG101_SERIAL_H + +/* + * define UART clock + */ +//#define UART_CLOCK 22118400 //22.118400 MHZ ASIC version +//#define UART_CLOCK 18432000 //ASIC320, comes from faraday.h +#define UART_CLOCK (18432000 * 20) / 25 // comes from andes.h (now merged into configs/ag101.h) +//#define UART_CLOCK CONFIG_SYS_CLK_FREQ/2 // CONFIG_SYS_CLK_FREQ/2 FPGA version + +/* + * UART definitions + */ +#define SERIAL_THR 0x00 /* Transmitter Holding Register(Write).*/ +#define SERIAL_RBR 0x00 /* Receive Buffer register (Read).*/ +#define SERIAL_IER 0x04 /* Interrupt Enable register.*/ +#define SERIAL_IIR 0x08 /* Interrupt Identification register(Read).*/ +#define SERIAL_FCR 0x08 /* FIFO control register(Write).*/ +#define SERIAL_LCR 0x0C /* Line Control register.*/ +#define SERIAL_MCR 0x10 /* Modem Control Register.*/ +#define SERIAL_LSR 0x14 /* Line status register(Read) .*/ +#define SERIAL_MSR 0x18 /* Modem Status register (Read).*/ +#define SERIAL_SPR 0x1C /* Scratch pad register */ +#define SERIAL_DLL 0x0 /* Divisor Register LSB */ +#define SERIAL_DLM 0x4 /* Divisor Register MSB */ +#define SERIAL_PSR 0x8 /* Prescale Divison Factor */ + +#define SERIAL_MDR 0x20 +#define SERIAL_ACR 0x24 +#define SERIAL_TXLENL 0x28 +#define SERIAL_TXLENH 0x2C +#define SERIAL_MRXLENL 0x30 +#define SERIAL_MRXLENH 0x34 +#define SERIAL_PLR 0x38 +#define SERIAL_FMIIR_PIO 0x3C + +/* IER Register */ +#define SERIAL_IER_DR 0x1 /* Data ready Enable */ +#define SERIAL_IER_TE 0x2 /* THR Empty Enable */ +#define SERIAL_IER_RLS 0x4 /* Receive Line Status Enable */ +#define SERIAL_IER_MS 0x8 /* Modem Staus Enable */ + +/* IIR Register */ +#define SERIAL_IIR_NONE 0x1 /* No interrupt pending */ +#define SERIAL_IIR_RLS 0x6 /* Receive Line Status */ +#define SERIAL_IIR_DR 0x4 /* Receive Data Ready */ +#define SERIAL_IIR_TIMEOUT 0xc /* Receive Time Out */ +#define SERIAL_IIR_TE 0x2 /* THR Empty */ +#define SERIAL_IIR_MODEM 0x0 /* Modem Status */ + +/* FCR Register */ +#define SERIAL_FCR_FE 0x1 /* FIFO Enable */ +#define SERIAL_FCR_RXFR 0x2 /* Rx FIFO Reset */ +#define SERIAL_FCR_TXFR 0x4 /* Tx FIFO Reset */ + +/* LCR Register */ +#define SERIAL_LCR_LEN5 0x0 +#define SERIAL_LCR_LEN6 0x1 +#define SERIAL_LCR_LEN7 0x2 +#define SERIAL_LCR_LEN8 0x3 + +#define SERIAL_LCR_STOP 0x4 +#define SERIAL_LCR_EVEN 0x18 /* Even Parity */ +#define SERIAL_LCR_ODD 0x8 /* Odd Parity */ +#define SERIAL_LCR_PE 0x8 /* Parity Enable */ +#define SERIAL_LCR_SETBREAK 0x40 /* Set Break condition */ +#define SERIAL_LCR_STICKPARITY 0x20 /* Stick Parity Enable */ +#define SERIAL_LCR_DLAB 0x80 /* Divisor Latch Access Bit */ + +/* LSR Register */ +#define SERIAL_LSR_DR 0x1 /* Data Ready */ +#define SERIAL_LSR_OE 0x2 /* Overrun Error */ +#define SERIAL_LSR_PE 0x4 /* Parity Error */ +#define SERIAL_LSR_FE 0x8 /* Framing Error */ +#define SERIAL_LSR_BI 0x10 /* Break Interrupt */ +#define SERIAL_LSR_THRE 0x20 /* THR Empty */ +#define SERIAL_LSR_TE 0x40 /* Transmitte Empty */ +#define SERIAL_LSR_DE 0x80 /* FIFO Data Error */ + +/* MCR Register */ +#define SERIAL_MCR_DTR 0x1 /* Data Terminal Ready */ +#define SERIAL_MCR_RTS 0x2 /* Request to Send */ +#define SERIAL_MCR_OUT1 0x4 /* output 1 */ +#define SERIAL_MCR_OUT2 0x8 /* output2 or global interrupt enable */ +#define SERIAL_MCR_LPBK 0x10 /* loopback mode */ + +/* MSR Register */ +#define SERIAL_MSR_DELTACTS 0x1 /* Delta CTS */ +#define SERIAL_MSR_DELTADSR 0x2 /* Delta DSR */ +#define SERIAL_MSR_TERI 0x4 /* Trailing Edge RI */ +#define SERIAL_MSR_DELTACD 0x8 /* Delta CD */ +#define SERIAL_MSR_CTS 0x10 /* Clear To Send */ +#define SERIAL_MSR_DSR 0x20 /* Data Set Ready */ +#define SERIAL_MSR_RI 0x40 /* Ring Indicator */ +#define SERIAL_MSR_DCD 0x80 /* Data Carrier Detect */ + +/* MDR register */ +#define SERIAL_MDR_MODE_SEL 0x03 +#define SERIAL_MDR_UART 0x0 +#define SERIAL_MDR_SIR 0x1 +#define SERIAL_MDR_FIR 0x2 + +/* ACR register */ +#define SERIAL_ACR_TXENABLE 0x1 +#define SERIAL_ACR_RXENABLE 0x2 +#define SERIAL_ACR_SET_EOT 0x4 + +/* + * API + */ +#ifdef not_complete_yet +extern UINT32 DebugSerialPort; +extern UINT32 SystemSerialPort; +#endif /* end_of_not */ + +extern void fLib_SerialInit(UINT32 port, UINT32 baudrate, UINT32 parity,UINT32 num,UINT32 len); +extern void fLib_SetSerialFifoCtrl(UINT32 port, UINT32 level, UINT32 resettx, UINT32 resetrx); +extern void fLib_DisableSerialFifo(UINT32 port); +extern void fLib_SetSerialInt(UINT32 port, UINT32 IntMask); + +extern char fLib_GetSerialChar(UINT32 port); +extern void fLib_PutSerialChar(UINT32 port, char Ch); +extern void fLib_PutSerialStr(UINT32 port, char *Str); + +extern void fLib_EnableSerialInt(UINT32 port, UINT32 mode); +extern void fLib_DisableSerialInt(UINT32 port, UINT32 mode); + +extern void fLib_SerialRequestToSend(UINT32 port); +extern void fLib_SerialStopToSend(UINT32 port); +extern void fLib_SerialDataTerminalReady(UINT32 port); +extern void fLib_SerialDataTerminalNotReady(UINT32 port); + +extern void fLib_SetSerialLineBreak(UINT32 port); +extern void fLib_SetSerialLoopBack(UINT32 port,UINT32 onoff); +extern UINT32 fLib_SerialIntIdentification(UINT32 port); + +extern UINT32 fLib_ReadSerialLineStatus(UINT32 port); +extern UINT32 fLib_ReadSerialModemStatus(UINT32 port); + +extern void fLib_SetSerialMode(UINT32 port, UINT32 mode); +extern void fLib_EnableIRMode(UINT32 port, UINT32 TxEnable, UINT32 RxEnable); + +extern void fLib_Modem_call(UINT32 port, char *tel); +extern void fLib_Modem_waitcall(UINT32 port); +extern int fLib_Modem_getchar(UINT32 port,int TIMEOUT); +extern BOOL fLib_Modem_putchar(UINT32 port, INT8 Ch); +//extern BOOL fLib_Modem_Initial(UINT32 port, int baudRate, UINT32 parity, UINT32 stopbit, UINT32 databit); +//extern void fLib_Modem_close(UINT32 port); + +#endif diff --git a/board/AndesTech/include/symbol.h b/board/AndesTech/include/symbol.h new file mode 100644 index 0000000..51b22fe --- /dev/null +++ b/board/AndesTech/include/symbol.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*************************************************************************** +* Copyright Faraday Technology Corp 2002-2003. All rights reserved. * +*--------------------------------------------------------------------------* +* Name:symbol.h * +* Description: Faraday code library define * +* Author: Fred Chien * +* Date: 2002/03/01 * +* Version:1.0 * +*--------------------------------------------------------------------------* +* Update by macpaul@andestech.com Andes Tech Crop. 2010 * +****************************************************************************/ + +#ifndef SYMBOL_H +#define SYMBOL_H + +/* ASCII symbol define */ + +#define CR 0x0D +#define LF 0x0A +#define BS 0x08 +#define ESC 27 + +/* These defines are in a common coding practices header file */ + +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef NULL +#define NULL 0 +#endif + +#ifndef ON +#define ON 1 +#endif + +#ifndef OFF +#define OFF 0 +#endif + + +#ifndef ENABLE +#define ENABLE 1 +#endif + +#ifndef DISABLE +#define DISABLE 0 +#endif + +#ifndef PARITY_NONE +#define PARITY_NONE 0 +#endif + +#ifndef PARITY_ODD +#define PARITY_ODD 1 +#endif + +#ifndef PARITY_EVEN +#define PARITY_EVEN 2 +#endif + +#ifndef PARITY_MARK +#define PARITY_MARK 3 +#endif + +#ifndef PARITY_SPACE +#define PARITY_SPACE 4 +#endif + +/* type define */ +typedef unsigned long long UINT64; +typedef long long INT64; +typedef unsigned int UINT32; +typedef int INT32; +typedef unsigned short UINT16; +typedef short INT16; +typedef unsigned char UINT8; +typedef char INT8; +typedef unsigned char BOOL; + +#endif

Add nds32 with examples standalone program support.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- examples/standalone/nds32.lds | 64 +++++++++++++++++++++++++++++++++++++ examples/standalone/stubs.c | 17 +++++++++- examples/standalone/x86-testapp.c | 12 +++++++ 3 files changed, 92 insertions(+), 1 deletions(-) create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds new file mode 100644 index 0000000..1058e3a --- /dev/null +++ b/examples/standalone/nds32.lds @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2006 Andes Technology Corporation + * Shawn Lin, Andes Tech Crop. nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32") +OUTPUT_ARCH(nds32) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + . = ALIGN(4); + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + + _end = .; + + . = 0x02000000; + .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) } +} diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index f3e1ab5..a4c99f6 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -167,8 +167,23 @@ gd_t *global_data; " jmp %%g1\n" \ " nop\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" ); - +#elif defined(CONFIG_NDS32) +/* + * r16 holds the pointer to the global_data. gp is call clobbered. + * not support reduced register (16 GPR). + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" lwi $r16, [$gp + (%0)]\n" \ +" lwi $r16, [$r16 + (%1)]\n" \ +" jr $r16\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16" ); #else +/*" addi $sp, $sp, -24\n" \ +" br $r16\n" */ + #error stubs definition missing for this architecture #endif

diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c index e8603d9..9f80a5d 100644 --- a/examples/standalone/x86-testapp.c +++ b/examples/standalone/x86-testapp.c @@ -52,6 +52,16 @@ asm volatile ( \ " lw $25, %1($25)\n" \ " jr $25\n" \ : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9"); +#elif defined(__nds32__) +#define EXPORT_FUNC(x) \ +asm volatile ( \ +" .globl mon_" #x "\n" \ +"mon_" #x ":\n" \ +" lwi $r16, [$gp + (%0)]\n" \ +" lwi $r16, [$r16 + (%1)]\n" \ +" jr $r16\n" \ + : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16"); + #else #error [No stub code for this arch] #endif @@ -72,6 +82,8 @@ int main(void) register volatile xxx_t *pq asm("r8"); #elif defined(__mips__) register volatile xxx_t *pq asm("k0"); +#elif defined(__nds32__) + register volatile xxx_t *pq asm("$r16"); #endif char buf[32];

Add nds32 support in u-boot Makefile.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- Makefile | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/Makefile b/Makefile index c26e491..c6424ad 100644 --- a/Makefile +++ b/Makefile @@ -479,6 +479,16 @@ unconfig: $(MAKE)

#======================================================================== +# ANDES +#======================================================================== + +######################################################################### +## NDS32 adp-ag101 (also for FPGA_X5) +######################################################################### +adp-ag101_config: unconfig + @$(MKCONFIG) $(@:_config=) nds32 n1213s $(@:_config=) AndesTech ag101 + +#======================================================================== # PowerPC #========================================================================