Shinya Kuribayashi wrote:

Andrew Dyer wrote:

...

looking at how cache_flush() is used (see common/cmd_load.c, common/cmd_elf.c, etc), I believe this loop should also do a cache_op with Hit_Invalidate_I to invalidate the icache.

seems like it would be easier to read if the condition was included in the while() statement

Hm, then is this ok?

<snip>

@@ -41,6 +52,17 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

void flush_cache(ulong start_addr, ulong size) {

• unsigned long lsize = CFG_DCACHE_SIZE;

^^^^^^^^^^^^^^^ Oops, this should have been cache line size.

Patch updated.

P.S. I'll introduce <asm/r4kcache.h> and remove cache_op macro in the future. But it takes some time.

================>

[MIPS] Implement flush_cache()

Signed-off-by: Shinya Kuribayashi skuribay@ruby.dti.ne.jp ---

cpu/mips/cpu.c | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 7559ac6..de70c4d 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -25,6 +25,17 @@ #include <command.h> #include <asm/inca-ip.h> #include <asm/mipsregs.h> +#include <asm/cacheops.h> + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr)))

int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -41,6 +52,17 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

void flush_cache(ulong start_addr, ulong size) { + unsigned long lsize = CFG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, start_addr); + cache_op(Hit_Invalidate_I, start_addr); + if (addr == aend) + break; + addr += lsize; + } }

void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)