New function - configure_pcie_dpll() - has been added to allow setting up the PCIe DPLL clock (1500 MHz).

Signed-off-by: Lukasz Majewski lukma@denx.de --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 2 ++ 2 files changed, 24 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 9b97583..56476bf 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -208,6 +208,17 @@ static const struct dpll_params *get_gmac_dpll_params } #endif

+static const struct dpll_params *get_pcie_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->pcie) + return NULL; + + return &dpll_data->pcie[sysclk_ind]; +} + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { @@ -302,6 +313,17 @@ u32 omap_ddr_clk(void) return ddr_clk; }

+void configure_pcie_dpll(void) +{ + const struct dpll_params *params; + + params = get_pcie_dpll_params(*dplls_data); + + do_setup_dpll((*prcm)->cm_clkmode_dpll_pcie_ref, params, DPLL_LOCK, + "pcie"); + debug("PCIE DPLL locked\n"); +} + /* * Lock MPU dpll * diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index cc40ee9..bb74321 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -612,6 +612,8 @@ void enable_basic_uboot_clocks(void); void enable_usb_clocks(int index); void disable_usb_clocks(int index);

+void configure_pcie_dpll(void); + void scale_vcores(struct vcores_data const *); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);

On Monday 16 January 2017 04:09 AM, Lukasz Majewski wrote:

With this code only 19.2 HMz SYSCLK (input) frequency is supported on dra7xx based SoCs.

This wold be breaking dra74x-evm which has 20MHz sysclk. May I know what is intention for configuring PCIE dpll in u-boot?(you want to use PCIE at u-boot or for kernel to depend on this configuration?)

Thanks and regards, Lokesh

Signed-off-by: Lukasz Majewski lukma@denx.de

arch/arm/cpu/armv7/omap5/hw_data.c | 12 ++++++++++++ arch/arm/include/asm/omap_common.h | 1 + 2 files changed, 13 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 2192090..e16bd2c 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -257,6 +257,17 @@ static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ };

+static const struct dpll_params pcie_dpll_params_1500mhz[NUM_SYS_CLKS] = {

• {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
• {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
• {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
• {625, 7, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
• {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
• {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
• {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */

+};

struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -294,6 +305,7 @@ struct dplls dra7xx_dplls = { .usb = usb_dpll_params_1920mhz, .ddr = ddr_dpll_params_2128mhz, .gmac = gmac_dpll_params_2000mhz,

• .pcie = pcie_dpll_params_1500mhz,

};

struct dplls dra72x_dplls = { diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 605c549..cc40ee9 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -526,6 +526,7 @@ struct dplls { const struct dpll_params *usb; const struct dpll_params *ddr; const struct dpll_params *gmac;

• const struct dpll_params *pcie;

};

struct pmic_data {