[U-Boot] [PATCH v2 00/55] dm: x86: Convert ivybridge code to use driver model
At present ivybridge is the only x86 implementation that includes a reasonably full board init. This means there is a lot more code than with a board that uses FSP (even then we don't have memory init or graphics init code).
This code does not use proper drivers for the devices and so its use of driver model is limited. This series refactors the code to improve this. In particular it drops use of the old x86_pci_...() API in favour of dm_pci_...(). The latter requires that each PCI device has a driver.
A few very minor driver model improvements are added to support this. Also a Northbridge uclass is added - this could instead be done with the syscon, so comments are well as to which is best.
A small amount of additional work will be needed to remove use of the x86_pci_...() in arch/x86, but this series represents the bulk of it.
Changes in v2: - Fix -EEPFNOSUPPORT typo - Add missing of_match member init so that ehci_pci_ids[] is used - Add missing 'given' word - Drop unnecessary/incorrect non-DM code in dm_pci_run_vga_bios() - Drop unused 'gen-dec' device tree property - Drop the init() method in the PCH - Rename this commit from 'x86: ivybridge: Set up the PCH init' - Drop unnecessary DECLARE_GLOBAL_DATA_PTR - Drop explicit PCH probe - Drop LPC init method - Rename patch from 'Add an init() method for the bd82x6x LPC' - Update to drop LPC init method and use probe() instead - Fix 'baords' typo in the commit message - Add a comment as to why we are initing the devices again - Drop northbridge_enable() - Rename from 'Move northbridge setup to the northbridge driver' - Drop this unnecessary init - Rename the AHCI uclass to DISK - Update to use the disk uclass - Update to use the disk uclass - Drop unnecessary IRQ and command register init - Update to use LPC probe() method instead of init() - Drop the special compatible string in chromebook_link.dts - Expand the Kconfig help a little - Avoid needing the pch device to set up the USB bar - Fix incorrect bits in bridge_silicon_revision() comment - Rename from 'Convert EHCI init to use the DM PCI API' - Drop this init - Fix the USB PCI address in the device tree - Enable SYSCON and REGMAP for panther to avoid a build error - Drop bd82x6x_pci_init() function and associated DM-conversion patch - Drop LPC init method an 'Add an init() method to the LPC uclass' patch
Simon Glass (55): dm: core: Display the error number when driver binding fails dm: usb: Add a compatible string for PCI EHCI controller dm: syscon: Allow finding devices by driver data dm: pci: Convert bios_emu to use the driver model PCI API x86: ivybridge: Set up the LPC device using driver model x86: ivybridge: Move lpc_early_init() to probe() x86: ivybridge: Move more init to the probe() function x86: ivybridge: Rename bd82x6x_init() dm: x86: Add a northbridge uclass x86: ivybridge: Add a driver for the bd82x6x northbridge x86: ivybridge: Move northbridge init into the probe() method x86: ivybridge: Move LPC and PCH init into northbridge probe() x86: ivybridge: Rename lpc_init() to lpc_init_extra() x86: ivybridge: Probe the LPC in CPU init x86: ivybridge: Move graphics init much later x86: ivybridge: Move sandybridge init to the lpc probe() method x86: ivybridge: Move GPIO init to the LPC init() method x86: ivybridge: Use common CPU init code x86: ivybridge: Move CPU init code into the driver x86: ivybridge: Set up the thermal target correctly x86: ivybridge: Drop the dead MTRR code x86: ivybridge: Move early init code into northbridge.c x86: Make x86_init_cpus() static x86: Don't show an error when the MRC cache is up to date x86: Bring up northbridge, pch and lpc after the CPUs x86: ivybridge: Move northbridge and PCH init into drivers x86: ivybridge: Use driver model PCI API in bd82x6x.c x86: ivybridge: Drop unnecessary northbridge setup ahci: Add a disk-controller uclass x86: ivybridge: Do the SATA init before relocation x86: ivybridge: Drop the unused bd82x6x_init_extra() x86: ivybridge: Use the SATA driver to do the init x86: ivybridge: Use driver model PCI API in sata.c x86: ivybridge: Move lpc_enable() into gma.c x86: ivybridge: Move LPC init into the LPC probe() method x86: ivybridge: Drop the special PCI driver x86: ivybridge: Convert lpc init code to DM PCI API x86: Enable DM_USB for link and panther x86: i2c: Add a stub driver for Intel I2C/SMbus x86: ivybridge: Use the I2C driver to perform SMbus init x86: ivybridge: Convert enable_usb_bar() to use DM PCI API x86: ivybridge: Convert dram_init() to use DM PCI API x86: ivybridge: Convert sdram_initialise() to use DM PCI API x86: chromebook_link: Enable the syscon uclass x86: ivybridge: Convert SDRAM init to use driver model x86: ivybridge: Convert report_platform to DM PCI API x86: ivybridge: Convert pch.c to use DM PCI API x86: ivybridge: Move code from pch.c to bd82x6x.c x86: ivybridge: Sort out the calls to bridge_silicon_revision() x86: ivybridge: Drop special EHCI init x86: ivybridge: Drop XHCI support x86: ivybridge: Drop the SMM-locking code x86: Set up a shared syscon numbering schema x86: ivybridge: Use syscon for the GMA device x86: fdt: Drop the unused compatible strings in fdtdec
arch/x86/cpu/cpu.c | 22 +- arch/x86/cpu/ivybridge/Makefile | 5 - arch/x86/cpu/ivybridge/bd82x6x.c | 217 ++++++++++------ arch/x86/cpu/ivybridge/cpu.c | 146 +++-------- arch/x86/cpu/ivybridge/early_init.c | 147 ----------- arch/x86/cpu/ivybridge/early_me.c | 70 +++-- arch/x86/cpu/ivybridge/gma.c | 114 ++++++-- arch/x86/cpu/ivybridge/lpc.c | 301 ++++++++++++---------- arch/x86/cpu/ivybridge/model_206ax.c | 126 ++++----- arch/x86/cpu/ivybridge/northbridge.c | 126 ++++++--- arch/x86/cpu/ivybridge/pch.c | 123 --------- arch/x86/cpu/ivybridge/pci.c | 67 ----- arch/x86/cpu/ivybridge/report_platform.c | 11 +- arch/x86/cpu/ivybridge/sata.c | 132 ++++++---- arch/x86/cpu/ivybridge/sdram.c | 64 +++-- arch/x86/cpu/ivybridge/usb_ehci.c | 29 --- arch/x86/cpu/ivybridge/usb_xhci.c | 32 --- arch/x86/dts/chromebook_link.dts | 86 ++++++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 23 +- arch/x86/include/asm/arch-ivybridge/me.h | 45 +++- arch/x86/include/asm/arch-ivybridge/pch.h | 27 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 13 +- arch/x86/include/asm/cpu.h | 11 + arch/x86/include/asm/u-boot-x86.h | 2 - arch/x86/lib/Makefile | 1 + arch/x86/lib/mrccache.c | 6 +- arch/x86/lib/northbridge-uclass.c | 15 ++ board/google/chromebook_link/link.c | 8 - configs/chromebook_link_defconfig | 9 + configs/chromebox_panther_defconfig | 4 + drivers/bios_emulator/atibios.c | 109 +++++++- drivers/bios_emulator/bios.c | 39 +++ drivers/block/Kconfig | 9 + drivers/block/Makefile | 1 + drivers/block/disk-uclass.c | 14 + drivers/core/lists.c | 3 +- drivers/core/syscon-uclass.c | 31 ++- drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/intel_i2c.c | 75 ++++++ drivers/pci/pci_rom.c | 6 +- drivers/usb/host/ehci-pci.c | 6 + include/bios_emul.h | 19 +- include/dm/uclass-id.h | 2 + include/fdtdec.h | 5 - include/syscon.h | 14 + lib/fdtdec.c | 5 - test/dm/syscon.c | 17 ++ 48 files changed, 1288 insertions(+), 1059 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/early_init.c delete mode 100644 arch/x86/cpu/ivybridge/pch.c delete mode 100644 arch/x86/cpu/ivybridge/pci.c delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c delete mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c create mode 100644 arch/x86/lib/northbridge-uclass.c create mode 100644 drivers/block/disk-uclass.c create mode 100644 drivers/i2c/intel_i2c.c
This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not compiled in. Display the error number to make this easier to spot.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Fix -EEPFNOSUPPORT typo
drivers/core/lists.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/core/lists.c b/drivers/core/lists.c index a1c9478..c4fc216 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -172,7 +172,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, dm_dbg(" - found match at '%s'\n", entry->name); ret = device_bind(parent, entry, name, NULL, offset, &dev); if (ret) { - dm_warn("Error binding driver '%s'\n", entry->name); + dm_warn("Error binding driver '%s': %d\n", entry->name, + ret); return ret; } else { dev->driver_data = id->data;
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not compiled in. Display the error number to make this easier to spot.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Add a compatible string to allow this to be specified in the device tree if needed.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add missing of_match member init so that ehci_pci_ids[] is used
drivers/usb/host/ehci-pci.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index cda1c6d..f21a1fa 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -137,11 +137,17 @@ static int ehci_pci_remove(struct udevice *dev) return 0; }
+static const struct udevice_id ehci_pci_ids[] = { + { .compatible = "ehci-pci" }, + { } +}; + U_BOOT_DRIVER(ehci_pci) = { .name = "ehci_pci", .id = UCLASS_USB, .probe = ehci_pci_probe, .remove = ehci_pci_remove, + .of_match = ehci_pci_ids, .ops = &ehci_usb_ops, .platdata_auto_alloc_size = sizeof(struct usb_platdata), .priv_auto_alloc_size = sizeof(struct ehci_pci_priv),
On Monday, January 18, 2016 at 12:11:07 AM, Simon Glass wrote:
Add a compatible string to allow this to be specified in the device tree if needed.
Signed-off-by: Simon Glass sjg@chromium.org
Acked-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Add a compatible string to allow this to be specified in the device tree if needed.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Add missing of_match member init so that ehci_pci_ids[] is used
drivers/usb/host/ehci-pci.c | 6 ++++++ 1 file changed, 6 insertions(+)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 1:56 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Add a compatible string to allow this to be specified in the device tree if needed.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Add missing of_match member init so that ehci_pci_ids[] is used
drivers/usb/host/ehci-pci.c | 6 ++++++ 1 file changed, 6 insertions(+)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
We have a way to find a regmap by its syscon driver data value. Add the same for syscon itself.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add missing 'given' word
drivers/core/syscon-uclass.c | 31 +++++++++++++++++++------------ include/syscon.h | 14 ++++++++++++++ test/dm/syscon.c | 17 +++++++++++++++++ 3 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index 686c320..a0666d0 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -32,7 +32,7 @@ static int syscon_pre_probe(struct udevice *dev) return regmap_init_mem(dev, &priv->regmap); }
-struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data) +int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp) { struct udevice *dev; struct uclass *uc; @@ -40,22 +40,29 @@ struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data)
ret = uclass_get(UCLASS_SYSCON, &uc); if (ret) - return ERR_PTR(ret); + return ret; uclass_foreach_dev(dev, uc) { if (dev->driver_data == driver_data) { - struct syscon_uc_info *priv; - int ret; - - ret = device_probe(dev); - if (ret) - return ERR_PTR(ret); - priv = dev_get_uclass_priv(dev); - - return priv->regmap; + *devp = dev; + return device_probe(dev); } }
- return ERR_PTR(-ENODEV); + return -ENODEV; +} + +struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data) +{ + struct syscon_uc_info *priv; + struct udevice *dev; + int ret; + + ret = syscon_get_by_driver_data(driver_data, &dev); + if (ret) + return ERR_PTR(ret); + priv = dev_get_uclass_priv(dev); + + return priv->regmap; }
void *syscon_get_first_range(ulong driver_data) diff --git a/include/syscon.h b/include/syscon.h index c62ccd6..4593b6e 100644 --- a/include/syscon.h +++ b/include/syscon.h @@ -37,6 +37,20 @@ struct regmap *syscon_get_regmap(struct udevice *dev); * * Each system controller can be accessed by its driver data, which is * assumed to be unique through the scope of all system controllers that + * are in use. This function looks up the controller given this driver data. + * + * @driver_data: Driver data value to look up + * @devp: Returns the controller correponding to @driver_data + * @return 0 on success, -ENODEV if the ID was not found, or other -ve error + * code + */ +int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp); + +/** + * syscon_get_regmap_by_driver_data() - Look up a controller by its ID + * + * Each system controller can be accessed by its driver data, which is + * assumed to be unique through the scope of all system controllers that * are in use. This function looks up the regmap given this driver data. * * @driver_data: Driver data value to look up diff --git a/test/dm/syscon.c b/test/dm/syscon.c index 3642481..c40f5fc 100644 --- a/test/dm/syscon.c +++ b/test/dm/syscon.c @@ -29,3 +29,20 @@ static int dm_test_syscon_base(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_syscon_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test system controller finding */ +static int dm_test_syscon_by_driver_data(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(syscon_get_by_driver_data(SYSCON0, &dev)); + ut_asserteq(SYSCON0, dev->driver_data); + + ut_assertok(syscon_get_by_driver_data(SYSCON1, &dev)); + ut_asserteq(SYSCON1, dev->driver_data); + + ut_asserteq(-ENODEV, syscon_get_by_driver_data(2, &dev)); + + return 0; +} +DM_TEST(dm_test_syscon_by_driver_data, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
We have a way to find a regmap by its syscon driver data value. Add the same for syscon itself.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Add missing 'given' word
drivers/core/syscon-uclass.c | 31 +++++++++++++++++++------------ include/syscon.h | 14 ++++++++++++++ test/dm/syscon.c | 17 +++++++++++++++++ 3 files changed, 50 insertions(+), 12 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 1:58 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
We have a way to find a regmap by its syscon driver data value. Add the same for syscon itself.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Add missing 'given' word
drivers/core/syscon-uclass.c | 31 +++++++++++++++++++------------ include/syscon.h | 14 ++++++++++++++ test/dm/syscon.c | 17 +++++++++++++++++ 3 files changed, 50 insertions(+), 12 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
At present this BIOS emulator uses a bus/device/function number. Change it to use a device if CONFIG_DM_PCI is enabled.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Drop unnecessary/incorrect non-DM code in dm_pci_run_vga_bios()
drivers/bios_emulator/atibios.c | 109 ++++++++++++++++++++++++++++++++++++++-- drivers/bios_emulator/bios.c | 39 ++++++++++++++ drivers/pci/pci_rom.c | 6 +-- include/bios_emul.h | 19 ++++++- 4 files changed, 165 insertions(+), 8 deletions(-)
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index dec6230..7717246 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -226,11 +226,19 @@ This function executes the BIOS POST code on the controller. We assume that at this stage the controller has its I/O and memory space enabled and that all other controllers are in a disabled state. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +static void PCI_doBIOSPOST(struct udevice *pcidev, BE_VGAInfo *vga_info, + int vesa_mode, struct vbe_mode_info *mode_info) +#else static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info, int vesa_mode, struct vbe_mode_info *mode_info) +#endif { RMREGS regs; RMSREGS sregs; +#ifdef CONFIG_DM_PCI + pci_dev_t bdf; +#endif
/* Determine the value to store in AX for BIOS POST. Per the PCI specs, AH must contain the bus and AL must contain the devfn, encoded as @@ -238,9 +246,14 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info, */ memset(®s, 0, sizeof(regs)); memset(&sregs, 0, sizeof(sregs)); +#ifdef CONFIG_DM_PCI + bdf = dm_pci_get_bdf(pcidev); + regs.x.ax = (int)PCI_BUS(bdf) << 8 | + (int)PCI_DEV(bdf) << 3 | (int)PCI_FUNC(bdf); +#else regs.x.ax = ((int)PCI_BUS(pcidev) << 8) | ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev); - +#endif /*Setup the X86 emulator for the VGA BIOS*/ BE_setVGA(vga_info);
@@ -281,15 +294,28 @@ NOTE: This function leaves the original memory aperture disabled by leaving it programmed to all 1's. It must be restored to the correct value later. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +static u32 PCI_findBIOSAddr(struct udevice *pcidev, int *bar) +#else static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar) +#endif { u32 base, size;
for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) { +#ifdef CONFIG_DM_PCI + dm_pci_read_config32(pcidev, *bar, &base); +#else pci_read_config_dword(pcidev, *bar, &base); +#endif if (!(base & 0x1)) { +#ifdef CONFIG_DM_PCI + dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF); + dm_pci_read_config32(pcidev, *bar, &size); +#else pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF); pci_read_config_dword(pcidev, *bar, &size); +#endif size = ~(size & ~0xFF) + 1; if (size >= MAX_BIOSLEN) return base & ~0xFF; @@ -312,11 +338,19 @@ necessary). Anyway to fix this we change all I/O mapped base registers and chop off the top bits. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +static void PCI_fixupIObase(struct udevice *pcidev, int reg, u32 *base) +#else static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base) +#endif { if ((*base & 0x1) && (*base > 0xFFFE)) { *base &= 0xFFFF; +#ifdef CONFIG_DM_PCI + dm_pci_write_config32(pcidev, reg, *base); +#else pci_write_config_dword(pcidev, reg, *base); +#endif
} } @@ -331,18 +365,30 @@ Pointers to the mapped BIOS image REMARKS: Maps a pointer to the BIOS image on the graphics card on the PCI bus. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +void *PCI_mapBIOSImage(struct udevice *pcidev) +#else void *PCI_mapBIOSImage(pci_dev_t pcidev) +#endif { u32 BIOSImageBus; int BIOSImageBAR; u8 *BIOSImage;
/*Save PCI BAR registers that might get changed*/ +#ifdef CONFIG_DM_PCI + dm_pci_read_config32(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress); + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10); + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14); + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18); + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20); +#else pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress); pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10); pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14); pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18); pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20); +#endif
/*Fix up I/O base registers to less than 64K */ if(saveBaseAddress14 != 0) @@ -361,13 +407,21 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev) return NULL; }
+#ifdef CONFIG_DM_PCI + BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus, + PCI_REGION_MEM, 0, MAP_NOCACHE); + + /*Change the PCI BAR registers to map it onto the bus.*/ + dm_pci_write_config32(pcidev, BIOSImageBAR, 0); + dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); +#else BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus, PCI_REGION_MEM, 0, MAP_NOCACHE);
/*Change the PCI BAR registers to map it onto the bus.*/ pci_write_config_dword(pcidev, BIOSImageBAR, 0); pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); - +#endif udelay(1);
/*Check that the BIOS image is valid. If not fail, or return the @@ -387,6 +441,16 @@ pcidev - PCI device info for the video card on the bus REMARKS: Unmaps the BIOS image for the device and restores framebuffer mappings ****************************************************************************/ +#ifdef CONFIG_DM_PCI +void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage) +{ + dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10); + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14); + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20); +} +#else void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage) { pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); @@ -395,6 +459,7 @@ void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage) pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20); } +#endif
/**************************************************************************** PARAMETERS: @@ -408,13 +473,22 @@ REMARKS: Loads and POST's the display controllers BIOS, directly from the BIOS image we can extract over the PCI bus. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +static int PCI_postController(struct udevice *pcidev, uchar *bios_rom, + int bios_len, BE_VGAInfo *vga_info, + int vesa_mode, struct vbe_mode_info *mode_info) +#else static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, BE_VGAInfo *vga_info, int vesa_mode, struct vbe_mode_info *mode_info) +#endif { u32 bios_image_len; uchar *mapped_bios; uchar *copy_of_bios; +#ifdef CONFIG_DM_PCI + pci_dev_t bdf; +#endif
if (bios_rom) { copy_of_bios = bios_rom; @@ -442,9 +516,16 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, }
/*Save information in vga_info structure*/ +#ifdef CONFIG_DM_PCI + bdf = dm_pci_get_bdf(pcidev); + vga_info->function = PCI_FUNC(bdf); + vga_info->device = PCI_DEV(bdf); + vga_info->bus = PCI_BUS(bdf); +#else vga_info->function = PCI_FUNC(pcidev); vga_info->device = PCI_DEV(pcidev); vga_info->bus = PCI_BUS(pcidev); +#endif vga_info->pcidev = pcidev; vga_info->BIOSImage = copy_of_bios; vga_info->BIOSImageLen = bios_image_len; @@ -462,13 +543,22 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, return true; }
+#ifdef CONFIG_DM_PCI +int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **vga_infop) +#else int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop) +#endif { BE_VGAInfo *VGAInfo; +#ifdef CONFIG_DM_PCI + pci_dev_t bdf = dm_pci_get_bdf(pcidev);
printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n", - PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev)); - + PCI_BUS(bdf), PCI_FUNC(bdf), PCI_DEV(bdf)); +#else + printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n", + PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev)); +#endif /*Initialise the x86 BIOS emulator*/ if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) { printf("videoboot: Out of memory!\n"); @@ -486,9 +576,15 @@ void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)) X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func); }
+#ifdef CONFIG_DM_PCI +int biosemu_run(struct udevice *pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info) +#else int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, BE_VGAInfo *vga_info, int clean_up, int vesa_mode, struct vbe_mode_info *mode_info) +#endif { /*Post all the display controller BIOS'es*/ if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info, @@ -522,7 +618,12 @@ REMARKS: Boots the PCI/AGP video card on the bus using the Video ROM BIOS image and the X86 BIOS emulator module. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo, + int clean_up) +#else int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up) +#endif { BE_VGAInfo *VGAInfo; int ret; diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index dd4c0a4..77c7f94 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -185,12 +185,21 @@ static void X86API int1A(int unused) case 0xB103: /* Find PCI class code */ M.x86.R_AH = DEVICE_NOT_FOUND; #ifdef __KERNEL__ +#ifdef CONFIG_DM_PCI + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG, + &interface); + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE, + &subclass); + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, + PCI_CLASS_DEVICE + 1, &baseclass); +#else pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG, &interface); pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE, &subclass); pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE + 1, &baseclass); +#endif if (M.x86.R_CL == interface && M.x86.R_CH == subclass && (u8) (M.x86.R_ECX >> 16) == baseclass) { #else @@ -209,8 +218,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, M.x86.R_DI, + &M.x86.R_CL); +# else pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI, &M.x86.R_CL); +# endif #else M.x86.R_CL = (u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE, @@ -224,8 +238,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_read_config16(_BE_env.vgaInfo.pcidev, M.x86.R_DI, + &M.x86.R_CX); +# else pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI, &M.x86.R_CX); +# endif #else M.x86.R_CX = (u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD, @@ -239,8 +258,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_read_config32(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, &M.x86.R_ECX); +# else pci_read_config_dword(_BE_env.vgaInfo.pcidev, M.x86.R_DI, &M.x86.R_ECX); +# endif #else M.x86.R_ECX = (u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD, @@ -254,8 +278,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_write_config8(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_CL); +# else pci_write_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI, M.x86.R_CL); +# endif #else PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE, _BE_env.vgaInfo.pciInfo); @@ -268,8 +297,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_write_config32(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_CX); +# else pci_write_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI, M.x86.R_CX); +# endif #else PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD, _BE_env.vgaInfo.pciInfo); @@ -282,8 +316,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_write_config32(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_ECX); +# else pci_write_config_dword(_BE_env.vgaInfo.pcidev, M.x86.R_DI, M.x86.R_ECX); +# endif #else PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD, _BE_env.vgaInfo.pciInfo); diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 8c83be6..1b37820 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -328,12 +328,12 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), #ifdef CONFIG_BIOSEMU BE_VGAInfo *info;
- ret = biosemu_setup(dm_pci_get_bdf(dev), &info); + ret = biosemu_setup(dev, &info); if (ret) goto err; biosemu_set_interrupt_handler(0x15, int15_handler); - ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16, - info, true, vesa_mode, &mode_info); + ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, + true, vesa_mode, &mode_info); if (ret) goto err; #endif diff --git a/include/bios_emul.h b/include/bios_emul.h index 80979ed..7571263 100644 --- a/include/bios_emul.h +++ b/include/bios_emul.h @@ -31,7 +31,11 @@ typedef struct { int bus; u32 VendorID; u32 DeviceID; +#ifdef CONFIG_DM_PCI + struct udevice *pcidev; +#else pci_dev_t pcidev; +#endif void *BIOSImage; u32 BIOSImageLen; u8 LowMem[1536]; @@ -39,7 +43,12 @@ typedef struct {
struct vbe_mode_info;
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp); +#ifdef CONFIG_DM_PCI +int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo, + int clean_up); +#else +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up); +#endif
/* Run a BIOS ROM natively (only supported on x86 machines) */ void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode, @@ -57,10 +66,18 @@ void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
+#ifdef CONFIG_DM_PCI +int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo); + +int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info); +#else int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, BE_VGAInfo *vga_info, int clean_up, int vesa_mode, struct vbe_mode_info *mode_info); +#endif
#endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
At present this BIOS emulator uses a bus/device/function number. Change it to use a device if CONFIG_DM_PCI is enabled.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop unnecessary/incorrect non-DM code in dm_pci_run_vga_bios()
drivers/bios_emulator/atibios.c | 109 ++++++++++++++++++++++++++++++++++++++-- drivers/bios_emulator/bios.c | 39 ++++++++++++++ drivers/pci/pci_rom.c | 6 +-- include/bios_emul.h | 19 ++++++- 4 files changed, 165 insertions(+), 8 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:02 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
At present this BIOS emulator uses a bus/device/function number. Change it to use a device if CONFIG_DM_PCI is enabled.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop unnecessary/incorrect non-DM code in dm_pci_run_vga_bios()
drivers/bios_emulator/atibios.c | 109 ++++++++++++++++++++++++++++++++++++++-- drivers/bios_emulator/bios.c | 39 ++++++++++++++ drivers/pci/pci_rom.c | 6 +-- include/bios_emul.h | 19 ++++++- 4 files changed, 165 insertions(+), 8 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 3 +++ arch/x86/cpu/ivybridge/cpu.c | 6 +++++- arch/x86/cpu/ivybridge/lpc.c | 6 ++++++ arch/x86/dts/chromebook_link.dts | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index c000aca..72f2ed4 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -65,6 +65,9 @@ static int bd82x6x_probe(struct udevice *dev) int sata_node, gma_node; int ret;
+ if (!(gd->flags & GD_FLG_RELOC)) + return 0; + hose = pci_bus_to_hose(0); lpc_enable(PCH_LPC_DEV); lpc_init(hose, PCH_LPC_DEV); diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 343bfb4..6ffc843 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -126,7 +126,7 @@ int arch_cpu_init_dm(void) { const void *blob = gd->fdt_blob; struct pci_controller *hose; - struct udevice *bus; + struct udevice *bus, *dev; int node; int ret;
@@ -141,6 +141,10 @@ int arch_cpu_init_dm(void) /* TODO(sjg@chromium.org): Get rid of gd->hose */ gd->hose = hose;
+ ret = uclass_first_device(UCLASS_LPC, &dev); + if (!dev) + return -ENODEV; + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT; diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index af5d4a8..51a4073 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -559,6 +559,11 @@ void lpc_enable(pci_dev_t dev) setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); }
+static int bd82x6x_lpc_probe(struct udevice *dev) +{ + return 0; +} + static const struct udevice_id bd82x6x_lpc_ids[] = { { .compatible = "intel,bd82x6x-lpc" }, { } @@ -568,4 +573,5 @@ U_BOOT_DRIVER(bd82x6x_lpc_drv) = { .name = "lpc", .id = UCLASS_LPC, .of_match = bd82x6x_lpc_ids, + .probe = bd82x6x_lpc_probe, }; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index a5c5dc1..d5c5bfd 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -223,6 +223,7 @@ compatible = "intel,bd82x6x-lpc"; #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc; cros-ec@200 { compatible = "google,cros-ec"; reg = <0x204 1 0x200 1 0x880 0x80>;
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 3 +++ arch/x86/cpu/ivybridge/cpu.c | 6 +++++- arch/x86/cpu/ivybridge/lpc.c | 6 ++++++ arch/x86/dts/chromebook_link.dts | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:05 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 3 +++ arch/x86/cpu/ivybridge/cpu.c | 6 +++++- arch/x86/cpu/ivybridge/lpc.c | 6 ++++++ arch/x86/dts/chromebook_link.dts | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Drop unused 'gen-dec' device tree property
arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 32 ++++++++++++++++++++++++------- arch/x86/dts/chromebook_link.dts | 3 +-- arch/x86/include/asm/arch-ivybridge/pch.h | 10 ---------- 4 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 6ffc843..4c6ffb2 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -124,10 +124,8 @@ int arch_cpu_init(void)
int arch_cpu_init_dm(void) { - const void *blob = gd->fdt_blob; struct pci_controller *hose; struct udevice *bus, *dev; - int node; int ret;
post_code(0x70); @@ -145,13 +143,6 @@ int arch_cpu_init_dm(void) if (!dev) return -ENODEV;
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); - if (node < 0) - return -ENOENT; - ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); - if (ret) - return ret; - enable_spi_prefetch(hose, PCH_LPC_DEV);
/* This is already done in start.S, but let's do it in C */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 51a4073..9d089c7 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -454,7 +454,13 @@ static void pch_fixups(pci_dev_t dev) setbits_le32(RCB_REG(0x21a8), 0x3); }
-int lpc_early_init(const void *blob, int node, pci_dev_t dev) +/** + * lpc_early_init() - set up LPC serial ports and other early things + * + * @dev: LPC device + * @return 0 if OK, -ve on error + */ +static int lpc_early_init(struct udevice *dev) { struct reg_info { u32 base; @@ -463,17 +469,18 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) int count; int i;
- count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec", - (u32 *)values, sizeof(values) / sizeof(u32)); + count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, + "intel,gen-dec", (u32 *)values, + sizeof(values) / sizeof(u32)); if (count < 0) return -EINVAL;
/* Set COM1/COM2 decode range */ - x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010); + dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ - x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | - GAMEL_LPC_EN | COMA_LPC_EN); + dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + GAMEL_LPC_EN | COMA_LPC_EN);
/* Write all registers but use 0 if we run out of data */ count = count * sizeof(u32) / sizeof(values[0]); @@ -482,7 +489,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
if (i < count) reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); - x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg); + dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg); }
return 0; @@ -561,6 +568,17 @@ void lpc_enable(pci_dev_t dev)
static int bd82x6x_lpc_probe(struct udevice *dev) { + int ret; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + ret = lpc_early_init(dev); + if (ret) { + debug("%s: lpc_early_init() failed\n", __func__); + return ret; + } + return 0; }
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index d5c5bfd..f2db844 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -192,8 +192,6 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - gen-dec = <0x800 0xfc 0x900 0xfc>; - intel,gen-dec = <0x800 0xfc 0x900 0xfc>; intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b 0x80 0x80 0x80 0x80>; intel,gpi-routing = <0 0 0 0 0 0 0 2 @@ -224,6 +222,7 @@ #address-cells = <1>; #size-cells = <0>; u-boot,dm-pre-reloc; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; cros-ec@200 { compatible = "google,cros-ec"; reg = <0x204 1 0x200 1 0x880 0x80>; diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 31437c8..19cd7e5 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -473,14 +473,4 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); int lpc_init(struct pci_controller *hose, pci_dev_t dev); void lpc_enable(pci_dev_t dev);
-/** - * lpc_early_init() - set up LPC serial ports and other early things - * - * @blob: Device tree blob - * @node: Offset of LPC node - * @dev: PCH PCI device containing the LPC - * @return 0 if OK, -ve on error - */ -int lpc_early_init(const void *blob, int node, pci_dev_t dev); - #endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop unused 'gen-dec' device tree property
arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 32 ++++++++++++++++++++++++------- arch/x86/dts/chromebook_link.dts | 3 +-- arch/x86/include/asm/arch-ivybridge/pch.h | 10 ---------- 4 files changed, 26 insertions(+), 28 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:14 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop unused 'gen-dec' device tree property
arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 32 ++++++++++++++++++++++++------- arch/x86/dts/chromebook_link.dts | 3 +-- arch/x86/include/asm/arch-ivybridge/pch.h | 10 ---------- 4 files changed, 26 insertions(+), 28 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 43 ------------------------------------------- arch/x86/cpu/ivybridge/lpc.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 4c6ffb2..1e6f656 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -30,26 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) -{ - /* Enable port 80 POST on LPC */ - pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); - clrbits_le32(RCB_REG(GCS), 4); -} - -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) -{ - u8 reg8; - - pci_hose_read_config_byte(hose, dev, 0xdc, ®8); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_hose_write_config_byte(hose, dev, 0xdc, reg8); -} - static int set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -99,22 +79,6 @@ static int set_flex_ratio_to_tdp_nominal(void) return -EINVAL; }
-static void set_spi_speed(void) -{ - u32 fdod; - - /* Observe SPI Descriptor Component Section 0 */ - writel(0x1000, RCB_REG(SPI_DESC_COMP0)); - - /* Extract the1 Write/Erase SPI Frequency from descriptor */ - fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); - fdod >>= 24; - fdod &= 7; - - /* Set Software Sequence frequency to match */ - clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); -} - int arch_cpu_init(void) { post_code(POST_CPU_INIT); @@ -143,13 +107,6 @@ int arch_cpu_init_dm(void) if (!dev) return -ENODEV;
- enable_spi_prefetch(hose, PCH_LPC_DEV); - - /* This is already done in start.S, but let's do it in C */ - enable_port80_on_lpc(hose, PCH_LPC_DEV); - - set_spi_speed(); - /* * We should do as little as possible before the serial console is * up. Perhaps this should move to later. Our next lot of init diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 9d089c7..9dad9e4 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -454,6 +454,42 @@ static void pch_fixups(pci_dev_t dev) setbits_le32(RCB_REG(0x21a8), 0x3); }
+/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(struct udevice *pch) +{ + u8 reg8; + + dm_pci_read_config8(pch, 0xdc, ®8); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + dm_pci_write_config8(pch, 0xdc, reg8); +} + +static void enable_port80_on_lpc(struct udevice *pch) +{ + /* Enable port 80 POST on LPC */ + dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + clrbits_le32(RCB_REG(GCS), 4); +} + +static void set_spi_speed(void) +{ + u32 fdod; + + /* Observe SPI Descriptor Component Section 0 */ + writel(0x1000, RCB_REG(SPI_DESC_COMP0)); + + /* Extract the1 Write/Erase SPI Frequency from descriptor */ + fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); + fdod >>= 24; + fdod &= 7; + + /* Set Software Sequence frequency to match */ + clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); +} + /** * lpc_early_init() - set up LPC serial ports and other early things * @@ -492,6 +528,13 @@ static int lpc_early_init(struct udevice *dev) dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg); }
+ enable_spi_prefetch(dev->parent); + + /* This is already done in start.S, but let's do it in C */ + enable_port80_on_lpc(dev->parent); + + set_spi_speed(); + return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 43 ------------------------------------------- arch/x86/cpu/ivybridge/lpc.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 43 deletions(-)
applied to u-boot-x86/master, thanks!
Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Drop the init() method in the PCH - Rename this commit from 'x86: ivybridge: Set up the PCH init'
arch/x86/cpu/ivybridge/bd82x6x.c | 2 +- arch/x86/cpu/ivybridge/cpu.c | 8 ++++++++ arch/x86/cpu/ivybridge/pci.c | 2 +- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 72f2ed4..6556eeb 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -102,7 +102,7 @@ static int bd82x6x_probe(struct udevice *dev) }
/* TODO(sjg@chromium.org): Move this to the PCH init() method */ -int bd82x6x_init(void) +int bd82x6x_init_extra(void) { const void *blob = gd->fdt_blob; int sata_node; diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 1e6f656..2a15fc0 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -15,6 +15,7 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <pch.h> #include <asm/cpu.h> #include <asm/io.h> #include <asm/lapic.h> @@ -211,6 +212,7 @@ int print_cpuinfo(void) { enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; char processor_name[CPU_MAX_NAME_LEN]; + struct udevice *dev; const char *name; uint32_t pm1_cnt; uint16_t pm1_sts; @@ -241,6 +243,12 @@ int print_cpuinfo(void) }
/* Early chipset init required before RAM init can work */ + ret = uclass_first_device(UCLASS_PCH, &dev); + if (ret) + return ret; + if (!dev) + return -ENODEV; + sandybridge_early_init(SANDYBRIDGE_MOBILE);
/* Check PM1_STS[15] to see if we are waking from Sx */ diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c index 5e90f30..8af99b4 100644 --- a/arch/x86/cpu/ivybridge/pci.c +++ b/arch/x86/cpu/ivybridge/pci.c @@ -26,7 +26,7 @@ static int pci_ivybridge_probe(struct udevice *bus) if (!(gd->flags & GD_FLG_RELOC)) return 0; post_code(0x50); - bd82x6x_init(); + bd82x6x_init_extra(); post_code(0x51);
reg16 = 0xff; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index fcdf6e2..d76cb8d 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -13,7 +13,7 @@ void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node); -int bd82x6x_init(void); +int bd82x6x_init_extra(void);
/** * struct x86_cpu_priv - Information about a single CPU
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop the init() method in the PCH
- Rename this commit from 'x86: ivybridge: Set up the PCH init'
arch/x86/cpu/ivybridge/bd82x6x.c | 2 +- arch/x86/cpu/ivybridge/cpu.c | 8 ++++++++ arch/x86/cpu/ivybridge/pci.c | 2 +- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:18 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop the init() method in the PCH
- Rename this commit from 'x86: ivybridge: Set up the PCH init'
arch/x86/cpu/ivybridge/bd82x6x.c | 2 +- arch/x86/cpu/ivybridge/cpu.c | 8 ++++++++ arch/x86/cpu/ivybridge/pci.c | 2 +- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Add a uclass for the northbridge / SDRAM controller found on some older Intel chipsets.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Drop unnecessary DECLARE_GLOBAL_DATA_PTR
arch/x86/lib/Makefile | 1 + arch/x86/lib/northbridge-uclass.c | 15 +++++++++++++++ include/dm/uclass-id.h | 1 + 3 files changed, 17 insertions(+) create mode 100644 arch/x86/lib/northbridge-uclass.c
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 43792bc..d9fc296 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -19,6 +19,7 @@ obj-y += lpc-uclass.o obj-y += mpspec.o obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o obj-y += cmd_mtrr.o +obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o ifndef CONFIG_DM_PCI diff --git a/arch/x86/lib/northbridge-uclass.c b/arch/x86/lib/northbridge-uclass.c new file mode 100644 index 0000000..64b6257 --- /dev/null +++ b/arch/x86/lib/northbridge-uclass.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/root.h> + +UCLASS_DRIVER(northbridge) = { + .id = UCLASS_NORTHBRIDGE, + .name = "northbridge", +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index ef145af..4a6827b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -46,6 +46,7 @@ enum uclass_id { UCLASS_MMC, /* SD / MMC card or chip */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ UCLASS_MTD, /* Memory Technology Device (MTD) device */ + UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */ UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Add a uclass for the northbridge / SDRAM controller found on some older Intel chipsets.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Drop unnecessary DECLARE_GLOBAL_DATA_PTR
arch/x86/lib/Makefile | 1 + arch/x86/lib/northbridge-uclass.c | 15 +++++++++++++++ include/dm/uclass-id.h | 1 + 3 files changed, 17 insertions(+) create mode 100644 arch/x86/lib/northbridge-uclass.c
applied to u-boot-x86/master, thanks!
Add a driver with an empty probe function where we can move init code in follow-on patches.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/early_init.c | 18 ++++++++++++++++++ arch/x86/dts/chromebook_link.dts | 7 +++++++ 2 files changed, 25 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 9ca008e..945ae2d 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -8,6 +8,7 @@ */
#include <common.h> +#include <dm.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/arch/pch.h> @@ -145,3 +146,20 @@ void sandybridge_early_init(int chipset_type)
sandybridge_setup_graphics(pch_dev, video_dev); } + +static int bd82x6x_northbridge_probe(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id bd82x6x_northbridge_ids[] = { + { .compatible = "intel,bd82x6x-northbridge" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { + .name = "bd82x6x_northbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = bd82x6x_northbridge_ids, + .probe = bd82x6x_northbridge_probe, +}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index f2db844..e2c722d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -166,6 +166,13 @@ ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x1000 0x1000 0 0xefff>; + + northbridge@0,0 { + reg = <0x00000000 0 0 0 0>; + compatible = "intel,bd82x6x-northbridge"; + u-boot,dm-pre-reloc; + }; + sata { compatible = "intel,pantherpoint-ahci"; intel,sata-mode = "ahci";
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Add a driver with an empty probe function where we can move init code in follow-on patches.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/early_init.c | 18 ++++++++++++++++++ arch/x86/dts/chromebook_link.dts | 7 +++++++ 2 files changed, 25 insertions(+)
applied to u-boot-x86/master, thanks!
Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 2 ++ arch/x86/cpu/ivybridge/early_init.c | 33 +++++++++++++++++++-------------- 2 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 2a15fc0..f32b4a1 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -243,6 +243,8 @@ int print_cpuinfo(void) }
/* Early chipset init required before RAM init can work */ + uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + ret = uclass_first_device(UCLASS_PCH, &dev); if (ret) return ret; diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 945ae2d..c629f5b 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -123,20 +123,6 @@ void sandybridge_early_init(int chipset_type) pci_dev_t pch_dev = PCH_DEV; pci_dev_t video_dev = PCH_VIDEO_DEV; pci_dev_t lpc_dev = PCH_LPC_DEV; - u32 capid0_a; - u8 reg8; - - /* Device ID Override Enable should be done very early */ - capid0_a = x86_pci_read_config32(pch_dev, 0xe4); - if (capid0_a & (1 << 10)) { - reg8 = x86_pci_read_config8(pch_dev, 0xf3); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == SANDYBRIDGE_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - x86_pci_write_config8(pch_dev, 0xf3, reg8); - }
/* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(pch_dev, lpc_dev); @@ -149,6 +135,25 @@ void sandybridge_early_init(int chipset_type)
static int bd82x6x_northbridge_probe(struct udevice *dev) { + const int chipset_type = SANDYBRIDGE_MOBILE; + u32 capid0_a; + u8 reg8; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + /* Device ID Override Enable should be done very early */ + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 10)) { + dm_pci_read_config8(dev, 0xf3, ®8); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + dm_pci_write_config8(dev, 0xf3, reg8); + } + return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 2 ++ arch/x86/cpu/ivybridge/early_init.c | 33 +++++++++++++++++++-------------- 2 files changed, 21 insertions(+), 14 deletions(-)
applied to u-boot-x86/master, thanks!
Move more code into the northbridge probe() function.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/early_init.c | 47 +++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 23 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index c629f5b..029f5ef 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -14,7 +14,7 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>
-static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev) +static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev) { /* Setting up Southbridge. In the northbridge code. */ debug("Setting up static southbridge registers\n"); @@ -26,30 +26,31 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev) debug("Disabling watchdog reboot\n"); setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ +}
+static void sandybridge_setup_northbridge_bars(struct udevice *dev) +{ /* Set up all hardcoded northbridge BARs */ debug("Setting up static registers\n"); - x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1); - x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1); - x86_pci_write_config32(pch_dev, MCHBAR + 4, - (0LL + DEFAULT_MCHBAR) >> 32); + dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); + dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); + dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); /* 64MB - busses 0-63 */ - x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); - x86_pci_write_config32(pch_dev, PCIEXBAR + 4, - (0LL + DEFAULT_PCIEXBAR) >> 32); - x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1); - x86_pci_write_config32(pch_dev, DMIBAR + 4, - (0LL + DEFAULT_DMIBAR) >> 32); + dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + dm_pci_write_config32(dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); + dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */ - x86_pci_write_config8(pch_dev, PAM0, 0x30); - x86_pci_write_config8(pch_dev, PAM1, 0x33); - x86_pci_write_config8(pch_dev, PAM2, 0x33); - x86_pci_write_config8(pch_dev, PAM3, 0x33); - x86_pci_write_config8(pch_dev, PAM4, 0x33); - x86_pci_write_config8(pch_dev, PAM5, 0x33); - x86_pci_write_config8(pch_dev, PAM6, 0x33); + dm_pci_write_config8(dev, PAM0, 0x30); + dm_pci_write_config8(dev, PAM1, 0x33); + dm_pci_write_config8(dev, PAM2, 0x33); + dm_pci_write_config8(dev, PAM3, 0x33); + dm_pci_write_config8(dev, PAM4, 0x33); + dm_pci_write_config8(dev, PAM5, 0x33); + dm_pci_write_config8(dev, PAM6, 0x33); }
static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) @@ -122,10 +123,6 @@ void sandybridge_early_init(int chipset_type) { pci_dev_t pch_dev = PCH_DEV; pci_dev_t video_dev = PCH_VIDEO_DEV; - pci_dev_t lpc_dev = PCH_LPC_DEV; - - /* Setup all BARs required for early PCIe and raminit */ - sandybridge_setup_bars(pch_dev, lpc_dev);
/* Device Enable */ x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); @@ -154,6 +151,10 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) dm_pci_write_config8(dev, 0xf3, reg8); }
+ sandybridge_setup_lpc_bars(PCH_LPC_DEV); + + sandybridge_setup_northbridge_bars(dev); + return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Move more code into the northbridge probe() function.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/early_init.c | 47 +++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 23 deletions(-)
applied to u-boot-x86/master, thanks!
In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 2 +- arch/x86/cpu/ivybridge/lpc.c | 2 +- arch/x86/include/asm/arch-ivybridge/pch.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 6556eeb..c71596d 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -70,7 +70,7 @@ static int bd82x6x_probe(struct udevice *dev)
hose = pci_bus_to_hose(0); lpc_enable(PCH_LPC_DEV); - lpc_init(hose, PCH_LPC_DEV); + lpc_init_extra(hose, PCH_LPC_DEV); sata_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PANTHERPOINT_AHCI); if (sata_node < 0) { diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 9dad9e4..9f41f22 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -538,7 +538,7 @@ static int lpc_early_init(struct udevice *dev) return 0; }
-int lpc_init(struct pci_controller *hose, pci_dev_t dev) +int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev) { const void *blob = gd->fdt_blob; int node; diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 19cd7e5..f35803b 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -470,7 +470,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66
-int lpc_init(struct pci_controller *hose, pci_dev_t dev); +int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev); void lpc_enable(pci_dev_t dev);
#endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 2 +- arch/x86/cpu/ivybridge/lpc.c | 2 +- arch/x86/include/asm/arch-ivybridge/pch.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:23 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 2 +- arch/x86/cpu/ivybridge/lpc.c | 2 +- arch/x86/include/asm/arch-ivybridge/pch.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Drop explicit PCH probe - Drop LPC init method - Rename patch from 'Add an init() method for the bd82x6x LPC'
arch/x86/cpu/ivybridge/cpu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index f32b4a1..65eea1f 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -212,7 +212,7 @@ int print_cpuinfo(void) { enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; char processor_name[CPU_MAX_NAME_LEN]; - struct udevice *dev; + struct udevice *dev, *lpc; const char *name; uint32_t pm1_cnt; uint16_t pm1_sts; @@ -245,12 +245,11 @@ int print_cpuinfo(void) /* Early chipset init required before RAM init can work */ uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
- ret = uclass_first_device(UCLASS_PCH, &dev); + ret = uclass_first_device(UCLASS_LPC, &lpc); if (ret) return ret; if (!dev) return -ENODEV; - sandybridge_early_init(SANDYBRIDGE_MOBILE);
/* Check PM1_STS[15] to see if we are waking from Sx */
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop explicit PCH probe
- Drop LPC init method
- Rename patch from 'Add an init() method for the bd82x6x LPC'
arch/x86/cpu/ivybridge/cpu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:25 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop explicit PCH probe
- Drop LPC init method
- Rename patch from 'Add an init() method for the bd82x6x LPC'
arch/x86/cpu/ivybridge/cpu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/ivybridge/early_init.c | 80 ++----------------------------------- arch/x86/cpu/ivybridge/gma.c | 73 +++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 78 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 65eea1f..c3626c4 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -250,7 +250,6 @@ int print_cpuinfo(void) return ret; if (!dev) return -ENODEV; - sandybridge_early_init(SANDYBRIDGE_MOBILE);
/* Check PM1_STS[15] to see if we are waking from Sx */ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 029f5ef..83ef7b7 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -53,83 +53,6 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) dm_pci_write_config8(dev, PAM6, 0x33); }
-static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) -{ - u32 reg32; - u16 reg16; - u8 reg8; - - reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID); - switch (reg16) { - case 0x0102: /* GT1 Desktop */ - case 0x0106: /* GT1 Mobile */ - case 0x010a: /* GT1 Server */ - case 0x0112: /* GT2 Desktop */ - case 0x0116: /* GT2 Mobile */ - case 0x0122: /* GT2 Desktop >=1.3GHz */ - case 0x0126: /* GT2 Mobile >=1.3GHz */ - case 0x0156: /* IvyBridge */ - case 0x0166: /* IvyBridge */ - break; - default: - debug("Graphics not supported by this CPU/chipset\n"); - return; - } - - debug("Initialising Graphics\n"); - - /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ - reg16 = x86_pci_read_config16(pch_dev, GGC); - reg16 &= ~0x00f8; - reg16 |= 1 << 3; - /* Program GTT memory by setting GGC[9:8] = 2MB */ - reg16 &= ~0x0300; - reg16 |= 2 << 8; - /* Enable VGA decode */ - reg16 &= ~0x0002; - x86_pci_write_config16(pch_dev, GGC, reg16); - - /* Enable 256MB aperture */ - reg8 = x86_pci_read_config8(video_dev, MSAC); - reg8 &= ~0x06; - reg8 |= 0x02; - x86_pci_write_config8(video_dev, MSAC, reg8); - - /* Erratum workarounds */ - reg32 = readl(MCHBAR_REG(0x5f00)); - reg32 |= (1 << 9) | (1 << 10); - writel(reg32, MCHBAR_REG(0x5f00)); - - /* Enable SA Clock Gating */ - reg32 = readl(MCHBAR_REG(0x5f00)); - writel(reg32 | 1, MCHBAR_REG(0x5f00)); - - /* GPU RC6 workaround for sighting 366252 */ - reg32 = readl(MCHBAR_REG(0x5d14)); - reg32 |= (1 << 31); - writel(reg32, MCHBAR_REG(0x5d14)); - - /* VLW */ - reg32 = readl(MCHBAR_REG(0x6120)); - reg32 &= ~(1 << 0); - writel(reg32, MCHBAR_REG(0x6120)); - - reg32 = readl(MCHBAR_REG(0x5418)); - reg32 |= (1 << 4) | (1 << 5); - writel(reg32, MCHBAR_REG(0x5418)); -} - -void sandybridge_early_init(int chipset_type) -{ - pci_dev_t pch_dev = PCH_DEV; - pci_dev_t video_dev = PCH_VIDEO_DEV; - - /* Device Enable */ - x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); - - sandybridge_setup_graphics(pch_dev, video_dev); -} - static int bd82x6x_northbridge_probe(struct udevice *dev) { const int chipset_type = SANDYBRIDGE_MOBILE; @@ -155,6 +78,9 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
sandybridge_setup_northbridge_bars(dev);
+ /* Device Enable */ + dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + return 0; }
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 85a09c6..1748f7f 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -8,6 +8,7 @@
#include <common.h> #include <bios_emul.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <pci_rom.h> @@ -728,16 +729,88 @@ static int int15_handler(void) return res; }
+void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev) +{ + u32 reg32; + u16 reg16; + u8 reg8; + + dm_pci_read_config16(video_dev, PCI_DEVICE_ID, ®16); + switch (reg16) { + case 0x0102: /* GT1 Desktop */ + case 0x0106: /* GT1 Mobile */ + case 0x010a: /* GT1 Server */ + case 0x0112: /* GT2 Desktop */ + case 0x0116: /* GT2 Mobile */ + case 0x0122: /* GT2 Desktop >=1.3GHz */ + case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0156: /* IvyBridge */ + case 0x0166: /* IvyBridge */ + break; + default: + debug("Graphics not supported by this CPU/chipset\n"); + return; + } + + debug("Initialising Graphics\n"); + + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + dm_pci_read_config16(dev, GGC, ®16); + reg16 &= ~0x00f8; + reg16 |= 1 << 3; + /* Program GTT memory by setting GGC[9:8] = 2MB */ + reg16 &= ~0x0300; + reg16 |= 2 << 8; + /* Enable VGA decode */ + reg16 &= ~0x0002; + dm_pci_write_config16(dev, GGC, reg16); + + /* Enable 256MB aperture */ + dm_pci_read_config8(video_dev, MSAC, ®8); + reg8 &= ~0x06; + reg8 |= 0x02; + dm_pci_write_config8(video_dev, MSAC, reg8); + + /* Erratum workarounds */ + reg32 = readl(MCHBAR_REG(0x5f00)); + reg32 |= (1 << 9) | (1 << 10); + writel(reg32, MCHBAR_REG(0x5f00)); + + /* Enable SA Clock Gating */ + reg32 = readl(MCHBAR_REG(0x5f00)); + writel(reg32 | 1, MCHBAR_REG(0x5f00)); + + /* GPU RC6 workaround for sighting 366252 */ + reg32 = readl(MCHBAR_REG(0x5d14)); + reg32 |= (1 << 31); + writel(reg32, MCHBAR_REG(0x5d14)); + + /* VLW */ + reg32 = readl(MCHBAR_REG(0x6120)); + reg32 &= ~(1 << 0); + writel(reg32, MCHBAR_REG(0x6120)); + + reg32 = readl(MCHBAR_REG(0x5418)); + reg32 |= (1 << 4) | (1 << 5); + writel(reg32, MCHBAR_REG(0x5418)); +} + int gma_func0_init(struct udevice *dev, const void *blob, int node) { #ifdef CONFIG_VIDEO ulong start; #endif + struct udevice *nbridge; void *gtt_bar; ulong base; u32 reg32; int ret;
+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge); + if (!nbridge) + return -ENODEV; + sandybridge_setup_graphics(nbridge, dev); + /* IGD needs to be Bus Master */ dm_pci_read_config32(dev, PCI_COMMAND, ®32); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/ivybridge/early_init.c | 80 ++----------------------------------- arch/x86/cpu/ivybridge/gma.c | 73 +++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 78 deletions(-)
applied to u-boot-x86/master, thanks!
The watchdog can be reset later when probing the LPC after relocation. Move it.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Update to drop LPC init method and use probe() instead
arch/x86/cpu/ivybridge/early_init.c | 16 ---------------- arch/x86/cpu/ivybridge/lpc.c | 19 ++++++++++++++++++- 2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 83ef7b7..5b16abc 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -14,20 +14,6 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>
-static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev) -{ - /* Setting up Southbridge. In the northbridge code. */ - debug("Setting up static southbridge registers\n"); - x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); - - x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1); - x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ - - debug("Disabling watchdog reboot\n"); - setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ -} - static void sandybridge_setup_northbridge_bars(struct udevice *dev) { /* Set up all hardcoded northbridge BARs */ @@ -74,8 +60,6 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) dm_pci_write_config8(dev, 0xf3, reg8); }
- sandybridge_setup_lpc_bars(PCH_LPC_DEV); - sandybridge_setup_northbridge_bars(dev);
/* Device Enable */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 9f41f22..c88733d 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -609,6 +609,23 @@ void lpc_enable(pci_dev_t dev) setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); }
+static int bd82x6x_lpc_early_init(struct udevice *dev) +{ + /* Setting up Southbridge. In the northbridge code. */ + debug("Setting up static southbridge registers\n"); + dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); + + /* Enable ACPI BAR */ + dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80); + + debug("Disabling watchdog reboot\n"); + setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ + outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + + return 0; +} + static int bd82x6x_lpc_probe(struct udevice *dev) { int ret; @@ -622,7 +639,7 @@ static int bd82x6x_lpc_probe(struct udevice *dev) return ret; }
- return 0; + return bd82x6x_lpc_early_init(dev); }
static const struct udevice_id bd82x6x_lpc_ids[] = {
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
The watchdog can be reset later when probing the LPC after relocation. Move it.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Update to drop LPC init method and use probe() instead
arch/x86/cpu/ivybridge/early_init.c | 16 ---------------- arch/x86/cpu/ivybridge/lpc.c | 19 ++++++++++++++++++- 2 files changed, 18 insertions(+), 17 deletions(-)
applied to u-boot-x86/master, thanks!
This init can happen in the driver also. Move it.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 4 ---- arch/x86/cpu/ivybridge/lpc.c | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index c3626c4..6d3f477 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -278,10 +278,6 @@ int print_cpuinfo(void)
gd->arch.pei_boot_mode = boot_mode;
- /* TODO: Move this to the board or driver */ - x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); - /* Print processor name */ name = cpu_get_name(processor_name); printf("CPU: %s\n", name); diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index c88733d..0d85de2 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -623,6 +623,9 @@ static int bd82x6x_lpc_early_init(struct udevice *dev) setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+ dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1); + dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10); + return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This init can happen in the driver also. Move it.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 4 ---- arch/x86/cpu/ivybridge/lpc.c | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-)
applied to u-boot-x86/master, thanks!
The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 94 ++++++++++++++++-------------------- arch/x86/dts/chromebook_link.dts | 34 +++++++++++++ configs/chromebook_link_defconfig | 3 ++ 3 files changed, 79 insertions(+), 52 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index fd7db97..9fa1226 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -8,10 +8,13 @@ */
#include <common.h> +#include <cpu.h> +#include <dm.h> #include <fdtdec.h> #include <malloc.h> #include <asm/acpi.h> #include <asm/cpu.h> +#include <asm/cpu_x86.h> #include <asm/lapic.h> #include <asm/msr.h> #include <asm/mtrr.h> @@ -400,55 +403,6 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif
-/* - * Initialize any extra cores/threads in this package. - */ -static int intel_cores_init(struct x86_cpu_priv *cpu) -{ - struct cpuid_result result; - unsigned threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - debug("CPU: %u has %u cores, %u threads per core\n", - cpu->apic_id, threads_per_package / threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct x86_cpu_priv *new_cpu; - - new_cpu = calloc(1, sizeof(*new_cpu)); - if (!new_cpu) - return -ENOMEM; - - new_cpu->apic_id = cpu->apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads_per_core == 1) - new_cpu->apic_id <<= 1; - - debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id); - -#if 0 && CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* TODO(sjg@chromium.org): Start the new cpu */ - if (!start_cpu(new_cpu)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new_cpu->apic_id); - new_cpu->start_err = 1; - } -#endif - } - - return 0; -} - int model_206ax_init(struct x86_cpu_priv *cpu) { int ret; @@ -492,8 +446,10 @@ int model_206ax_init(struct x86_cpu_priv *cpu)
/* Thermal throttle activation offset */ ret = configure_thermal_target(); - if (ret) + if (ret) { + debug("Cannot set thermal target\n"); return ret; + }
/* Enable Direct Cache Access */ configure_dca_cap(); @@ -507,8 +463,42 @@ int model_206ax_init(struct x86_cpu_priv *cpu) /* Enable Turbo */ turbo_enable();
- /* Start up extra cores */ - intel_cores_init(cpu); + return 0; +} + +static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info) +{ + info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU; + + return 0; +} + +static int model_206ax_get_count(struct udevice *dev) +{ + return 4; +}
+static int cpu_x86_model_206ax_probe(struct udevice *dev) +{ return 0; } + +static const struct cpu_ops cpu_x86_model_206ax_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = model_206ax_get_info, + .get_count = model_206ax_get_count, +}; + +static const struct udevice_id cpu_x86_model_206ax_ids[] = { + { .compatible = "intel,core-gen3" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = { + .name = "cpu_x86_model_206ax", + .id = UCLASS_CPU, + .of_match = cpu_x86_model_206ax_ids, + .bind = cpu_x86_bind, + .probe = cpu_x86_model_206ax_probe, + .ops = &cpu_x86_model_206ax_ops, +}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index e2c722d..3ed6662 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -18,6 +18,40 @@ silent_console = <0>; };
+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <3>; + intel,apic-id = <3>; + }; + + }; + gpioa { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index dbfbb97..06e4ce6 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -5,7 +5,9 @@ CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y CONFIG_HAVE_MRC=y CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y +CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -17,6 +19,7 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y +CONFIG_CPU=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 94 ++++++++++++++++-------------------- arch/x86/dts/chromebook_link.dts | 34 +++++++++++++ configs/chromebook_link_defconfig | 3 ++ 3 files changed, 79 insertions(+), 52 deletions(-)
applied to u-boot-x86/master, thanks!
Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 6 ------ arch/x86/cpu/ivybridge/model_206ax.c | 5 ++++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 15 --------------- 3 files changed, 4 insertions(+), 22 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index c71596d..149c1d2 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -61,7 +61,6 @@ static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; struct pci_controller *hose; - struct x86_cpu_priv *cpu; int sata_node, gma_node; int ret;
@@ -81,11 +80,6 @@ static int bd82x6x_probe(struct udevice *dev) bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
- cpu = calloc(1, sizeof(*cpu)); - if (!cpu) - return -ENOMEM; - model_206ax_init(cpu); - gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); if (gma_node < 0) { debug("%s: Cannot find GMA node\n", __func__); diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 9fa1226..6ab6ede 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -403,7 +403,7 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif
-int model_206ax_init(struct x86_cpu_priv *cpu) +static int model_206ax_init(void) { int ret;
@@ -480,6 +480,9 @@ static int model_206ax_get_count(struct udevice *dev)
static int cpu_x86_model_206ax_probe(struct udevice *dev) { + if (dev->seq == 0) + model_206ax_init(); + return 0; }
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index d76cb8d..fc7fc6d 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -15,19 +15,4 @@ void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node); int bd82x6x_init_extra(void);
-/** - * struct x86_cpu_priv - Information about a single CPU - * - * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is - * just a number representing the CPU core - * - * TODO: Move this to driver model once lifecycle is understood - */ -struct x86_cpu_priv { - int apic_id; - int start_err; -}; - -int model_206ax_init(struct x86_cpu_priv *cpu); - #endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 6 ------ arch/x86/cpu/ivybridge/model_206ax.c | 5 ++++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 15 --------------- 3 files changed, 4 insertions(+), 22 deletions(-)
applied to u-boot-x86/master, thanks!
This uses a non-existent node at present. It should use the first CPU node. The referenced property does not exist (the correct value is the default of 0), but this allows the follow-on init to complete.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 6ab6ede..a217954 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -283,18 +283,13 @@ static void configure_c_states(void) msr_write(MSR_PP1_CURRENT_CONFIG, msr); }
-static int configure_thermal_target(void) +static int configure_thermal_target(struct udevice *dev) { int tcc_offset; msr_t msr; - int node;
- /* Find pointer to CPU configuration */ - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_INTEL_MODEL_206AX); - if (node < 0) - return -ENOENT; - tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0); + tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset", + 0);
/* Set TCC activaiton offset if supported */ msr = msr_read(MSR_PLATFORM_INFO); @@ -403,7 +398,7 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif
-static int model_206ax_init(void) +static int model_206ax_init(struct udevice *dev) { int ret;
@@ -445,7 +440,7 @@ static int model_206ax_init(void) configure_misc();
/* Thermal throttle activation offset */ - ret = configure_thermal_target(); + ret = configure_thermal_target(dev); if (ret) { debug("Cannot set thermal target\n"); return ret; @@ -468,6 +463,10 @@ static int model_206ax_init(void)
static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info) { + msr_t msr; + + msr = msr_read(IA32_PERF_CTL); + info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000; info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
return 0; @@ -481,7 +480,7 @@ static int model_206ax_get_count(struct udevice *dev) static int cpu_x86_model_206ax_probe(struct udevice *dev) { if (dev->seq == 0) - model_206ax_init(); + model_206ax_init(dev);
return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This uses a non-existent node at present. It should use the first CPU node. The referenced property does not exist (the correct value is the default of 0), but this allows the follow-on init to complete.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-)
applied to u-boot-x86/master, thanks!
This is not used and MTRRs are set up elsewhere now. Drop it.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 10 ---------- 1 file changed, 10 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index a217954..9654600 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -412,16 +412,6 @@ static int model_206ax_init(struct udevice *dev) set_ehci_debug(0); #endif
- /* Setup MTRRs based on physical address size */ -#if 0 /* TODO: Implement this */ - struct cpuid_result cpuid_regs; - - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); - x86_mtrr_check(); -#endif - #if CONFIG_USBDEBUG set_ehci_debug(ehci_debug_addr); #endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This is not used and MTRRs are set up elsewhere now. Drop it.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 10 ---------- 1 file changed, 10 deletions(-)
applied to u-boot-x86/master, thanks!
This code is now part of the northbridge driver, so move it into the same place.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/early_init.c | 81 ------------------------------------ arch/x86/cpu/ivybridge/northbridge.c | 67 +++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 82 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/early_init.c
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 0c7efae..bdbd3fa 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,7 +7,6 @@ obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o -obj-y += early_init.o obj-y += early_me.o obj-y += gma.o obj-y += lpc.o diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c deleted file mode 100644 index 5b16abc..0000000 --- a/arch/x86/cpu/ivybridge/early_init.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * From Coreboot - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> -#include <asm/arch/sandybridge.h> - -static void sandybridge_setup_northbridge_bars(struct udevice *dev) -{ - /* Set up all hardcoded northbridge BARs */ - debug("Setting up static registers\n"); - dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); - dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); - dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); - /* 64MB - busses 0-63 */ - dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); - dm_pci_write_config32(dev, PCIEXBAR + 4, - (0LL + DEFAULT_PCIEXBAR) >> 32); - dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); - dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); - - /* Set C0000-FFFFF to access RAM on both reads and writes */ - dm_pci_write_config8(dev, PAM0, 0x30); - dm_pci_write_config8(dev, PAM1, 0x33); - dm_pci_write_config8(dev, PAM2, 0x33); - dm_pci_write_config8(dev, PAM3, 0x33); - dm_pci_write_config8(dev, PAM4, 0x33); - dm_pci_write_config8(dev, PAM5, 0x33); - dm_pci_write_config8(dev, PAM6, 0x33); -} - -static int bd82x6x_northbridge_probe(struct udevice *dev) -{ - const int chipset_type = SANDYBRIDGE_MOBILE; - u32 capid0_a; - u8 reg8; - - if (gd->flags & GD_FLG_RELOC) - return 0; - - /* Device ID Override Enable should be done very early */ - dm_pci_read_config32(dev, 0xe4, &capid0_a); - if (capid0_a & (1 << 10)) { - dm_pci_read_config8(dev, 0xf3, ®8); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == SANDYBRIDGE_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - dm_pci_write_config8(dev, 0xf3, reg8); - } - - sandybridge_setup_northbridge_bars(dev); - - /* Device Enable */ - dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); - - return 0; -} - -static const struct udevice_id bd82x6x_northbridge_ids[] = { - { .compatible = "intel,bd82x6x-northbridge" }, - { } -}; - -U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { - .name = "bd82x6x_northbridge", - .id = UCLASS_NORTHBRIDGE, - .of_match = bd82x6x_northbridge_ids, - .probe = bd82x6x_northbridge_probe, -}; diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index e3d8c13..6b00d31 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -8,6 +8,7 @@ */
#include <common.h> +#include <dm.h> #include <asm/msr.h> #include <asm/acpi.h> #include <asm/cpu.h> @@ -170,3 +171,69 @@ void northbridge_init(pci_dev_t dev) void northbridge_enable(pci_dev_t dev) { } + +static void sandybridge_setup_northbridge_bars(struct udevice *dev) +{ + /* Set up all hardcoded northbridge BARs */ + debug("Setting up static registers\n"); + dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); + dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); + dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + /* 64MB - busses 0-63 */ + dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + dm_pci_write_config32(dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); + dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + dm_pci_write_config8(dev, PAM0, 0x30); + dm_pci_write_config8(dev, PAM1, 0x33); + dm_pci_write_config8(dev, PAM2, 0x33); + dm_pci_write_config8(dev, PAM3, 0x33); + dm_pci_write_config8(dev, PAM4, 0x33); + dm_pci_write_config8(dev, PAM5, 0x33); + dm_pci_write_config8(dev, PAM6, 0x33); +} + +static int bd82x6x_northbridge_probe(struct udevice *dev) +{ + const int chipset_type = SANDYBRIDGE_MOBILE; + u32 capid0_a; + u8 reg8; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + /* Device ID Override Enable should be done very early */ + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 10)) { + dm_pci_read_config8(dev, 0xf3, ®8); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + dm_pci_write_config8(dev, 0xf3, reg8); + } + + sandybridge_setup_northbridge_bars(dev); + + /* Device Enable */ + dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + + return 0; +} + +static const struct udevice_id bd82x6x_northbridge_ids[] = { + { .compatible = "intel,bd82x6x-northbridge" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { + .name = "bd82x6x_northbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = bd82x6x_northbridge_ids, + .probe = bd82x6x_northbridge_probe, +};
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This code is now part of the northbridge driver, so move it into the same place.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/early_init.c | 81 ------------------------------------ arch/x86/cpu/ivybridge/northbridge.c | 67 +++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 82 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/early_init.c
applied to u-boot-x86/master, thanks!
There are no other implementations of this function, and boards that need it can implement a CPU driver.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Fix 'baords' typo in the commit message
arch/x86/cpu/cpu.c | 2 +- arch/x86/include/asm/u-boot-x86.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 381d835..3c812e9 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -688,7 +688,7 @@ static int x86_mp_init(void) } #endif
-__weak int x86_init_cpus(void) +static int x86_init_cpus(void) { #ifdef CONFIG_SMP debug("Init additional CPUs\n"); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index dbf8e95..9c143ca 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -77,8 +77,6 @@ uint64_t timer_get_tsc(void);
void quick_ram_check(void);
-int x86_init_cpus(void); - #define PCI_VGA_RAM_IMAGE_START 0xc0000
#endif /* _U_BOOT_I386_H_ */
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
There are no other implementations of this function, and boards that need it can implement a CPU driver.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Fix 'baords' typo in the commit message
arch/x86/cpu/cpu.c | 2 +- arch/x86/include/asm/u-boot-x86.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-)
applied to u-boot-x86/master, thanks!
When the final MRC cache record is the same as the one we want to write, we skip writing since there is no point. This is normal behaviour.
Avoiding printing an error when this happens.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/lib/mrccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 53a1259..67bace4 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -243,8 +243,12 @@ int mrccache_save(void) goto err_entry; data = (struct mrc_data_container *)gd->arch.mrc_output; ret = mrccache_update(sf, &entry, data); - if (!ret) + if (!ret) { debug("Saved MRC data with checksum %04x\n", data->checksum); + } else if (ret == -EEXIST) { + debug("MRC data is the same as last time, skipping save\n"); + ret = 0; + }
err_entry: if (ret)
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
When the final MRC cache record is the same as the one we want to write, we skip writing since there is no point. This is normal behaviour.
Avoiding printing an error when this happens.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/lib/mrccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
applied to u-boot-x86/master, thanks!
These devices currently need to be inited early in boot. Once we have the init in the right places (with each device doing its own init and no problems with ordering) we should be able to remove this. For now it is needed to keep things working.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add a comment as to why we are initing the devices again
arch/x86/cpu/cpu.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 3c812e9..6c3a748 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -709,8 +709,24 @@ static int x86_init_cpus(void)
int cpu_init_r(void) { - if (ll_boot_init()) - return x86_init_cpus(); + struct udevice *dev; + int ret; + + if (!ll_boot_init()) + return 0; + + ret = x86_init_cpus(); + if (ret) + return ret; + + /* + * Set up the northbridge, PCH and LPC if available. Note that these + * may have had some limited pre-relocation init if they were probed + * before relocation, but this is post relocation. + */ + uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + uclass_first_device(UCLASS_PCH, &dev); + uclass_first_device(UCLASS_LPC, &dev);
return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
These devices currently need to be inited early in boot. Once we have the init in the right places (with each device doing its own init and no problems with ordering) we should be able to remove this. For now it is needed to keep things working.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Add a comment as to why we are initing the devices again
arch/x86/cpu/cpu.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:48 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
These devices currently need to be inited early in boot. Once we have the init in the right places (with each device doing its own init and no problems with ordering) we should be able to remove this. For now it is needed to keep things working.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Add a comment as to why we are initing the devices again
arch/x86/cpu/cpu.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 42 --------------------------- arch/x86/cpu/ivybridge/northbridge.c | 16 +++++++--- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - board/google/chromebook_link/link.c | 8 ----- 4 files changed, 12 insertions(+), 55 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 149c1d2..c5a5d4d 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -18,45 +18,6 @@
#define BIOS_CTRL 0xdc
-void bd82x6x_pci_init(pci_dev_t dev) -{ - u16 reg16; - u8 reg8; - - debug("bd82x6x PCI init.\n"); - /* Enable Bus Master */ - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - x86_pci_write_config16(dev, PCI_COMMAND, reg16); - - /* This device has no interrupt */ - x86_pci_write_config8(dev, INTR, 0xff); - - /* disable parity error response and SERR */ - reg16 = x86_pci_read_config16(dev, BCTRL); - reg16 &= ~(1 << 0); - reg16 &= ~(1 << 1); - x86_pci_write_config16(dev, BCTRL, reg16); - - /* Master Latency Count must be set to 0x04! */ - reg8 = x86_pci_read_config8(dev, SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - x86_pci_write_config8(dev, SMLT, reg8); - - /* Will this improve throughput of bus masters? */ - x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06); - - /* Clear errors in status registers */ - reg16 = x86_pci_read_config16(dev, PSTS); - /* reg16 |= 0xf900; */ - x86_pci_write_config16(dev, PSTS, reg16); - - reg16 = x86_pci_read_config16(dev, SECSTS); - /* reg16 |= 0xf900; */ - x86_pci_write_config16(dev, SECSTS, reg16); -} - static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; @@ -108,10 +69,7 @@ int bd82x6x_init_extra(void) return -EINVAL; }
- bd82x6x_pci_init(PCH_DEV); bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); - northbridge_enable(PCH_DEV); - northbridge_init(PCH_DEV);
return 0; } diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 6b00d31..2eed0af 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -197,15 +197,12 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) dm_pci_write_config8(dev, PAM6, 0x33); }
-static int bd82x6x_northbridge_probe(struct udevice *dev) +static int bd82x6x_northbridge_early_init(struct udevice *dev) { const int chipset_type = SANDYBRIDGE_MOBILE; u32 capid0_a; u8 reg8;
- if (gd->flags & GD_FLG_RELOC) - return 0; - /* Device ID Override Enable should be done very early */ dm_pci_read_config32(dev, 0xe4, &capid0_a); if (capid0_a & (1 << 10)) { @@ -226,6 +223,17 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) return 0; }
+static int bd82x6x_northbridge_probe(struct udevice *dev) +{ + if (!(gd->flags & GD_FLG_RELOC)) + return bd82x6x_northbridge_early_init(dev); + + northbridge_enable(PCH_DEV); + northbridge_init(PCH_DEV); + + return 0; +} + static const struct udevice_id bd82x6x_northbridge_ids[] = { { .compatible = "intel,bd82x6x-northbridge" }, { } diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index fc7fc6d..0f4fe47 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -9,7 +9,6 @@
void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); -void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node); diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 1b97a8f..d12d742 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -14,14 +14,6 @@
int arch_early_init_r(void) { - struct udevice *dev; - int ret; - - /* Make sure the platform controller hub is up and running */ - ret = uclass_get_device(UCLASS_PCH, 0, &dev); - if (ret) - return ret; - return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 42 --------------------------- arch/x86/cpu/ivybridge/northbridge.c | 16 +++++++--- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - board/google/chromebook_link/link.c | 8 ----- 4 files changed, 12 insertions(+), 55 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:54 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 42 --------------------------- arch/x86/cpu/ivybridge/northbridge.c | 16 +++++++--- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - board/google/chromebook_link/link.c | 8 ----- 4 files changed, 12 insertions(+), 55 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Adjust most of the remaining functions in this file to use the driver model PCI API. The one remaining function is bridge_silicon_revision() which will need a little more work.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Drop northbridge_enable()
arch/x86/cpu/ivybridge/northbridge.c | 20 +++++++------------- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 3 --- 2 files changed, 7 insertions(+), 16 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 2eed0af..d52eb39 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -48,15 +48,14 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384;
-static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len) { - pci_dev_t dev = PCI_BDF(0, 0, 0); u32 pciexbar_reg;
*base = 0; *len = 0;
- pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR); + dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg);
if (!(pciexbar_reg & (1 << 0))) return 0; @@ -82,17 +81,17 @@ static int get_pcie_bar(u32 *base, u32 *len) return 0; }
-static void add_fixed_resources(pci_dev_t dev, int index) +static void add_fixed_resources(struct udevice *dev, int index) { u32 pcie_config_base, pcie_config_size;
- if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { + if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) { debug("Adding PCIe config bar base=0x%08x size=0x%x\n", pcie_config_base, pcie_config_size); } }
-static void northbridge_dmi_init(pci_dev_t dev) +static void northbridge_dmi_init(struct udevice *dev) { /* Clear error status bits */ writel(0xffffffff, DMIBAR_REG(0x1c4)); @@ -120,7 +119,7 @@ static void northbridge_dmi_init(pci_dev_t dev) setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); }
-void northbridge_init(pci_dev_t dev) +static void northbridge_init(struct udevice *dev) { u32 bridge_type;
@@ -168,10 +167,6 @@ void northbridge_init(pci_dev_t dev) writel(0x00100001, MCHBAR_REG(0x5500)); }
-void northbridge_enable(pci_dev_t dev) -{ -} - static void sandybridge_setup_northbridge_bars(struct udevice *dev) { /* Set up all hardcoded northbridge BARs */ @@ -228,8 +223,7 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) if (!(gd->flags & GD_FLG_RELOC)) return bd82x6x_northbridge_early_init(dev);
- northbridge_enable(PCH_DEV); - northbridge_init(PCH_DEV); + northbridge_init(dev);
return 0; } diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index c960525..af8a9f7 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -110,9 +110,6 @@
int bridge_silicon_revision(void);
-void northbridge_enable(pci_dev_t dev); -void northbridge_init(pci_dev_t dev); - void report_platform_info(void);
void sandybridge_early_init(int chipset_type);
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Adjust most of the remaining functions in this file to use the driver model PCI API. The one remaining function is bridge_silicon_revision() which will need a little more work.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Drop northbridge_enable()
arch/x86/cpu/ivybridge/northbridge.c | 20 +++++++------------- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 3 --- 2 files changed, 7 insertions(+), 16 deletions(-)
applied to u-boot-x86/master, thanks!
This is done by default with PCI auto-config. Drop it.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Rename from 'Move northbridge setup to the northbridge driver' - Drop this unnecessary init
arch/x86/cpu/ivybridge/pci.c | 20 -------------------- 1 file changed, 20 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c index 8af99b4..b081469 100644 --- a/arch/x86/cpu/ivybridge/pci.c +++ b/arch/x86/cpu/ivybridge/pci.c @@ -19,32 +19,12 @@
static int pci_ivybridge_probe(struct udevice *bus) { - struct pci_controller *hose = dev_get_uclass_priv(bus); - pci_dev_t dev; - u16 reg16; - if (!(gd->flags & GD_FLG_RELOC)) return 0; post_code(0x50); bd82x6x_init_extra(); post_code(0x51);
- reg16 = 0xff; - dev = PCH_DEV; - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - x86_pci_write_config16(dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - - pci_write_bar32(hose, dev, 0, 0xf0000000); - post_code(0x52); - return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This is done by default with PCI auto-config. Drop it.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Rename from 'Move northbridge setup to the northbridge driver'
- Drop this unnecessary init
arch/x86/cpu/ivybridge/pci.c | 20 -------------------- 1 file changed, 20 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 2:57 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This is done by default with PCI auto-config. Drop it.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Rename from 'Move northbridge setup to the northbridge driver'
- Drop this unnecessary init
arch/x86/cpu/ivybridge/pci.c | 20 -------------------- 1 file changed, 20 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Add a uclass ID for a disk controller. This can be used by AHCI/SATA or other controller types. There are no operations and no interface so far, but it is possible to probe a SATA device.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Rename the AHCI uclass to DISK
drivers/block/Kconfig | 9 +++++++++ drivers/block/Makefile | 1 + drivers/block/disk-uclass.c | 14 ++++++++++++++ include/dm/uclass-id.h | 1 + 4 files changed, 25 insertions(+) create mode 100644 drivers/block/disk-uclass.c
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index e69de29..989b21d 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -0,0 +1,9 @@ +config DISK + bool "Support disk controllers with driver model" + depends on DM + default y if DM + help + This enables a uclass for disk controllers in U-Boot. Various driver + types can use this, such as AHCI/SATA. It does not provide any standard + operations at present. The block device interface has not been converted + to driver model. diff --git a/drivers/block/Makefile b/drivers/block/Makefile index eb8bda9..5eb87e0 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ #
+obj-$(CONFIG_DISK) += disk-uclass.o obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c new file mode 100644 index 0000000..d665b35 --- /dev/null +++ b/drivers/block/disk-uclass.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> + +UCLASS_DRIVER(disk) = { + .id = UCLASS_DISK, + .name = "disk", +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 4a6827b..2e10953 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -29,6 +29,7 @@ enum uclass_id { UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */ + UCLASS_DISK, /* Disk controller, e.g. SATA */ UCLASS_DISPLAY_PORT, /* Display port video */ UCLASS_RAM, /* RAM controller */ UCLASS_ETH, /* Ethernet device */
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Add a uclass ID for a disk controller. This can be used by AHCI/SATA or other controller types. There are no operations and no interface so far, but it is possible to probe a SATA device.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Rename the AHCI uclass to DISK
drivers/block/Kconfig | 9 +++++++++ drivers/block/Makefile | 1 + drivers/block/disk-uclass.c | 14 ++++++++++++++ include/dm/uclass-id.h | 1 + 4 files changed, 25 insertions(+) create mode 100644 drivers/block/disk-uclass.c
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index e69de29..989b21d 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -0,0 +1,9 @@ +config DISK
bool "Support disk controllers with driver model"depends on DMdefault y if DMhelpThis enables a uclass for disk controllers in U-Boot. Various driver
nits: one more space before "in U-Boot"
I can fix this when applying.
types can use this, such as AHCI/SATA. It does not provide any standardoperations at present. The block device interface has not been convertedto driver model.diff --git a/drivers/block/Makefile b/drivers/block/Makefile index eb8bda9..5eb87e0 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ #
+obj-$(CONFIG_DISK) += disk-uclass.o obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c new file mode 100644 index 0000000..d665b35 --- /dev/null +++ b/drivers/block/disk-uclass.c @@ -0,0 +1,14 @@ +/*
- Copyright (c) 2015 Google, Inc
- Written by Simon Glass sjg@chromium.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <dm.h>
+UCLASS_DRIVER(disk) = {
.id = UCLASS_DISK,.name = "disk",+}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 4a6827b..2e10953 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -29,6 +29,7 @@ enum uclass_id { UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_DISK, /* Disk controller, e.g. SATA */ UCLASS_DISPLAY_PORT, /* Display port video */ UCLASS_RAM, /* RAM controller */ UCLASS_ETH, /* Ethernet device */--
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 3:08 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Add a uclass ID for a disk controller. This can be used by AHCI/SATA or other controller types. There are no operations and no interface so far, but it is possible to probe a SATA device.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Rename the AHCI uclass to DISK
drivers/block/Kconfig | 9 +++++++++ drivers/block/Makefile | 1 + drivers/block/disk-uclass.c | 14 ++++++++++++++ include/dm/uclass-id.h | 1 + 4 files changed, 25 insertions(+) create mode 100644 drivers/block/disk-uclass.c
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index e69de29..989b21d 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -0,0 +1,9 @@ +config DISK
bool "Support disk controllers with driver model"depends on DMdefault y if DMhelpThis enables a uclass for disk controllers in U-Boot. Various drivernits: one more space before "in U-Boot"
I can fix this when applying.
Fixed nits, and
types can use this, such as AHCI/SATA. It does not provide any standardoperations at present. The block device interface has not been convertedto driver model.diff --git a/drivers/block/Makefile b/drivers/block/Makefile index eb8bda9..5eb87e0 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ #
+obj-$(CONFIG_DISK) += disk-uclass.o obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c new file mode 100644 index 0000000..d665b35 --- /dev/null +++ b/drivers/block/disk-uclass.c @@ -0,0 +1,14 @@ +/*
- Copyright (c) 2015 Google, Inc
- Written by Simon Glass sjg@chromium.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <dm.h>
+UCLASS_DRIVER(disk) = {
.id = UCLASS_DISK,.name = "disk",+}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 4a6827b..2e10953 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -29,6 +29,7 @@ enum uclass_id { UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_DISK, /* Disk controller, e.g. SATA */ UCLASS_DISPLAY_PORT, /* Display port video */ UCLASS_RAM, /* RAM controller */ UCLASS_ETH, /* Ethernet device */--
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Update to use the disk uclass
arch/x86/cpu/ivybridge/bd82x6x.c | 2 -- arch/x86/cpu/ivybridge/cpu.c | 3 +++ arch/x86/cpu/ivybridge/sata.c | 25 ++++++++++++++++++++++++- arch/x86/dts/chromebook_link.dts | 16 +++++++++------- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 5 files changed, 36 insertions(+), 11 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index c5a5d4d..8e98fa2 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -69,8 +69,6 @@ int bd82x6x_init_extra(void) return -EINVAL; }
- bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); - return 0; }
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 6d3f477..4cf2ba0 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -251,6 +251,9 @@ int print_cpuinfo(void) if (!dev) return -ENODEV;
+ /* Cause the SATA device to do its early init */ + uclass_first_device(UCLASS_DISK, &dev); + /* Check PM1_STS[15] to see if we are waking from Sx */ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index e7bf03c..c46ec3a 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -6,12 +6,15 @@ */
#include <common.h> +#include <dm.h> #include <fdtdec.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/arch/pch.h> #include <asm/arch/bd82x6x.h>
+DECLARE_GLOBAL_DATA_PTR; + static inline u32 sir_read(pci_dev_t dev, int idx) { x86_pci_write_config32(dev, SATA_SIRI, idx); @@ -206,7 +209,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); }
-void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) +static void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) { unsigned port_map; const char *mode; @@ -224,3 +227,23 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) map |= (port_map ^ 0x3f) << 8; x86_pci_write_config16(dev, 0x90, map); } + +static int bd82x6x_sata_probe(struct udevice *dev) +{ + if (!(gd->flags & GD_FLG_RELOC)) + bd82x6x_sata_enable(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset); + + return 0; +} + +static const struct udevice_id bd82x6x_ahci_ids[] = { + { .compatible = "intel,pantherpoint-ahci" }, + { } +}; + +U_BOOT_DRIVER(ahci_ivybridge_drv) = { + .name = "ahci_ivybridge", + .id = UCLASS_DISK, + .of_match = bd82x6x_ahci_ids, + .probe = bd82x6x_sata_probe, +}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 3ed6662..022b04c 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -207,13 +207,6 @@ u-boot,dm-pre-reloc; };
- sata { - compatible = "intel,pantherpoint-ahci"; - intel,sata-mode = "ahci"; - intel,sata-port-map = <1>; - intel,sata-port0-gen3-tx = <0x00880a7f>; - }; - gma { compatible = "intel,gma"; intel,dp_hotplug = <0 0 0x06>; @@ -281,6 +274,15 @@ }; }; }; + + sata@1f,2 { + compatible = "intel,pantherpoint-ahci"; + reg = <0x0000fa00 0 0 0 0>; + u-boot,dm-pre-reloc; + intel,sata-mode = "ahci"; + intel,sata-port-map = <1>; + intel,sata-port0-gen3-tx = <0x00880a7f>; + }; };
tpm { diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 0f4fe47..faae5ff 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -8,7 +8,6 @@ #define _ASM_ARCH_BD82X6X_H
void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); -void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node);
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Update to use the disk uclass
arch/x86/cpu/ivybridge/bd82x6x.c | 2 -- arch/x86/cpu/ivybridge/cpu.c | 3 +++ arch/x86/cpu/ivybridge/sata.c | 25 ++++++++++++++++++++++++- arch/x86/dts/chromebook_link.dts | 16 +++++++++------- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 5 files changed, 36 insertions(+), 11 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 3:10 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Update to use the disk uclass
arch/x86/cpu/ivybridge/bd82x6x.c | 2 -- arch/x86/cpu/ivybridge/cpu.c | 3 +++ arch/x86/cpu/ivybridge/sata.c | 25 ++++++++++++++++++++++++- arch/x86/dts/chromebook_link.dts | 16 +++++++++------- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 5 files changed, 36 insertions(+), 11 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
This function does nothing now so can be dropped.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 16 ---------------- arch/x86/cpu/ivybridge/pci.c | 1 - arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 3 files changed, 18 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 8e98fa2..1fe2ce1 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -56,22 +56,6 @@ static int bd82x6x_probe(struct udevice *dev) return 0; }
-/* TODO(sjg@chromium.org): Move this to the PCH init() method */ -int bd82x6x_init_extra(void) -{ - const void *blob = gd->fdt_blob; - int sata_node; - - sata_node = fdtdec_next_compatible(blob, 0, - COMPAT_INTEL_PANTHERPOINT_AHCI); - if (sata_node < 0) { - debug("%s: Cannot find SATA node\n", __func__); - return -EINVAL; - } - - return 0; -} - static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) { u32 rcba; diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c index b081469..5195002 100644 --- a/arch/x86/cpu/ivybridge/pci.c +++ b/arch/x86/cpu/ivybridge/pci.c @@ -22,7 +22,6 @@ static int pci_ivybridge_probe(struct udevice *bus) if (!(gd->flags & GD_FLG_RELOC)) return 0; post_code(0x50); - bd82x6x_init_extra(); post_code(0x51);
return 0; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index faae5ff..7a05c7e 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -11,6 +11,5 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node); -int bd82x6x_init_extra(void);
#endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This function does nothing now so can be dropped.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 16 ---------------- arch/x86/cpu/ivybridge/pci.c | 1 - arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 3 files changed, 18 deletions(-)
applied to u-boot-x86/master, thanks!
Instead of manually initing the device, probe the SATA device and move the init there.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Update to use the disk uclass
arch/x86/cpu/ivybridge/bd82x6x.c | 13 +++++-------- arch/x86/cpu/ivybridge/sata.c | 4 +++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 1fe2ce1..188b7da 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -22,7 +22,7 @@ static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; struct pci_controller *hose; - int sata_node, gma_node; + int gma_node; int ret;
if (!(gd->flags & GD_FLG_RELOC)) @@ -31,13 +31,10 @@ static int bd82x6x_probe(struct udevice *dev) hose = pci_bus_to_hose(0); lpc_enable(PCH_LPC_DEV); lpc_init_extra(hose, PCH_LPC_DEV); - sata_node = fdtdec_next_compatible(blob, 0, - COMPAT_INTEL_PANTHERPOINT_AHCI); - if (sata_node < 0) { - debug("%s: Cannot find SATA node\n", __func__); - return -EINVAL; - } - bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); + + /* Cause the SATA device to do its init */ + uclass_first_device(UCLASS_DISK, &dev); + bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index c46ec3a..6314566 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -47,7 +47,7 @@ static void common_sata_init(pci_dev_t dev, unsigned int port_map) x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); }
-void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) +static void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) { unsigned int port_map, speed_support, port_tx; struct pci_controller *hose = pci_bus_to_hose(0); @@ -232,6 +232,8 @@ static int bd82x6x_sata_probe(struct udevice *dev) { if (!(gd->flags & GD_FLG_RELOC)) bd82x6x_sata_enable(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset); + else + bd82x6x_sata_init(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset);
return 0; } diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 7a05c7e..bb3a6c9 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -7,7 +7,6 @@ #ifndef _ASM_ARCH_BD82X6X_H #define _ASM_ARCH_BD82X6X_H
-void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node);
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Instead of manually initing the device, probe the SATA device and move the init there.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Update to use the disk uclass
arch/x86/cpu/ivybridge/bd82x6x.c | 13 +++++-------- arch/x86/cpu/ivybridge/sata.c | 4 +++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 3 files changed, 8 insertions(+), 10 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 3:16 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Instead of manually initing the device, probe the SATA device and move the init there.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Update to use the disk uclass
arch/x86/cpu/ivybridge/bd82x6x.c | 13 +++++-------- arch/x86/cpu/ivybridge/sata.c | 4 +++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 3 files changed, 8 insertions(+), 10 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Adjust the functions in this file to use the driver model PCI API.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Drop unnecessary IRQ and command register init
arch/x86/cpu/ivybridge/sata.c | 94 +++++++++++++++++++++---------------------- 1 file changed, 45 insertions(+), 49 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index 6314566..21e11d1 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -15,42 +15,47 @@
DECLARE_GLOBAL_DATA_PTR;
-static inline u32 sir_read(pci_dev_t dev, int idx) +static inline u32 sir_read(struct udevice *dev, int idx) { - x86_pci_write_config32(dev, SATA_SIRI, idx); - return x86_pci_read_config32(dev, SATA_SIRD); + u32 data; + + dm_pci_write_config32(dev, SATA_SIRI, idx); + dm_pci_read_config32(dev, SATA_SIRD, &data); + + return data; }
-static inline void sir_write(pci_dev_t dev, int idx, u32 value) +static inline void sir_write(struct udevice *dev, int idx, u32 value) { - x86_pci_write_config32(dev, SATA_SIRI, idx); - x86_pci_write_config32(dev, SATA_SIRD, value); + dm_pci_write_config32(dev, SATA_SIRI, idx); + dm_pci_write_config32(dev, SATA_SIRD, value); }
-static void common_sata_init(pci_dev_t dev, unsigned int port_map) +static void common_sata_init(struct udevice *dev, unsigned int port_map) { u32 reg32; u16 reg16;
/* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - x86_pci_write_config32(dev, IDE_CONFIG, reg32); + dm_pci_write_config32(dev, IDE_CONFIG, reg32);
/* Port enable */ - reg16 = x86_pci_read_config16(dev, 0x92); + dm_pci_read_config16(dev, 0x92, ®16); reg16 &= ~0x3f; reg16 |= port_map; - x86_pci_write_config16(dev, 0x92, reg16); + dm_pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */ port_map &= 0xff; - x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); + dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); }
-static void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) +static void bd82x6x_sata_init(struct udevice *dev) { unsigned int port_map, speed_support, port_tx; - struct pci_controller *hose = pci_bus_to_hose(0); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; const char *mode; u32 reg32; u16 reg16; @@ -62,33 +67,27 @@ static void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) speed_support = fdtdec_get_int(blob, node, "sata_interface_speed_support", 0);
- /* Enable BARs */ - x86_pci_write_config16(dev, PCI_COMMAND, 0x0007); - mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); if (!mode || !strcmp(mode, "ahci")) { u32 abar;
debug("SATA: Controller in AHCI mode\n");
- /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */ - x86_pci_write_config8(dev, INTR_LN, 0x0a); - /* Set timings */ - x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); - x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
/* Sync DMA */ - x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); + dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); + dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
common_sata_init(dev, 0x8000 | port_map);
/* Initialize AHCI memory-mapped space */ - abar = pci_read_bar32(hose, dev, 5); + abar = dm_pci_read_bar32(dev, 5); debug("ABAR: %08X\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = readl(abar + 0x00); @@ -116,59 +115,54 @@ static void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) debug("SATA: Controller in combined mode\n");
/* No AHCI: clear AHCI base */ - pci_write_bar32(hose, dev, 5, 0x00000000); + dm_pci_write_bar32(dev, 5, 0x00000000); /* And without AHCI BAR no memory decoding */ - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); + dm_pci_read_config16(dev, PCI_COMMAND, ®16); reg16 &= ~PCI_COMMAND_MEMORY; - x86_pci_write_config16(dev, PCI_COMMAND, reg16); + dm_pci_write_config16(dev, PCI_COMMAND, reg16);
- x86_pci_write_config8(dev, 0x09, 0x80); + dm_pci_write_config8(dev, 0x09, 0x80);
/* Set timings */ - x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0);
/* Sync DMA */ - x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); + dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
common_sata_init(dev, port_map); } else { debug("SATA: Controller in plain-ide mode\n");
/* No AHCI: clear AHCI base */ - pci_write_bar32(hose, dev, 5, 0x00000000); + dm_pci_write_bar32(dev, 5, 0x00000000);
/* And without AHCI BAR no memory decoding */ - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); + dm_pci_read_config16(dev, PCI_COMMAND, ®16); reg16 &= ~PCI_COMMAND_MEMORY; - x86_pci_write_config16(dev, PCI_COMMAND, reg16); + dm_pci_write_config16(dev, PCI_COMMAND, reg16);
/* * Native mode capable on both primary and secondary (0xa) * OR'ed with enabled (0x50) = 0xf */ - x86_pci_write_config8(dev, 0x09, 0x8f); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - x86_pci_write_config8(dev, INTR_LN, 0xff); + dm_pci_write_config8(dev, 0x09, 0x8f);
/* Set timings */ - x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); - x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_SITRE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
/* Sync DMA */ - x86_pci_write_config16(dev, IDE_SDMA_CNT, - IDE_SSDE0 | IDE_PSDE0); - x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); + dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); + dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
common_sata_init(dev, port_map); } @@ -209,8 +203,10 @@ static void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); }
-static void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) +static void bd82x6x_sata_enable(struct udevice *dev) { + const void *blob = gd->fdt_blob; + int node = dev->of_offset; unsigned port_map; const char *mode; u16 map = 0; @@ -225,15 +221,15 @@ static void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
map |= (port_map ^ 0x3f) << 8; - x86_pci_write_config16(dev, 0x90, map); + dm_pci_write_config16(dev, 0x90, map); }
static int bd82x6x_sata_probe(struct udevice *dev) { if (!(gd->flags & GD_FLG_RELOC)) - bd82x6x_sata_enable(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset); + bd82x6x_sata_enable(dev); else - bd82x6x_sata_init(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset); + bd82x6x_sata_init(dev);
return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Adjust the functions in this file to use the driver model PCI API.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop unnecessary IRQ and command register init
arch/x86/cpu/ivybridge/sata.c | 94 +++++++++++++++++++++---------------------- 1 file changed, 45 insertions(+), 49 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 3:19 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Adjust the functions in this file to use the driver model PCI API.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop unnecessary IRQ and command register init
arch/x86/cpu/ivybridge/sata.c | 94 +++++++++++++++++++++---------------------- 1 file changed, 45 insertions(+), 49 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
This graphics init code is best placed in the gma init code. Move the code and drop the function.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 1 - arch/x86/cpu/ivybridge/gma.c | 4 ++++ arch/x86/cpu/ivybridge/lpc.c | 7 ------- arch/x86/include/asm/arch-ivybridge/pch.h | 1 - 4 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 188b7da..9e7e30a 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -29,7 +29,6 @@ static int bd82x6x_probe(struct udevice *dev) return 0;
hose = pci_bus_to_hose(0); - lpc_enable(PCH_LPC_DEV); lpc_init_extra(hose, PCH_LPC_DEV);
/* Cause the SATA device to do its init */ diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 1748f7f..b94536c 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -806,6 +806,10 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node) u32 reg32; int ret;
+ /* Enable PCH Display Port */ + writew(0x0010, RCB_REG(DISPBDF)); + setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); + ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge); if (!nbridge) return -ENODEV; diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 0d85de2..44c4825 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -602,13 +602,6 @@ int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev) return 0; }
-void lpc_enable(pci_dev_t dev) -{ - /* Enable PCH Display Port */ - writew(0x0010, RCB_REG(DISPBDF)); - setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); -} - static int bd82x6x_lpc_early_init(struct udevice *dev) { /* Setting up Southbridge. In the northbridge code. */ diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index f35803b..682a557 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -471,6 +471,5 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define TCO2_STS 0x66
int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev); -void lpc_enable(pci_dev_t dev);
#endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This graphics init code is best placed in the gma init code. Move the code and drop the function.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 1 - arch/x86/cpu/ivybridge/gma.c | 4 ++++ arch/x86/cpu/ivybridge/lpc.c | 7 ------- arch/x86/include/asm/arch-ivybridge/pch.h | 1 - 4 files changed, 4 insertions(+), 9 deletions(-)
applied to u-boot-x86/master, thanks!
Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Update to use LPC probe() method instead of init()
arch/x86/cpu/ivybridge/bd82x6x.c | 4 ---- arch/x86/cpu/ivybridge/lpc.c | 17 +++++++++-------- arch/x86/include/asm/arch-ivybridge/pch.h | 2 -- 3 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 9e7e30a..5cb4152 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -21,16 +21,12 @@ static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; - struct pci_controller *hose; int gma_node; int ret;
if (!(gd->flags & GD_FLG_RELOC)) return 0;
- hose = pci_bus_to_hose(0); - lpc_init_extra(hose, PCH_LPC_DEV); - /* Cause the SATA device to do its init */ uclass_first_device(UCLASS_DISK, &dev);
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 44c4825..79224d9 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -538,7 +538,7 @@ static int lpc_early_init(struct udevice *dev) return 0; }
-int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev) +static int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev) { const void *blob = gd->fdt_blob; int node; @@ -626,16 +626,17 @@ static int bd82x6x_lpc_probe(struct udevice *dev) { int ret;
- if (gd->flags & GD_FLG_RELOC) - return 0; + if (!(gd->flags & GD_FLG_RELOC)) { + ret = lpc_early_init(dev); + if (ret) { + debug("%s: lpc_early_init() failed\n", __func__); + return ret; + }
- ret = lpc_early_init(dev); - if (ret) { - debug("%s: lpc_early_init() failed\n", __func__); - return ret; + return bd82x6x_lpc_early_init(dev); }
- return bd82x6x_lpc_early_init(dev); + return lpc_init_extra(pci_bus_to_hose(0), PCH_LPC_DEV); }
static const struct udevice_id bd82x6x_lpc_ids[] = { diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 682a557..629a144 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -470,6 +470,4 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66
-int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev); - #endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Update to use LPC probe() method instead of init()
arch/x86/cpu/ivybridge/bd82x6x.c | 4 ---- arch/x86/cpu/ivybridge/lpc.c | 17 +++++++++-------- arch/x86/include/asm/arch-ivybridge/pch.h | 2 -- 3 files changed, 9 insertions(+), 14 deletions(-)
applied to u-boot-x86/master, thanks!
There is nothing special about the ivybridge pci driver now, so just use the generic one.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Drop the special compatible string in chromebook_link.dts
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/pci.c | 46 ---------------------------------------- arch/x86/dts/chromebook_link.dts | 2 +- 3 files changed, 1 insertion(+), 48 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/pci.c
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index bdbd3fa..259a5df 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -15,7 +15,6 @@ obj-y += model_206ax.o obj-y += microcode_intel.o obj-y += northbridge.o obj-y += pch.o -obj-y += pci.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c deleted file mode 100644 index 5195002..0000000 --- a/arch/x86/cpu/ivybridge/pci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008,2009 - * Graeme Russ, graeme.russ@gmail.com - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <pci.h> -#include <asm/pci.h> -#include <asm/post.h> -#include <asm/arch/bd82x6x.h> -#include <asm/arch/pch.h> - -static int pci_ivybridge_probe(struct udevice *bus) -{ - if (!(gd->flags & GD_FLG_RELOC)) - return 0; - post_code(0x50); - post_code(0x51); - - return 0; -} - -static const struct dm_pci_ops pci_ivybridge_ops = { - .read_config = pci_x86_read_config, - .write_config = pci_x86_write_config, -}; - -static const struct udevice_id pci_ivybridge_ids[] = { - { .compatible = "intel,pci-ivybridge" }, - { } -}; - -U_BOOT_DRIVER(pci_ivybridge_drv) = { - .name = "pci_ivybridge", - .id = UCLASS_PCI, - .of_match = pci_ivybridge_ids, - .ops = &pci_ivybridge_ops, - .probe = pci_ivybridge_probe, -}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 022b04c..18305a3 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -193,7 +193,7 @@ };
pci { - compatible = "intel,pci-ivybridge", "pci-x86"; + compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; u-boot,dm-pre-reloc;
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
There is nothing special about the ivybridge pci driver now, so just use the generic one.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop the special compatible string in chromebook_link.dts
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/pci.c | 46 ---------------------------------------- arch/x86/dts/chromebook_link.dts | 2 +- 3 files changed, 1 insertion(+), 48 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/pci.c
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 3:22 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
There is nothing special about the ivybridge pci driver now, so just use the generic one.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Drop the special compatible string in chromebook_link.dts
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/pci.c | 46 ---------------------------------------- arch/x86/dts/chromebook_link.dts | 2 +- 3 files changed, 1 insertion(+), 48 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/pci.c
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra().
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 129 ++++++++++++++++++++++--------------------- 1 file changed, 66 insertions(+), 63 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 79224d9..0cf55c5 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -24,13 +24,13 @@ #define ENABLE_ACPI_MODE_IN_COREBOOT 0 #define TEST_SMM_FLASH_LOCKDOWN 0
-static int pch_enable_apic(pci_dev_t dev) +static int pch_enable_apic(struct udevice *pch) { u32 reg32; int i;
/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */ - x86_pci_write_config8(dev, ACPI_CNTL, 0x80); + dm_pci_write_config8(pch, ACPI_CNTL, 0x80);
writel(0, IO_APIC_INDEX); writel(1 << 25, IO_APIC_DATA); @@ -66,36 +66,36 @@ static int pch_enable_apic(pci_dev_t dev) return 0; }
-static void pch_enable_serial_irqs(pci_dev_t dev) +static void pch_enable_serial_irqs(struct udevice *pch) { u32 value;
/* Set packet length and toggle silent mode bit for one frame. */ value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE - x86_pci_write_config8(dev, SERIRQ_CNTL, value); + dm_pci_write_config8(pch, SERIRQ_CNTL, value); #else - x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6)); + dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6)); #endif }
-static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) +static int pch_pirq_init(struct udevice *pch) { uint8_t route[8], *ptr;
- if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route, - sizeof(route))) + if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset, + "intel,pirq-routing", route, sizeof(route))) return -EINVAL; ptr = route; - x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++);
- x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++);
/* * TODO(sjg@chromium.org): U-Boot does not set up the interrupts @@ -104,26 +104,28 @@ static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) return 0; }
-static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev) +static int pch_gpi_routing(struct udevice *pch) { u8 route[16]; u32 reg; int gpi;
- if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route, - sizeof(route))) + if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset, + "intel,gpi-routing", route, sizeof(route))) return -EINVAL;
for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) reg |= route[gpi] << (gpi * 2);
- x86_pci_write_config32(dev, 0xb8, reg); + dm_pci_write_config32(pch, 0xb8, reg);
return 0; }
-static int pch_power_options(const void *blob, int node, pci_dev_t dev) +static int pch_power_options(struct udevice *pch) { + const void *blob = gd->fdt_blob; + int node = pch->of_offset; u8 reg8; u16 reg16, pmbase; u32 reg32; @@ -142,7 +144,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) */ pwr_on = MAINBOARD_POWER_ON;
- reg16 = x86_pci_read_config16(dev, GEN_PMCON_3); + dm_pci_read_config16(pch, GEN_PMCON_3, ®16); reg16 &= 0xfffe; switch (pwr_on) { case MAINBOARD_POWER_OFF: @@ -169,7 +171,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
- x86_pci_write_config16(dev, GEN_PMCON_3, reg16); + dm_pci_write_config16(pch, GEN_PMCON_3, reg16); debug("Set power %s after power failure.\n", state);
/* Set up NMI on errors. */ @@ -193,21 +195,22 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) outb(reg8, 0x70);
/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ - reg16 = x86_pci_read_config16(dev, GEN_PMCON_1); + dm_pci_read_config16(pch, GEN_PMCON_1, ®16); reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ reg16 |= (3 << 0); /* Periodic SMI every 8s */ #endif - x86_pci_write_config16(dev, GEN_PMCON_1, reg16); + dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
/* Set the board's GPI routing. */ - ret = pch_gpi_routing(blob, node, dev); + ret = pch_gpi_routing(pch); if (ret) return ret;
- pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe; + dm_pci_read_config16(pch, 0x40, &pmbase); + pmbase &= 0xfffe;
writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, "intel,gpe0-enable", 0)); @@ -227,16 +230,16 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) return 0; }
-static void pch_rtc_init(pci_dev_t dev) +static void pch_rtc_init(struct udevice *pch) { int rtc_failed; u8 reg8;
- reg8 = x86_pci_read_config8(dev, GEN_PMCON_3); + dm_pci_read_config8(pch, GEN_PMCON_3, ®8); rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; - x86_pci_write_config8(dev, GEN_PMCON_3, reg8); + dm_pci_write_config8(pch, GEN_PMCON_3, reg8); } debug("rtc_failed = 0x%x\n", rtc_failed);
@@ -246,10 +249,10 @@ static void pch_rtc_init(pci_dev_t dev) }
/* CougarPoint PCH Power Management init */ -static void cpt_pm_init(pci_dev_t dev) +static void cpt_pm_init(struct udevice *pch) { debug("CougarPoint PM init\n"); - x86_pci_write_config8(dev, 0xa9, 0x47); + dm_pci_write_config8(pch, 0xa9, 0x47); setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
setbits_le32(RCB_REG(0x228c), 1 << 0); @@ -290,10 +293,10 @@ static void cpt_pm_init(pci_dev_t dev) }
/* PantherPoint PCH Power Management init */ -static void ppt_pm_init(pci_dev_t dev) +static void ppt_pm_init(struct udevice *pch) { debug("PantherPoint PM init\n"); - x86_pci_write_config8(dev, 0xa9, 0x47); + dm_pci_write_config8(pch, 0xa9, 0x47); setbits_le32(RCB_REG(0x2238), 1 << 0); setbits_le32(RCB_REG(0x228c), 1 << 0); setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); @@ -340,16 +343,16 @@ static void enable_hpet(void) clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); }
-static void enable_clock_gating(pci_dev_t dev) +static void enable_clock_gating(struct udevice *pch) { u32 reg32; u16 reg16;
setbits_le32(RCB_REG(0x2234), 0xf);
- reg16 = x86_pci_read_config16(dev, GEN_PMCON_1); + dm_pci_read_config16(pch, GEN_PMCON_1, ®16); reg16 |= (1 << 2) | (1 << 11); - x86_pci_write_config16(dev, GEN_PMCON_1, reg16); + dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); @@ -429,24 +432,24 @@ static void pch_lock_smm(pci_dev_t dev) } #endif
-static void pch_disable_smm_only_flashing(pci_dev_t dev) +static void pch_disable_smm_only_flashing(struct udevice *pch) { u8 reg8;
debug("Enabling BIOS updates outside of SMM... "); - reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */ reg8 &= ~(1 << 5); - x86_pci_write_config8(dev, 0xdc, reg8); + dm_pci_write_config8(pch, 0xdc, reg8); }
-static void pch_fixups(pci_dev_t dev) +static void pch_fixups(struct udevice *pch) { u8 gen_pmcon_2;
/* Indicate DRAM init done for MRC S3 to know it can resume */ - gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2); + dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2); gen_pmcon_2 |= (1 << 7); - x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2);
/* Enable DMI ASPM in the PCH */ clrbits_le32(RCB_REG(0x2304), 1 << 10); @@ -538,66 +541,66 @@ static int lpc_early_init(struct udevice *dev) return 0; }
-static int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev) +static int lpc_init_extra(struct udevice *dev) { + struct udevice *pch = dev->parent; const void *blob = gd->fdt_blob; int node;
debug("pch: lpc_init\n"); - pci_write_bar32(hose, dev, 0, 0); - pci_write_bar32(hose, dev, 1, 0xff800000); - pci_write_bar32(hose, dev, 2, 0xfec00000); - pci_write_bar32(hose, dev, 3, 0x800); - pci_write_bar32(hose, dev, 4, 0x900); + dm_pci_write_bar32(pch, 0, 0); + dm_pci_write_bar32(pch, 1, 0xff800000); + dm_pci_write_bar32(pch, 2, 0xfec00000); + dm_pci_write_bar32(pch, 3, 0x800); + dm_pci_write_bar32(pch, 4, 0x900);
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT;
/* Set the value for PCI command register. */ - x86_pci_write_config16(dev, PCI_COMMAND, 0x000f); + dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_apic(pch);
- pch_enable_serial_irqs(dev); + pch_enable_serial_irqs(pch);
/* Setup the PIRQ. */ - pch_pirq_init(blob, node, dev); + pch_pirq_init(pch);
/* Setup power options. */ - pch_power_options(blob, node, dev); + pch_power_options(pch);
/* Initialize power management */ switch (pch_silicon_type()) { case PCH_TYPE_CPT: /* CougarPoint */ - cpt_pm_init(dev); + cpt_pm_init(pch); break; case PCH_TYPE_PPT: /* PantherPoint */ - ppt_pm_init(dev); + ppt_pm_init(pch); break; default: - printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev), - PCI_FUNC(dev)); + printf("Unknown Chipset: %s\n", pch->name); return -ENOSYS; }
/* Initialize the real time clock. */ - pch_rtc_init(dev); + pch_rtc_init(pch);
/* Initialize the High Precision Event Timers, if present. */ enable_hpet();
/* Initialize Clock Gating */ - enable_clock_gating(dev); + enable_clock_gating(pch);
- pch_disable_smm_only_flashing(dev); + pch_disable_smm_only_flashing(pch);
#if CONFIG_HAVE_SMI_HANDLER pch_lock_smm(dev); #endif
- pch_fixups(dev); + pch_fixups(pch);
return 0; } @@ -636,7 +639,7 @@ static int bd82x6x_lpc_probe(struct udevice *dev) return bd82x6x_lpc_early_init(dev); }
- return lpc_init_extra(pci_bus_to_hose(0), PCH_LPC_DEV); + return lpc_init_extra(dev); }
static const struct udevice_id bd82x6x_lpc_ids[] = {
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra().
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 129 ++++++++++++++++++++++--------------------- 1 file changed, 66 insertions(+), 63 deletions(-)
applied to u-boot-x86/master, thanks!
Move these two boards to use driver model for USB.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
configs/chromebook_link_defconfig | 2 ++ configs/chromebox_panther_defconfig | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 06e4ce6..f367f81 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -37,6 +37,8 @@ CONFIG_SYS_NS16550=y CONFIG_ICH_SPI=y CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index ed4428f..4b78292 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_NS16550=y CONFIG_ICH_SPI=y CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Move these two boards to use driver model for USB.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
configs/chromebook_link_defconfig | 2 ++ configs/chromebox_panther_defconfig | 2 ++ 2 files changed, 4 insertions(+)
applied to u-boot-x86/master, thanks!
This is used on most Intel platforms. We don't have a driver for it yet, but add a stub to handle the init. For now this targets ivybridge so we may want to add a device tree binding and generalise it when other platforms are supported.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Heiko Schocher hs@denx.de Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Expand the Kconfig help a little
drivers/i2c/Kconfig | 9 +++++++++ drivers/i2c/Makefile | 1 + drivers/i2c/intel_i2c.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 drivers/i2c/intel_i2c.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 14adda2..46b83e7 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -58,6 +58,15 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SYS_I2C_INTEL + bool "Intel I2C/SMBUS driver" + depends on DM_I2C + help + Add support for the Intel SMBUS driver. So far this driver is just + a stub which perhaps some basic init. There is no implementation of + the I2C API meaning that any I2C operations will immediately fail + for now. + config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 811ad9b..a2a956a 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o +obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c new file mode 100644 index 0000000..1082d1a --- /dev/null +++ b/drivers/i2c/intel_i2c.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <asm/io.h> + +int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + return -ENOSYS; +} + +int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags) +{ + return -ENOSYS; +} + +int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + return 0; +} + +static int intel_i2c_probe(struct udevice *dev) +{ + return 0; +} + +static const struct dm_i2c_ops intel_i2c_ops = { + .xfer = intel_i2c_xfer, + .probe_chip = intel_i2c_probe_chip, + .set_bus_speed = intel_i2c_set_bus_speed, +}; + +static const struct udevice_id intel_i2c_ids[] = { + { .compatible = "intel,ich-i2c" }, + { } +}; + +U_BOOT_DRIVER(intel_i2c) = { + .name = "i2c_intel", + .id = UCLASS_I2C, + .of_match = intel_i2c_ids, + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), + .ops = &intel_i2c_ops, + .probe = intel_i2c_probe, +};
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This is used on most Intel platforms. We don't have a driver for it yet, but add a stub to handle the init. For now this targets ivybridge so we may want to add a device tree binding and generalise it when other platforms are supported.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Heiko Schocher hs@denx.de Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Expand the Kconfig help a little
drivers/i2c/Kconfig | 9 +++++++++ drivers/i2c/Makefile | 1 + drivers/i2c/intel_i2c.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 drivers/i2c/intel_i2c.c
applied to u-boot-x86/master, thanks!
Move the init code into the I2C driver.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Heiko Schocher hs@denx.de Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 39 +++------------------------------------ arch/x86/dts/chromebook_link.dts | 6 ++++++ configs/chromebook_link_defconfig | 2 ++ drivers/i2c/intel_i2c.c | 24 ++++++++++++++++++++++++ 4 files changed, 35 insertions(+), 36 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 4cf2ba0..b9dda4c7 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -120,41 +120,6 @@ int arch_cpu_init_dm(void) return 0; }
-static int enable_smbus(void) -{ - pci_dev_t dev; - uint16_t value; - - /* Set the SMBus device statically. */ - dev = PCI_BDF(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - value = x86_pci_read_config16(dev, 0x0); - if (value != 0x8086) { - printf("SMBus controller not found\n"); - return -ENOSYS; - } - - /* Set SMBus I/O base. */ - x86_pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - x86_pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - debug("SMBus controller enabled\n"); - - return 0; -} - #define PCH_EHCI0_TEMP_BAR0 0xe8000000 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 #define PCH_XHCI_TEMP_BAR0 0xe8001000 @@ -271,9 +236,11 @@ int print_cpuinfo(void) post_code(POST_EARLY_INIT);
/* Enable SPD ROMs and DDR-III DRAM */ - ret = enable_smbus(); + ret = uclass_first_device(UCLASS_I2C, &dev); if (ret) return ret; + if (!dev) + return -ENODEV;
/* Prepare USB controller early in S3 resume */ if (boot_mode == PEI_BOOT_RESUME) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 18305a3..54f2043 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -283,6 +283,12 @@ intel,sata-port-map = <1>; intel,sata-port0-gen3-tx = <0x00880a7f>; }; + + smbus: smbus@1f,3 { + compatible = "intel,ich-i2c"; + reg = <0x0000fb00 0 0 0 0>; + u-boot,dm-pre-reloc; + }; };
tpm { diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index f367f81..daa958e 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,5 +1,6 @@ CONFIG_X86=y CONFIG_SYS_MALLOC_F_LEN=0x1800 +CONFIG_DM_I2C=y CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y @@ -20,6 +21,7 @@ CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y CONFIG_CPU=y +CONFIG_SYS_I2C_INTEL=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c index 1082d1a..3d777ff 100644 --- a/drivers/i2c/intel_i2c.c +++ b/drivers/i2c/intel_i2c.c @@ -9,6 +9,7 @@ #include <dm.h> #include <i2c.h> #include <asm/io.h> +#include <asm/arch/pch.h>
int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { @@ -27,6 +28,29 @@ int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
static int intel_i2c_probe(struct udevice *dev) { + /* + * So far this is just setup code for ivybridge SMbus. When we have + * a full I2C driver this may need to be moved, generalised or made + * dependant on a particular compatible string. + * + * Set SMBus I/O base + */ + dm_pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + dm_pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + debug("SMBus controller enabled\n"); + return 0; }
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Move the init code into the I2C driver.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Heiko Schocher hs@denx.de Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 39 +++------------------------------------ arch/x86/dts/chromebook_link.dts | 6 ++++++ configs/chromebook_link_defconfig | 2 ++ drivers/i2c/intel_i2c.c | 24 ++++++++++++++++++++++++ 4 files changed, 35 insertions(+), 36 deletions(-)
applied to u-boot-x86/master, thanks!
Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Avoid needing the pch device to set up the USB bar
arch/x86/cpu/ivybridge/cpu.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index b9dda4c7..948833c 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -133,33 +133,33 @@ int arch_cpu_init_dm(void) * * This is used to speed up the resume path. */ -static void enable_usb_bar(void) +static void enable_usb_bar(struct udevice *bus) { pci_dev_t usb0 = PCH_EHCI1_DEV; pci_dev_t usb1 = PCH_EHCI2_DEV; pci_dev_t usb3 = PCH_XHCI_DEV; - u32 cmd; + ulong cmd;
/* USB Controller 1 */ - x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0, - PCH_EHCI0_TEMP_BAR0); - cmd = x86_pci_read_config32(usb0, PCI_COMMAND); + pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0, + PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32); + pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - x86_pci_write_config32(usb0, PCI_COMMAND, cmd); + pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
- /* USB Controller 1 */ - x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); - cmd = x86_pci_read_config32(usb1, PCI_COMMAND); + /* USB Controller 2 */ + pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0, + PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32); + pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - x86_pci_write_config32(usb1, PCI_COMMAND, cmd); + pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
- /* USB3 Controller */ - x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0, - PCH_XHCI_TEMP_BAR0); - cmd = x86_pci_read_config32(usb3, PCI_COMMAND); + /* USB3 Controller 1 */ + pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0, + PCH_XHCI_TEMP_BAR0, PCI_SIZE_32); + pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - x86_pci_write_config32(usb3, PCI_COMMAND, cmd); + pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32); }
static int report_bist_failure(void) @@ -244,7 +244,7 @@ int print_cpuinfo(void)
/* Prepare USB controller early in S3 resume */ if (boot_mode == PEI_BOOT_RESUME) - enable_usb_bar(); + enable_usb_bar(pci_get_controller(lpc->parent));
gd->arch.pei_boot_mode = boot_mode;
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Avoid needing the pch device to set up the USB bar
arch/x86/cpu/ivybridge/cpu.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-)
applied to u-boot-x86/master, thanks!
Convert the top part of the DRAM init to use the driver model PCI API. Further work will complete the transformation.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/sdram.c | 39 +++++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 4372a5c..5c1b788 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -495,8 +495,10 @@ static int add_memory_area(struct memory_info *info, * * This is a bit complicated since on x86 there are system memory holes all * over the place. We create a list of available memory blocks + * + * @dev: Northbridge device */ -static int sdram_find(pci_dev_t dev) +static int sdram_find(struct udevice *dev) { struct memory_info *info = &gd->arch.meminfo; uint32_t tseg_base, uma_size, tolud; @@ -505,6 +507,7 @@ static int sdram_find(pci_dev_t dev) uint64_t uma_memory_size; unsigned long long tomk; uint16_t ggc; + u32 val;
/* Total Memory 2GB example: * @@ -533,24 +536,27 @@ static int sdram_find(pci_dev_t dev) */
/* Top of Upper Usable DRAM, including remap */ - touud = x86_pci_read_config32(dev, TOUUD+4); - touud <<= 32; - touud |= x86_pci_read_config32(dev, TOUUD); + dm_pci_read_config32(dev, TOUUD + 4, &val); + touud = (uint64_t)val << 32; + dm_pci_read_config32(dev, TOUUD, &val); + touud |= val;
/* Top of Lower Usable DRAM */ - tolud = x86_pci_read_config32(dev, TOLUD); + dm_pci_read_config32(dev, TOLUD, &tolud);
/* Top of Memory - does not account for any UMA */ - tom = x86_pci_read_config32(dev, 0xa4); - tom <<= 32; - tom |= x86_pci_read_config32(dev, 0xa0); + dm_pci_read_config32(dev, 0xa4, &val); + tom = (uint64_t)val << 32; + dm_pci_read_config32(dev, 0xa0, &val); + tom |= val;
debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
/* ME UMA needs excluding if total memory <4GB */ - me_base = x86_pci_read_config32(dev, 0x74); - me_base <<= 32; - me_base |= x86_pci_read_config32(dev, 0x70); + dm_pci_read_config32(dev, 0x74, &val); + me_base = (uint64_t)val << 32; + dm_pci_read_config32(dev, 0x70, &val); + me_base |= val;
debug("MEBASE %llx\n", me_base);
@@ -568,7 +574,7 @@ static int sdram_find(pci_dev_t dev) }
/* Graphics memory comes next */ - ggc = x86_pci_read_config16(dev, GGC); + dm_pci_read_config16(dev, GGC, &ggc); if (!(ggc & 2)) { debug("IGD decoded, subtracting ");
@@ -588,7 +594,7 @@ static int sdram_find(pci_dev_t dev) }
/* Calculate TSEG size from its base which must be below GTT */ - tseg_base = x86_pci_read_config32(dev, 0xb8); + dm_pci_read_config32(dev, 0xb8, &tseg_base); uma_size = (uma_memory_base - tseg_base) >> 10; tomk -= uma_size; uma_memory_base = tomk * 1024ULL; @@ -723,7 +729,7 @@ int dram_init(void) { 0, 4, 0x0000 }, /* P13= Empty */ }, }; - pci_dev_t dev = PCI_BDF(0, 0, 0); + struct udevice *dev; int ret;
debug("Boot mode %d\n", gd->arch.pei_boot_mode); @@ -742,6 +748,11 @@ int dram_init(void)
post_code(POST_DRAM);
+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + if (ret) + return ret; + if (!dev) + return -ENODEV; ret = sdram_find(dev); if (ret) return ret;
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Convert the top part of the DRAM init to use the driver model PCI API. Further work will complete the transformation.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/sdram.c | 39 +++++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 14 deletions(-)
applied to u-boot-x86/master, thanks!
Convert this function to use the the driver model PCI API. We just need to pass in the northbridge device.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/sdram.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 5c1b788..6105cc0 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -283,9 +283,10 @@ static int recovery_mode_enabled(void) /** * Find the PEI executable in the ROM and execute it. * - * @param pei_data: configuration data for UEFI PEI reference code + * @dev: Northbridge device + * @pei_data: configuration data for UEFI PEI reference code */ -int sdram_initialise(struct pei_data *pei_data) +int sdram_initialise(struct udevice *dev, struct pei_data *pei_data) { unsigned version; const char *data; @@ -374,7 +375,7 @@ int sdram_initialise(struct pei_data *pei_data) * Send ME init done for SandyBridge here. This is done inside the * SystemAgent binary on IvyBridge */ - done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID); + dm_pci_read_config16(dev, PCI_DEVICE_ID, &done); done &= BASE_REV_MASK; if (BASE_REV_SNB == done) intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); @@ -732,12 +733,17 @@ int dram_init(void) struct udevice *dev; int ret;
+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + if (ret) + return ret; + if (!dev) + return -ENODEV; debug("Boot mode %d\n", gd->arch.pei_boot_mode); debug("mrc_input %p\n", pei_data.mrc_input); pei_data.boot_mode = gd->arch.pei_boot_mode; ret = copy_spd(&pei_data); if (!ret) - ret = sdram_initialise(&pei_data); + ret = sdram_initialise(dev, &pei_data); if (ret) return ret;
@@ -748,11 +754,6 @@ int dram_init(void)
post_code(POST_DRAM);
- ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); - if (ret) - return ret; - if (!dev) - return -ENODEV; ret = sdram_find(dev); if (ret) return ret;
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Convert this function to use the the driver model PCI API. We just need to pass in the northbridge device.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/sdram.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)
applied to u-boot-x86/master, thanks!
We will use a system controller to model the Intel Management Engine. Enable this for link.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
configs/chromebook_link_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index daa958e..f44bef7 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_SYS_I2C_INTEL=y CONFIG_CMD_CROS_EC=y
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
We will use a system controller to model the Intel Management Engine. Enable this for link.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
configs/chromebook_link_defconfig | 2 ++ 1 file changed, 2 insertions(+)
applied to u-boot-x86/master, thanks!
SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/early_me.c | 68 ++++++++++++++++++++------------ arch/x86/cpu/ivybridge/sdram.c | 20 ++++++---- arch/x86/dts/chromebook_link.dts | 6 +++ arch/x86/include/asm/arch-ivybridge/me.h | 45 ++++++++++++++++++--- 4 files changed, 101 insertions(+), 38 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index 711470f..612c910 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -7,6 +7,7 @@ */
#include <common.h> +#include <dm.h> #include <errno.h> #include <asm/pci.h> #include <asm/processor.h> @@ -25,33 +26,36 @@ static const char *const me_ack_values[] = { [ME_HFS_ACK_CONTINUE] = "Continue to boot" };
-static inline void pci_read_dword_ptr(void *ptr, int offset) +static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr, + int offset) { u32 dword;
- dword = x86_pci_read_config32(PCH_ME_DEV, offset); + dm_pci_read_config32(me_dev, offset, &dword); memcpy(ptr, &dword, sizeof(dword)); }
-static inline void pci_write_dword_ptr(void *ptr, int offset) +static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr, + int offset) { u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); - x86_pci_write_config32(PCH_ME_DEV, offset, dword); + dm_pci_write_config32(me_dev, offset, dword); }
-void intel_early_me_status(void) +void intel_early_me_status(struct udevice *me_dev) { struct me_hfs hfs; struct me_gmes gmes;
- pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&gmes, PCI_ME_GMES); + pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); + pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
intel_me_status(&hfs, &gmes); }
-int intel_early_me_init(void) +int intel_early_me_init(struct udevice *me_dev) { int count; struct me_uma uma; @@ -61,7 +65,7 @@ int intel_early_me_init(void)
/* Wait for ME UMA SIZE VALID bit to be set */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&uma, PCI_ME_UMA); + pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA); if (uma.valid) break; udelay(ME_DELAY); @@ -72,7 +76,7 @@ int intel_early_me_init(void) }
/* Check for valid firmware */ - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); if (hfs.fpt_bad) { printf("WARNING: ME has bad firmware\n"); return -EBADF; @@ -83,11 +87,11 @@ int intel_early_me_init(void) return 0; }
-int intel_early_me_uma_size(void) +int intel_early_me_uma_size(struct udevice *me_dev) { struct me_uma uma;
- pci_read_dword_ptr(&uma, PCI_ME_UMA); + pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA); if (uma.valid) { debug("ME: Requested %uMB UMA\n", uma.size); return uma.size; @@ -97,11 +101,11 @@ int intel_early_me_uma_size(void) return -EINVAL; }
-static inline void set_global_reset(int enable) +static inline void set_global_reset(struct udevice *dev, int enable) { u32 etr3;
- etr3 = x86_pci_read_config32(PCH_LPC_DEV, ETR3); + dm_pci_read_config32(dev, ETR3, &etr3);
/* Clear CF9 Without Resume Well Reset Enable */ etr3 &= ~ETR3_CWORWRE; @@ -112,10 +116,11 @@ static inline void set_global_reset(int enable) else etr3 &= ~ETR3_CF9GR;
- x86_pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + dm_pci_write_config32(dev, ETR3, etr3); }
-int intel_early_me_init_done(u8 status) +int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, + uint status) { int count; u32 mebase_l, mebase_h; @@ -126,8 +131,8 @@ int intel_early_me_init_done(u8 status) };
/* MEBASE from MESEG_BASE[35:20] */ - mebase_l = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L); - mebase_h = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H); + dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l); + dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h); mebase_h &= 0xf; did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
@@ -135,25 +140,25 @@ int intel_early_me_init_done(u8 status) debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n", status, did.uma_base);
- pci_write_dword_ptr(&did, PCI_ME_H_GS); + pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
/* Must wait for ME acknowledgement */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); if (hfs.bios_msg_ack) break; udelay(ME_DELAY); } if (!count) { printf("ERROR: ME failed to respond\n"); - return -1; + return -ETIMEDOUT; }
/* Return the requested BIOS action */ debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
/* Check status after acknowledgement */ - intel_early_me_status(); + intel_early_me_status(me_dev);
switch (hfs.ack_data) { case ME_HFS_ACK_CONTINUE: @@ -161,17 +166,17 @@ int intel_early_me_init_done(u8 status) return 0; case ME_HFS_ACK_RESET: /* Non-power cycle reset */ - set_global_reset(0); + set_global_reset(dev, 0); reset_cpu(0); break; case ME_HFS_ACK_PWR_CYCLE: /* Power cycle reset */ - set_global_reset(0); + set_global_reset(dev, 0); x86_full_reset(); break; case ME_HFS_ACK_GBL_RESET: /* Global reset */ - set_global_reset(1); + set_global_reset(dev, 1); x86_full_reset(); break; case ME_HFS_ACK_S3: @@ -180,5 +185,16 @@ int intel_early_me_init_done(u8 status) break; }
- return -1; + return -EINVAL; } + +static const struct udevice_id ivybridge_syscon_ids[] = { + { .compatible = "intel,me", }, + { } +}; + +U_BOOT_DRIVER(syscon_intel_me) = { + .name = "intel_me_syscon", + .id = UCLASS_SYSCON, + .of_match = ivybridge_syscon_ids, +}; diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 6105cc0..696351b 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -286,7 +286,8 @@ static int recovery_mode_enabled(void) * @dev: Northbridge device * @pei_data: configuration data for UEFI PEI reference code */ -int sdram_initialise(struct udevice *dev, struct pei_data *pei_data) +int sdram_initialise(struct udevice *dev, struct udevice *me_dev, + struct pei_data *pei_data) { unsigned version; const char *data; @@ -296,10 +297,10 @@ int sdram_initialise(struct udevice *dev, struct pei_data *pei_data) report_platform_info();
/* Wait for ME to be ready */ - ret = intel_early_me_init(); + ret = intel_early_me_init(me_dev); if (ret) return ret; - ret = intel_early_me_uma_size(); + ret = intel_early_me_uma_size(me_dev); if (ret < 0) return ret;
@@ -378,9 +379,9 @@ int sdram_initialise(struct udevice *dev, struct pei_data *pei_data) dm_pci_read_config16(dev, PCI_DEVICE_ID, &done); done &= BASE_REV_MASK; if (BASE_REV_SNB == done) - intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); + intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS); else - intel_early_me_status(); + intel_early_me_status(me_dev);
post_system_agent_init(pei_data); report_memory_config(); @@ -730,7 +731,7 @@ int dram_init(void) { 0, 4, 0x0000 }, /* P13= Empty */ }, }; - struct udevice *dev; + struct udevice *dev, *me_dev; int ret;
ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); @@ -738,12 +739,17 @@ int dram_init(void) return ret; if (!dev) return -ENODEV; + ret = uclass_first_device(UCLASS_SYSCON, &me_dev); + if (ret) + return ret; + if (!me_dev) + return -ENODEV; debug("Boot mode %d\n", gd->arch.pei_boot_mode); debug("mrc_input %p\n", pei_data.mrc_input); pei_data.boot_mode = gd->arch.pei_boot_mode; ret = copy_spd(&pei_data); if (!ret) - ret = sdram_initialise(dev, &pei_data); + ret = sdram_initialise(dev, me_dev, &pei_data); if (ret) return ret;
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 54f2043..329eae8 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -220,6 +220,12 @@ intel,pch-backlight = <0x04000000>; };
+ me@16,0 { + reg = <0x0000b000 0 0 0 0>; + compatible = "intel,me"; + u-boot,dm-pre-reloc; + }; + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,bd82x6x", "intel,pch9"; diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h index 3a0809d..eb1b73f 100644 --- a/arch/x86/include/asm/arch-ivybridge/me.h +++ b/arch/x86/include/asm/arch-ivybridge/me.h @@ -345,12 +345,47 @@ struct __packed me_fwcaps { u8 reserved[3]; };
-/* Defined in me_status.c for both romstage and ramstage */ +/** + * intel_me_status() - Check Intel Management Engine status + * + * struct hfs: Firmware status + * struct gmes: Management engine status + */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
-void intel_early_me_status(void); -int intel_early_me_init(void); -int intel_early_me_uma_size(void); -int intel_early_me_init_done(u8 status); +/** + * intel_early_me_status() - Check early Management Engine Status + * + * @me_dev: Management engine PCI device + */ +void intel_early_me_status(struct udevice *me_dev); + +/** + * intel_early_me_init() - Early Intel Management Engine init + * + * @me_dev: Management engine PCI device + * @return 0 if OK, -ve on error + */ +int intel_early_me_init(struct udevice *me_dev); + +/** + * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine + * + * @me_dev: Management engine PCI device + * @return UMA size if OK, -EINVAL on error + */ +int intel_early_me_uma_size(struct udevice *me_dev); + +/** + * intel_early_me_init_done() - Complete Intel Management Engine init + * + * @dev: Northbridge device + * @me_dev: Management engine PCI device + * @status: Status result (ME_INIT_...) + * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT + * if ME did not respond + */ +int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, + uint status);
#endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/early_me.c | 68 ++++++++++++++++++++------------ arch/x86/cpu/ivybridge/sdram.c | 20 ++++++---- arch/x86/dts/chromebook_link.dts | 6 +++ arch/x86/include/asm/arch-ivybridge/me.h | 45 ++++++++++++++++++--- 4 files changed, 101 insertions(+), 38 deletions(-)
applied to u-boot-x86/master, thanks!
Convert these functions to use the driver model PCI API.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/report_platform.c | 11 ++++++----- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c index 4493870..c78322a 100644 --- a/arch/x86/cpu/ivybridge/report_platform.c +++ b/arch/x86/cpu/ivybridge/report_platform.c @@ -10,6 +10,7 @@ #include <asm/cpu.h> #include <asm/pci.h> #include <asm/arch/pch.h> +#include <asm/arch/sandybridge.h>
static void report_cpu_info(void) { @@ -63,27 +64,27 @@ static struct { {0x1E5F, "NM70"}, };
-static void report_pch_info(void) +static void report_pch_info(struct udevice *dev) { const char *pch_type = "Unknown"; int i; u16 dev_id; uint8_t rev_id;
- dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2); + dm_pci_read_config16(dev, 2, &dev_id); for (i = 0; i < ARRAY_SIZE(pch_table); i++) { if (pch_table[i].dev_id == dev_id) { pch_type = pch_table[i].dev_name; break; } } - rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8); + dm_pci_read_config8(dev, 8, &rev_id); debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id, rev_id); }
-void report_platform_info(void) +void report_platform_info(struct udevice *dev) { report_cpu_info(); - report_pch_info(); + report_pch_info(dev); } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 696351b..3e5be4e 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -294,7 +294,7 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev, uint16_t done; int ret;
- report_platform_info(); + report_platform_info(dev);
/* Wait for ME to be ready */ ret = intel_early_me_init(me_dev); diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index af8a9f7..ce8d030 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -110,7 +110,7 @@
int bridge_silicon_revision(void);
-void report_platform_info(void); +void report_platform_info(struct udevice *dev);
void sandybridge_early_init(int chipset_type);
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Convert these functions to use the driver model PCI API.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/report_platform.c | 11 ++++++----- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-)
applied to u-boot-x86/master, thanks!
Convert this file to use the driver model PCI API.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 10 ++++---- arch/x86/cpu/ivybridge/pch.c | 35 ++++++++++++++------------ arch/x86/cpu/ivybridge/sata.c | 21 +++++++++++----- arch/x86/include/asm/arch-ivybridge/pch.h | 42 +++++++++++++++++++++++++++---- 4 files changed, 76 insertions(+), 32 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 0cf55c5..12e86cb 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -354,10 +354,10 @@ static void enable_clock_gating(struct udevice *pch) reg16 |= (1 << 2) | (1 << 11); dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
- pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31)); + pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7)); + pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31)); + pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
reg32 = readl(RCB_REG(CG)); reg32 |= (1 << 31); @@ -573,7 +573,7 @@ static int lpc_init_extra(struct udevice *dev) pch_power_options(pch);
/* Initialize power management */ - switch (pch_silicon_type()) { + switch (pch_silicon_type(pch)) { case PCH_TYPE_CPT: /* CougarPoint */ cpt_pm_init(pch); break; diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c index bbab646..c7ce408 100644 --- a/arch/x86/cpu/ivybridge/pch.c +++ b/arch/x86/cpu/ivybridge/pch.c @@ -14,32 +14,34 @@ static int pch_revision_id = -1; static int pch_type = -1;
-int pch_silicon_revision(void) +int pch_silicon_revision(struct udevice *dev) { - pci_dev_t dev; + u8 val;
- dev = PCH_LPC_DEV; + if (pch_revision_id < 0) { + dm_pci_read_config8(dev, PCI_REVISION_ID, &val); + pch_revision_id = val; + }
- if (pch_revision_id < 0) - pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID); return pch_revision_id; }
-int pch_silicon_type(void) +int pch_silicon_type(struct udevice *dev) { - pci_dev_t dev; + u8 val;
- dev = PCH_LPC_DEV; + if (pch_type < 0) { + dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); + pch_type = val; + }
- if (pch_type < 0) - pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1); return pch_type; }
-int pch_silicon_supported(int type, int rev) +int pch_silicon_supported(struct udevice *dev, int type, int rev) { - int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); + int cur_type = pch_silicon_type(dev); + int cur_rev = pch_silicon_revision(dev);
switch (type) { case PCH_TYPE_CPT: @@ -78,7 +80,8 @@ static inline int iobp_poll(void) return 0; }
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue) { u32 data;
@@ -86,7 +89,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) writel(address, RCB_REG(IOBPIRI));
/* READ OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) writel(IOBPS_RW_BX, RCB_REG(IOBPS)); else writel(IOBPS_READ_AX, RCB_REG(IOBPS)); @@ -109,7 +112,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) data |= orvalue;
/* WRITE OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) writel(IOBPS_RW_BX, RCB_REG(IOBPS)); else writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index 21e11d1..a59d9ed 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -51,7 +51,7 @@ static void common_sata_init(struct udevice *dev, unsigned int port_map) dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); }
-static void bd82x6x_sata_init(struct udevice *dev) +static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch) { unsigned int port_map, speed_support, port_tx; const void *blob = gd->fdt_blob; @@ -170,11 +170,11 @@ static void bd82x6x_sata_init(struct udevice *dev) /* Set Gen3 Transmitter settings if needed */ port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); if (port_tx) - pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx); + pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); if (port_tx) - pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx); + pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
/* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); @@ -199,8 +199,8 @@ static void bd82x6x_sata_init(struct udevice *dev) sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000);
- pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); - pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); + pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000); + pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100); }
static void bd82x6x_sata_enable(struct udevice *dev) @@ -226,10 +226,19 @@ static void bd82x6x_sata_enable(struct udevice *dev)
static int bd82x6x_sata_probe(struct udevice *dev) { + struct udevice *pch; + int ret; + + ret = uclass_first_device(UCLASS_PCH, &pch); + if (ret) + return ret; + if (!pch) + return -ENODEV; + if (!(gd->flags & GD_FLG_RELOC)) bd82x6x_sata_enable(dev); else - bd82x6x_sata_init(dev); + bd82x6x_sata_init(dev, pch);
return 0; } diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 629a144..0f1aa01 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -30,11 +30,6 @@
#define SMBUS_IO_BASE 0x0400
-int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); - #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 @@ -470,4 +465,41 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66
+/** + * pch_silicon_revision() - Read silicon revision ID from the PCH + * + * @dev: PCH device + * @return silicon revision ID + */ +int pch_silicon_revision(struct udevice *dev); + +/** + * pch_silicon_revision() - Read silicon device ID from the PCH + * + * @dev: PCH device + * @return silicon device ID + */ +int pch_silicon_type(struct udevice *dev); + +/** + * pch_silicon_supported() - Check if a certain revision is supported + * + * @dev: PCH device + * @type: PCH type + * @rev: Minimum required resion + * @return 0 if not supported, 1 if supported + */ +int pch_silicon_supported(struct udevice *dev, int type, int rev); + +/** + * pch_pch_iobp_update() - Update a pch register + * + * @dev: PCH device + * @address: Address to update + * @andvalue: Value to AND with existing value + * @orvalue: Value to OR with existing value + */ +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue); + #endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Convert this file to use the driver model PCI API.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 10 ++++---- arch/x86/cpu/ivybridge/pch.c | 35 ++++++++++++++------------ arch/x86/cpu/ivybridge/sata.c | 21 +++++++++++----- arch/x86/include/asm/arch-ivybridge/pch.h | 42 +++++++++++++++++++++++++++---- 4 files changed, 76 insertions(+), 32 deletions(-)
applied to u-boot-x86/master, thanks!
This code relates to the PCH, so we should move it into the same file.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/bd82x6x.c | 129 ++++++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/pch.c | 126 ----------------------------- arch/x86/include/asm/arch-ivybridge/pch.h | 18 ----- 4 files changed, 129 insertions(+), 145 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/pch.c
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 259a5df..7007d5f 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -14,7 +14,6 @@ obj-y += me_status.o obj-y += model_206ax.o obj-y += microcode_intel.o obj-y += northbridge.o -obj-y += pch.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 5cb4152..70a0aea 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -9,6 +9,7 @@ #include <fdtdec.h> #include <malloc.h> #include <pch.h> +#include <asm/io.h> #include <asm/lapic.h> #include <asm/pci.h> #include <asm/arch/bd82x6x.h> @@ -18,6 +19,134 @@
#define BIOS_CTRL 0xdc
+static int pch_revision_id = -1; +static int pch_type = -1; + +/** + * pch_silicon_revision() - Read silicon revision ID from the PCH + * + * @dev: PCH device + * @return silicon revision ID + */ +static int pch_silicon_revision(struct udevice *dev) +{ + u8 val; + + if (pch_revision_id < 0) { + dm_pci_read_config8(dev, PCI_REVISION_ID, &val); + pch_revision_id = val; + } + + return pch_revision_id; +} + +int pch_silicon_type(struct udevice *dev) +{ + u8 val; + + if (pch_type < 0) { + dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); + pch_type = val; + } + + return pch_type; +} + +/** + * pch_silicon_supported() - Check if a certain revision is supported + * + * @dev: PCH device + * @type: PCH type + * @rev: Minimum required resion + * @return 0 if not supported, 1 if supported + */ +static int pch_silicon_supported(struct udevice *dev, int type, int rev) +{ + int cur_type = pch_silicon_type(dev); + int cur_rev = pch_silicon_revision(dev); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned try = IOBP_RETRY; + u32 data; + + while (try--) { + data = readl(RCB_REG(IOBPS)); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printf("IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue) +{ + u32 data; + + /* Set the address */ + writel(address, RCB_REG(IOBPIRI)); + + /* READ OPCODE */ + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_READ_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = readl(RCB_REG(IOBPD)); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { + printf("IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Write IOBP data */ + writel(data, RCB_REG(IOBPD)); + if (!iobp_poll()) + return; +} + static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c deleted file mode 100644 index c7ce408..0000000 --- a/arch/x86/cpu/ivybridge/pch.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * From Coreboot - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -static int pch_revision_id = -1; -static int pch_type = -1; - -int pch_silicon_revision(struct udevice *dev) -{ - u8 val; - - if (pch_revision_id < 0) { - dm_pci_read_config8(dev, PCI_REVISION_ID, &val); - pch_revision_id = val; - } - - return pch_revision_id; -} - -int pch_silicon_type(struct udevice *dev) -{ - u8 val; - - if (pch_type < 0) { - dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); - pch_type = val; - } - - return pch_type; -} - -int pch_silicon_supported(struct udevice *dev, int type, int rev) -{ - int cur_type = pch_silicon_type(dev); - int cur_rev = pch_silicon_revision(dev); - - switch (type) { - case PCH_TYPE_CPT: - /* CougarPoint minimum revision */ - if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) - return 1; - /* PantherPoint any revision */ - if (cur_type == PCH_TYPE_PPT) - return 1; - break; - - case PCH_TYPE_PPT: - /* PantherPoint minimum revision */ - if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) - return 1; - break; - } - - return 0; -} - -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned try = IOBP_RETRY; - u32 data; - - while (try--) { - data = readl(RCB_REG(IOBPS)); - if ((data & 1) == 0) - return 1; - udelay(10); - } - - printf("IOBP timeout\n"); - return 0; -} - -void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, - u32 orvalue) -{ - u32 data; - - /* Set the address */ - writel(address, RCB_REG(IOBPIRI)); - - /* READ OPCODE */ - if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) - writel(IOBPS_RW_BX, RCB_REG(IOBPS)); - else - writel(IOBPS_READ_AX, RCB_REG(IOBPS)); - if (!iobp_poll()) - return; - - /* Read IOBP data */ - data = readl(RCB_REG(IOBPD)); - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { - printf("IOBP read 0x%08x failed\n", address); - return; - } - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - /* WRITE OPCODE */ - if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) - writel(IOBPS_RW_BX, RCB_REG(IOBPS)); - else - writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); - if (!iobp_poll()) - return; - - /* Write IOBP data */ - writel(data, RCB_REG(IOBPD)); - if (!iobp_poll()) - return; -} diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 0f1aa01..af3e8e7 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -466,14 +466,6 @@ #define TCO2_STS 0x66
/** - * pch_silicon_revision() - Read silicon revision ID from the PCH - * - * @dev: PCH device - * @return silicon revision ID - */ -int pch_silicon_revision(struct udevice *dev); - -/** * pch_silicon_revision() - Read silicon device ID from the PCH * * @dev: PCH device @@ -482,16 +474,6 @@ int pch_silicon_revision(struct udevice *dev); int pch_silicon_type(struct udevice *dev);
/** - * pch_silicon_supported() - Check if a certain revision is supported - * - * @dev: PCH device - * @type: PCH type - * @rev: Minimum required resion - * @return 0 if not supported, 1 if supported - */ -int pch_silicon_supported(struct udevice *dev, int type, int rev); - -/** * pch_pch_iobp_update() - Update a pch register * * @dev: PCH device
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This code relates to the PCH, so we should move it into the same file.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/bd82x6x.c | 129 ++++++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/pch.c | 126 ----------------------------- arch/x86/include/asm/arch-ivybridge/pch.h | 18 ----- 4 files changed, 129 insertions(+), 145 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/pch.c
applied to u-boot-x86/master, thanks!
This function is called all over the place. Convert it use the driver model PCI API, and rationalise the calls.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Fix incorrect bits in bridge_silicon_revision() comment
arch/x86/cpu/ivybridge/gma.c | 33 ++++++++-------- arch/x86/cpu/ivybridge/northbridge.c | 47 +++++++++++------------ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 8 +++- 3 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index b94536c..f9b03f2 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -353,14 +353,13 @@ static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value) return 0; }
-static int gma_pm_init_pre_vbios(void *gtt_bar) +static int gma_pm_init_pre_vbios(void *gtt_bar, int rev) { u32 reg32;
- debug("GT Power Management Init, silicon = %#x\n", - bridge_silicon_revision()); + debug("GT Power Management Init, silicon = %#x\n", rev);
- if (bridge_silicon_revision() < IVB_STEP_C0) { + if (rev < IVB_STEP_C0) { /* 1: Enable force wake */ gtt_write(gtt_bar, 0xa18c, 0x00000001); gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0)); @@ -370,14 +369,14 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0)); }
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ reg32 = gtt_read(gtt_bar, 0x42004); reg32 |= (1 << 14) | (1 << 15); gtt_write(gtt_bar, 0x42004, reg32); }
- if (bridge_silicon_revision() >= IVB_STEP_A0) { + if (rev >= IVB_STEP_A0) { /* Display Reset Acknowledge Settings */ reg32 = gtt_read(gtt_bar, 0x45010); reg32 |= (1 << 1) | (1 << 0); @@ -386,7 +385,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
/* 2: Get GT SKU from GTT+0x911c[13] */ reg32 = gtt_read(gtt_bar, 0x911c); - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { if (reg32 & (1 << 13)) { debug("SNB GT1 Power Meter Weights\n"); gtt_write_powermeter(gtt_bar, snb_pm_gt1); @@ -435,13 +434,13 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) reg32 = gtt_read(gtt_bar, 0xa180); reg32 |= (1 << 26) | (1 << 31); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ - if (bridge_silicon_revision() >= SNB_STEP_D1) + if (rev >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(gtt_bar, 0xa180, reg32);
/* 6a: for SnB step D2+ only */ - if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && - (bridge_silicon_revision() >= SNB_STEP_D2)) { + if (((rev & BASE_REV_MASK) == BASE_REV_SNB) && + (rev >= SNB_STEP_D2)) { reg32 = gtt_read(gtt_bar, 0x9400); reg32 |= (1 << 7); gtt_write(gtt_bar, 0x9400, reg32); @@ -453,7 +452,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1)); }
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { reg32 = gtt_read(gtt_bar, 0x907c); reg32 |= (1 << 16); gtt_write(gtt_bar, 0x907c, reg32); @@ -505,7 +504,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
/* 11a: Enable Render Standby (RC6) */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { /* * IvyBridge should also support DeepRenderStandby. * @@ -539,14 +538,14 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) return 0; }
-int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node) +int gma_pm_init_post_vbios(int rev, void *gtt_bar, const void *blob, int node) { u32 reg32, cycle_delay;
debug("GT Power Management Init (post VBIOS)\n");
/* 15: Deassert Force Wake */ - if (bridge_silicon_revision() < IVB_STEP_C0) { + if (rev < IVB_STEP_C0) { gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1); gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0)); } else { @@ -805,6 +804,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node) ulong base; u32 reg32; int ret; + int rev;
/* Enable PCH Display Port */ writew(0x0010, RCB_REG(DISPBDF)); @@ -813,6 +813,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node) ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge); if (!nbridge) return -ENODEV; + rev = bridge_silicon_revision(nbridge); sandybridge_setup_graphics(nbridge, dev);
/* IGD needs to be Bus Master */ @@ -827,7 +828,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
gtt_bar = (void *)dm_pci_read_bar32(dev, 0); debug("GT bar %p\n", gtt_bar); - ret = gma_pm_init_pre_vbios(gtt_bar); + ret = gma_pm_init_pre_vbios(gtt_bar, rev); if (ret) return ret;
@@ -838,7 +839,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node) debug("BIOS ran in %lums\n", get_timer(start)); #endif /* Post VBIOS init */ - ret = gma_pm_init_post_vbios(gtt_bar, blob, node); + ret = gma_pm_init_post_vbios(rev, gtt_bar, blob, node); if (ret) return ret;
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index d52eb39..a066607 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -19,23 +19,17 @@ #include <asm/arch/model_206ax.h> #include <asm/arch/sandybridge.h>
-static int bridge_revision_id = -1; - -int bridge_silicon_revision(void) +int bridge_silicon_revision(struct udevice *dev) { - if (bridge_revision_id < 0) { - struct cpuid_result result; - uint8_t stepping, bridge_id; - pci_dev_t dev; - - result = cpuid(1); - stepping = result.eax & 0xf; - dev = PCI_BDF(0, 0, 0); - bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0; - bridge_revision_id = bridge_id | stepping; - } - - return bridge_revision_id; + struct cpuid_result result; + u16 bridge_id; + u8 stepping; + + result = cpuid(1); + stepping = result.eax & 0xf; + dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id); + bridge_id &= 0xf0; + return bridge_id | stepping; }
/* @@ -91,45 +85,45 @@ static void add_fixed_resources(struct udevice *dev, int index) } }
-static void northbridge_dmi_init(struct udevice *dev) +static void northbridge_dmi_init(struct udevice *dev, int rev) { /* Clear error status bits */ writel(0xffffffff, DMIBAR_REG(0x1c4)); writel(0xffffffff, DMIBAR_REG(0x1d0));
/* Steps prior to DMI ASPM */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), 1 << 21); }
setbits_le32(DMIBAR_REG(0x238), 1 << 29);
- if (bridge_silicon_revision() >= SNB_STEP_D0) { + if (rev >= SNB_STEP_D0) { setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); - } else if (bridge_silicon_revision() >= SNB_STEP_D1) { + } else if (rev >= SNB_STEP_D1) { clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); }
/* Enable ASPM on SNB link, should happen before PCH link */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); }
-static void northbridge_init(struct udevice *dev) +static void northbridge_init(struct udevice *dev, int rev) { u32 bridge_type;
add_fixed_resources(dev, 6); - northbridge_dmi_init(dev); + northbridge_dmi_init(dev, rev);
bridge_type = readl(MCHBAR_REG(0x5f10)); bridge_type &= ~0xff;
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { /* Enable Power Aware Interrupt Routing - fixed priority */ clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
@@ -220,10 +214,13 @@ static int bd82x6x_northbridge_early_init(struct udevice *dev)
static int bd82x6x_northbridge_probe(struct udevice *dev) { + int rev; + if (!(gd->flags & GD_FLG_RELOC)) return bd82x6x_northbridge_early_init(dev);
- northbridge_init(dev); + rev = bridge_silicon_revision(dev); + northbridge_init(dev, rev);
return 0; } diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index ce8d030..d137d67 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -108,7 +108,13 @@
#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
-int bridge_silicon_revision(void); +/** + * bridge_silicon_revision() - Get the Northbridge revision + * + * @dev: Northbridge device + * @return revision ID (bits 3:0) and bridge ID (bits 7:4) + */ +int bridge_silicon_revision(struct udevice *dev);
void report_platform_info(struct udevice *dev);
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This function is called all over the place. Convert it use the driver model PCI API, and rationalise the calls.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Fix incorrect bits in bridge_silicon_revision() comment
arch/x86/cpu/ivybridge/gma.c | 33 ++++++++-------- arch/x86/cpu/ivybridge/northbridge.c | 47 +++++++++++------------ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 8 +++- 3 files changed, 46 insertions(+), 42 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 3:35 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This function is called all over the place. Convert it use the driver model PCI API, and rationalise the calls.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Fix incorrect bits in bridge_silicon_revision() comment
arch/x86/cpu/ivybridge/gma.c | 33 ++++++++-------- arch/x86/cpu/ivybridge/northbridge.c | 47 +++++++++++------------ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 8 +++- 3 files changed, 46 insertions(+), 42 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Rename from 'Convert EHCI init to use the DM PCI API' - Drop this init - Fix the USB PCI address in the device tree
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/bd82x6x.c | 3 --- arch/x86/cpu/ivybridge/usb_ehci.c | 29 --------------------------- arch/x86/dts/chromebook_link.dts | 12 +++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 5 files changed, 12 insertions(+), 34 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 7007d5f..ac41853 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -17,5 +17,4 @@ obj-y += northbridge.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o -obj-y += usb_ehci.o obj-y += usb_xhci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 70a0aea..2591b20 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -159,9 +159,6 @@ static int bd82x6x_probe(struct udevice *dev) /* Cause the SATA device to do its init */ uclass_first_device(UCLASS_DISK, &dev);
- bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); - bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); - gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); if (gma_node < 0) { debug("%s: Cannot find GMA node\n", __func__); diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c deleted file mode 100644 index da11aee..0000000 --- a/arch/x86/cpu/ivybridge/usb_ehci.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * From Coreboot - * Copyright (C) 2008-2009 coresystems GmbH - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -void bd82x6x_usb_ehci_init(pci_dev_t dev) -{ - u32 reg32; - - /* Disable Wake on Disconnect in RMH */ - reg32 = readl(RCB_REG(0x35b0)); - reg32 |= 0x22; - writel(reg32, RCB_REG(0x35b0)); - - debug("EHCI: Setting up controller.. "); - reg32 = x86_pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - /* reg32 |= PCI_COMMAND_SERR; */ - x86_pci_write_config32(dev, PCI_COMMAND, reg32); - - debug("done.\n"); -} diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 329eae8..662e5d9 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -12,6 +12,8 @@
aliases { spi0 = "/pci/pch/spi"; + usb0 = &usb_0; + usb1 = &usb_1; };
config { @@ -226,6 +228,16 @@ u-boot,dm-pre-reloc; };
+ usb_1: usb@1a,0 { + reg = <0x0000d000 0 0 0 0>; + compatible = "ehci-pci"; + }; + + usb_0: usb@1d,0 { + reg = <0x0000e800 0 0 0 0>; + compatible = "ehci-pci"; + }; + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,bd82x6x", "intel,pch9"; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index bb3a6c9..5959717 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -7,7 +7,6 @@ #ifndef _ASM_ARCH_BD82X6X_H #define _ASM_ARCH_BD82X6X_H
-void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node);
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Rename from 'Convert EHCI init to use the DM PCI API'
- Drop this init
- Fix the USB PCI address in the device tree
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/bd82x6x.c | 3 --- arch/x86/cpu/ivybridge/usb_ehci.c | 29 --------------------------- arch/x86/dts/chromebook_link.dts | 12 +++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 5 files changed, 12 insertions(+), 34 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Jan 21, 2016 at 3:39 PM, Bin Meng bmeng.cn@gmail.com wrote:
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Rename from 'Convert EHCI init to use the DM PCI API'
- Drop this init
- Fix the USB PCI address in the device tree
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/bd82x6x.c | 3 --- arch/x86/cpu/ivybridge/usb_ehci.c | 29 --------------------------- arch/x86/dts/chromebook_link.dts | 12 +++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 5 files changed, 12 insertions(+), 34 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!
This is not used on link which is the only ivybridge board. Drop this code.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/usb_xhci.c | 32 --------------------------- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 3 files changed, 34 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index ac41853..45ef141 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -17,4 +17,3 @@ obj-y += northbridge.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o -obj-y += usb_xhci.o diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c deleted file mode 100644 index f77b804..0000000 --- a/arch/x86/cpu/ivybridge/usb_xhci.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * From Coreboot - * Copyright (C) 2008-2009 coresystems GmbH - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -void bd82x6x_usb_xhci_init(pci_dev_t dev) -{ - u32 reg32; - - debug("XHCI: Setting up controller.. "); - - /* lock overcurrent map */ - reg32 = x86_pci_read_config32(dev, 0x44); - reg32 |= 1; - x86_pci_write_config32(dev, 0x44, reg32); - - /* Enable clock gating */ - reg32 = x86_pci_read_config32(dev, 0x40); - reg32 &= ~((1 << 20) | (1 << 21)); - reg32 |= (1 << 19) | (1 << 18) | (1 << 17); - reg32 |= (1 << 10) | (1 << 9) | (1 << 8); - reg32 |= (1 << 31); /* lock */ - x86_pci_write_config32(dev, 0x40, reg32); - - debug("done.\n"); -} diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 5959717..2607da6 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -7,7 +7,6 @@ #ifndef _ASM_ARCH_BD82X6X_H #define _ASM_ARCH_BD82X6X_H
-void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node);
#endif
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
This is not used on link which is the only ivybridge board. Drop this code.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/usb_xhci.c | 32 --------------------------- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 - 3 files changed, 34 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c
applied to u-boot-x86/master, thanks!
U-Boot does not support SMM yet, so we can drop this code. It is easy to bring back when needed.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 57 -------------------------------------------- 1 file changed, 57 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 12e86cb..9ab5ed3 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -379,59 +379,6 @@ static void enable_clock_gating(struct udevice *pch) setbits_le32(RCB_REG(0x3564), 0x3); }
-#if CONFIG_HAVE_SMI_HANDLER -static void pch_lock_smm(pci_dev_t dev) -{ -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - - if (acpi_slp_type != 3) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - debug("Enabling ACPI via APMC:\n"); - outb(0xe1, 0xb2); /* Enable ACPI mode */ - debug("done.\n"); -#else - debug("Disabling ACPI via APMC:\n"); - outb(0x1e, 0xb2); /* Disable ACPI mode */ - debug("done.\n"); -#endif - } - - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - debug("Locking BIOS to RO... "); - reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", - (reg8 & 1) ? "rw" : "ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - x86_pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - x86_pci_write_config8(dev, 0xdc, reg8); - debug("ok.\n"); - reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", - (reg8 & 1) ? "rw" : "ro"); - - debug("Writing:\n"); - writeb(0, 0xfff00000); - debug("Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - x86_pci_write_config8(dev, 0xdc, reg8); - - reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", - (reg8 & 1) ? "rw" : "ro"); - debug("Done.\n"); -#endif -} -#endif - static void pch_disable_smm_only_flashing(struct udevice *pch) { u8 reg8; @@ -596,10 +543,6 @@ static int lpc_init_extra(struct udevice *dev)
pch_disable_smm_only_flashing(pch);
-#if CONFIG_HAVE_SMI_HANDLER - pch_lock_smm(dev); -#endif - pch_fixups(pch);
return 0;
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
U-Boot does not support SMM yet, so we can drop this code. It is easy to bring back when needed.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 57 -------------------------------------------- 1 file changed, 57 deletions(-)
applied to u-boot-x86/master, thanks!
Each system controller can have a number to identify it. It can then be accessed using syscon_get_by_driver_data(). Put this in a shared header file and update the only current user.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Enable SYSCON and REGMAP for panther to avoid a build error
arch/x86/cpu/ivybridge/early_me.c | 3 ++- arch/x86/cpu/ivybridge/sdram.c | 6 +++--- arch/x86/include/asm/cpu.h | 9 +++++++++ configs/chromebox_panther_defconfig | 2 ++ 4 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index 612c910..f0d6899 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -10,6 +10,7 @@ #include <dm.h> #include <errno.h> #include <asm/pci.h> +#include <asm/cpu.h> #include <asm/processor.h> #include <asm/arch/me.h> #include <asm/arch/pch.h> @@ -189,7 +190,7 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, }
static const struct udevice_id ivybridge_syscon_ids[] = { - { .compatible = "intel,me", }, + { .compatible = "intel,me", .data = X86_SYSCON_ME }, { } };
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 3e5be4e..e23c422 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -18,6 +18,8 @@ #include <rtc.h> #include <spi.h> #include <spi_flash.h> +#include <syscon.h> +#include <asm/cpu.h> #include <asm/processor.h> #include <asm/gpio.h> #include <asm/global_data.h> @@ -739,11 +741,9 @@ int dram_init(void) return ret; if (!dev) return -ENODEV; - ret = uclass_first_device(UCLASS_SYSCON, &me_dev); + ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); if (ret) return ret; - if (!me_dev) - return -ENODEV; debug("Boot mode %d\n", gd->arch.pei_boot_mode); debug("mrc_input %p\n", pei_data.mrc_input); pei_data.boot_mode = gd->arch.pei_boot_mode; diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index c70183c..76cdf47 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -45,6 +45,15 @@ enum { GDT_BASE_HIGH_MASK = 0xf, };
+/* + * System controllers in an x86 system. We mostly need to just find these and + * use them on PCI. At some point these might have their own uclass. + */ +enum { + X86_NONE, + X86_SYSCON_ME, /* Intel Management Engine */ +}; + struct cpuid_result { uint32_t eax; uint32_t ebx; diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 4b78292..bb6c5d4 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -16,6 +16,8 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Each system controller can have a number to identify it. It can then be accessed using syscon_get_by_driver_data(). Put this in a shared header file and update the only current user.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Enable SYSCON and REGMAP for panther to avoid a build error
arch/x86/cpu/ivybridge/early_me.c | 3 ++- arch/x86/cpu/ivybridge/sdram.c | 6 +++--- arch/x86/include/asm/cpu.h | 9 +++++++++ configs/chromebox_panther_defconfig | 2 ++ 4 files changed, 16 insertions(+), 4 deletions(-)
applied to u-boot-x86/master, thanks!
Until we have a proper video uclass we can use syscon to handle the GMA device, and avoid the special device tree and PCI searching. Update the code to work this way.
Reviewed-by: Bin Meng bmeng.cn@gmail.com Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 14 +++++--------- arch/x86/cpu/ivybridge/early_me.c | 1 + arch/x86/cpu/ivybridge/gma.c | 8 +++++--- arch/x86/dts/chromebook_link.dts | 3 ++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 +- arch/x86/include/asm/cpu.h | 4 +++- 6 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 2591b20..2b172d4 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -9,6 +9,8 @@ #include <fdtdec.h> #include <malloc.h> #include <pch.h> +#include <syscon.h> +#include <asm/cpu.h> #include <asm/io.h> #include <asm/lapic.h> #include <asm/pci.h> @@ -149,8 +151,7 @@ void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
static int bd82x6x_probe(struct udevice *dev) { - const void *blob = gd->fdt_blob; - int gma_node; + struct udevice *gma_dev; int ret;
if (!(gd->flags & GD_FLG_RELOC)) @@ -159,15 +160,10 @@ static int bd82x6x_probe(struct udevice *dev) /* Cause the SATA device to do its init */ uclass_first_device(UCLASS_DISK, &dev);
- gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); - if (gma_node < 0) { - debug("%s: Cannot find GMA node\n", __func__); - return -EINVAL; - } - ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev); + ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev); if (ret) return ret; - ret = gma_func0_init(dev, blob, gma_node); + ret = gma_func0_init(gma_dev); if (ret) return ret;
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index f0d6899..b1df77d 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -191,6 +191,7 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
static const struct udevice_id ivybridge_syscon_ids[] = { { .compatible = "intel,me", .data = X86_SYSCON_ME }, + { .compatible = "intel,gma", .data = X86_SYSCON_GMA }, { } };
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index f9b03f2..3b6291e 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -538,8 +538,10 @@ static int gma_pm_init_pre_vbios(void *gtt_bar, int rev) return 0; }
-int gma_pm_init_post_vbios(int rev, void *gtt_bar, const void *blob, int node) +int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar) { + const void *blob = gd->fdt_blob; + int node = dev->of_offset; u32 reg32, cycle_delay;
debug("GT Power Management Init (post VBIOS)\n"); @@ -794,7 +796,7 @@ void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev) writel(reg32, MCHBAR_REG(0x5418)); }
-int gma_func0_init(struct udevice *dev, const void *blob, int node) +int gma_func0_init(struct udevice *dev) { #ifdef CONFIG_VIDEO ulong start; @@ -839,7 +841,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node) debug("BIOS ran in %lums\n", get_timer(start)); #endif /* Post VBIOS init */ - ret = gma_pm_init_post_vbios(rev, gtt_bar, blob, node); + ret = gma_pm_init_post_vbios(dev, rev, gtt_bar); if (ret) return ret;
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 662e5d9..d148d6e 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -209,7 +209,8 @@ u-boot,dm-pre-reloc; };
- gma { + gma@2,0 { + reg = <0x00001000 0 0 0 0>; compatible = "intel,gma"; intel,dp_hotplug = <0 0 0x06>; intel,panel-port-select = <1>; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 2607da6..e866580 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -7,6 +7,6 @@ #ifndef _ASM_ARCH_BD82X6X_H #define _ASM_ARCH_BD82X6X_H
-int gma_func0_init(struct udevice *dev, const void *blob, int node); +int gma_func0_init(struct udevice *dev);
#endif diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 76cdf47..18b0345 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -47,11 +47,13 @@ enum {
/* * System controllers in an x86 system. We mostly need to just find these and - * use them on PCI. At some point these might have their own uclass. + * use them on PCI. At some point these might have their own uclass (e.g. + * UCLASS_VIDEO for the GMA device). */ enum { X86_NONE, X86_SYSCON_ME, /* Intel Management Engine */ + X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */ };
struct cpuid_result {
On Mon, Jan 18, 2016 at 7:11 AM, Simon Glass sjg@chromium.org wrote:
Until we have a proper video uclass we can use syscon to handle the GMA device, and avoid the special device tree and PCI searching. Update the code to work this way.
Reviewed-by: Bin Meng bmeng.cn@gmail.com Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 14 +++++--------- arch/x86/cpu/ivybridge/early_me.c | 1 + arch/x86/cpu/ivybridge/gma.c | 8 +++++--- arch/x86/dts/chromebook_link.dts | 3 ++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 +- arch/x86/include/asm/cpu.h | 4 +++- 6 files changed, 17 insertions(+), 15 deletions(-)
applied to u-boot-x86/master, thanks!
We have drivers for several more devices now, so drop the strings which are no-longer used.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Drop bd82x6x_pci_init() function and associated DM-conversion patch - Drop LPC init method an 'Add an init() method to the LPC uclass' patch
arch/x86/cpu/ivybridge/lpc.c | 6 ------ include/fdtdec.h | 5 ----- lib/fdtdec.c | 5 ----- 3 files changed, 16 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 9ab5ed3..deda2f5 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -491,8 +491,6 @@ static int lpc_early_init(struct udevice *dev) static int lpc_init_extra(struct udevice *dev) { struct udevice *pch = dev->parent; - const void *blob = gd->fdt_blob; - int node;
debug("pch: lpc_init\n"); dm_pci_write_bar32(pch, 0, 0); @@ -501,10 +499,6 @@ static int lpc_init_extra(struct udevice *dev) dm_pci_write_bar32(pch, 3, 0x800); dm_pci_write_bar32(pch, 4, 0x900);
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); - if (node < 0) - return -ENOENT; - /* Set the value for PCI command register. */ dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
diff --git a/include/fdtdec.h b/include/fdtdec.h index 27b350e..e545866 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,15 +155,10 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ COMPAT_MEMORY_SPD, /* Memory SPD information */ - COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ - COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */ - COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ - COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_INTEL_X86_PINCTRL, /* Intel ICH7/9 pin control */ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ - COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index b50d105..3c05559 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -60,15 +60,10 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(INTEL_MICROCODE, "intel,microcode"), COMPAT(MEMORY_SPD, "memory-spd"), - COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"), - COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"), - COMPAT(INTEL_GMA, "intel,gma"), COMPAT(AMS_AS3722, "ams,as3722"), - COMPAT(INTEL_ICH_SPI, "intel,ich-spi"), COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"), COMPAT(INTEL_X86_PINCTRL, "intel,x86-pinctrl"), COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"), - COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"), COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"), COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
Hi Simon,
On Mon, Jan 18, 2016 at 7:12 AM, Simon Glass sjg@chromium.org wrote:
We have drivers for several more devices now, so drop the strings which are no-longer used.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Drop bd82x6x_pci_init() function and associated DM-conversion patch
- Drop LPC init method an 'Add an init() method to the LPC uclass' patch
arch/x86/cpu/ivybridge/lpc.c | 6 ------ include/fdtdec.h | 5 ----- lib/fdtdec.c | 5 ----- 3 files changed, 16 deletions(-)
This patch does not apply on existing u-boot-x86/master. I tried to rebase u-boot-x86/master on top of latest u-boot/master, but it still does not apply. Please rebase this patch on top of current u-boot-x86/master and submit a new version. Thanks!
Regards, Bin
participants (3)
-
Bin Meng -
Marek Vasut -
Simon Glass