[U-Boot] [next PATCH v2 1/2] ARM: mvebu: Add SoC IDs for Marvell's integrated CPUs
These SoCs are network packet processors (switch chips) with integrated ARMv7 cores. They share a great deal of commonality with the Armada-XP CPUs.
Signed-off-by: Chris Packham judge.packham@gmail.com --- There are actually a number of IDs for these chips, probably a dozen in total. I haven't enumerated them all in this patch, the 98DX4251, 98DX3336 and 98DX3236 are the base versions in their respective ranges. These 3 IDs also happen to suit my immediate need but I can add the additional ones in an follow up patch or a re-roll of this one.
Changes in v2: - none
arch/arm/mach-mvebu/cpu.c | 14 ++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 1 + arch/arm/mach-mvebu/include/mach/soc.h | 3 +++ 3 files changed, 18 insertions(+)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 14457317ce76..f7f83bfa3655 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -62,6 +62,11 @@ int mvebu_soc_family(void) case SOC_88F6820_ID: case SOC_88F6828_ID: return MVEBU_SOC_A38X; + + case SOC_98DX3236_ID: + case SOC_98DX3336_ID: + case SOC_98DX4251_ID: + return MVEBU_SOC_MSYS; }
return MVEBU_SOC_UNKNOWN; @@ -208,6 +213,15 @@ int print_cpuinfo(void) case SOC_88F6828_ID: puts("MV88F6828-"); break; + case SOC_98DX3236_ID: + puts("98DX3236-"); + break; + case SOC_98DX3336_ID: + puts("98DX3336-"); + break; + case SOC_98DX4251_ID: + puts("98DX4251-"); + break; default: puts("Unknown-"); break; diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index d241eea9568d..b67b77ae0df4 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -65,6 +65,7 @@ enum { MVEBU_SOC_AXP, MVEBU_SOC_A375, MVEBU_SOC_A38X, + MVEBU_SOC_MSYS, MVEBU_SOC_UNKNOWN, };
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 0900e4008c12..cdd64fb28527 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -18,6 +18,9 @@ #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 #define SOC_88F6828_ID 0x6828 +#define SOC_98DX3236_ID 0xf410 +#define SOC_98DX3336_ID 0xf400 +#define SOC_98DX4251_ID 0xfc00
/* A375 revisions */ #define MV_88F67XX_A0_ID 0x3
From: Joshua Scott joshua.scott@alliedtelesis.co.nz
Display more information about the current RAM configuration. With these changes the output on a 88F6820 board is
SoC: MV88F6820-A0 at 1600 MHz DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)
Signed-off-by: Joshua Scott joshua.scott@alliedtelesis.co.nz Signed-off-by: Chris Packham judge.packham@gmail.com --- One of the hardware designers at $dayjob expressed a desire to keep track of various tweaks to the DDR setup during hardware debugging sessions. This is the result.
I've based this on what is available for the fsl platforms. It might be nice to add a few more things but I'm concious of keeping the information relevant and succinct.
Changes in v2: - A375 and A38x have 16/32b DDR bus
arch/arm/mach-mvebu/dram.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)
diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index e3f304c36683..55e9ad726a88 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -216,6 +216,35 @@ static int ecc_enabled(void)
return 0; } + +/* Return the width of the DRAM bus, or 0 for unknown. */ +static int bus_width(void) +{ + int full_width = 0; + + if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) + full_width = 1; + + switch (mvebu_soc_family()) { + case MVEBU_SOC_AXP: + return full_width ? 64 : 32; + break; + case MVEBU_SOC_A375: + case MVEBU_SOC_A38X: + case MVEBU_SOC_MSYS: + return full_width ? 32 : 16; + default: + return 0; + } +} + +static int cycle_mode(void) +{ + int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR); + + return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK; +} + #else static void dram_ecc_scrubbing(void) { @@ -295,10 +324,26 @@ int dram_init_banksize(void) void board_add_ram_info(int use_default) { struct sar_freq_modes sar_freq; + int mode; + int width;
get_sar_freq(&sar_freq); printf(" (%d MHz, ", sar_freq.d_clk);
+ width = bus_width(); + if (width) + printf("%d-bit, ", width); + + mode = cycle_mode(); + /* Mode 0 = Single cycle + * Mode 1 = Two cycles (2T) + * Mode 2 = Three cycles (3T) + */ + if (mode == 1) + printf("2T, "); + if (mode == 2) + printf("3T, "); + if (ecc_enabled()) printf("ECC"); else
On 04.09.2017 07:38, Chris Packham wrote:
From: Joshua Scott joshua.scott@alliedtelesis.co.nz
Display more information about the current RAM configuration. With these changes the output on a 88F6820 board is
SoC: MV88F6820-A0 at 1600 MHz DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)
Signed-off-by: Joshua Scott joshua.scott@alliedtelesis.co.nz Signed-off-by: Chris Packham judge.packham@gmail.com
One of the hardware designers at $dayjob expressed a desire to keep track of various tweaks to the DDR setup during hardware debugging sessions. This is the result.
I've based this on what is available for the fsl platforms. It might be nice to add a few more things but I'm concious of keeping the information relevant and succinct.
Changes in v2:
A375 and A38x have 16/32b DDR bus
arch/arm/mach-mvebu/dram.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On 04.09.2017 07:38, Chris Packham wrote:
From: Joshua Scott joshua.scott@alliedtelesis.co.nz
Display more information about the current RAM configuration. With these changes the output on a 88F6820 board is
SoC: MV88F6820-A0 at 1600 MHz DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)
Signed-off-by: Joshua Scott joshua.scott@alliedtelesis.co.nz Signed-off-by: Chris Packham judge.packham@gmail.com
One of the hardware designers at $dayjob expressed a desire to keep track of various tweaks to the DDR setup during hardware debugging sessions. This is the result.
I've based this on what is available for the fsl platforms. It might be nice to add a few more things but I'm concious of keeping the information relevant and succinct.
Changes in v2:
- A375 and A38x have 16/32b DDR bus
Applied to u-boot-marvell/master.
Thanks, Stefan
On 04.09.2017 07:38, Chris Packham wrote:
These SoCs are network packet processors (switch chips) with integrated ARMv7 cores. They share a great deal of commonality with the Armada-XP CPUs.
Signed-off-by: Chris Packham judge.packham@gmail.com
There are actually a number of IDs for these chips, probably a dozen in total. I haven't enumerated them all in this patch, the 98DX4251, 98DX3336 and 98DX3236 are the base versions in their respective ranges. These 3 IDs also happen to suit my immediate need but I can add the additional ones in an follow up patch or a re-roll of this one.
Changes in v2:
none
arch/arm/mach-mvebu/cpu.c | 14 ++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 1 + arch/arm/mach-mvebu/include/mach/soc.h | 3 +++ 3 files changed, 18 insertions(+)
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On 04.09.2017 07:38, Chris Packham wrote:
These SoCs are network packet processors (switch chips) with integrated ARMv7 cores. They share a great deal of commonality with the Armada-XP CPUs.
Signed-off-by: Chris Packham judge.packham@gmail.com
There are actually a number of IDs for these chips, probably a dozen in total. I haven't enumerated them all in this patch, the 98DX4251, 98DX3336 and 98DX3236 are the base versions in their respective ranges. These 3 IDs also happen to suit my immediate need but I can add the additional ones in an follow up patch or a re-roll of this one.
Changes in v2:
- none
Applied to u-boot-marvell/master.
Thanks, Stefan
participants (2)
-
Chris Packham -
Stefan Roese