[U-Boot] [PATCH 01/12 v2] arm: at91: Makefile: Compile lowlevel_init only when really necessary
Make sure that lowlevel_init is not compiled when CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - No change
arch/arm/mach-at91/arm926ejs/Makefile | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index 0639d7ea1e..6b0b28957a 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -24,8 +24,10 @@ obj-y += timer.o endif
ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY obj-y += lowlevel_init.o endif +endif
ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2
This patch adds a call to spl_early_init() to board_init_f() which is needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for the early SPL setup including the DTB setup for later usage.
Please note that this call might also be needed for non SPL_OF_CONTROL board, like the smartweb target. But smartweb fails to build with this call because its binary grows too big. So I disabled it for these kind of targets for now.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - No change
arch/arm/mach-at91/spl_at91.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index 23ebaa99b1..1065f090e0 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -75,6 +75,16 @@ void __weak spl_board_init(void)
void board_init_f(ulong dummy) { +#if CONFIG_IS_ENABLED(OF_CONTROL) + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } +#endif + lowlevel_clock_init(); #if !defined(CONFIG_WDT_AT91) at91_disable_wdt();
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch adds a call to spl_early_init() to board_init_f() which is needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for the early SPL setup including the DTB setup for later usage.
Please note that this call might also be needed for non SPL_OF_CONTROL board, like the smartweb target. But smartweb fails to build with this call because its binary grows too big. So I disabled it for these kind of targets for now.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
arch/arm/mach-at91/spl_at91.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
Yes ... smartweb board ... The problem is, I have there only 4k for SPL ... no chance for DM nor DTS ...
bye, Heiko
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
If some boards need a different clock than the one provided with this patch, then support for this needs to be added later.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/atmel_usart.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..049172baef 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };
+#ifdef CONFIG_SPL_BUILD +static int atmel_serial_enable_clk(struct udevice *dev) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + /* Use fixed clock value in SPL */ + priv->usart_clk_rate = 132096000; + + return 0; +} +#else static int atmel_serial_enable_clk(struct udevice *dev) { struct atmel_serial_priv *priv = dev_get_priv(dev); @@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
return 0; } +#endif
static int atmel_serial_probe(struct udevice *dev) {
On 26.03.2019 14:16, Stefan Roese wrote:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
Hello Stefan,
For example, sama5d2_xplained_mmc_defconfig has DM_SERIAL and SPL. This means it's affected ? If so, then it's not OK to take it as-is.
And another question, is the rest of your patch series OK if this patch is missing ? Or it's any dependency on this ? the SPL for Gardena will not fit in the SRAM without this patch ?
Eugen
If some boards need a different clock than the one provided with this patch, then support for this needs to be added later.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/atmel_usart.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..049172baef 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };
+#ifdef CONFIG_SPL_BUILD +static int atmel_serial_enable_clk(struct udevice *dev) +{
- struct atmel_serial_priv *priv = dev_get_priv(dev);
- /* Use fixed clock value in SPL */
- priv->usart_clk_rate = 132096000;
- return 0;
+} +#else static int atmel_serial_enable_clk(struct udevice *dev) { struct atmel_serial_priv *priv = dev_get_priv(dev); @@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
return 0; } +#endif
static int atmel_serial_probe(struct udevice *dev) {
On 29.03.19 10:54, Eugen.Hristev@microchip.com wrote:
On 26.03.2019 14:16, Stefan Roese wrote:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
Hello Stefan,
For example, sama5d2_xplained_mmc_defconfig has DM_SERIAL and SPL.
Ah, I was not aware of that. It also has CONFIG_SPL_CLK enabled, that's why I didn't spot it. I should make sure that in such cases the original atmel_serial_enable_clk() function is used.
BTW: I did not enable CONFIG_SPL_CLK for size reasons of the SPL.
This means it's affected ? If so, then it's not OK to take it as-is.
Sure, this is not good, as mentioned above. I'll re-work this path to only enable the new fixed clock value for !SPL_CLK.
And another question, is the rest of your patch series OK if this patch is missing ? Or it's any dependency on this ? the SPL for Gardena will not fit in the SRAM without this patch ?
Without this patch, building the gardena board will break (IIRC), most likely because the CLK stuff is missing. And enabling SPL_CLK will result in a too big image.
Thanks, Stefan
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
If some boards need a different clock than the one provided with this patch, then support for this needs to be added later.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/atmel_usart.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..049172baef 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };
+#ifdef CONFIG_SPL_BUILD +static int atmel_serial_enable_clk(struct udevice *dev) +{
- struct atmel_serial_priv *priv = dev_get_priv(dev);
- /* Use fixed clock value in SPL */
- priv->usart_clk_rate = 132096000;
Hmm... could we have this value immediately configurable?
Beside of this nitpick:
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
On 29.03.19 11:21, Heiko Schocher wrote:
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
If some boards need a different clock than the one provided with this patch, then support for this needs to be added later.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/atmel_usart.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..049172baef 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };
+#ifdef CONFIG_SPL_BUILD +static int atmel_serial_enable_clk(struct udevice *dev) +{
- struct atmel_serial_priv *priv = dev_get_priv(dev);
- /* Use fixed clock value in SPL */
- priv->usart_clk_rate = 132096000;
Hmm... could we have this value immediately configurable?
Sure. I'll add the CONFIG_SPL_UART_CLOCK as discussed before with Eugen.
Thanks, Stefan
Beside of this nitpick:
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
Viele Grüße, Stefan
This patch adds some checks, so that the watchdog can be enabled in main U-Boot proper but can be disabled in SPL.
This will be used by some AT91SAM based boards, which might enable the watchdog in the main U-Boot proper and not in SPL. It will be enabled in SPL by default there, so no need to configure it there. This approach saves some space in SPL.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - No change
include/watchdog.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/watchdog.h b/include/watchdog.h index 14073cfdd2..3a357de903 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -51,9 +51,15 @@ int init_func_watchdog_reset(void); #if defined(__ASSEMBLY__) #define WATCHDOG_RESET bl watchdog_reset #else - extern void watchdog_reset(void); + /* Don't require the watchdog to be enabled in SPL */ + #if defined(CONFIG_SPL_BUILD) && \ + !defined(CONFIG_SPL_WATCHDOG_SUPPORT) + #define WATCHDOG_RESET() {} + #else + extern void watchdog_reset(void);
- #define WATCHDOG_RESET watchdog_reset + #define WATCHDOG_RESET watchdog_reset + #endif #endif #else /*
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch adds some checks, so that the watchdog can be enabled in main U-Boot proper but can be disabled in SPL.
This will be used by some AT91SAM based boards, which might enable the watchdog in the main U-Boot proper and not in SPL. It will be enabled in SPL by default there, so no need to configure it there. This approach saves some space in SPL.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
include/watchdog.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
This patch fixes the timer register setup in at91_wdt_start() to correctly configure the register again. The input timeout value is now in milli-seconds instead of seconds with the new watchdog API. Make sure to take this into account and only use a max timeout value of 16 seconds as appropriate for this SoC.
Also the check against a lower timeout value than 0 is removed. This check makes no sense, as the timeout value is unsigned.
Signed-off-by: Stefan Roese sr@denx.de Reported-by: Heiko Schocher hs@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - No change
drivers/watchdog/at91sam9_wdt.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 13f8772e41..b0a3b4ed58 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/arch/at91_wdt.h> #include <common.h> +#include <div64.h> #include <dm.h> #include <errno.h> #include <wdt.h> @@ -31,27 +32,30 @@ DECLARE_GLOBAL_DATA_PTR; #define WDT_SEC2TICKS(s) (((s) << 8) - 1)
/* Hardware timeout in seconds */ -#define WDT_MAX_TIMEOUT 16 -#define WDT_MIN_TIMEOUT 0 -#define WDT_DEFAULT_TIMEOUT 2 +#define WDT_MAX_TIMEOUT 16 +#define WDT_DEFAULT_TIMEOUT 2
struct at91_wdt_priv { void __iomem *regs; - u32 regval; - u32 timeout; + u32 regval; + u32 timeout; };
/* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit. */ -static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) +static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { struct at91_wdt_priv *priv = dev_get_priv(dev); - u32 timeout = WDT_SEC2TICKS(timeout_s); + u64 timeout; + u32 ticks;
- if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT) - timeout = priv->timeout; + /* Calculate timeout in seconds and the resulting ticks */ + timeout = timeout_ms; + do_div(timeout, 1000); + timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT); + ticks = WDT_SEC2TICKS(timeout);
/* Check if disabled */ if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) { @@ -65,12 +69,10 @@ static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ - priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ - | AT91_WDT_MR_WDV(timeout); /* timer value */ - + | AT91_WDT_MR_WDV(ticks); /* timer value */ writel(priv->regval, priv->regs + AT91_WDT_MR);
return 0;
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch fixes the timer register setup in at91_wdt_start() to correctly configure the register again. The input timeout value is now in milli-seconds instead of seconds with the new watchdog API. Make sure to take this into account and only use a max timeout value of 16 seconds as appropriate for this SoC.
Also the check against a lower timeout value than 0 is removed. This check makes no sense, as the timeout value is unsigned.
Signed-off-by: Stefan Roese sr@denx.de Reported-by: Heiko Schocher hs@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
drivers/watchdog/at91sam9_wdt.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-)
Thanks!
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
This patch enables and starts the watchdog on the AT91 platform if configured. Currently the WD timeout is configured to 16 seconds, which is the longest value for this timer.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - Remove #ifdef to enable compilation also in SPL version
arch/arm/mach-at91/clock.c | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 64cbc3d1ed..e3513f3473 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -5,12 +5,16 @@ */
#include <common.h> +#include <dm.h> +#include <wdt.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h>
#define EN_UPLL_TIMEOUT 500
+static struct udevice *watchdog_dev; + void at91_periph_clk_enable(int id) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; @@ -118,3 +122,38 @@ void at91_pllicpr_init(u32 icpr)
writel(icpr, &pmc->pllicpr); } + +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + static ulong next_reset; + ulong now; + + if (!watchdog_dev) + return; + + now = get_timer(0); + + /* Do not reset the watchdog too often */ + if (now > next_reset) { + next_reset = now + 1000; /* reset every 1000ms */ + wdt_reset(watchdog_dev); + } +} + +int arch_misc_init(void) +{ + /* Init watchdog */ + if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { + debug("Watchdog: Not found by seq!\n"); + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { + puts("Watchdog: Not found!\n"); + return 0; + } + } + + wdt_start(watchdog_dev, 16000, 0); /* 16 seconds is max */ + printf("Watchdog: Started\n"); + + return 0; +}
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch enables and starts the watchdog on the AT91 platform if configured. Currently the WD timeout is configured to 16 seconds, which is the longest value for this timer.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
Remove #ifdef to enable compilation also in SPL version
arch/arm/mach-at91/clock.c | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 64cbc3d1ed..e3513f3473 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -5,12 +5,16 @@ */
#include <common.h> +#include <dm.h> +#include <wdt.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h>
#define EN_UPLL_TIMEOUT 500
+static struct udevice *watchdog_dev;
This does not work for me on the taurus Board!
This variable sits in the BSS, which is not set to 0 before U-Boot is relocated.
On the taurus board I see:
System.map: 21040930 b next_reset.9546 21040934 b watchdog_dev 21040938 b data.8182
hexudmp u-boot.bin: (TEXT_BASE 0x21000000)
00040920 00 00 00 00 00 00 00 00 01 00 00 00 20 00 00 21 |............ ..!| 00040930 17 00 00 00 24 00 00 21 17 00 00 00 28 00 00 21 |....$..!....(..!| 00040940 17 00 00 00 2c 00 00 21 17 00 00 00 30 00 00 21 |....,..!....0..!|
And I see before relocation 0x21000024 for *watchdog_dev ... which leads in failure of the check "if (!watchdog_dev)" and cpu accesses wrong addresses in the end ...
As discussed offline moving watchdog_dev to data section helps:
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index e3513f3473..45e5f2fb57 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -13,7 +13,7 @@
#define EN_UPLL_TIMEOUT 500
-static struct udevice *watchdog_dev; +static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
void at91_periph_clk_enable(int id) {
The big question is, how many places do we have in code, where we access BSS before relocation ?
May we better clear BSS very early (at last may possible on arm)?
- void at91_periph_clk_enable(int id) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
@@ -118,3 +122,38 @@ void at91_pllicpr_init(u32 icpr)
writel(icpr, &pmc->pllicpr); }
+/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{
- static ulong next_reset;
- ulong now;
- if (!watchdog_dev)
return;- now = get_timer(0);
- /* Do not reset the watchdog too often */
- if (now > next_reset) {
next_reset = now + 1000; /* reset every 1000ms */wdt_reset(watchdog_dev);- }
+}
+int arch_misc_init(void) +{
- /* Init watchdog */
- if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
debug("Watchdog: Not found by seq!\n");if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {puts("Watchdog: Not found!\n");return 0;}- }
- wdt_start(watchdog_dev, 16000, 0); /* 16 seconds is max */
Here we have now a fix wdt timeout for all at91 based boards ...
We should use the value from DTS.
Beside of this, wdt is now running fine again on the taurus board!
Thanks for this work.
- printf("Watchdog: Started\n");
- return 0;
+}
bye, Heiko
Dear Heiko,
In message 81e69dec-21e7-7b34-a261-e22ae9bef795@denx.de you wrote:
The big question is, how many places do we have in code, where we access BSS before relocation ?
Hopefully none.
May we better clear BSS very early (at last may possible on arm)?
You cannot. There is no storage allocated for BSS - this happens only during relocation, and then it also gets zeroed.
Best regards,
Wolfgang Denk
Hi Wolfgang,
On 29.03.19 13:06, Wolfgang Denk wrote:
In message 81e69dec-21e7-7b34-a261-e22ae9bef795@denx.de you wrote:
The big question is, how many places do we have in code, where we access BSS before relocation ?
Hopefully none.
May we better clear BSS very early (at last may possible on arm)?
You cannot. There is no storage allocated for BSS - this happens only during relocation, and then it also gets zeroed.
This is not 100% correct for all platforms. On some targets, e.g. where the DDR is initialized by SPL, the BSS location before relocation is already a valid address space in DDR in the main U-Boot proper. AFAICT, the BSS *could* already be used before relocation in these cases. Here the BBS could be cleared very early and relocated later with the code etc. No clearing in the relocation stage necessary.
But since this is a special case, it makes no real sense to implement such an "early BSS" strategy into U-Boot, as other platforms will always exist, where the BSS is really only available after relocation (as you mentioned above).
Thanks, Stefan
Hello Wolfgang,
added Simon Goldschmidt to cc, as he just posted a patchset, which exactly wants to introduce "clear BSS before relocation" ...
Am 29.03.2019 um 13:06 schrieb Wolfgang Denk:
Dear Heiko,
In message 81e69dec-21e7-7b34-a261-e22ae9bef795@denx.de you wrote:
The big question is, how many places do we have in code, where we access BSS before relocation ?
Hopefully none.
Hmm... Hopefully, but I think, not easy to detect when reviewing patches ... I just stumbeld over this issue in this patch from Stefan, because I could try it on a hardware, and my hardware doesn;t boot with this patch...
Theoretically you must check all vars, which are in BSS segment, if they are used before relocation ... and drop an error, no idea yet, how to detect this at compile time ...
May we better clear BSS very early (at last may possible on arm)?
You cannot. There is no storage allocated for BSS - this happens only during relocation, and then it also gets zeroed.
Yes, valid for the boards which have no SPL ... but if U-Boot is loaded with SPL into RAM, BSS is writeable. But as this is not valid for all boards, we cannot do this!
Just see the patches from Simon:
https://lists.denx.de/pipermail/u-boot/2019-March/361452.html
http://patchwork.ozlabs.org/patch/1067363/
Same problem ...
bye, Heiko
On Mon, Apr 1, 2019 at 7:41 AM Heiko Schocher hs@denx.de wrote:
Hello Wolfgang,
added Simon Goldschmidt to cc, as he just posted a patchset, which exactly wants to introduce "clear BSS before relocation" ...
Am 29.03.2019 um 13:06 schrieb Wolfgang Denk:
Dear Heiko,
In message 81e69dec-21e7-7b34-a261-e22ae9bef795@denx.de you wrote:
The big question is, how many places do we have in code, where we access BSS before relocation ?
Hopefully none.
Hmm... Hopefully, but I think, not easy to detect when reviewing patches ... I just stumbeld over this issue in this patch from Stefan, because I could try it on a hardware, and my hardware doesn;t boot with this patch...
Theoretically you must check all vars, which are in BSS segment, if they are used before relocation ... and drop an error, no idea yet, how to detect this at compile time ...
May we better clear BSS very early (at last may possible on arm)?
You cannot. There is no storage allocated for BSS - this happens only during relocation, and then it also gets zeroed.
Yes, valid for the boards which have no SPL ... but if U-Boot is loaded with SPL into RAM, BSS is writeable. But as this is not valid for all boards, we cannot do this!
Just see the patches from Simon:
https://lists.denx.de/pipermail/u-boot/2019-March/361452.html
http://patchwork.ozlabs.org/patch/1067363/
Same problem ...
OK, so the word stands "BSS is not used before relocation". Like already mentioned, we don't have a check that tells us when this rule is violated. Being like that, I would be surprised if such a check (if added) would yield zero failures...
However, I'm not sure what "relocation" means for SPL boards where the SPL is loaded into SRAM (as is the case on many ARM boards at least). The correct wording here might be "RAM available" or something like that, instead of "relocation".
With this definition, a new question arises: how can I be forced to provide a malloc implementation in "pre-reloc" phase (for pre-reloc driver model, e.g. drivers for serial and SDRAM) when people keep telling me bss might not even be available? That sounds a bit confusing to me.
Regards, Simon
Hello Simon,
Am 01.04.2019 um 11:13 schrieb Simon Goldschmidt:
On Mon, Apr 1, 2019 at 7:41 AM Heiko Schocher hs@denx.de wrote:
Hello Wolfgang,
added Simon Goldschmidt to cc, as he just posted a patchset, which exactly wants to introduce "clear BSS before relocation" ...
Am 29.03.2019 um 13:06 schrieb Wolfgang Denk:
Dear Heiko,
In message 81e69dec-21e7-7b34-a261-e22ae9bef795@denx.de you wrote:
The big question is, how many places do we have in code, where we access BSS before relocation ?
Hopefully none.
Hmm... Hopefully, but I think, not easy to detect when reviewing patches ... I just stumbeld over this issue in this patch from Stefan, because I could try it on a hardware, and my hardware doesn;t boot with this patch...
Theoretically you must check all vars, which are in BSS segment, if they are used before relocation ... and drop an error, no idea yet, how to detect this at compile time ...
May we better clear BSS very early (at last may possible on arm)?
You cannot. There is no storage allocated for BSS - this happens only during relocation, and then it also gets zeroed.
Yes, valid for the boards which have no SPL ... but if U-Boot is loaded with SPL into RAM, BSS is writeable. But as this is not valid for all boards, we cannot do this!
Just see the patches from Simon:
https://lists.denx.de/pipermail/u-boot/2019-March/361452.html
http://patchwork.ozlabs.org/patch/1067363/
Same problem ...
OK, so the word stands "BSS is not used before relocation". Like already mentioned, we don't have a check that tells us when this rule is violated. Being like that, I would be surprised if such a check (if added) would yield zero failures...
Hmm... I hope not.
However, I'm not sure what "relocation" means for SPL boards where the SPL is loaded into SRAM (as is the case on many ARM boards at least). The correct wording here might be "RAM available" or something like that, instead of "relocation".
In case of SPL ... there is no code relocation and "after relocation" is equivalent to "RAM available".
With this definition, a new question arises: how can I be forced to provide a malloc implementation in "pre-reloc" phase (for pre-reloc driver model, e.g. drivers for serial and SDRAM) when people keep telling me bss might not even be available? That sounds a bit confusing to me.
But Simon Glass suggestion to put all variables dlmalloc needs into a struct and put a pointer into GD should solve this problem, or?
bye, Heiko
This patch adds _image_binary_end to the SPL linker script. This will be used be the upcoming GARDENA AT91SAM based platform, which uses DT in SPL and configures CONFIGURE_SPL_SEPARATE_BSS.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - No change
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index f18b17dc93..3955bea23a 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -39,6 +39,8 @@ SECTIONS *(.__end) } >.sram
+ _image_binary_end = .; + .bss : { . = ALIGN(4);
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch adds _image_binary_end to the SPL linker script. This will be used be the upcoming GARDENA AT91SAM based platform, which uses DT in SPL and configures CONFIGURE_SPL_SEPARATE_BSS.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
This patch moves the AT91SAM NAND booting SPL image "boot.bin" which includes the ECC values from the root directory into the spl directory, where all SPL related images are located.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - No change
scripts/Makefile.spl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 54b160d72b..56dbbe127b 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -179,10 +179,10 @@ MKIMAGEFLAGS_boot.bin = -T atmelimage ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y) MKIMAGEFLAGS_boot.bin += -n $(shell $(obj)/../tools/atmel_pmecc_params)
-boot.bin: $(obj)/../tools/atmel_pmecc_params +$(obj)/boot.bin: $(obj)/../tools/atmel_pmecc_params endif
-boot.bin: $(obj)/u-boot-spl.bin FORCE +$(obj)/boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) else ifdef CONFIG_ARCH_ZYNQ @@ -225,7 +225,7 @@ endif endif
ifeq ($(CONFIG_SYS_SOC),"at91") -ALL-y += boot.bin +ALL-y += $(obj)/boot.bin endif
ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch moves the AT91SAM NAND booting SPL image "boot.bin" which includes the ECC values from the root directory into the spl directory, where all SPL related images are located.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
scripts/Makefile.spl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details.
+config SPL_IMAGE + string "SPL image filename that is generated" + default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT + default "spl/u-boot-spl.bin" + help + The SPL image filename that is generated by the build process. + This image might be used to generated a combined image with + SPL and main U-Boot proper as well. + config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 @@ -232,6 +241,7 @@ config BUILD_TARGET default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD + default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help Some SoCs need special image types (e.g. U-Boot binary with a special header) as build targets. By defining diff --git a/Makefile b/Makefile index c1af9307b3..077bb6634e 100644 --- a/Makefile +++ b/Makefile @@ -1225,9 +1225,11 @@ else SPL_PAYLOAD := u-boot.bin endif
+SPL_IMAGE := $(CONFIG_SPL_IMAGE:"%"=%) + OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) -u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE +u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat)
ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
On 26.03.2019 14:16, Stefan Roese wrote:
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin". > This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details.
+config SPL_IMAGE
- string "SPL image filename that is generated"
- default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
- default "spl/u-boot-spl.bin"
Hi Stefan,
This means that the old spl/u-boot-spl.bin is gone for AT91 and NAND ? Please correct me if I am wrong
- help
The SPL image filename that is generated by the build process.This image might be used to generated a combined image withSPL and main U-Boot proper as well.- config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
@@ -232,6 +241,7 @@ config BUILD_TARGET default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD
- default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
This means that before this patch, there was no special target for AT91 ? Thus no special image was built ? And after this patch, there will also be a new binary u-boot-with-spl.bin, except spl/boot.bin and spl/u-boot-spl.bin ? Thus your patch does a bit more than what it's explained in the commit message ?
Thanks, Eugen
help Some SoCs need special image types (e.g. U-Boot binary with a special header) as build targets. By defining diff --git a/Makefile b/Makefile index c1af9307b3..077bb6634e 100644 --- a/Makefile +++ b/Makefile @@ -1225,9 +1225,11 @@ else SPL_PAYLOAD := u-boot.bin endif
+SPL_IMAGE := $(CONFIG_SPL_IMAGE:"%"=%)
- OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO)
-u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE +u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat)
ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
On 29.03.19 11:04, Eugen.Hristev@microchip.com wrote:
On 26.03.2019 14:16, Stefan Roese wrote:
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin". > This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details.
+config SPL_IMAGE
- string "SPL image filename that is generated"
- default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
- default "spl/u-boot-spl.bin"
Hi Stefan,
This means that the old spl/u-boot-spl.bin is gone for AT91 and NAND ? Please correct me if I am wrong
No, its still there.
- help
The SPL image filename that is generated by the build process.This image might be used to generated a combined image withSPL and main U-Boot proper as well.- config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
@@ -232,6 +241,7 @@ config BUILD_TARGET default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD
- default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
This means that before this patch, there was no special target for AT91 ?
Yes.
Thus no special image was built ?
Yes.
And after this patch, there will also be a new binary u-boot-with-spl.bin, except spl/boot.bin and spl/u-boot-spl.bin ?
The old binaries are still generated. Only a new combined image is generated too.
Thus your patch does a bit more than what it's explained in the commit message ?
Does it? What exactly is missing in the commit message? Please explain and I'll add something in the next patch version.
Thanks, Stefan
On 29.03.2019 17:53, Stefan Roese wrote:
External E-Mail
On 29.03.19 11:04, Eugen.Hristev@microchip.com wrote:
On 26.03.2019 14:16, Stefan Roese wrote:
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin". > This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
- No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details. +config SPL_IMAGE + string "SPL image filename that is generated" + default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT + default "spl/u-boot-spl.bin"
Hi Stefan,
This means that the old spl/u-boot-spl.bin is gone for AT91 and NAND ? Please correct me if I am wrong
No, its still there.
+ help + The SPL image filename that is generated by the build process. + This image might be used to generated a combined image with + SPL and main U-Boot proper as well.
config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 @@ -232,6 +241,7 @@ config BUILD_TARGET default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD + default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
This means that before this patch, there was no special target for AT91 ?
Yes.
Thus no special image was built ?
Yes.
And after this patch, there will also be a new binary u-boot-with-spl.bin, except spl/boot.bin and spl/u-boot-spl.bin ?
The old binaries are still generated. Only a new combined image is generated too.
Thus your patch does a bit more than what it's explained in the commit message ?
Does it? What exactly is missing in the commit message? Please explain and I'll add something in the next patch version.
A new binary is generated on build after this patch is applied. Your commit states that you add a new Kconfig to select the name of a file which is included in a generating a binary (which did not exist before )
So I see 2 changes: 1) new binary will be created from now on 2) to create this binary a new Kconfig is used which selects one of the files used to create it
Thanks, Stefan
On 29.03.19 16:59, Eugen.Hristev@microchip.com wrote:
<snip>
And after this patch, there will also be a new binary u-boot-with-spl.bin, except spl/boot.bin and spl/u-boot-spl.bin ?
The old binaries are still generated. Only a new combined image is generated too.
Thus your patch does a bit more than what it's explained in the commit message ?
Does it? What exactly is missing in the commit message? Please explain and I'll add something in the next patch version.
A new binary is generated on build after this patch is applied. Your commit states that you add a new Kconfig to select the name of a file which is included in a generating a binary (which did not exist before )
This "new binary" is already generated on other platforms (e.g. MVEBU). So its not introduced with this patch.
So I see 2 changes: 1) new binary will be created from now on 2) to create this binary a new Kconfig is used which selects one of the files used to create it
I'll add that this "new binary" is now generated for AT91 & SPL_NAND. Like this:
Makefile: Add Kconfig option CONFIG_SPL_IMAGE to select the SPL binary
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND). For these build targets the combined image "u-boot-with-spl.bin" is now automatically generated and can be programmed into NAND as one single image (vs. SPL image and U-Boot as 2 separate images).
What do you think?
Thanks, Stefan
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
This patch adds the necessary defines to the Siemens AT91SAM based boards (smartweb, corvus and taurus) to generate the combined binary image with SPL and main U-Boot image combined (u-boot-with-spl.bin).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - No change
include/configs/corvus.h | 3 +++ include/configs/smartweb.h | 4 ++++ include/configs/taurus.h | 3 +++ 3 files changed, 10 insertions(+)
diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 5dd5c28e08..749a67d4b0 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -139,4 +139,7 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302
+#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + #endif diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 28af575bf2..f95b29480d 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -221,4 +221,8 @@ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #endif + +#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + #endif /* __CONFIG_H */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index f283ab7fca..8e56e62282 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -177,4 +177,7 @@ #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) #define CONFIG_SYS_AT91_PLLB 0x10193F05
+#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + #endif
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch adds the necessary defines to the Siemens AT91SAM based boards (smartweb, corvus and taurus) to generate the combined binary image with SPL and main U-Boot image combined (u-boot-with-spl.bin).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
include/configs/corvus.h | 3 +++ include/configs/smartweb.h | 4 ++++ include/configs/taurus.h | 3 +++ 3 files changed, 10 insertions(+)
Thanks for adapting this boards!
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
Test for corvus and smartweb follow, but no time yet.
bye, Heiko
This makes it possible to reference the watchdog DT node via "&watchdog" from board dts files.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - New patch
arch/arm/dts/at91sam9x5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi index ea319cc18b..bd4abe00d6 100644 --- a/arch/arm/dts/at91sam9x5.dtsi +++ b/arch/arm/dts/at91sam9x5.dtsi @@ -1180,7 +1180,7 @@ }; };
- watchdog@fffffe40 { + watchdog: watchdog@fffffe40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This makes it possible to reference the watchdog DT node via "&watchdog" from board dts files.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
New patch
arch/arm/dts/at91sam9x5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Heiko Schocher hs@denx.de
I have such a similiar patch now in my queue for at91sam9260.dtsi as I tested with the taurus board.
bye, Heiko
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v2: - Add dtb build target in dts Makefile - Add gardena-smart-gateway-at91sam-u-boot.dtsi file with U-Boot specific DT properties - at91sam9x5ek.dtsi is not included in the dts file any more as this did enable too much unused devices
arch/arm/dts/Makefile | 3 + .../gardena-smart-gateway-at91sam-u-boot.dtsi | 5 + .../arm/dts/gardena-smart-gateway-at91sam.dts | 119 +++++++++++++++ arch/arm/mach-at91/Kconfig | 8 ++ board/gardena/smart-gateway-at91sam/Kconfig | 12 ++ .../gardena/smart-gateway-at91sam/MAINTAINERS | 7 + board/gardena/smart-gateway-at91sam/Makefile | 7 + board/gardena/smart-gateway-at91sam/board.c | 59 ++++++++ board/gardena/smart-gateway-at91sam/spl.c | 135 ++++++++++++++++++ .../gardena-smart-gateway-at91sam_defconfig | 84 +++++++++++ .../configs/gardena-smart-gateway-at91sam.h | 88 ++++++++++++ 11 files changed, 527 insertions(+) create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam.dts create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS create mode 100644 board/gardena/smart-gateway-at91sam/Makefile create mode 100644 board/gardena/smart-gateway-at91sam/board.c create mode 100644 board/gardena/smart-gateway-at91sam/spl.c create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig create mode 100644 include/configs/gardena-smart-gateway-at91sam.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..e890492456 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -607,6 +607,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
+dtb-$(CONFIG_TARGET_GARDENA_SMART_GATWAY_AT91SAM) += \ + gardena-smart-gateway-at91sam.dtb + dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb
dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb diff --git a/arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi b/arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi new file mode 100644 index 0000000000..732dee6c0e --- /dev/null +++ b/arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&dbgu { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/gardena-smart-gateway-at91sam.dts b/arch/arm/dts/gardena-smart-gateway-at91sam.dts new file mode 100644 index 0000000000..dddd138aa3 --- /dev/null +++ b/arch/arm/dts/gardena-smart-gateway-at91sam.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the GARDENA smart Gateway (AT91SAM) + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre nicolas.ferre@atmel.com + */ + +/dts-v1/; + +#include "at91sam9g25.dtsi" + +/ { + model = "GARDENA smart Gateway (AT91SAM)"; + compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9"; + + aliases { + serial0 = &dbgu; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_blue { + label = "smartgw:power:blue"; + gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power_green { + label = "smartgw:power:green"; + gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + power_red { + label = "smartgw:power:red"; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_blue { + label = "smartgw:radio:blue"; + gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_green { + label = "smartgw:radio:green"; + gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_red { + label = "smartgw:radio:red"; + gpios = <&pioC 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_blue { + label = "smartgw:internet:blue"; + gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_green { + label = "smartgw:internet:green"; + gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_red { + label = "smartgw:internet:red"; + gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&dbgu { + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&nand0 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; /* Enable PMECC */ + atmel,pmecc-cap = <2>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a6329dc022..87b986ae38 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -147,6 +147,13 @@ config TARGET_AT91SAM9X5EK select BOARD_LATE_INIT select SUPPORT_SPL
+config TARGET_GARDENA_SMART_GATWAY_AT91SAM + bool "GARDENA smart Gateway (AT91SAM)" + select AT91SAM9X5 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select SUPPORT_SPL + config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" select BOARD_EARLY_INIT_F @@ -283,6 +290,7 @@ source "board/bluewater/snapper9260/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" +source "board/gardena/smart-gateway-at91sam/Kconfig" source "board/l+g/vinco/Kconfig" source "board/mini-box/picosam9g45/Kconfig" source "board/ronetix/pm9261/Kconfig" diff --git a/board/gardena/smart-gateway-at91sam/Kconfig b/board/gardena/smart-gateway-at91sam/Kconfig new file mode 100644 index 0000000000..a09a3eaa74 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GARDENA_SMART_GATWAY_AT91SAM + +config SYS_BOARD + default "smart-gateway-at91sam" + +config SYS_VENDOR + default "gardena" + +config SYS_CONFIG_NAME + default "gardena-smart-gateway-at91sam" + +endif diff --git a/board/gardena/smart-gateway-at91sam/MAINTAINERS b/board/gardena/smart-gateway-at91sam/MAINTAINERS new file mode 100644 index 0000000000..a5e4c71b82 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/MAINTAINERS @@ -0,0 +1,7 @@ +GARDENA_SMART_GATEWAY_AT91SAM BOARD +M: Stefan Roese sr@denx.de +S: Maintained +F: board/gardena/smart-gateway-at91sam/ +F: include/configs/gardena-smart-gateway-at91sam.h +F: configs/gardena-smart-gateway-at91sam_defconfig +F: arch/arm/dts/gardena-smart-gateway-at91sam.dts diff --git a/board/gardena/smart-gateway-at91sam/Makefile b/board/gardena/smart-gateway-at91sam/Makefile new file mode 100644 index 0000000000..a2ed79fd06 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c new file mode 100644 index 0000000000..6a1389eb05 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/board.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Atmel Corporation + * Copyright (C) 2019 Stefan Roese sr@denx.de + */ + +#include <common.h> +#include <debug_uart.h> +#include <led.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void at91_prepare_cpu_var(void) +{ + env_set("cpu", get_cpu_name()); +} + +int board_late_init(void) +{ + at91_prepare_cpu_var(); + + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + + return 0; +} + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c new file mode 100644 index 0000000000..3ab6760df7 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/spl.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Atmel Corporation + * Copyright (C) 2019 Stefan Roese sr@denx.de + */ + +#include <common.h> +#include <nand.h> +#include <spl.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> + +static void at91sam9x5ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + + /* NAND flash on D16 */ + csa |= AT91_MATRIX_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOCD); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); +} + +void at91_spl_board_init(void) +{ + at91sam9x5ek_nand_hw_init(); +} + +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddrc_config ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* Enable DDR2 clock */ + writel(AT91_PMC_DDR, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; + csa |= AT91_MATRIX_EBI_DBPD_OFF; + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); +} diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig new file mode 100644 index 0000000000..af324184b8 --- /dev/null +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x22900000 +CONFIG_TARGET_GARDENA_SMART_GATWAY_AT91SAM=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_SMBIOS_PRODUCT_NAME="at91sam9x5ek" +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_TPL_BANNER_PRINT is not set +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand0" +CONFIG_MTDPARTS_DEFAULT="nand0:1536k(uboot),1024k(unused),512k(dtb_old),4608k(kernel_old),86528k(ubi),-(rootfs_old)" +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-at91sam" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names" +CONFIG_ENV_IS_IN_UBI=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_BLK=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +# CONFIG_MMC is not set +CONFIG_NAND_ATMEL=y +CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y +# CONFIG_CONFIG_UBI_SILENCE_MSG is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +# CONFIG_SYS_WHITE_ON_BLACK is not set +CONFIG_WATCHDOG=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y +CONFIG_AT91_HW_WDT_TIMEOUT=y +# CONFIG_UBIFS_SILENCE_MSG is not set +CONFIG_USE_TINY_PRINTF=y diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h new file mode 100644 index 0000000000..e9a06e6d00 --- /dev/null +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Atmel Corporation + * Copyright (C) 2019 Stefan Roese sr@denx.de + * + * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25) + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) + +/* NAND flash */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* environment organization */ +#define CONFIG_ENV_UBI_PART "ubi" +#define CONFIG_ENV_UBI_VOLUME "env" +#define CONFIG_ENV_UBI_VOLUME_REDUND "env_r" +#define CONFIG_ENV_SIZE (64 << 10) + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x7000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + +#endif
On 26.03.2019 14:16, Stefan Roese wrote:
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
Add dtb build target in dts Makefile
Add gardena-smart-gateway-at91sam-u-boot.dtsi file with U-Boot specific DT properties
at91sam9x5ek.dtsi is not included in the dts file any more as this did enable too much unused devices
arch/arm/dts/Makefile | 3 + .../gardena-smart-gateway-at91sam-u-boot.dtsi | 5 + .../arm/dts/gardena-smart-gateway-at91sam.dts | 119 +++++++++++++++ arch/arm/mach-at91/Kconfig | 8 ++ board/gardena/smart-gateway-at91sam/Kconfig | 12 ++ .../gardena/smart-gateway-at91sam/MAINTAINERS | 7 + board/gardena/smart-gateway-at91sam/Makefile | 7 + board/gardena/smart-gateway-at91sam/board.c | 59 ++++++++ board/gardena/smart-gateway-at91sam/spl.c | 135 ++++++++++++++++++ .../gardena-smart-gateway-at91sam_defconfig | 84 +++++++++++ .../configs/gardena-smart-gateway-at91sam.h | 88 ++++++++++++ 11 files changed, 527 insertions(+) create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam.dts create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS create mode 100644 board/gardena/smart-gateway-at91sam/Makefile create mode 100644 board/gardena/smart-gateway-at91sam/board.c create mode 100644 board/gardena/smart-gateway-at91sam/spl.c create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig create mode 100644 include/configs/gardena-smart-gateway-at91sam.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..e890492456 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -607,6 +607,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
+dtb-$(CONFIG_TARGET_GARDENA_SMART_GATWAY_AT91SAM) += \
Hi Stefan,
Is the "GATWAY" intentional? would be difficult to find if someone searches for it...
Eugen
[snip]
On 26.03.19 14:58, Eugen.Hristev@microchip.com wrote:
On 26.03.2019 14:16, Stefan Roese wrote:
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
Add dtb build target in dts Makefile
Add gardena-smart-gateway-at91sam-u-boot.dtsi file with U-Boot specific DT properties
at91sam9x5ek.dtsi is not included in the dts file any more as this did enable too much unused devices
arch/arm/dts/Makefile | 3 + .../gardena-smart-gateway-at91sam-u-boot.dtsi | 5 + .../arm/dts/gardena-smart-gateway-at91sam.dts | 119 +++++++++++++++ arch/arm/mach-at91/Kconfig | 8 ++ board/gardena/smart-gateway-at91sam/Kconfig | 12 ++ .../gardena/smart-gateway-at91sam/MAINTAINERS | 7 + board/gardena/smart-gateway-at91sam/Makefile | 7 + board/gardena/smart-gateway-at91sam/board.c | 59 ++++++++ board/gardena/smart-gateway-at91sam/spl.c | 135 ++++++++++++++++++ .../gardena-smart-gateway-at91sam_defconfig | 84 +++++++++++ .../configs/gardena-smart-gateway-at91sam.h | 88 ++++++++++++ 11 files changed, 527 insertions(+) create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam.dts create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS create mode 100644 board/gardena/smart-gateway-at91sam/Makefile create mode 100644 board/gardena/smart-gateway-at91sam/board.c create mode 100644 board/gardena/smart-gateway-at91sam/spl.c create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig create mode 100644 include/configs/gardena-smart-gateway-at91sam.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..e890492456 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -607,6 +607,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
+dtb-$(CONFIG_TARGET_GARDENA_SMART_GATWAY_AT91SAM) += \
Hi Stefan,
Is the "GATWAY" intentional? would be difficult to find if someone searches for it...
Ups. Definitely not! Thanks for catching. I'll fix it in the next version.
I also thought about adding "at91sam9g25-" to the beginning of the dts file to better include it in the dts directory to the SoC family. What is your thinking about this?
Thanks, Stefan
On 26.03.2019 16:01, Stefan Roese wrote:
On 26.03.19 14:58, Eugen.Hristev@microchip.com wrote:
On 26.03.2019 14:16, Stefan Roese wrote:
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
- Add dtb build target in dts Makefile
- Add gardena-smart-gateway-at91sam-u-boot.dtsi file with U-Boot
specific DT properties
- at91sam9x5ek.dtsi is not included in the dts file any more as this
did enable too much unused devices
arch/arm/dts/Makefile | 3 + .../gardena-smart-gateway-at91sam-u-boot.dtsi | 5 + .../arm/dts/gardena-smart-gateway-at91sam.dts | 119 +++++++++++++++ arch/arm/mach-at91/Kconfig | 8 ++ board/gardena/smart-gateway-at91sam/Kconfig | 12 ++ .../gardena/smart-gateway-at91sam/MAINTAINERS | 7 + board/gardena/smart-gateway-at91sam/Makefile | 7 + board/gardena/smart-gateway-at91sam/board.c | 59 ++++++++ board/gardena/smart-gateway-at91sam/spl.c | 135 ++++++++++++++++++ .../gardena-smart-gateway-at91sam_defconfig | 84 +++++++++++ .../configs/gardena-smart-gateway-at91sam.h | 88 ++++++++++++ 11 files changed, 527 insertions(+) create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam.dts create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS create mode 100644 board/gardena/smart-gateway-at91sam/Makefile create mode 100644 board/gardena/smart-gateway-at91sam/board.c create mode 100644 board/gardena/smart-gateway-at91sam/spl.c create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig create mode 100644 include/configs/gardena-smart-gateway-at91sam.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..e890492456 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -607,6 +607,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb +dtb-$(CONFIG_TARGET_GARDENA_SMART_GATWAY_AT91SAM) += \
Hi Stefan,
Is the "GATWAY" intentional? would be difficult to find if someone searches for it...
Ups. Definitely not! Thanks for catching. I'll fix it in the next version.
I also thought about adding "at91sam9g25-" to the beginning of the dts file to better include it in the dts directory to the SoC family. What is your thinking about this?
I do not have a strong opinion. As you like.
Thanks, Stefan
On 26.03.19 15:12, Eugen.Hristev@microchip.com wrote:
On 26.03.2019 16:01, Stefan Roese wrote:
On 26.03.19 14:58, Eugen.Hristev@microchip.com wrote:
On 26.03.2019 14:16, Stefan Roese wrote:
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
- Add dtb build target in dts Makefile
- Add gardena-smart-gateway-at91sam-u-boot.dtsi file with U-Boot
specific DT properties
- at91sam9x5ek.dtsi is not included in the dts file any more as this
did enable too much unused devices
arch/arm/dts/Makefile | 3 + .../gardena-smart-gateway-at91sam-u-boot.dtsi | 5 + .../arm/dts/gardena-smart-gateway-at91sam.dts | 119 +++++++++++++++ arch/arm/mach-at91/Kconfig | 8 ++ board/gardena/smart-gateway-at91sam/Kconfig | 12 ++ .../gardena/smart-gateway-at91sam/MAINTAINERS | 7 + board/gardena/smart-gateway-at91sam/Makefile | 7 + board/gardena/smart-gateway-at91sam/board.c | 59 ++++++++ board/gardena/smart-gateway-at91sam/spl.c | 135 ++++++++++++++++++ .../gardena-smart-gateway-at91sam_defconfig | 84 +++++++++++ .../configs/gardena-smart-gateway-at91sam.h | 88 ++++++++++++ 11 files changed, 527 insertions(+) create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam.dts create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS create mode 100644 board/gardena/smart-gateway-at91sam/Makefile create mode 100644 board/gardena/smart-gateway-at91sam/board.c create mode 100644 board/gardena/smart-gateway-at91sam/spl.c create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig create mode 100644 include/configs/gardena-smart-gateway-at91sam.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..e890492456 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -607,6 +607,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb +dtb-$(CONFIG_TARGET_GARDENA_SMART_GATWAY_AT91SAM) += \
Hi Stefan,
Is the "GATWAY" intentional? would be difficult to find if someone searches for it...
Ups. Definitely not! Thanks for catching. I'll fix it in the next version.
I also thought about adding "at91sam9g25-" to the beginning of the dts file to better include it in the dts directory to the SoC family. What is your thinking about this?
I do not have a strong opinion. As you like.
I've changed it locally and will send v3 in a few days (waiting for some further review comments).
Thanks, Stefan
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
Add dtb build target in dts Makefile
Add gardena-smart-gateway-at91sam-u-boot.dtsi file with U-Boot specific DT properties
at91sam9x5ek.dtsi is not included in the dts file any more as this did enable too much unused devices
arch/arm/dts/Makefile | 3 + .../gardena-smart-gateway-at91sam-u-boot.dtsi | 5 + .../arm/dts/gardena-smart-gateway-at91sam.dts | 119 +++++++++++++++ arch/arm/mach-at91/Kconfig | 8 ++ board/gardena/smart-gateway-at91sam/Kconfig | 12 ++ .../gardena/smart-gateway-at91sam/MAINTAINERS | 7 + board/gardena/smart-gateway-at91sam/Makefile | 7 + board/gardena/smart-gateway-at91sam/board.c | 59 ++++++++ board/gardena/smart-gateway-at91sam/spl.c | 135 ++++++++++++++++++ .../gardena-smart-gateway-at91sam_defconfig | 84 +++++++++++ .../configs/gardena-smart-gateway-at91sam.h | 88 ++++++++++++ 11 files changed, 527 insertions(+) create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam-u-boot.dtsi create mode 100644 arch/arm/dts/gardena-smart-gateway-at91sam.dts create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS create mode 100644 board/gardena/smart-gateway-at91sam/Makefile create mode 100644 board/gardena/smart-gateway-at91sam/board.c create mode 100644 board/gardena/smart-gateway-at91sam/spl.c create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig create mode 100644 include/configs/gardena-smart-gateway-at91sam.h
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Hello Stefan,
Am 26.03.2019 um 13:16 schrieb Stefan Roese:
Make sure that lowlevel_init is not compiled when CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v2:
No change
arch/arm/mach-at91/arm926ejs/Makefile | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
participants (5)
-
Eugen.Hristev＠microchip.com -
Heiko Schocher -
Simon Goldschmidt -
Stefan Roese -
Wolfgang Denk