[U-Boot] [PATCH V2 1/6] imx: Align the imximage header and payload to multiples of 4k
The MX53 ROM loads the data from NAND in multiples of pages and supports maximum page size of 4k. Thus, align the image and header to 4k to be safe from ROM bugs.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com --- tools/imximage.c | 11 +++++++---- tools/imximage.h | 3 ++- 2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/tools/imximage.c b/tools/imximage.c index fa308c9..c018562 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -518,11 +518,14 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
/* * ROM bug alert - * mx53 only loads 512 byte multiples. - * The remaining fraction of a block bytes would - * not be loaded. + * + * MX53 only loads 512 byte multiples in case of SD boot. + * MX53 only loads NAND page multiples in case of NAND boot and + * supports up to 4096 byte large pages, thus align to 4096. + * + * The remaining fraction of a block bytes would not be loaded! */ - *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512); + *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096); }
int imximage_check_params(struct mkimage_params *params) diff --git a/tools/imximage.h b/tools/imximage.h index 42b6090..dfd2e9e 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -151,13 +151,14 @@ typedef struct { dcd_v2_t dcd_table; } imx_header_v2_t;
+/* The header must be aligned to 4k on MX53 for NAND boot */ struct imx_header { union { imx_header_v1_t hdr_v1; imx_header_v2_t hdr_v2; } header; uint32_t flash_offset; -}; +} __attribute__((aligned(4096)));
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, char *name, int lineno,
Add support for generic NAND SPL via the SPL framework into the mxc_nand_spl driver. This is basically just a simple rename and publication of the already implemented functions. To avoid the bare-bones functions getting in the way of the NAND_SPL, build them only if CONFIG_SPL_FRAMEWORK is not defined.
Also make sure the requested payload is aligned to full pages, otherwise this simple driver fails to load the last page.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com --- drivers/mtd/nand/mxc_nand_spl.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)
V2: Check CONFIG_SPL_FRAMEWORK instead to test if we're building with NAND_SPL or really bare-bones SPL.
diff --git a/drivers/mtd/nand/mxc_nand_spl.c b/drivers/mtd/nand/mxc_nand_spl.c index 09f23c3..5608352 100644 --- a/drivers/mtd/nand/mxc_nand_spl.c +++ b/drivers/mtd/nand/mxc_nand_spl.c @@ -290,7 +290,7 @@ static int is_badblock(int pagenumber) return 0; }
-static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) +int nand_spl_load_image(uint32_t from, unsigned int size, void *buf) { int i; unsigned int page; @@ -303,6 +303,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) page = from / CONFIG_SYS_NAND_PAGE_SIZE; i = 0;
+ size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE); while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) { if (nfc_read_page(page, buf) < 0) return -1; @@ -332,6 +333,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) return 0; }
+#ifndef CONFIG_SPL_FRAMEWORK /* * The main entry for NAND booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image @@ -345,8 +347,9 @@ void nand_boot(void) * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must * be aligned to full pages */ - if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) { + if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) { /* Copy from NAND successful, start U-boot */ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); @@ -364,3 +367,7 @@ void hang(void) /* Loop forever */ while (1) ; } +#endif + +void nand_init(void) {} +void nand_deselect(void) {}
On 04/21/2013 10:52:23 AM, Marek Vasut wrote:
Add support for generic NAND SPL via the SPL framework into the mxc_nand_spl driver. This is basically just a simple rename and publication of the already implemented functions. To avoid the bare-bones functions getting in the way of the NAND_SPL, build them only if CONFIG_SPL_FRAMEWORK is not defined.
Also make sure the requested payload is aligned to full pages, otherwise this simple driver fails to load the last page.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com
drivers/mtd/nand/mxc_nand_spl.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)
V2: Check CONFIG_SPL_FRAMEWORK instead to test if we're building with NAND_SPL or really bare-bones SPL.
Acked-by: Scott Wood scottwood@freescale.com
-Scott
The U-Boot SPL can parse the uImage format and gather information from it about the payload. Make use of this and wrap u-boot.bin into uImage format. The benefit is the SPL will know the size of the payload instead of using fixed size of the payload defined at compile time.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com --- arch/arm/imx-common/Makefile | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
V2: Extend uImage usage to u-boot-with-spl.imx target
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 44b6822..bff1e67 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -58,8 +58,11 @@ $(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONF $(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ -I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx - cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@ - rm $(OBJTREE)/spl/u-boot-spl-pad.imx + $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ + -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \ + $(OBJTREE)/u-boot.uim + cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim > $@ + rm $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim
$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \ @@ -69,8 +72,11 @@ $(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin -I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \ $(OBJTREE)/spl/u-boot-nand-spl-pad.imx rm $(OBJTREE)/spl/u-boot-nand-spl.imx - cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin > $@ - rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx + $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ + -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \ + $(OBJTREE)/u-boot.uim + cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim > $@ + rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim
#########################################################################
Fix minor adjustments needed to get SPL framework building on MX5.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com --- arch/arm/include/asm/arch-mx5/spl.h | 19 +++++++++++++++++++ spl/Makefile | 4 ++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx5/spl.h
diff --git a/arch/arm/include/asm/arch-mx5/spl.h b/arch/arm/include/asm/arch-mx5/spl.h new file mode 100644 index 0000000..e0b6e3e --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/spl.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013 Marek Vasut marex@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_NAND 1 + +#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/spl/Makefile b/spl/Makefile index b5a8de7..90f932a 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -88,6 +88,10 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o +endif + ifneq ($(CONFIG_TEGRA),) LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
Augment the MX5 clock code with function to enable and configure NFC clock. This is necessary to get NFC working on MX5.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/mx5/clock.c | 14 ++++++++++++-- arch/arm/include/asm/arch-mx5/clock.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 76c2c52..431756e 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -739,10 +739,11 @@ static int config_core_clk(u32 ref, u32 freq) static int config_nfc_clk(u32 nfc_clk) { u32 parent_rate = get_emi_slow_clk(); - u32 div = parent_rate / nfc_clk; + u32 div;
- if (nfc_clk <= 0) + if (nfc_clk == 0) return -EINVAL; + div = parent_rate / nfc_clk; if (div == 0) div++; if (parent_rate / div > NFC_CLK_MAX) @@ -755,6 +756,15 @@ static int config_nfc_clk(u32 nfc_clk) return 0; }
+void enable_nfc_clk(unsigned char enable) +{ + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; + + clrsetbits_le32(&mxc_ccm->CCGR5, + MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK), + MXC_CCM_CCGR5_EMI_ENFC(cg)); +} + /* Config main_bus_clock for periphs */ static int config_periph_clk(u32 ref, u32 freq) { diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 9cdfb48..6910192 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -68,5 +68,6 @@ void set_usboh3_clk(void); void enable_usboh3_clk(unsigned char enable); void mxc_set_sata_internal_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +void enable_nfc_clk(unsigned char enable);
#endif /* __ASM_ARCH_CLOCK_H */
Add basic support for the DENX M53EVK board. Currently supported is: MMC (incl. booting) NAND (incl. booting) Ethernet, I2C, USB, SATA, RTC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de --- MAINTAINERS | 1 + board/denx/m53evk/Makefile | 40 ++++ board/denx/m53evk/imximage.cfg | 108 +++++++++++ board/denx/m53evk/m53evk.c | 420 ++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/m53evk.h | 255 ++++++++++++++++++++++++ 6 files changed, 825 insertions(+) create mode 100644 board/denx/m53evk/Makefile create mode 100644 board/denx/m53evk/imximage.cfg create mode 100644 board/denx/m53evk/m53evk.c create mode 100644 include/configs/m53evk.h
V2: Init M4IF and WEIM Clean up config file
diff --git a/MAINTAINERS b/MAINTAINERS index 643a5ac..e109be6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -954,6 +954,7 @@ Marek Vasut marek.vasut@gmail.com mx23_olinuxino i.MX23 m28evk i.MX28 sc_sps_1 i.MX28 + m53evk i.MX53
Hugo Villeneuve hugo.villeneuve@lyrtech.com
diff --git a/board/denx/m53evk/Makefile b/board/denx/m53evk/Makefile new file mode 100644 index 0000000..bfb040a --- /dev/null +++ b/board/denx/m53evk/Makefile @@ -0,0 +1,40 @@ +# +# DENX M53EVK +# Copyright (C) 2012-2013 Marek Vasut marex@denx.de +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := m53evk.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg new file mode 100644 index 0000000..3d60de0 --- /dev/null +++ b/board/denx/m53evk/imximage.cfg @@ -0,0 +1,108 @@ +/* + * DENX M53 DRAM init values + * Copyright (C) 2012-2013 Marek Vasut marex@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd, nand + */ +BOOT_FROM nand + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ +DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ +DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ +DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ + +DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ +DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ +DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ + +DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ +DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ +DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ + +DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ +DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ +DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ + +DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ +DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ +DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ + +DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */ +DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */ + +DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ +DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ +DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */ +DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ + +DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ +DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ + +/* ESDCTL */ +DATA 4 0x63fd9088 0x32383535 +DATA 4 0x63fd9090 0x40383538 +DATA 4 0x63fd907c 0x0136014d +DATA 4 0x63fd9080 0x01510141 + +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd900c 0x555952e3 +DATA 4 0x63fd9010 0xb68e8b63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c new file mode 100644 index 0000000..07fd6f4 --- /dev/null +++ b/board/denx/m53evk/m53evk.c @@ -0,0 +1,420 @@ +/* + * DENX M53 module + * + * Copyright (C) 2012-2013 Marek Vasut marex@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/spl.h> +#include <asm/errno.h> +#include <netdev.h> +#include <i2c.h> +#include <mmc.h> +#include <spl.h> +#include <fsl_esdhc.h> +#include <asm/gpio.h> +#include <usb/ehci-fsl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + u32 size1, size2; + + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + gd->ram_size = size1 + size2; + + return 0; +} +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +static void setup_iomux_uart(void) +{ + mxc_request_iomux(MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3); + mxc_request_iomux(MX53_PIN_ATA_DMARQ, IOMUX_CONFIG_ALT3); + + mxc_iomux_set_pad(MX53_PIN_ATA_BUFFER_EN, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE); + mxc_iomux_set_pad(MX53_PIN_ATA_DMARQ, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE); + + mxc_iomux_set_input(MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); +} + +#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{ + if (port == 0) { + /* USB OTG PWRON */ + mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_GPIO_4, + PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PD | + PAD_CTL_DRV_HIGH + ); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_4), 0); + + /* USB OTG Over Current */ + mxc_request_iomux(MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT1); + mxc_iomux_set_input(MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, 1); + } else if (port == 1) { + /* USB Host PWRON */ + mxc_request_iomux(MX53_PIN_GPIO_2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_GPIO_2, + PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PD | + PAD_CTL_DRV_HIGH + ); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_2), 0); + + /* USB Host Over Current */ + mxc_request_iomux(MX53_PIN_GPIO_3, IOMUX_CONFIG_ALT6); + mxc_iomux_set_input(MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT, 1); + } + + return 0; +} +#endif + +static void setup_iomux_fec(void) +{ + /* MDIO IOMUX */ + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); + + /* FEC 0 IOMUX */ + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); + + /* FEC 1 IOMUX */ + mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6); /* RXD3 */ + mxc_request_iomux(MX53_PIN_KEY_ROW0, IOMUX_CONFIG_ALT6); /* TX_ER */ + mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6); /* RX_CLK */ + mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6); /* COL */ + mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6); /* RXD2 */ + mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6); /* TXD2 */ + mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6); /* CRS */ + mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6); /* TXD3 */ + + /* MDIO PADs */ + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); + + /* FEC 0 PADs */ + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); + + /* FEC 1 PADs */ + mxc_iomux_set_pad(MX53_PIN_KEY_COL0, /* RXD3 */ + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW0, /* TX_ER */ + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_KEY_COL1, /* RX_CLK */ + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, /* COL */ + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_KEY_COL2, /* RXD2 */ + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, /* TXD2 */ + PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, /* CRS */ + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_GPIO_19, /* TXD3 */ + PAD_CTL_DRV_HIGH); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg = { + MMC_SDHC1_BASE_ADDR, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + gpio_direction_input(IMX_GPIO_NR(1, 1)); + + return !gpio_get_value(IMX_GPIO_NR(1, 1)); +} + +int board_mmc_init(bd_t *bis) +{ + esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_DA13, + IOMUX_CONFIG_ALT1); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + + /* GPIO 2_31 is SD power */ + mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); + gpio_direction_output(IMX_GPIO_NR(2, 31), 0); + + return fsl_esdhc_initialize(bis, &esdhc_cfg); +} +#endif + +static void setup_iomux_i2c(void) +{ + mxc_request_iomux(MX53_PIN_EIM_D16, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX53_PIN_EIM_EB2, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + + mxc_iomux_set_pad(MX53_PIN_EIM_D16, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + + mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, 0x1); + mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, 0x1); +} + +static void setup_iomux_nand(void) +{ + mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT3); + mxc_request_iomux(MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT3); + mxc_request_iomux(MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT3); + mxc_request_iomux(MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT3); + mxc_request_iomux(MX53_PIN_ATA_DATA4, IOMUX_CONFIG_ALT3); + mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_ALT3); + mxc_request_iomux(MX53_PIN_ATA_DATA6, IOMUX_CONFIG_ALT3); + mxc_request_iomux(MX53_PIN_ATA_DATA7, IOMUX_CONFIG_ALT3); + + mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA4, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA6, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA7, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); +} + +static void m53_set_clock(void) +{ + int ret; + const uint32_t ref_clk = MXC_HCLK; + const uint32_t dramclk = 400; + uint32_t cpuclk; + + mxc_request_iomux(MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX53_PIN_GPIO_10, PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_10)); + + /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ + cpuclk = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10)) ? 1200 : 800; + + ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); + + ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); + if (ret) { + printf("CPU: Switch peripheral clock to %dMHz failed\n", + dramclk); + } + + ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); +} + +static void m53_set_nand(void) +{ + u32 i; + + #define M4IF_GENP_WEIM_MM 0x00000001 + #define WEIM_GCR2_MUX16_BYP_GRANT 0x00001000 + + /* NAND flash is muxed on ATA pins */ + setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM); + + /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */ + for (i = 0x4; i < 0x94; i += 0x18) + clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT); + + mxc_set_clock(0, 33, MXC_NFC_CLK); + enable_nfc_clk(1); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_fec(); + setup_iomux_i2c(); + setup_iomux_nand(); + + m53_set_clock(); + + mxc_set_sata_internal_clock(); + + /* NAND clock @ 33MHz */ + m53_set_nand(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: DENX M53EVK\n"); + + return 0; +} + +/* + * NAND SPL + */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ + setup_iomux_nand(); + m53_set_clock(); + m53_set_nand(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NAND; +} +#endif diff --git a/boards.cfg b/boards.cfg index 31483d6..822ae01 100644 --- a/boards.cfg +++ b/boards.cfg @@ -246,6 +246,7 @@ am335x_evm_usbspl arm armv7 am335x ti ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 highbank arm armv7 highbank - highbank +m53evk arm armv7 m53evk denx mx5 m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h new file mode 100644 index 0000000..78e1226 --- /dev/null +++ b/include/configs/m53evk.h @@ -0,0 +1,255 @@ +/* + * DENX M53 configuration + * Copyright (C) 2012-2013 Marek Vasut marex@denx.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __M53EVK_CONFIG_H__ +#define __M53EVK_CONFIG_H__ + +#define CONFIG_MX53 +#define CONFIG_MXC_GPIO +#define CONFIG_SYS_HZ 1000 + +#include <asm/arch/imx-regs.h> + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_NO_FLASH + +/* + * U-Boot Commands + */ +#include <config_cmd_default.h> +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SATA +#define CONFIG_CMD_USB + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0xaff00000 + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_TEXT_BASE 0x71000000 + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Serial Driver + */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 +#endif + +/* + * NAND + */ +#define CONFIG_ENV_SIZE (16 * 1024) +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* Environment is in NAND */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_RANGE (512 * 1024) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) + +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=mxc-nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=mxc-nand:" \ + "1m(bootloader)ro," \ + "512k(environment)," \ + "512k(redundant-environment)," \ + "4m(kernel)," \ + "128k(fdt)," \ + "8m(ramdisk)," \ + "-(filesystem)" +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +/* + * Ethernet on SOC (FEC) + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#endif + +/* + * I2C + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_M41T62 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#endif + +/* + * SATA + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "m53evk/uImage" +#define CONFIG_BOOTARGS "console=ttymxc1,115200" +#define CONFIG_LOADADDR 0x70800000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_OF_LIBFDT + +/* + * NAND SPL + */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_TEXT_BASE 0x70008000 +#define CONFIG_SPL_PAD_TO 0x8000 +#define CONFIG_SPL_STACK 0x70004000 +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + +#endif /* __M53EVK_CONFIG_H__ */
Dear Marek Vasut,
On Sunday, April 21, 2013 5:52:27 PM, Marek Vasut wrote:
Add basic support for the DENX M53EVK board. Currently supported is: MMC (incl. booting)
^ Can you clarify this, please? spl_boot_device() points only to NAND, so you're clearly talking about hardware MMC boot, and not about hardware NAND boot followed by SPL payload fetched from MMC. But MMC boot does not need SPL here, in which case you will have to generate a simple u-boot.imx, or you will rather want to use u-boot-with-spl.imx for SD (NAND header dropped to leave room for MBR). And in the latter case, why have spl_boot_device() point to NAND for MMC boot?
NAND (incl. booting) Ethernet, I2C, USB, SATA, RTC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de
MAINTAINERS | 1 + board/denx/m53evk/Makefile | 40 ++++ board/denx/m53evk/imximage.cfg | 108 +++++++++++ board/denx/m53evk/m53evk.c | 420 ++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/m53evk.h | 255 ++++++++++++++++++++++++ 6 files changed, 825 insertions(+) create mode 100644 board/denx/m53evk/Makefile create mode 100644 board/denx/m53evk/imximage.cfg create mode 100644 board/denx/m53evk/m53evk.c create mode 100644 include/configs/m53evk.h
V2: Init M4IF and WEIM Clean up config file
diff --git a/MAINTAINERS b/MAINTAINERS index 643a5ac..e109be6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -954,6 +954,7 @@ Marek Vasut marek.vasut@gmail.com mx23_olinuxino i.MX23 m28evk i.MX28 sc_sps_1 i.MX28
- m53evk i.MX53
Hugo Villeneuve hugo.villeneuve@lyrtech.com
diff --git a/board/denx/m53evk/Makefile b/board/denx/m53evk/Makefile new file mode 100644 index 0000000..bfb040a --- /dev/null +++ b/board/denx/m53evk/Makefile @@ -0,0 +1,40 @@ +# +# DENX M53EVK +# Copyright (C) 2012-2013 Marek Vasut marex@denx.de +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).o
+COBJS := m53evk.o
+SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
+$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend
+######################################################################### diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg new file mode 100644 index 0000000..3d60de0 --- /dev/null +++ b/board/denx/m53evk/imximage.cfg @@ -0,0 +1,108 @@ +/*
- DENX M53 DRAM init values
- Copyright (C) 2012-2013 Marek Vasut marex@denx.de
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not write to the Free Software
- Foundation Inc. 51 Franklin Street Fifth Floor Boston,
- MA 02110-1301 USA
- Refer docs/README.imxmage for more details about how-to configure
- and create imximage boot image
- The syntax is taken as close as possible with the kwbimage
- */
+/* image version */ +IMAGE_VERSION 2
+/*
- Boot Device : one of
- spi, sd, nand
- */
+BOOT_FROM nand
+/*
- Device Configuration Data (DCD)
- Each entry must have the format:
- Addr-type Address Value
- where:
- Addr-type register length (1,2 or 4 bytes)
- Address absolute address of the register
- value value to be stored in the register
- */
+DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ +DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ +DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ +DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
+DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ +DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ +DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
+DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ +DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ +DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
+DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ +DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ +DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
+DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ +DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ +DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
+DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */ +DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
+DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ +DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ +DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */ +DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
+DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ +DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
+/* ESDCTL */ +DATA 4 0x63fd9088 0x32383535 +DATA 4 0x63fd9090 0x40383538 +DATA 4 0x63fd907c 0x0136014d +DATA 4 0x63fd9080 0x01510141
+DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd900c 0x555952e3 +DATA 4 0x63fd9010 0xb68e8b63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c new file mode 100644 index 0000000..07fd6f4 --- /dev/null +++ b/board/denx/m53evk/m53evk.c @@ -0,0 +1,420 @@ +/*
- DENX M53 module
- Copyright (C) 2012-2013 Marek Vasut marex@denx.de
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/spl.h> +#include <asm/errno.h> +#include <netdev.h> +#include <i2c.h> +#include <mmc.h> +#include <spl.h> +#include <fsl_esdhc.h> +#include <asm/gpio.h> +#include <usb/ehci-fsl.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
- u32 size1, size2;
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
- gd->ram_size = size1 + size2;
- return 0;
+} +void dram_init_banksize(void) +{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+u32 get_board_rev(void) +{
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- struct fuse_bank *bank = &iim->bank[0];
- struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;- int rev = readl(&fuse->gp[6]);
- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+static void setup_iomux_uart(void) +{
- mxc_request_iomux(MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3);
- mxc_request_iomux(MX53_PIN_ATA_DMARQ, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX53_PIN_ATA_BUFFER_EN,
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_HYS_ENABLE);- mxc_iomux_set_pad(MX53_PIN_ATA_DMARQ,
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_HYS_ENABLE);- mxc_iomux_set_input(MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
+}
+#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{
- if (port == 0) {
/* USB OTG PWRON */mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);mxc_iomux_set_pad(MX53_PIN_GPIO_4,PAD_CTL_PKE_ENABLE |PAD_CTL_100K_PD |PAD_CTL_DRV_HIGH);gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_4), 0);/* USB OTG Over Current */mxc_request_iomux(MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT1);mxc_iomux_set_input(MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, 1);- } else if (port == 1) {
/* USB Host PWRON */mxc_request_iomux(MX53_PIN_GPIO_2, IOMUX_CONFIG_ALT1);mxc_iomux_set_pad(MX53_PIN_GPIO_2,PAD_CTL_PKE_ENABLE |PAD_CTL_100K_PD |PAD_CTL_DRV_HIGH);gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_2), 0);/* USB Host Over Current */mxc_request_iomux(MX53_PIN_GPIO_3, IOMUX_CONFIG_ALT6);mxc_iomux_set_input(MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT, 1);- }
- return 0;
+} +#endif
+static void setup_iomux_fec(void) +{
- /* MDIO IOMUX */
- mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
- /* FEC 0 IOMUX */
- mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
- /* FEC 1 IOMUX */
- mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6); /* RXD3 */
- mxc_request_iomux(MX53_PIN_KEY_ROW0, IOMUX_CONFIG_ALT6); /* TX_ER */
- mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6); /* RX_CLK */
- mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6); /* COL */
- mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6); /* RXD2 */
- mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6); /* TXD2 */
- mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6); /* CRS */
- mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6); /* TXD3 */
- /* MDIO PADs */
- mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);- mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
- /* FEC 0 PADs */
- mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
- /* FEC 1 PADs */
- mxc_iomux_set_pad(MX53_PIN_KEY_COL0, /* RXD3 */
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_KEY_ROW0, /* TX_ER */
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_KEY_COL1, /* RX_CLK */
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, /* COL */
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_KEY_COL2, /* RXD2 */
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, /* TXD2 */
PAD_CTL_DRV_HIGH);- mxc_iomux_set_pad(MX53_PIN_KEY_COL3, /* CRS */
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_GPIO_19, /* TXD3 */
PAD_CTL_DRV_HIGH);+}
+#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg = {
- MMC_SDHC1_BASE_ADDR,
+};
+int board_mmc_getcd(struct mmc *mmc) +{
- mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
- gpio_direction_input(IMX_GPIO_NR(1, 1));
- return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+int board_mmc_init(bd_t *bis) +{
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA0,
IOMUX_CONFIG_ALT0);- mxc_request_iomux(MX53_PIN_SD1_DATA1,
IOMUX_CONFIG_ALT0);- mxc_request_iomux(MX53_PIN_SD1_DATA2,
IOMUX_CONFIG_ALT0);- mxc_request_iomux(MX53_PIN_SD1_DATA3,
IOMUX_CONFIG_ALT0);- mxc_request_iomux(MX53_PIN_EIM_DA13,
IOMUX_CONFIG_ALT1);- mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);- mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |PAD_CTL_DRV_HIGH);- mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);- mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);- mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);- mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);- /* GPIO 2_31 is SD power */
- mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
- gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
+} +#endif
+static void setup_iomux_i2c(void) +{
- mxc_request_iomux(MX53_PIN_EIM_D16,
IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);- mxc_request_iomux(MX53_PIN_EIM_EB2,
IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);- mxc_iomux_set_pad(MX53_PIN_EIM_D16,
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |PAD_CTL_PUE_PULL |PAD_CTL_ODE_OPENDRAIN_ENABLE);- mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |PAD_CTL_PUE_PULL |PAD_CTL_ODE_OPENDRAIN_ENABLE);- mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, 0x1);
- mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, 0x1);
+}
+static void setup_iomux_nand(void) +{
- mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT3);
- mxc_request_iomux(MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT3);
- mxc_request_iomux(MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT3);
- mxc_request_iomux(MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT3);
- mxc_request_iomux(MX53_PIN_ATA_DATA4, IOMUX_CONFIG_ALT3);
- mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_ALT3);
- mxc_request_iomux(MX53_PIN_ATA_DATA6, IOMUX_CONFIG_ALT3);
- mxc_request_iomux(MX53_PIN_ATA_DATA7, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_ATA_DATA4, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_ATA_DATA6, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- mxc_iomux_set_pad(MX53_PIN_ATA_DATA7, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);+}
+static void m53_set_clock(void) +{
- int ret;
- const uint32_t ref_clk = MXC_HCLK;
- const uint32_t dramclk = 400;
- uint32_t cpuclk;
- mxc_request_iomux(MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX53_PIN_GPIO_10, PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);- gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_10));
- /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
- cpuclk = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10)) ? 1200 : 800;
- ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
- if (ret)
printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);- ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
- if (ret) {
printf("CPU: Switch peripheral clock to %dMHz failed\n",dramclk);- }
- ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
- if (ret)
printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);+}
+static void m53_set_nand(void) +{
- u32 i;
- #define M4IF_GENP_WEIM_MM 0x00000001
- #define WEIM_GCR2_MUX16_BYP_GRANT 0x00001000
- /* NAND flash is muxed on ATA pins */
- setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM);
This should be clrbits_le32().
- /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
- for (i = 0x4; i < 0x94; i += 0x18)
clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT);- mxc_set_clock(0, 33, MXC_NFC_CLK);
- enable_nfc_clk(1);
+}
+int board_early_init_f(void) +{
- setup_iomux_uart();
- setup_iomux_fec();
- setup_iomux_i2c();
- setup_iomux_nand();
- m53_set_clock();
- mxc_set_sata_internal_clock();
- /* NAND clock @ 33MHz */
- m53_set_nand();
- return 0;
+}
+int board_init(void) +{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
+}
+int checkboard(void) +{
- puts("Board: DENX M53EVK\n");
- return 0;
+}
+/*
- NAND SPL
- */
+#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{
- setup_iomux_nand();
- m53_set_clock();
- m53_set_nand();
+}
+u32 spl_boot_device(void) +{
- return BOOT_DEVICE_NAND;
+} +#endif diff --git a/boards.cfg b/boards.cfg index 31483d6..822ae01 100644 --- a/boards.cfg +++ b/boards.cfg @@ -246,6 +246,7 @@ am335x_evm_usbspl arm armv7 am335x ti ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 highbank arm armv7 highbank - highbank +m53evk arm armv7 m53evk denx mx5 m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h new file mode 100644 index 0000000..78e1226 --- /dev/null +++ b/include/configs/m53evk.h @@ -0,0 +1,255 @@ +/*
- DENX M53 configuration
- Copyright (C) 2012-2013 Marek Vasut marex@denx.de
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef __M53EVK_CONFIG_H__ +#define __M53EVK_CONFIG_H__
+#define CONFIG_MX53 +#define CONFIG_MXC_GPIO +#define CONFIG_SYS_HZ 1000
+#include <asm/arch/imx-regs.h>
+#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_NO_FLASH
+/*
- U-Boot Commands
- */
+#include <config_cmd_default.h> +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SATA +#define CONFIG_CMD_USB
+/*
- Memory configurations
- */
+#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0xaff00000
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_SYS_TEXT_BASE 0x71000000
+/*
- U-Boot general configurations
- */
+#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER
+/*
- Serial Driver
- */
+#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200
+/*
- MMC Driver
- */
+#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 +#endif
+/*
- NAND
- */
+#define CONFIG_ENV_SIZE (16 * 1024) +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_USE_FLASH_BBT
+/* Environment is in NAND */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_RANGE (512 * 1024) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)+#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=mxc-nand" +#define MTDPARTS_DEFAULT \
- "mtdparts=mxc-nand:" \
"1m(bootloader)ro," \"512k(environment)," \"512k(redundant-environment)," \"4m(kernel)," \"128k(fdt)," \"8m(ramdisk)," \"-(filesystem)"+#else +#define CONFIG_ENV_IS_NOWHERE +#endif
+/*
- Ethernet on SOC (FEC)
- */
+#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#endif
+/*
- I2C
- */
+#ifdef CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#endif
+/*
- RTC
- */
+#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_M41T62 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 +#endif
+/*
- USB
- */
+#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#endif
+/*
- SATA
- */
+#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif
+/*
- Boot Linux
- */
+#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "m53evk/uImage" +#define CONFIG_BOOTARGS "console=ttymxc1,115200" +#define CONFIG_LOADADDR 0x70800000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_OF_LIBFDT
+/*
- NAND SPL
- */
+#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_TEXT_BASE 0x70008000 +#define CONFIG_SPL_PAD_TO 0x8000 +#define CONFIG_SPL_STACK 0x70004000 +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#endif /* __M53EVK_CONFIG_H__ */
1.7.10.4
And 1 to 5/6 are fine with me.
Best regards, Benoît
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Sunday, April 21, 2013 5:52:27 PM, Marek Vasut wrote:
Add basic support for the DENX M53EVK board. Currently supported is: MMC (incl. booting)
^Can you clarify this, please?
Use u-boot.imx for SD booting as usual.
spl_boot_device() points only to NAND, so you're clearly talking about hardware MMC boot, and not about hardware NAND boot followed by SPL payload fetched from MMC. But MMC boot does not need SPL here, in which case you will have to generate a simple u-boot.imx, or you will rather want to use u-boot-with-spl.imx for SD (NAND header dropped to leave room for MBR). And in the latter case, why have spl_boot_device() point to NAND for MMC boot?
No, regular u-boot.imx will be used for SD boot.
NAND (incl. booting) Ethernet, I2C, USB, SATA, RTC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de
[...]
+static void m53_set_nand(void) +{
- u32 i;
- #define M4IF_GENP_WEIM_MM 0x00000001
- #define WEIM_GCR2_MUX16_BYP_GRANT 0x00001000
- /* NAND flash is muxed on ATA pins */
- setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM);
This should be clrbits_le32().
Why?
- /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
- for (i = 0x4; i < 0x94; i += 0x18)
clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT);- mxc_set_clock(0, 33, MXC_NFC_CLK);
- enable_nfc_clk(1);
+}
[...]
Dear Marek Vasut,
On Sunday, April 21, 2013 9:12:31 PM, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Sunday, April 21, 2013 5:52:27 PM, Marek Vasut wrote:
Add basic support for the DENX M53EVK board. Currently supported is: MMC (incl. booting)
^Can you clarify this, please?
Use u-boot.imx for SD booting as usual.
spl_boot_device() points only to NAND, so you're clearly talking about hardware MMC boot, and not about hardware NAND boot followed by SPL payload fetched from MMC. But MMC boot does not need SPL here, in which case you will have to generate a simple u-boot.imx, or you will rather want to use u-boot-with-spl.imx for SD (NAND header dropped to leave room for MBR). And in the latter case, why have spl_boot_device() point to NAND for MMC boot?
No, regular u-boot.imx will be used for SD boot.
OK. So this will require to call make with u-boot.imx as the explicit target. Should this be documented somewhere, perhaps in a README file for this board?
Another solution would be, like for woodburn, to have an sd-specific config: - m53evk_nand_config would define CONFIG_SPL from boards.cfg, so u-boot-with-nand-spl.imx would be generated. - mx53evk_sd_config would not define CONFIG_SPL from boards.cfg, so u-boot.imx would be generated. And CONFIG_SPL would be removed from m53evk.h.
Or, change the various config.mk in order to build u-boot.imx even if CONFIG_SPL is defined, which would be useless for some boards, but useful here in order to avoid having 2 configs for almost the same build, while still not having to explicitly give a make target.
NAND (incl. booting) Ethernet, I2C, USB, SATA, RTC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de
[...]
+static void m53_set_nand(void) +{
- u32 i;
- #define M4IF_GENP_WEIM_MM 0x00000001
- #define WEIM_GCR2_MUX16_BYP_GRANT 0x00001000
- /* NAND flash is muxed on ATA pins */
- setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM);
This should be clrbits_le32().
Why?
Because I mistakenly assumed (without checking, and even without reading your comment above) that the NFC pins used on this board were muxed on EIM like for mx53ard. So your patch is correct here. ;)
- /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
- for (i = 0x4; i < 0x94; i += 0x18)
clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT);- mxc_set_clock(0, 33, MXC_NFC_CLK);
- enable_nfc_clk(1);
+}
[...]
Best regards, Benoît
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Sunday, April 21, 2013 9:12:31 PM, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Sunday, April 21, 2013 5:52:27 PM, Marek Vasut wrote:
Add basic support for the DENX M53EVK board. Currently supported is: MMC (incl. booting)
^Can you clarify this, please?
Use u-boot.imx for SD booting as usual.
spl_boot_device() points only to NAND, so you're clearly talking about hardware MMC boot, and not about hardware NAND boot followed by SPL payload fetched from MMC. But MMC boot does not need SPL here, in which case you will have to generate a simple u-boot.imx, or you will rather want to use u-boot-with-spl.imx for SD (NAND header dropped to leave room for MBR). And in the latter case, why have spl_boot_device() point to NAND for MMC boot?
No, regular u-boot.imx will be used for SD boot.
OK. So this will require to call make with u-boot.imx as the explicit target. Should this be documented somewhere, perhaps in a README file for this board?
Another solution would be, like for woodburn, to have an sd-specific config: - m53evk_nand_config would define CONFIG_SPL from boards.cfg, so u-boot-with-nand-spl.imx would be generated.
- mx53evk_sd_config would not define CONFIG_SPL from boards.cfg, so
u-boot.imx would be generated. And CONFIG_SPL would be removed from m53evk.h.
Or, change the various config.mk in order to build u-boot.imx even if CONFIG_SPL is defined, which would be useless for some boards, but useful here in order to avoid having 2 configs for almost the same build, while still not having to explicitly give a make target.
I'd love to see generic u-boot.nand , u-boot.sd etc. targets instead of these CPU specific stuffs.
Best regards, Marek Vasut
On 21/04/2013 22:29, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
Hi Marek,
On Sunday, April 21, 2013 9:12:31 PM, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Sunday, April 21, 2013 5:52:27 PM, Marek Vasut wrote:
Add basic support for the DENX M53EVK board. Currently supported is: MMC (incl. booting)
^Can you clarify this, please?
Use u-boot.imx for SD booting as usual.
spl_boot_device() points only to NAND, so you're clearly talking about hardware MMC boot, and not about hardware NAND boot followed by SPL payload fetched from MMC. But MMC boot does not need SPL here, in which case you will have to generate a simple u-boot.imx, or you will rather want to use u-boot-with-spl.imx for SD (NAND header dropped to leave room for MBR). And in the latter case, why have spl_boot_device() point to NAND for MMC boot?
No, regular u-boot.imx will be used for SD boot.
OK. So this will require to call make with u-boot.imx as the explicit target. Should this be documented somewhere, perhaps in a README file for this board?
Another solution would be, like for woodburn, to have an sd-specific config: - m53evk_nand_config would define CONFIG_SPL from boards.cfg, so u-boot-with-nand-spl.imx would be generated.
- mx53evk_sd_config would not define CONFIG_SPL from boards.cfg, so
u-boot.imx would be generated. And CONFIG_SPL would be removed from m53evk.h.
Or, change the various config.mk in order to build u-boot.imx even if CONFIG_SPL is defined, which would be useless for some boards, but useful here in order to avoid having 2 configs for almost the same build, while still not having to explicitly give a make target.
I'd love to see generic u-boot.nand , u-boot.sd etc. targets instead of these CPU specific stuffs.
But you forget that a single image can be saved on multiple storage: u-boot.imx can be stored on SD or NOR or SPI-NOR, and that is the reason for having SOC-specific extension.
I agree with Benoit: at the moment, only people working with i.MX know that u-boot.im runs on SD. The third solution proposed by Benoit has the drawback that probably not all boards need u-boot.imx (a board without SD for example). At least we need an update of the README, but I think it is not bad to have a new entry in boards.cfg.
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
Best regards, Stefano
Hi Stefano,
On Wednesday, April 24, 2013 9:39:17 AM, Stefano Babic wrote:
On 21/04/2013 22:29, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
Hi Marek,
On Sunday, April 21, 2013 9:12:31 PM, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Sunday, April 21, 2013 5:52:27 PM, Marek Vasut wrote:
Add basic support for the DENX M53EVK board. Currently supported is: MMC (incl. booting)
^Can you clarify this, please?
Use u-boot.imx for SD booting as usual.
spl_boot_device() points only to NAND, so you're clearly talking about hardware MMC boot, and not about hardware NAND boot followed by SPL payload fetched from MMC. But MMC boot does not need SPL here, in which case you will have to generate a simple u-boot.imx, or you will rather want to use u-boot-with-spl.imx for SD (NAND header dropped to leave room for MBR). And in the latter case, why have spl_boot_device() point to NAND for MMC boot?
No, regular u-boot.imx will be used for SD boot.
OK. So this will require to call make with u-boot.imx as the explicit target. Should this be documented somewhere, perhaps in a README file for this board?
Another solution would be, like for woodburn, to have an sd-specific config: - m53evk_nand_config would define CONFIG_SPL from boards.cfg, so u-boot-with-nand-spl.imx would be generated.
- mx53evk_sd_config would not define CONFIG_SPL from boards.cfg, so
u-boot.imx would be generated. And CONFIG_SPL would be removed from m53evk.h.
Or, change the various config.mk in order to build u-boot.imx even if CONFIG_SPL is defined, which would be useless for some boards, but useful here in order to avoid having 2 configs for almost the same build, while still not having to explicitly give a make target.
I'd love to see generic u-boot.nand , u-boot.sd etc. targets instead of these CPU specific stuffs.
But you forget that a single image can be saved on multiple storage: u-boot.imx can be stored on SD or NOR or SPI-NOR, and that is the reason for having SOC-specific extension.
I agree with Benoit: at the moment, only people working with i.MX know that u-boot.im runs on SD. The third solution proposed by Benoit has the drawback that probably not all boards need u-boot.imx (a board without SD for example). At least we need an update of the README, but I think it is not bad to have a new entry in boards.cfg.
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
With this also comes the issue of BOOT_FROM in board/denx/m53evk/imximage.cfg. Strictly speaking, in order to be correct, it should be #if-ed depending on some config option: nand or sd.
Best regards, Benoît
On 24/04/2013 12:59, Benoît Thébaudeau wrote:
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
With this also comes the issue of BOOT_FROM in board/denx/m53evk/imximage.cfg. Strictly speaking, in order to be correct, it should be #if-ed depending on some config option: nand or sd.
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Best regards, Stefano
Hi Stefano,
On 25.04.2013 09:31, Stefano Babic wrote:
On 24/04/2013 12:59, Benoît Thébaudeau wrote:
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
With this also comes the issue of BOOT_FROM in board/denx/m53evk/imximage.cfg. Strictly speaking, in order to be correct, it should be #if-ed depending on some config option: nand or sd.
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
Thanks, Stefan
On 25/04/2013 10:38, Stefan Roese wrote:
Hi Stefano,
On 25.04.2013 09:31, Stefano Babic wrote:
On 24/04/2013 12:59, Benoît Thébaudeau wrote:
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
With this also comes the issue of BOOT_FROM in board/denx/m53evk/imximage.cfg. Strictly speaking, in order to be correct, it should be #if-ed depending on some config option: nand or sd.
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier.
Well, than this feature shoulb be added to the mkimage tool. I suggest to add a directive to the configuration file (imximage.cfg), such as PADDING or something like this.
We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool
To my knowledge: do you have the sources for this tool to better understand what it does ? I can find binaries with different version (I think 1.3 is the last), but no sources at all. I have not found if it is open source or not.
Best regards, Stefano
Dear Stefan Roese,
Hi Stefano,
On 25.04.2013 09:31, Stefano Babic wrote:
On 24/04/2013 12:59, Benoît Thébaudeau wrote:
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
With this also comes the issue of BOOT_FROM in board/denx/m53evk/imximage.cfg. Strictly speaking, in order to be correct, it should be #if-ed depending on some config option: nand or sd.
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
This would interfere with MBR on SD cards, the offset is there for a reason ;-)
Best regards, Marek Vasut
On 25.04.2013 14:38, Marek Vasut wrote:
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
This would interfere with MBR on SD cards, the offset is there for a reason ;-)
Yes, makes sense. But only for SD cards. On other mediums (e.g. SPI NOR, NAND) this padded image would be easier (less error prone) to handle.
Thanks, Stefan
Hi Stefan,
On Thursday, April 25, 2013 2:48:59 PM, Stefan Roese wrote:
Subject: Re: [U-Boot] [PATCH V2 6/6] arm: mx5: Add support for DENX M53EVK
On 25.04.2013 14:38, Marek Vasut wrote:
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
This would interfere with MBR on SD cards, the offset is there for a reason ;-)
Yes, makes sense. But only for SD cards. On other mediums (e.g. SPI NOR, NAND) this padded image would be easier (less error prone) to handle.
For NAND, we already have u-boot-with-nand-spl.imx. For SPI NOR, something similar could be done, or this could be done by imximage.
Best regards, Benoît
On 25/04/2013 14:49, Benoît Thébaudeau wrote:
Hi Stefan,
On Thursday, April 25, 2013 2:48:59 PM, Stefan Roese wrote:
Subject: Re: [U-Boot] [PATCH V2 6/6] arm: mx5: Add support for DENX M53EVK
On 25.04.2013 14:38, Marek Vasut wrote:
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
This would interfere with MBR on SD cards, the offset is there for a reason ;-)
Yes, makes sense. But only for SD cards. On other mediums (e.g. SPI NOR, NAND) this padded image would be easier (less error prone) to handle.
For NAND, we already have u-boot-with-nand-spl.imx.
Is it padded at the beginnig ? I have thought the pad is between SPL and u-boot based on CONFIG_SPL_PAD_TO, but we need to flash always at the right offset.
Regards, Stefano
Hi Stefano,
On Thursday, April 25, 2013 3:02:25 PM, Stefano Babic wrote:
On 25/04/2013 14:49, Benoît Thébaudeau wrote:
Hi Stefan,
On Thursday, April 25, 2013 2:48:59 PM, Stefan Roese wrote:
Subject: Re: [U-Boot] [PATCH V2 6/6] arm: mx5: Add support for DENX M53EVK
On 25.04.2013 14:38, Marek Vasut wrote:
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
This would interfere with MBR on SD cards, the offset is there for a reason ;-)
Yes, makes sense. But only for SD cards. On other mediums (e.g. SPI NOR, NAND) this padded image would be easier (less error prone) to handle.
For NAND, we already have u-boot-with-nand-spl.imx.
Is it padded at the beginnig ? I have thought the pad is between SPL and u-boot based on CONFIG_SPL_PAD_TO, but we need to flash always at the right offset.
Here are the image types that we currently have: - u-boot.imx: imx header + u-boot.bin, no padding to compensate for imx offset, generic usage, - SPL: imx header + u-boot-spl.bin, no padding to compensate for imx offset, generic SPL usage, - u-boot-with-spl.imx: SPL padded to CONFIG_SPL_PAD_TO + uImaged-u-boot.bin, no padding to compensate for imx offset, any non-NAND SPL + u-boot usage, - u-boot-with-nand-spl.imx: (FCB (filling normal imx offset) + SPL) padded to CONFIG_SPL_PAD_TO + uImaged-u-boot.bin, NAND SPL + u-boot usage.
Best regards, Benoît
On 25/04/2013 15:16, Benoît Thébaudeau wrote:
Is it padded at the beginnig ? I have thought the pad is between SPL and u-boot based on CONFIG_SPL_PAD_TO, but we need to flash always at the right offset.
Here are the image types that we currently have:
- u-boot.imx: imx header + u-boot.bin, no padding to compensate for imx offset, generic usage,
- SPL: imx header + u-boot-spl.bin, no padding to compensate for imx offset, generic SPL usage,
- u-boot-with-spl.imx: SPL padded to CONFIG_SPL_PAD_TO + uImaged-u-boot.bin, no padding to compensate for imx offset, any non-NAND SPL + u-boot usage,
- u-boot-with-nand-spl.imx: (FCB (filling normal imx offset) + SPL) padded to CONFIG_SPL_PAD_TO + uImaged-u-boot.bin, NAND SPL + u-boot usage.
Right, I see - thanks for this clear explanation.
Best regards, Stefano
Hi Benoît,
On 25.04.2013 14:49, Benoît Thébaudeau wrote:
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
This would interfere with MBR on SD cards, the offset is there for a reason ;-)
Yes, makes sense. But only for SD cards. On other mediums (e.g. SPI NOR, NAND) this padded image would be easier (less error prone) to handle.
For NAND, we already have u-boot-with-nand-spl.imx.
I'm thinking more about NAND on iMX6. Which doesn't support SPL (until now). We could add a new build target for imx6 for NAND booting as well. Not sure if this is better moved to a build target or to the imximage generation tool?
For SPI NOR, something similar could be done, or this could be done by imximage.
Yes. Perhaps its best to add this to imximage.
Thanks, Stefan
Dear Stefan Roese,
Hi Benoît,
On 25.04.2013 14:49, Benoît Thébaudeau wrote:
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
This would interfere with MBR on SD cards, the offset is there for a reason ;-)
Yes, makes sense. But only for SD cards. On other mediums (e.g. SPI NOR, NAND) this padded image would be easier (less error prone) to handle.
For NAND, we already have u-boot-with-nand-spl.imx.
I'm thinking more about NAND on iMX6. Which doesn't support SPL (until now). We could add a new build target for imx6 for NAND booting as well. Not sure if this is better moved to a build target or to the imximage generation tool?
Maybe we should focus on common u-boot.nand target too, which would produce correct result depending on the board configuration etc.
For SPI NOR, something similar could be done, or this could be done by imximage.
Yes. Perhaps its best to add this to imximage.
Thanks, Stefan
Best regards, Marek Vasut
On 25/04/2013 14:48, Stefan Roese wrote:
On 25.04.2013 14:38, Marek Vasut wrote:
Right, this is also correct. Anyway, BOOT_FROM is used to get the offset inside the storage, and only to be as much flexible as possible, each storage has defined its own offset. However, Freescale uses the same offset (0x400) for most storages (NAND, SD..) and another one for NOR or OneNAND (0x1000). Maybe it is easier to have only this two cases.
Yes, I would prefer that.
And being at it, why don't we add the offset to the resulting image as well? This would make programming the images to the destination (SD, NAND, MMC etc) easier. We would not have to care for the correct offset then (which is more error prone). And it is necessary btw, to have this offset added, when using the FSL kobs-ng tool to program the image to NAND flash.
This would interfere with MBR on SD cards, the offset is there for a reason ;-)
Yes, makes sense. But only for SD cards. On other mediums (e.g. SPI NOR, NAND) this padded image would be easier (less error prone) to handle.
If a board can boot only from a single storage, yes. Or at least from storages with have the same offset. For example, if we have a board with SPI-NOR and NAND, the offsets are different amd we need two images if we pad at the beginning. If we want to add such a feature, it should be in any case disabled to not break most of current boards.
Best regards, Stefano
Dear Stefano Babic,
On 21/04/2013 22:29, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
Hi Marek,
On Sunday, April 21, 2013 9:12:31 PM, Marek Vasut wrote:
Dear Benoît Thébaudeau,
Dear Marek Vasut,
On Sunday, April 21, 2013 5:52:27 PM, Marek Vasut wrote:
Add basic support for the DENX M53EVK board. Currently supported is: MMC (incl. booting)
^Can you clarify this, please?
Use u-boot.imx for SD booting as usual.
spl_boot_device() points only to NAND, so you're clearly talking about hardware MMC boot, and not about hardware NAND boot followed by SPL payload fetched from MMC. But MMC boot does not need SPL here, in which case you will have to generate a simple u-boot.imx, or you will rather want to use u-boot-with-spl.imx for SD (NAND header dropped to leave room for MBR). And in the latter case, why have spl_boot_device() point to NAND for MMC boot?
No, regular u-boot.imx will be used for SD boot.
OK. So this will require to call make with u-boot.imx as the explicit target. Should this be documented somewhere, perhaps in a README file for this board?
Another solution would be, like for woodburn, to have an sd-specific config: - m53evk_nand_config would define CONFIG_SPL from boards.cfg, so
u-boot-with-nand-spl.imx would be generated.
- mx53evk_sd_config would not define CONFIG_SPL from boards.cfg, so
u-boot.imx would be generated. And CONFIG_SPL would be removed from m53evk.h.
Or, change the various config.mk in order to build u-boot.imx even if CONFIG_SPL is defined, which would be useless for some boards, but useful here in order to avoid having 2 configs for almost the same build, while still not having to explicitly give a make target.
I'd love to see generic u-boot.nand , u-boot.sd etc. targets instead of these CPU specific stuffs.
But you forget that a single image can be saved on multiple storage: u-boot.imx can be stored on SD or NOR or SPI-NOR, and that is the reason for having SOC-specific extension.
I agree with Benoit: at the moment, only people working with i.MX know that u-boot.im runs on SD. The third solution proposed by Benoit has the drawback that probably not all boards need u-boot.imx (a board without SD for example). At least we need an update of the README, but I think it is not bad to have a new entry in boards.cfg.
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
Ok, I fail to grasp what is wanted from me. Shall I rework the patch somehow? How? Do we want m53evk_sd and m53evk_nand targets ?
Best regards, Marek Vasut
On 24/04/2013 20:52, Marek Vasut wrote:
But you forget that a single image can be saved on multiple storage: u-boot.imx can be stored on SD or NOR or SPI-NOR, and that is the reason for having SOC-specific extension.
I agree with Benoit: at the moment, only people working with i.MX know that u-boot.im runs on SD. The third solution proposed by Benoit has the drawback that probably not all boards need u-boot.imx (a board without SD for example). At least we need an update of the README, but I think it is not bad to have a new entry in boards.cfg.
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
Ok, I fail to grasp what is wanted from me. Shall I rework the patch somehow? How? Do we want m53evk_sd and m53evk_nand targets ?
At least add documentation in the README. It is only your choice if you will add two different targets to boards.cfg
Best regards, Stefano
Dear Stefano Babic,
On 24/04/2013 20:52, Marek Vasut wrote:
But you forget that a single image can be saved on multiple storage: u-boot.imx can be stored on SD or NOR or SPI-NOR, and that is the reason for having SOC-specific extension.
I agree with Benoit: at the moment, only people working with i.MX know that u-boot.im runs on SD. The third solution proposed by Benoit has the drawback that probably not all boards need u-boot.imx (a board without SD for example). At least we need an update of the README, but I think it is not bad to have a new entry in boards.cfg.
Apart of that and not related to this patch, if we in future use SPL also for booting from SD, we can get a single way to boot from different storage. TI based SOCs already do this: same SPL, it checks from SD and NAND.
Ok, I fail to grasp what is wanted from me. Shall I rework the patch somehow? How? Do we want m53evk_sd and m53evk_nand targets ?
At least add documentation in the README. It is only your choice if you will add two different targets to boards.cfg
I'd prefer not to do that. We're currently booting from NAND and SD, so we use u-boot.imx resp. u-boot-with-nand-spl.imx there. But using the BOOT_FROM "nand" in the imximage.cfg is indeed wrong. We should focus on fixing that.
We can now pre-process the imximage.cfg with CPP, so why don't we just replace BOOT_FROM "foobar" with BOOT_OFFSET CONFIG_IMX_BOOT_OFFSET as mentioned by someone in the thread already and setup the offset either in board config file or boards.cfg and even have some default value?
Best regards, Marek Vasut
On 25/04/2013 15:36, Marek Vasut wrote:
Dear Stefano Babic,
Hi Marek,
At least add documentation in the README. It is only your choice if you will add two different targets to boards.cfg
I'd prefer not to do that. We're currently booting from NAND and SD, so we use u-boot.imx resp. u-boot-with-nand-spl.imx there. But using the BOOT_FROM "nand" in the imximage.cfg is indeed wrong. We should focus on fixing that.
We can now pre-process the imximage.cfg with CPP, so why don't we just replace BOOT_FROM "foobar" with BOOT_OFFSET CONFIG_IMX_BOOT_OFFSET
+1
as mentioned by someone in the thread already and setup the offset either in board config file or boards.cfg and even have some default value?
Agree
Best regards, Stefano
Dear Stefano Babic,
On 25/04/2013 15:36, Marek Vasut wrote:
Dear Stefano Babic,
Hi Marek,
At least add documentation in the README. It is only your choice if you will add two different targets to boards.cfg
I'd prefer not to do that. We're currently booting from NAND and SD, so we use u-boot.imx resp. u-boot-with-nand-spl.imx there. But using the BOOT_FROM "nand" in the imximage.cfg is indeed wrong. We should focus on fixing that.
We can now pre-process the imximage.cfg with CPP, so why don't we just replace BOOT_FROM "foobar" with BOOT_OFFSET CONFIG_IMX_BOOT_OFFSET
+1
as mentioned by someone in the thread already and setup the offset either in board config file or boards.cfg and even have some default value?
Agree
even better, CONFIG_IMX_BOOT_OFFSET can be defined somewhere to either of the two values -- one for OneNAND and NOR and the other one for the rest. That'd make it even easier for people to grok down.
I'll wait for general agreement and then possibly look into implementing it.
Best regards, Marek Vasut
On Sun, Apr 21, 2013 at 12:52 PM, Marek Vasut marex@denx.de wrote:
+u32 get_board_rev(void) +{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;struct fuse_bank *bank = &iim->bank[0];struct fuse_bank0_regs *fuse =(struct fuse_bank0_regs *)bank->fuse_regs;int rev = readl(&fuse->gp[6]);return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
Do you really need to read the fuses on m53evk?
It would be better to do the same as we did for mx6:
Put it into a common mx5 file:
#ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { return get_cpu_rev(); } #endif
,and then remove get_board_rev from your board file.
+static void m53_set_nand(void) +{
u32 i;#define M4IF_GENP_WEIM_MM 0x00000001#define WEIM_GCR2_MUX16_BYP_GRANT 0x00001000
Please put these defines into a common file. mx53ard also uses them.
/* NAND flash is muxed on ATA pins */setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM);/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */for (i = 0x4; i < 0x94; i += 0x18)clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT);mxc_set_clock(0, 33, MXC_NFC_CLK);enable_nfc_clk(1);
Shouldn't this function be placed into a common mx5 location? mx53ard uses the same.
Dear Fabio Estevam,
On Sun, Apr 21, 2013 at 12:52 PM, Marek Vasut marex@denx.de wrote:
+u32 get_board_rev(void) +{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;struct fuse_bank *bank = &iim->bank[0];struct fuse_bank0_regs *fuse =(struct fuse_bank0_regs *)bank->fuse_regs;int rev = readl(&fuse->gp[6]);return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;Do you really need to read the fuses on m53evk?
It would be better to do the same as we did for mx6:
Put it into a common mx5 file:
#ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { return get_cpu_rev(); } #endif
,and then remove get_board_rev from your board file.
We don't have that on MX5. Or do you mean I should do the work and submit this patch afterwards ?
+static void m53_set_nand(void) +{
u32 i;#define M4IF_GENP_WEIM_MM 0x00000001#define WEIM_GCR2_MUX16_BYP_GRANT 0x00001000Please put these defines into a common file. mx53ard also uses them.
Which one? Or do you mean generate two files full of register sets because of these two bits?
/* NAND flash is muxed on ATA pins */setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM);/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT)*/ + for (i = 0x4; i < 0x94; i += 0x18)
clrbits_le32(WEIM_BASE_ADDR + i,WEIM_GCR2_MUX16_BYP_GRANT); +
mxc_set_clock(0, 33, MXC_NFC_CLK);enable_nfc_clk(1);Shouldn't this function be placed into a common mx5 location? mx53ard uses the same.
The WEIM and M4IF configuration is board-specific.
Best regards, Marek Vasut
On Wed, Apr 24, 2013 at 6:32 PM, Marek Vasut marex@denx.de wrote:
Dear Fabio Estevam,
On Sun, Apr 21, 2013 at 12:52 PM, Marek Vasut marex@denx.de wrote:
+u32 get_board_rev(void) +{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;struct fuse_bank *bank = &iim->bank[0];struct fuse_bank0_regs *fuse =(struct fuse_bank0_regs *)bank->fuse_regs;int rev = readl(&fuse->gp[6]);return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;Do you really need to read the fuses on m53evk?
It would be better to do the same as we did for mx6:
Put it into a common mx5 file:
#ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { return get_cpu_rev(); } #endif
,and then remove get_board_rev from your board file.
We don't have that on MX5. Or do you mean I should do the work and submit this patch afterwards ?
As a patch before this one, I'd say. No reason to add one more place to change it later.
-- Otavio Salvador O.S. Systems E-mail: otavio@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
On Wed, Apr 24, 2013 at 6:32 PM, Marek Vasut marex@denx.de wrote:
We don't have that on MX5. Or do you mean I should do the work and submit this patch afterwards ?
To make things easier, I just sent a patch series that you can use :-)
Which one? Or do you mean generate two files full of register sets because of these two bits?
No, my suggestion is just to put these 2 defines into imx-regs.h. This is also part of my series I just sent.
/* NAND flash is muxed on ATA pins */setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM);/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT)*/ + for (i = 0x4; i < 0x94; i += 0x18)
clrbits_le32(WEIM_BASE_ADDR + i,WEIM_GCR2_MUX16_BYP_GRANT); +
mxc_set_clock(0, 33, MXC_NFC_CLK);enable_nfc_clk(1);Shouldn't this function be placed into a common mx5 location? mx53ard uses the same.
The WEIM and M4IF configuration is board-specific.
Right, understood. It seems like a duplication of code from mx53ard, but anyway, what about:
clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT) ?
Accessing registers via offsets is not the best practice in U-boot.
What about the weim struct defined at arch/arm/include/asm/arch-mx5/imx-regs.h
for acessing such registers?
Dear Fabio Estevam,
[..]
Shouldn't this function be placed into a common mx5 location? mx53ard uses the same.
The WEIM and M4IF configuration is board-specific.
Right, understood. It seems like a duplication of code from mx53ard, but anyway, what about:
clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT) ?
Accessing registers via offsets is not the best practice in U-boot.
What about the weim struct defined at arch/arm/include/asm/arch-mx5/imx-regs.h
for acessing such registers?
Yes, I agree, but you won't be able to do that in a loop as above if accessed via struct-based access so I'm keeping this.
Best regards, Marek Vasut
On 21/04/2013 17:52, Marek Vasut wrote:
The MX53 ROM loads the data from NAND in multiples of pages and supports maximum page size of 4k. Thus, align the image and header to 4k to be safe from ROM bugs.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
participants (7)
-
Benoît Thébaudeau -
Fabio Estevam -
Marek Vasut -
Otavio Salvador -
Scott Wood -
Stefan Roese -
Stefano Babic