[U-Boot] [PATCH v2 1/4] x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: - Remove NORTHBRIDGE_INTEL_SANDYBRIDGE in Makefile too.
arch/x86/cpu/Makefile | 1 - arch/x86/cpu/ivybridge/Kconfig | 33 +-------------------------------- 2 files changed, 1 insertion(+), 33 deletions(-)
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index e797925..2ff2377 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_EFI_APP) += efi/ obj-$(CONFIG_QEMU) += qemu/ -obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 0e249a4..d20c038 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -5,37 +5,11 @@ # # SPDX-License-Identifier: GPL-2.0
- -config NORTHBRIDGE_INTEL_SANDYBRIDGE - bool - select CACHE_MRC_BIN - select CPU_INTEL_MODEL_206AX - config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN select CPU_INTEL_MODEL_306AX
-if NORTHBRIDGE_INTEL_SANDYBRIDGE - -config VGA_BIOS_ID - string - default "8086,0106" - -config CACHE_MRC_SIZE_KB - int - default 256 - -config DCACHE_RAM_BASE - hex - default 0xff7f0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -endif - if NORTHBRIDGE_INTEL_IVYBRIDGE
config VGA_BIOS_ID @@ -58,10 +32,6 @@ config DCACHE_RAM_SIZE hex default 0x20000
-endif - -if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE - config HAVE_MRC bool "Add a System Agent binary" help @@ -83,8 +53,7 @@ config DCACHE_RAM_MRC_VAR_SIZE config MRC_FILE string "Intel System Agent path and filename" depends on HAVE_MRC - default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE - default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE + default "systemagent-ivybridge.bin" help The path and filename of the file to use as System Agent binary.
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/x86/cpu/ivybridge/Kconfig | 30 ------------------------------ board/google/chromebook_link/Kconfig | 1 - board/google/chromebox_panther/Kconfig | 1 - include/configs/x86-chromebook.h | 1 - 4 files changed, 33 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index d20c038..0970382 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -8,18 +8,9 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN - select CPU_INTEL_MODEL_306AX
if NORTHBRIDGE_INTEL_IVYBRIDGE
-config VGA_BIOS_ID - string - default "8086,0166" - -config EXTERNAL_MRC_BLOB - bool - default n - config CACHE_MRC_SIZE_KB int default 512 @@ -50,24 +41,9 @@ config DCACHE_RAM_MRC_VAR_SIZE memory reference code. This should be set to 16KB (0x4000 hex) so that MRC has enough space to run.
-config MRC_FILE - string "Intel System Agent path and filename" - depends on HAVE_MRC - default "systemagent-ivybridge.bin" - help - The path and filename of the file to use as System Agent - binary. - config CPU_SPECIFIC_OPTIONS def_bool y select SMM_TSEG - select ARCH_BOOTBLOCK_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SSE2 - select UDELAY_LAPIC - select CPU_MICROCODE_IN_CBFS - select TSC_SYNC_MFENCE select HAVE_INTEL_ME select X86_RAMTEST
@@ -99,12 +75,6 @@ config CPU_INTEL_SOCKET_RPGA989
if CPU_INTEL_SOCKET_RPGA989
-config SOCKET_SPECIFIC_OPTIONS # dummy - def_bool y - select MMX - select SSE - select CACHE_AS_RAM - config CACHE_MRC_BIN bool default n diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index d3644a9..3843517 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SOUTHBRIDGE_INTEL_C216 select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index d56d903..88afff3 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SOUTHBRIDGE_INTEL_C216 select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 9fb1a7a..c575dab 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -14,7 +14,6 @@ #define CONFIG_MISC_INIT_R
#define CONFIG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_CACHE_MRC_SIZE_KB 512
#define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
On 25 November 2015 at 17:46, Bin Meng bmeng.cn@gmail.com wrote:
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/Kconfig | 30 ------------------------------ board/google/chromebook_link/Kconfig | 1 - board/google/chromebox_panther/Kconfig | 1 - include/configs/x86-chromebook.h | 1 - 4 files changed, 33 deletions(-)
Tested on link: Tested-by: Simon Glass sjg@chromium.org
This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/x86/cpu/ivybridge/Kconfig | 15 ++++----------- board/google/chromebook_link/Kconfig | 1 - board/google/chromebox_panther/Kconfig | 1 - 3 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 0970382..56abd8f 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -11,6 +11,10 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
if NORTHBRIDGE_INTEL_IVYBRIDGE
+config CACHE_MRC_BIN + bool + default n + config CACHE_MRC_SIZE_KB int default 512 @@ -69,14 +73,3 @@ config ENABLE_VMX slowly.
endif - -config CPU_INTEL_SOCKET_RPGA989 - bool - -if CPU_INTEL_SOCKET_RPGA989 - -config CACHE_MRC_BIN - bool - default n - -endif diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 3843517..ce976db 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -18,7 +18,6 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR - select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192 diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index 88afff3..c1cf89c 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -19,7 +19,6 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR - select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192
On 25 November 2015 at 17:46, Bin Meng bmeng.cn@gmail.com wrote:
This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/Kconfig | 15 ++++----------- board/google/chromebook_link/Kconfig | 1 - board/google/chromebox_panther/Kconfig | 1 - 3 files changed, 4 insertions(+), 13 deletions(-)
Tested on link: Tested-by: Simon Glass sjg@chromium.org
These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 9 --------- arch/x86/cpu/ivybridge/northbridge.c | 16 ---------------- board/google/chromebook_link/Kconfig | 1 - board/google/chromebox_panther/Kconfig | 1 - drivers/pci/pci_rom.c | 8 -------- 6 files changed, 44 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 0e6512c..de65d87 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -299,16 +299,7 @@ int print_cpuinfo(void) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - debug("Resume from S3 detected.\n"); - boot_mode = PEI_BOOT_RESUME; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else debug("Resume from S3 detected, but disabled.\n"); -#endif } else { /* * TODO: An indication of life might be possible here (e.g. diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 3efd3e8..af5d4a8 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -240,15 +240,6 @@ static void pch_rtc_init(pci_dev_t dev) } debug("rtc_failed = 0x%x\n", rtc_failed);
-#if CONFIG_HAVE_ACPI_RESUME - /* Avoid clearing pending interrupts and resetting the RTC control - * register in the resume path because the Linux kernel relies on - * this to know if it should restart the RTC timerqueue if the wake - * was due to the RTC alarm. - */ - if (acpi_get_slp_type() == 3) - return; -#endif /* TODO: Handle power failure */ if (rtc_failed) printf("RTC power failed\n"); diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index e95e60e..e3d8c13 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -169,20 +169,4 @@ void northbridge_init(pci_dev_t dev)
void northbridge_enable(pci_dev_t dev) { -#if CONFIG_HAVE_ACPI_RESUME - switch (x86_pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - debug("Normal boot.\n"); - apci_set_slp_type(0); - break; - case 0xcafed00d: - debug("S3 Resume.\n"); - apci_set_slp_type(3); - break; - default: - debug("Unknown boot method, assuming normal.\n"); - apci_set_slp_type(0); - break; - } -#endif } diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index ce976db..6b13939 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE - select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index c1cf89c..ae96d23 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE - select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192
config SYS_CAR_ADDR diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index d244543..ad1167e 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -33,10 +33,6 @@ #include <video_fb.h> #include <linux/screen_info.h>
-#ifdef CONFIG_HAVE_ACPI_RESUME -#include <asm/acpi.h> -#endif - __weak bool board_should_run_oprom(pci_dev_t dev) { return true; @@ -44,10 +40,6 @@ __weak bool board_should_run_oprom(pci_dev_t dev)
static bool should_load_oprom(pci_dev_t dev) { -#ifdef CONFIG_HAVE_ACPI_RESUME - if (acpi_get_slp_type() == 3) - return false; -#endif if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) return 1; if (board_should_run_oprom(dev))
On 25 November 2015 at 17:46, Bin Meng bmeng.cn@gmail.com wrote:
These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 9 --------- arch/x86/cpu/ivybridge/northbridge.c | 16 ---------------- board/google/chromebook_link/Kconfig | 1 - board/google/chromebox_panther/Kconfig | 1 - drivers/pci/pci_rom.c | 8 -------- 6 files changed, 44 deletions(-)
Tested on link: Tested-by: Simon Glass sjg@chromium.org
Hi Bin,
On 25 November 2015 at 17:46, Bin Meng bmeng.cn@gmail.com wrote:
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Remove NORTHBRIDGE_INTEL_SANDYBRIDGE in Makefile too.
arch/x86/cpu/Makefile | 1 - arch/x86/cpu/ivybridge/Kconfig | 33 +-------------------------------- 2 files changed, 1 insertion(+), 33 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
I'll be able to test this series next week.
- Simon
Hi Simon,
On Fri, Nov 27, 2015 at 12:50 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 25 November 2015 at 17:46, Bin Meng bmeng.cn@gmail.com wrote:
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Remove NORTHBRIDGE_INTEL_SANDYBRIDGE in Makefile too.
arch/x86/cpu/Makefile | 1 - arch/x86/cpu/ivybridge/Kconfig | 33 +-------------------------------- 2 files changed, 1 insertion(+), 33 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
I'll be able to test this series next week.
I see you sent a series of ivybridge dm update. Does that sit on top of my series? Have you got a chance to test this series?
Regards, Bin
On 8 December 2015 at 01:10, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Fri, Nov 27, 2015 at 12:50 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 25 November 2015 at 17:46, Bin Meng bmeng.cn@gmail.com wrote:
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Remove NORTHBRIDGE_INTEL_SANDYBRIDGE in Makefile too.
arch/x86/cpu/Makefile | 1 - arch/x86/cpu/ivybridge/Kconfig | 33 +-------------------------------- 2 files changed, 1 insertion(+), 33 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
I'll be able to test this series next week.
I see you sent a series of ivybridge dm update. Does that sit on top of my series? Have you got a chance to test this series?
No but a rebase is easy.
Tested on link: Tested-by: Simon Glass sjg@chromium.org
BTW you could apply this series if you like as it is a clean-up.
participants (2)
-
Bin Meng -
Simon Glass