[U-Boot] [PATCH 1/4] mx5: cosmetic: Clean up lowlevel_init
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 46 ++++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 683a7b5..a40b84f 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -36,9 +36,9 @@ /* reconfigure L2 cache aux control reg */ mov r0, #0xC0 /* tag RAM */ add r0, r0, #0x4 /* data RAM */ - orr r0, r0, #(1 << 24) /* disable write allocate delay */ - orr r0, r0, #(1 << 23) /* disable write allocate combine */ - orr r0, r0, #(1 << 22) /* disable write allocate */ + orr r0, r0, #1 << 24 /* disable write allocate delay */ + orr r0, r0, #1 << 23 /* disable write allocate combine */ + orr r0, r0, #1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51) ldr r1, =0x0 @@ -46,7 +46,7 @@ cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */ - orrls r0, r0, #(1 << 25) + orrls r0, r0, #1 << 25 #endif
mcr 15, 1, r0, c9, c0, 2 @@ -247,9 +247,9 @@ movhi r1, #0 #else mov r1, #0 - #endif str r1, [r0, #CLKCTL_CACRR] + /* Switch ARM back to PLL 1 */ mov r1, #0 str r1, [r0, #CLKCTL_CCSR] @@ -288,9 +288,9 @@ /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 - orr r1, r1, #(2 << 10) - orr r1, r1, #(0 << 16) - orr r1, r1, #(1 << 19) + orr r1, r1, #2 << 10 + orr r1, r1, #0 << 16 + orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154 @@ -331,10 +331,10 @@ ENTRY(lowlevel_init) #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] - orr r1, r1, #(1 << 23) + orr r1, r1, #1 << 23 str r1, [r0, #0x0] ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 23) + orr r1, r1, #1 << 23 str r1, [r0, #0x4] #endif
@@ -351,16 +351,16 @@ ENTRY(lowlevel_init) ENDPROC(lowlevel_init)
/* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 -W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +W_DP_OP_864: .word DP_OP_864 +W_DP_MFD_864: .word DP_MFD_864 +W_DP_MFN_864: .word DP_MFN_864 +W_DP_MFN_800_DIT: .word DP_MFN_800_DIT +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_665: .word DP_OP_665 +W_DP_MFD_665: .word DP_MFD_665 +W_DP_MFN_665: .word DP_MFN_665 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 112 +++++++++++--------- 1 file changed, 59 insertions(+), 53 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index a40b84f..529e35b 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -24,6 +24,8 @@ #include <generated/asm-offsets.h> #include <linux/linkage.h>
+.section ".text.init", "x" + /* * L2CC Cache setup/invalidation/disable */ @@ -34,15 +36,14 @@ mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */ - mov r0, #0xC0 /* tag RAM */ - add r0, r0, #0x4 /* data RAM */ - orr r0, r0, #1 << 24 /* disable write allocate delay */ - orr r0, r0, #1 << 23 /* disable write allocate combine */ - orr r0, r0, #1 << 22 /* disable write allocate */ + ldr r0, =0xC0 | /* tag RAM */ \ + 0x4 | /* data RAM */ \ + 1 << 24 | /* disable write allocate delay */ \ + 1 << 23 | /* disable write allocate combine */ \ + 1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51) - ldr r1, =0x0 - ldr r3, [r1, #ROM_SI_REV] + ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */ @@ -84,8 +85,7 @@ ldr r1, =0x00000203 str r1, [r0, #0x40]
- ldr r1, =0x0 - str r1, [r0, #0x44] + str r4, [r0, #0x44]
ldr r1, =0x00120125 str r1, [r0, #0x9C] @@ -98,20 +98,29 @@
.macro setup_pll pll, freq ldr r0, =\pll + adr r2, W_DP_\freq + bl setup_pll_func +.endm + +#define W_DP_OP 0 +#define W_DP_MFD 4 +#define W_DP_MFN 8 + +setup_pll_func: ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
- ldr r1, W_DP_OP_\freq + ldr r1, [r2, #W_DP_OP] str r1, [r0, #PLL_DP_OP] str r1, [r0, #PLL_DP_HFS_OP]
- ldr r1, W_DP_MFD_\freq + ldr r1, [r2, #W_DP_MFD] str r1, [r0, #PLL_DP_MFD] str r1, [r0, #PLL_DP_HFS_MFD]
- ldr r1, W_DP_MFN_\freq + ldr r1, [r2, #W_DP_MFN] str r1, [r0, #PLL_DP_MFN] str r1, [r0, #PLL_DP_HFS_MFN]
@@ -120,12 +129,13 @@ 1: ldr r1, [r0, #PLL_DP_CTL] ands r1, r1, #0x1 beq 1b -.endm + + /* r10 saved upper lr */ + mov pc, lr
.macro setup_pll_errata pll, freq ldr r2, =\pll - mov r1, #0x0 - str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */ + str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */ ldr r1, =0x00001236 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */ 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */ @@ -158,10 +168,9 @@ /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] - ldr r1, =0x0 - str r1, [r0, #CLKCTL_CCGR1] - str r1, [r0, #CLKCTL_CCGR2] - str r1, [r0, #CLKCTL_CCGR3] + str r4, [r0, #CLKCTL_CCGR1] + str r4, [r0, #CLKCTL_CCGR2] + str r4, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000 str r1, [r0, #CLKCTL_CCGR4] @@ -184,11 +193,10 @@ #else ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] - ldr r1, =0x0 - str r1, [r0, #CLKCTL_CCGR1] - str r1, [r0, #CLKCTL_CCGR2] - str r1, [r0, #CLKCTL_CCGR3] - str r1, [r0, #CLKCTL_CCGR7] + str r4, [r0, #CLKCTL_CCGR1] + str r4, [r0, #CLKCTL_CCGR2] + str r4, [r0, #CLKCTL_CCGR3] + str r4, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000 str r1, [r0, #CLKCTL_CCGR4] @@ -214,8 +222,7 @@
/* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x000010C0 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] @@ -225,8 +232,7 @@ ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] #endif setup_pll PLL3_BASE_ADDR, 216 @@ -240,8 +246,7 @@
#if defined(CONFIG_MX51) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ - ldr r1, =0x0 - ldr r3, [r1, #ROM_SI_REV] + ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 movls r1, #0x1 movhi r1, #0 @@ -251,14 +256,12 @@ str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */ - mov r1, #0 - str r1, [r0, #CLKCTL_CCSR] + str r4, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51) /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ - ldr r1, =0x000020C2 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ ldr r1, =CONFIG_SYS_CLKTL_CBCDR @@ -289,7 +292,6 @@ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 orr r1, r1, #2 << 10 - orr r1, r1, #0 << 16 orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR]
@@ -310,8 +312,7 @@ cmp r1, #0x0 bne 1b
- mov r1, #0x0 - str r1, [r0, #CLKCTL_CCDR] + str r4, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */ mov r1, #0x000A0000 @@ -325,9 +326,10 @@ strh r1, [r0] .endm
-.section ".text.init", "x" - ENTRY(lowlevel_init) + mov r10, lr + mov r4, #0 /* Fix R4 to 0 */ + #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] @@ -346,21 +348,25 @@ ENTRY(lowlevel_init)
init_clock
- /* r12 saved upper lr*/ - mov pc,lr + mov pc, r10 ENDPROC(lowlevel_init)
/* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 +#if defined(CONFIG_MX51_PLL_ERRATA) +W_DP_864: .word DP_OP_864 + .word DP_MFD_864 + .word DP_MFN_864 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +#else +W_DP_800: .word DP_OP_800 + .word DP_MFD_800 + .word DP_MFN_800 +#endif +#if defined(CONFIG_MX51) +W_DP_665: .word DP_OP_665 + .word DP_MFD_665 + .word DP_MFN_665 +#endif +W_DP_216: .word DP_OP_216 + .word DP_MFD_216 + .word DP_MFN_216
On Tue, Aug 14, 2012 at 11:44 AM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
What the patch does? Please use long description for it.
Optimize mx5 lowlevel_init.S code size: - Compute values at compile time rather than at runtime where possible. - Assign r4 to hold the zero value rather than setting registers to 0 again and again. - Associate a function to setup_pll rather than expanding its large macro code multiple times. - Allocate constant values in section only if used.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- Changes for v2: - Make patch description more detailed.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 112 +++++++++++--------- 1 file changed, 59 insertions(+), 53 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index a40b84f..529e35b 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -24,6 +24,8 @@ #include <generated/asm-offsets.h> #include <linux/linkage.h>
+.section ".text.init", "x" + /* * L2CC Cache setup/invalidation/disable */ @@ -34,15 +36,14 @@ mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */ - mov r0, #0xC0 /* tag RAM */ - add r0, r0, #0x4 /* data RAM */ - orr r0, r0, #1 << 24 /* disable write allocate delay */ - orr r0, r0, #1 << 23 /* disable write allocate combine */ - orr r0, r0, #1 << 22 /* disable write allocate */ + ldr r0, =0xC0 | /* tag RAM */ \ + 0x4 | /* data RAM */ \ + 1 << 24 | /* disable write allocate delay */ \ + 1 << 23 | /* disable write allocate combine */ \ + 1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51) - ldr r1, =0x0 - ldr r3, [r1, #ROM_SI_REV] + ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */ @@ -84,8 +85,7 @@ ldr r1, =0x00000203 str r1, [r0, #0x40]
- ldr r1, =0x0 - str r1, [r0, #0x44] + str r4, [r0, #0x44]
ldr r1, =0x00120125 str r1, [r0, #0x9C] @@ -98,20 +98,29 @@
.macro setup_pll pll, freq ldr r0, =\pll + adr r2, W_DP_\freq + bl setup_pll_func +.endm + +#define W_DP_OP 0 +#define W_DP_MFD 4 +#define W_DP_MFN 8 + +setup_pll_func: ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
- ldr r1, W_DP_OP_\freq + ldr r1, [r2, #W_DP_OP] str r1, [r0, #PLL_DP_OP] str r1, [r0, #PLL_DP_HFS_OP]
- ldr r1, W_DP_MFD_\freq + ldr r1, [r2, #W_DP_MFD] str r1, [r0, #PLL_DP_MFD] str r1, [r0, #PLL_DP_HFS_MFD]
- ldr r1, W_DP_MFN_\freq + ldr r1, [r2, #W_DP_MFN] str r1, [r0, #PLL_DP_MFN] str r1, [r0, #PLL_DP_HFS_MFN]
@@ -120,12 +129,13 @@ 1: ldr r1, [r0, #PLL_DP_CTL] ands r1, r1, #0x1 beq 1b -.endm + + /* r10 saved upper lr */ + mov pc, lr
.macro setup_pll_errata pll, freq ldr r2, =\pll - mov r1, #0x0 - str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */ + str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */ ldr r1, =0x00001236 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */ 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */ @@ -158,10 +168,9 @@ /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] - ldr r1, =0x0 - str r1, [r0, #CLKCTL_CCGR1] - str r1, [r0, #CLKCTL_CCGR2] - str r1, [r0, #CLKCTL_CCGR3] + str r4, [r0, #CLKCTL_CCGR1] + str r4, [r0, #CLKCTL_CCGR2] + str r4, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000 str r1, [r0, #CLKCTL_CCGR4] @@ -184,11 +193,10 @@ #else ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] - ldr r1, =0x0 - str r1, [r0, #CLKCTL_CCGR1] - str r1, [r0, #CLKCTL_CCGR2] - str r1, [r0, #CLKCTL_CCGR3] - str r1, [r0, #CLKCTL_CCGR7] + str r4, [r0, #CLKCTL_CCGR1] + str r4, [r0, #CLKCTL_CCGR2] + str r4, [r0, #CLKCTL_CCGR3] + str r4, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000 str r1, [r0, #CLKCTL_CCGR4] @@ -214,8 +222,7 @@
/* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x000010C0 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] @@ -225,8 +232,7 @@ ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] #endif setup_pll PLL3_BASE_ADDR, 216 @@ -240,8 +246,7 @@
#if defined(CONFIG_MX51) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ - ldr r1, =0x0 - ldr r3, [r1, #ROM_SI_REV] + ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 movls r1, #0x1 movhi r1, #0 @@ -251,14 +256,12 @@ str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */ - mov r1, #0 - str r1, [r0, #CLKCTL_CCSR] + str r4, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51) /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ - ldr r1, =0x000020C2 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ ldr r1, =CONFIG_SYS_CLKTL_CBCDR @@ -289,7 +292,6 @@ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 orr r1, r1, #2 << 10 - orr r1, r1, #0 << 16 orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR]
@@ -310,8 +312,7 @@ cmp r1, #0x0 bne 1b
- mov r1, #0x0 - str r1, [r0, #CLKCTL_CCDR] + str r4, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */ mov r1, #0x000A0000 @@ -325,9 +326,10 @@ strh r1, [r0] .endm
-.section ".text.init", "x" - ENTRY(lowlevel_init) + mov r10, lr + mov r4, #0 /* Fix R4 to 0 */ + #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] @@ -346,21 +348,25 @@ ENTRY(lowlevel_init)
init_clock
- /* r12 saved upper lr*/ - mov pc,lr + mov pc, r10 ENDPROC(lowlevel_init)
/* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 +#if defined(CONFIG_MX51_PLL_ERRATA) +W_DP_864: .word DP_OP_864 + .word DP_MFD_864 + .word DP_MFN_864 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +#else +W_DP_800: .word DP_OP_800 + .word DP_MFD_800 + .word DP_MFN_800 +#endif +#if defined(CONFIG_MX51) +W_DP_665: .word DP_OP_665 + .word DP_MFD_665 + .word DP_MFN_665 +#endif +W_DP_216: .word DP_OP_216 + .word DP_MFD_216 + .word DP_MFN_216
On 14/08/2012 17:19, Benoît Thébaudeau wrote:
Optimize mx5 lowlevel_init.S code size:
- Compute values at compile time rather than at runtime where possible.
- Assign r4 to hold the zero value rather than setting registers to 0 again and again.
- Associate a function to setup_pll rather than expanding its large macro code multiple times.
- Allocate constant values in section only if used.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Changes for v2:
- Make patch description more detailed.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 112 +++++++++++--------- 1 file changed, 59 insertions(+), 53 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index a40b84f..529e35b 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -24,6 +24,8 @@ #include <generated/asm-offsets.h> #include <linux/linkage.h>
+.section ".text.init", "x"
/*
- L2CC Cache setup/invalidation/disable
*/ @@ -34,15 +36,14 @@ mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #1 << 24 /* disable write allocate delay */
- orr r0, r0, #1 << 23 /* disable write allocate combine */
- orr r0, r0, #1 << 22 /* disable write allocate */
- ldr r0, =0xC0 | /* tag RAM */ \
0x4 | /* data RAM */ \1 << 24 | /* disable write allocate delay */ \1 << 23 | /* disable write allocate combine */ \1 << 22 /* disable write allocate */#if defined(CONFIG_MX51)
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
@@ -84,8 +85,7 @@ ldr r1, =0x00000203 str r1, [r0, #0x40]
- ldr r1, =0x0
- str r1, [r0, #0x44]
str r4, [r0, #0x44]
ldr r1, =0x00120125 str r1, [r0, #0x9C]
@@ -98,20 +98,29 @@
.macro setup_pll pll, freq ldr r0, =\pll
- adr r2, W_DP_\freq
- bl setup_pll_func
+.endm
+#define W_DP_OP 0 +#define W_DP_MFD 4 +#define W_DP_MFN 8
+setup_pll_func: ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
- ldr r1, W_DP_OP_\freq
- ldr r1, [r2, #W_DP_OP] str r1, [r0, #PLL_DP_OP] str r1, [r0, #PLL_DP_HFS_OP]
- ldr r1, W_DP_MFD_\freq
- ldr r1, [r2, #W_DP_MFD] str r1, [r0, #PLL_DP_MFD] str r1, [r0, #PLL_DP_HFS_MFD]
- ldr r1, W_DP_MFN_\freq
- ldr r1, [r2, #W_DP_MFN] str r1, [r0, #PLL_DP_MFN] str r1, [r0, #PLL_DP_HFS_MFN]
@@ -120,12 +129,13 @@ 1: ldr r1, [r0, #PLL_DP_CTL] ands r1, r1, #0x1 beq 1b -.endm
- /* r10 saved upper lr */
- mov pc, lr
.macro setup_pll_errata pll, freq ldr r2, =\pll
- mov r1, #0x0
- str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
- str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */ ldr r1, =0x00001236 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */ @@ -158,10 +168,9 @@ /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
str r4, [r0, #CLKCTL_CCGR1]
str r4, [r0, #CLKCTL_CCGR2]
str r4, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000 str r1, [r0, #CLKCTL_CCGR4]
@@ -184,11 +193,10 @@ #else ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR7]
str r4, [r0, #CLKCTL_CCGR1]
str r4, [r0, #CLKCTL_CCGR2]
str r4, [r0, #CLKCTL_CCGR3]
str r4, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000 str r1, [r0, #CLKCTL_CCGR4]
@@ -214,8 +222,7 @@
/* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
- ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR]
@@ -225,8 +232,7 @@ ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
- ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR]
#endif setup_pll PLL3_BASE_ADDR, 216 @@ -240,8 +246,7 @@
#if defined(CONFIG_MX51) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
- ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 movls r1, #0x1 movhi r1, #0
@@ -251,14 +256,12 @@ str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #CLKCTL_CCSR]
- str r4, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51) /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
@@ -289,7 +292,6 @@ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 orr r1, r1, #2 << 10
- orr r1, r1, #0 << 16 orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR]
@@ -310,8 +312,7 @@ cmp r1, #0x0 bne 1b
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCDR]
str r4, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */ mov r1, #0x000A0000
@@ -325,9 +326,10 @@ strh r1, [r0] .endm
-.section ".text.init", "x"
ENTRY(lowlevel_init)
- mov r10, lr
- mov r4, #0 /* Fix R4 to 0 */
#if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] @@ -346,21 +348,25 @@ ENTRY(lowlevel_init)
init_clock
- /* r12 saved upper lr*/
- mov pc,lr
- mov pc, r10
ENDPROC(lowlevel_init)
/* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 +#if defined(CONFIG_MX51_PLL_ERRATA) +W_DP_864: .word DP_OP_864
.word DP_MFD_864.word DP_MFN_864W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +#else +W_DP_800: .word DP_OP_800
.word DP_MFD_800.word DP_MFN_800+#endif +#if defined(CONFIG_MX51) +W_DP_665: .word DP_OP_665
.word DP_MFD_665.word DP_MFN_665+#endif +W_DP_216: .word DP_OP_216
.word DP_MFD_216.word DP_MFN_216
I don't see any issue with this patch.
Tested also on mx53loco.
Tested-by: Stefano Babic sbabic@denx.de Acked-by: Stefano Babic sbabic@denx.de
Regards, Stefano
On 14/08/2012 17:19, Benoît Thébaudeau wrote:
Optimize mx5 lowlevel_init.S code size:
- Compute values at compile time rather than at runtime where possible.
- Assign r4 to hold the zero value rather than setting registers to 0 again and again.
- Associate a function to setup_pll rather than expanding its large macro code multiple times.
- Allocate constant values in section only if used.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Applied to u-boot-imx, next branch, thanks.
Best regards, Stefano Babic
Add an option to optimize away revision-specific code from lowlevel_init.S. This can be useful for recently designed boards that may not be fitted with older revisions.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 ++-- .../doc/README.imx5 | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 529e35b..d0f75fa 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -42,7 +42,7 @@ 1 << 23 | /* disable write allocate combine */ \ 1 << 22 /* disable write allocate */
-#if defined(CONFIG_MX51) +#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3) ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10
@@ -244,7 +244,7 @@ setup_pll_func:
ldr r0, =CCM_BASE_ADDR
-#if defined(CONFIG_MX51) +#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5 index f7eab7d..938d3da 100644 --- u-boot-4d3c95f.orig/doc/README.imx5 +++ u-boot-4d3c95f/doc/README.imx5 @@ -6,7 +6,12 @@ i.MX5x SoCs. 1. CONFIGURATION OPTIONS/SETTINGS ---------------------------------
-1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. +1.1 CONFIG_MX51_TO_3: i.MX51 silicon revision 3 or higher. + This option can be enabled for these i.MX51 silicon revisions to optimize + away some specific behavior triggered by the detection of older silicon + revisions at runtime. + +1.2 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. This option should be enabled by all boards using the i.MX51 silicon version up until (including) 3.0 running at 800MHz. The PLL's in the i.MX51 processor can go out of lock due to a metastable
On Tue, Aug 14, 2012 at 11:44 AM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Add an option to optimize away revision-specific code from lowlevel_init.S. This can be useful for recently designed boards that may not be fitted with older revisions.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Looking at code I somewhat understood what you did but the commit log doesn't describe the change you did neither why you did.
The mx5 lowlevel_init.S contains code that detects the silicon revision at runtime, and that behaves differently if a silicon revision older than TO 3 is detected. This code is useless for recently designed boards that may not be fitted with older silicon revisions. Hence, this patch adds an option to optimize away this revision-specific code from lowlevel_init.S.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- Changes for v2: - Make patch description more detailed.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 ++-- .../doc/README.imx5 | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 529e35b..d0f75fa 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -42,7 +42,7 @@ 1 << 23 | /* disable write allocate combine */ \ 1 << 22 /* disable write allocate */
-#if defined(CONFIG_MX51) +#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3) ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10
@@ -244,7 +244,7 @@ setup_pll_func:
ldr r0, =CCM_BASE_ADDR
-#if defined(CONFIG_MX51) +#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5 index f7eab7d..938d3da 100644 --- u-boot-4d3c95f.orig/doc/README.imx5 +++ u-boot-4d3c95f/doc/README.imx5 @@ -6,7 +6,12 @@ i.MX5x SoCs. 1. CONFIGURATION OPTIONS/SETTINGS ---------------------------------
-1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. +1.1 CONFIG_MX51_TO_3: i.MX51 silicon revision 3 or higher. + This option can be enabled for these i.MX51 silicon revisions to optimize + away some specific behavior triggered by the detection of older silicon + revisions at runtime. + +1.2 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. This option should be enabled by all boards using the i.MX51 silicon version up until (including) 3.0 running at 800MHz. The PLL's in the i.MX51 processor can go out of lock due to a metastable
On 14/08/2012 17:19, Benoît Thébaudeau wrote:
The mx5 lowlevel_init.S contains code that detects the silicon revision at runtime, and that behaves differently if a silicon revision older than TO 3 is detected. This code is useless for recently designed boards that may not be fitted with older silicon revisions. Hence, this patch adds an option to optimize away this revision-specific code from lowlevel_init.S.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Hi Benoît,
Changes for v2:
- Make patch description more detailed.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 ++-- .../doc/README.imx5 | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-)
The ROM revision is currently detected at run time - because this does not fix an evident bug, your patch intends to reduce the footprint.
Then I chacked on a mx51evk, a board thet was shipped by Freescale with TO 2 (and maybe TO 1 ?), and there are surely samples with TO2 or TO3 in the world.
Without the poatch:
Configuring for mx51evk - Board: mx51evk, Options: IMX_CONFIG=board/freescale/mx51evk/imximage.cfg text data bss dec hex filename 258168 15872 268464 542504 84728 ./u-boot
With the patch:
Configuring for mx51evk - Board: mx51evk, Options: IMX_CONFIG=board/freescale/mx51evk/imximage.cfg text data bss dec hex filename 258140 15872 268492 542504 84728 ./u-boot
We win only 28 bytes - on the other side, we had a CONFIG_ that is not so clear how to be used, mainly if a board as the mx51evk was shipped with both versions.
I think the advantages are negligible here.
Best regards, Stefano
Hi Stefano,
On 14/08/2012 17:19, Benoît Thébaudeau wrote:
The mx5 lowlevel_init.S contains code that detects the silicon revision at runtime, and that behaves differently if a silicon revision older than TO 3 is detected. This code is useless for recently designed boards that may not be fitted with older silicon revisions. Hence, this patch adds an option to optimize away this revision-specific code from lowlevel_init.S.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Hi Benoît,
Changes for v2:
- Make patch description more detailed.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 ++-- .../doc/README.imx5 | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-)
The ROM revision is currently detected at run time - because this does not fix an evident bug, your patch intends to reduce the footprint.
Then I chacked on a mx51evk, a board thet was shipped by Freescale with TO 2 (and maybe TO 1 ?), and there are surely samples with TO2 or TO3 in the world.
Without the poatch:
Configuring for mx51evk - Board: mx51evk, Options: IMX_CONFIG=board/freescale/mx51evk/imximage.cfg text data bss dec hex filename 258168 15872 268464 542504 84728 ./u-boot
With the patch:
Configuring for mx51evk - Board: mx51evk, Options: IMX_CONFIG=board/freescale/mx51evk/imximage.cfg text data bss dec hex filename 258140 15872 268492 542504 84728 ./u-boot
We win only 28 bytes - on the other side, we had a CONFIG_ that is not so clear how to be used, mainly if a board as the mx51evk was shipped with both versions.
To make things easier, this config should be used only for boards always shipped with the newer versions.
I think the advantages are negligible here.
Indeed. I needed that for a specific case where any single byte was worth saving. For upstream U-Boot, I let you decide if this is interesting enough or not.
Best regards, Benoît
The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 2 +- .../doc/README.imx5 | 5 +++++ .../include/configs/efikamx.h | 1 + .../include/configs/mx51evk.h | 1 + .../include/configs/vision2.h | 1 + 5 files changed, 9 insertions(+), 1 deletion(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index d0f75fa..b25b3a7 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -330,7 +330,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */
-#if defined(CONFIG_MX51) +#if defined(CONFIG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5 index 938d3da..85d476f 100644 --- u-boot-4d3c95f.orig/doc/README.imx5 +++ u-boot-4d3c95f/doc/README.imx5 @@ -20,3 +20,8 @@ i.MX5x SoCs. mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. + +1.3 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. + This option should be enabled for boards having a SYS_ON_OFF_CTL signal + connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the + reference designs. diff --git u-boot-4d3c95f.orig/include/configs/efikamx.h u-boot-4d3c95f/include/configs/efikamx.h index 143b0f0..792b51b 100644 --- u-boot-4d3c95f.orig/include/configs/efikamx.h +++ u-boot-4d3c95f/include/configs/efikamx.h @@ -270,5 +270,6 @@
#define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 +#define CONFIG_SYS_MAIN_PWR_ON
#endif diff --git u-boot-4d3c95f.orig/include/configs/mx51evk.h u-boot-4d3c95f/include/configs/mx51evk.h index e975f54..6867f7b 100644 --- u-boot-4d3c95f.orig/include/configs/mx51evk.h +++ u-boot-4d3c95f/include/configs/mx51evk.h @@ -242,6 +242,7 @@
#define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON
/*----------------------------------------------------------------------- * FLASH and environment organization diff --git u-boot-4d3c95f.orig/include/configs/vision2.h u-boot-4d3c95f/include/configs/vision2.h index ed004a6..3ce4906 100644 --- u-boot-4d3c95f.orig/include/configs/vision2.h +++ u-boot-4d3c95f/include/configs/vision2.h @@ -203,6 +203,7 @@ /* 166 MHz DDR RAM */ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 +#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH
The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Adding missing board maintainers to Cc.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 2 +- .../doc/README.imx5 | 5 +++++ .../include/configs/efikamx.h | 1 + .../include/configs/mx51evk.h | 1 + .../include/configs/vision2.h | 1 + 5 files changed, 9 insertions(+), 1 deletion(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index d0f75fa..b25b3a7 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -330,7 +330,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */
-#if defined(CONFIG_MX51) +#if defined(CONFIG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5 index 938d3da..85d476f 100644 --- u-boot-4d3c95f.orig/doc/README.imx5 +++ u-boot-4d3c95f/doc/README.imx5 @@ -20,3 +20,8 @@ i.MX5x SoCs. mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure.
+1.3 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
- This option should be enabled for boards having a SYS_ON_OFF_CTL
signal
- connected to GPIO1[23] and triggering the MAIN_PWR_ON signal
like in the
- reference designs.
diff --git u-boot-4d3c95f.orig/include/configs/efikamx.h u-boot-4d3c95f/include/configs/efikamx.h index 143b0f0..792b51b 100644 --- u-boot-4d3c95f.orig/include/configs/efikamx.h +++ u-boot-4d3c95f/include/configs/efikamx.h @@ -270,5 +270,6 @@
#define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 +#define CONFIG_SYS_MAIN_PWR_ON
#endif diff --git u-boot-4d3c95f.orig/include/configs/mx51evk.h u-boot-4d3c95f/include/configs/mx51evk.h index e975f54..6867f7b 100644 --- u-boot-4d3c95f.orig/include/configs/mx51evk.h +++ u-boot-4d3c95f/include/configs/mx51evk.h @@ -242,6 +242,7 @@
#define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
- FLASH and environment organization
diff --git u-boot-4d3c95f.orig/include/configs/vision2.h u-boot-4d3c95f/include/configs/vision2.h index ed004a6..3ce4906 100644 --- u-boot-4d3c95f.orig/include/configs/vision2.h +++ u-boot-4d3c95f/include/configs/vision2.h @@ -203,6 +203,7 @@ /* 166 MHz DDR RAM */ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 +#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH
The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de Cc: Matt Sealey matt@genesi-usa.com --- Note for mx51_efikamx and vision2 board maintainers: Check if CONFIG_SYS_MAIN_PWR_ON should be defined or not for your hardware (I don't have your schematics). Anyway, this patch does not change the behavior for these boards, but it allows to fix a possible existing issue for these boards if they differ from the mx51evk on this point.
This patch supersedes http://patchwork.ozlabs.org/patch/177296/ . Changes for v2: - Rebase after other patch dropped in the original series (changes section number in doc/README.imx5). - Rebase after efikamx renamed to mx51_efikamx.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 2 +- {u-boot-imx-bad05afe.orig => u-boot-imx-bad05afe}/doc/README.imx5 | 5 +++++ .../include/configs/mx51_efikamx.h | 1 + .../include/configs/mx51evk.h | 1 + .../include/configs/vision2.h | 1 + 5 files changed, 9 insertions(+), 1 deletion(-)
diff --git u-boot-imx-bad05afe.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-imx-bad05afe/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 29ec957..6d9396a 100644 --- u-boot-imx-bad05afe.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-imx-bad05afe/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -396,7 +396,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */
-#if defined(CONFIG_MX51) +#if defined(CONFIG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git u-boot-imx-bad05afe.orig/doc/README.imx5 u-boot-imx-bad05afe/doc/README.imx5 index f7eab7d..e08941e 100644 --- u-boot-imx-bad05afe.orig/doc/README.imx5 +++ u-boot-imx-bad05afe/doc/README.imx5 @@ -15,3 +15,8 @@ i.MX5x SoCs. mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. + +1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. + This option should be enabled for boards having a SYS_ON_OFF_CTL signal + connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the + reference designs. diff --git u-boot-imx-bad05afe.orig/include/configs/mx51_efikamx.h u-boot-imx-bad05afe/include/configs/mx51_efikamx.h index ffe771f..a056566 100644 --- u-boot-imx-bad05afe.orig/include/configs/mx51_efikamx.h +++ u-boot-imx-bad05afe/include/configs/mx51_efikamx.h @@ -261,5 +261,6 @@
#define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 +#define CONFIG_SYS_MAIN_PWR_ON
#endif diff --git u-boot-imx-bad05afe.orig/include/configs/mx51evk.h u-boot-imx-bad05afe/include/configs/mx51evk.h index 8cf59fe..122871f 100644 --- u-boot-imx-bad05afe.orig/include/configs/mx51evk.h +++ u-boot-imx-bad05afe/include/configs/mx51evk.h @@ -235,6 +235,7 @@
#define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON
/*----------------------------------------------------------------------- * FLASH and environment organization diff --git u-boot-imx-bad05afe.orig/include/configs/vision2.h u-boot-imx-bad05afe/include/configs/vision2.h index 848df88..13c5702 100644 --- u-boot-imx-bad05afe.orig/include/configs/vision2.h +++ u-boot-imx-bad05afe/include/configs/vision2.h @@ -196,6 +196,7 @@ /* 166 MHz DDR RAM */ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 +#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH
On 05/11/2012 21:07, Benoît Thébaudeau wrote:
The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.
Right, and it is correct that this initialisation is not done for all boards.
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de Cc: Matt Sealey matt@genesi-usa.com
Note for mx51_efikamx and vision2 board maintainers: Check if CONFIG_SYS_MAIN_PWR_ON should be defined or not for your hardware (I don't have your schematics). Anyway, this patch does not change the behavior for these boards, but it allows to fix a possible existing issue for these boards if they differ from the mx51evk on this point.
This patch supersedes http://patchwork.ozlabs.org/patch/177296/ . Changes for v2:
- Rebase after other patch dropped in the original series (changes section number in doc/README.imx5).
- Rebase after efikamx renamed to mx51_efikamx.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 2 +- {u-boot-imx-bad05afe.orig => u-boot-imx-bad05afe}/doc/README.imx5 | 5 +++++ .../include/configs/mx51_efikamx.h | 1 + .../include/configs/mx51evk.h | 1 + .../include/configs/vision2.h | 1 + 5 files changed, 9 insertions(+), 1 deletion(-)
diff --git u-boot-imx-bad05afe.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-imx-bad05afe/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 29ec957..6d9396a 100644 --- u-boot-imx-bad05afe.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-imx-bad05afe/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -396,7 +396,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */
-#if defined(CONFIG_MX51) +#if defined(CONFIG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git u-boot-imx-bad05afe.orig/doc/README.imx5 u-boot-imx-bad05afe/doc/README.imx5 index f7eab7d..e08941e 100644 --- u-boot-imx-bad05afe.orig/doc/README.imx5 +++ u-boot-imx-bad05afe/doc/README.imx5 @@ -15,3 +15,8 @@ i.MX5x SoCs. mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure.
+1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
- This option should be enabled for boards having a SYS_ON_OFF_CTL signal
- connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
- reference designs.
diff --git u-boot-imx-bad05afe.orig/include/configs/mx51_efikamx.h u-boot-imx-bad05afe/include/configs/mx51_efikamx.h index ffe771f..a056566 100644 --- u-boot-imx-bad05afe.orig/include/configs/mx51_efikamx.h +++ u-boot-imx-bad05afe/include/configs/mx51_efikamx.h @@ -261,5 +261,6 @@
#define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 +#define CONFIG_SYS_MAIN_PWR_ON
#endif diff --git u-boot-imx-bad05afe.orig/include/configs/mx51evk.h u-boot-imx-bad05afe/include/configs/mx51evk.h index 8cf59fe..122871f 100644 --- u-boot-imx-bad05afe.orig/include/configs/mx51evk.h +++ u-boot-imx-bad05afe/include/configs/mx51evk.h @@ -235,6 +235,7 @@
#define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
- FLASH and environment organization
diff --git u-boot-imx-bad05afe.orig/include/configs/vision2.h u-boot-imx-bad05afe/include/configs/vision2.h index 848df88..13c5702 100644 --- u-boot-imx-bad05afe.orig/include/configs/vision2.h +++ u-boot-imx-bad05afe/include/configs/vision2.h @@ -196,6 +196,7 @@ /* 166 MHz DDR RAM */ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 +#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH
Hi Stefano,
On Wednesday, November 7, 2012 3:29:14 PM, Stefano Babic wrote:
On 05/11/2012 21:07, Benoît Thébaudeau wrote:
The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.
Right, and it is correct that this initialisation is not done for all boards.
Acked-by: Stefano Babic sbabic@denx.de
You seem to have forgotten this one in your last couple of application rounds.
Best regards, Benoît
On 16/11/2012 23:42, Benoît Thébaudeau wrote:
Hi Stefano,
On Wednesday, November 7, 2012 3:29:14 PM, Stefano Babic wrote:
On 05/11/2012 21:07, Benoît Thébaudeau wrote:
The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.
Right, and it is correct that this initialisation is not done for all boards.
Acked-by: Stefano Babic sbabic@denx.de
You seem to have forgotten this one in your last couple of application rounds.
That's right, I will push it - thanks.
Best regards, Stefano
On 05/11/2012 21:07, Benoît Thébaudeau wrote:
The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de Cc: Matt Sealey matt@genesi-usa.com
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
On Tue, Aug 14, 2012 at 11:43 AM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
The patch seems to be just code style changes, but it is not clear from the commit description.
Coding style cleanup: - Remove useless parentheses. - Use tabs for indentations and alignments.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- Changes for v2: - Make patch description more detailed.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 46 ++++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 683a7b5..a40b84f 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -36,9 +36,9 @@ /* reconfigure L2 cache aux control reg */ mov r0, #0xC0 /* tag RAM */ add r0, r0, #0x4 /* data RAM */ - orr r0, r0, #(1 << 24) /* disable write allocate delay */ - orr r0, r0, #(1 << 23) /* disable write allocate combine */ - orr r0, r0, #(1 << 22) /* disable write allocate */ + orr r0, r0, #1 << 24 /* disable write allocate delay */ + orr r0, r0, #1 << 23 /* disable write allocate combine */ + orr r0, r0, #1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51) ldr r1, =0x0 @@ -46,7 +46,7 @@ cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */ - orrls r0, r0, #(1 << 25) + orrls r0, r0, #1 << 25 #endif
mcr 15, 1, r0, c9, c0, 2 @@ -247,9 +247,9 @@ movhi r1, #0 #else mov r1, #0 - #endif str r1, [r0, #CLKCTL_CACRR] + /* Switch ARM back to PLL 1 */ mov r1, #0 str r1, [r0, #CLKCTL_CCSR] @@ -288,9 +288,9 @@ /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 - orr r1, r1, #(2 << 10) - orr r1, r1, #(0 << 16) - orr r1, r1, #(1 << 19) + orr r1, r1, #2 << 10 + orr r1, r1, #0 << 16 + orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154 @@ -331,10 +331,10 @@ ENTRY(lowlevel_init) #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] - orr r1, r1, #(1 << 23) + orr r1, r1, #1 << 23 str r1, [r0, #0x0] ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 23) + orr r1, r1, #1 << 23 str r1, [r0, #0x4] #endif
@@ -351,16 +351,16 @@ ENTRY(lowlevel_init) ENDPROC(lowlevel_init)
/* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 -W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +W_DP_OP_864: .word DP_OP_864 +W_DP_MFD_864: .word DP_MFD_864 +W_DP_MFN_864: .word DP_MFN_864 +W_DP_MFN_800_DIT: .word DP_MFN_800_DIT +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_665: .word DP_OP_665 +W_DP_MFD_665: .word DP_MFD_665 +W_DP_MFN_665: .word DP_MFN_665 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216
On 14/08/2012 17:18, Benoît Thébaudeau wrote:
Coding style cleanup:
- Remove useless parentheses.
- Use tabs for indentations and alignments.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Changes for v2:
- Make patch description more detailed.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 46 ++++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 683a7b5..a40b84f 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -36,9 +36,9 @@ /* reconfigure L2 cache aux control reg */ mov r0, #0xC0 /* tag RAM */ add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
- orr r0, r0, #1 << 24 /* disable write allocate delay */
- orr r0, r0, #1 << 23 /* disable write allocate combine */
- orr r0, r0, #1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51) ldr r1, =0x0 @@ -46,7 +46,7 @@ cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
- orrls r0, r0, #(1 << 25)
- orrls r0, r0, #1 << 25
#endif
mcr 15, 1, r0, c9, c0, 2 @@ -247,9 +247,9 @@ movhi r1, #0 #else mov r1, #0
#endif str r1, [r0, #CLKCTL_CACRR]
- /* Switch ARM back to PLL 1 */ mov r1, #0 str r1, [r0, #CLKCTL_CCSR]
@@ -288,9 +288,9 @@ /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145
- orr r1, r1, #(2 << 10)
- orr r1, r1, #(0 << 16)
- orr r1, r1, #(1 << 19)
orr r1, r1, #2 << 10
orr r1, r1, #0 << 16
orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
@@ -331,10 +331,10 @@ ENTRY(lowlevel_init) #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0]
- orr r1, r1, #(1 << 23)
- orr r1, r1, #1 << 23 str r1, [r0, #0x0] ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 23)
- orr r1, r1, #1 << 23 str r1, [r0, #0x4]
#endif
@@ -351,16 +351,16 @@ ENTRY(lowlevel_init) ENDPROC(lowlevel_init)
/* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 -W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +W_DP_OP_864: .word DP_OP_864 +W_DP_MFD_864: .word DP_MFD_864 +W_DP_MFN_864: .word DP_MFN_864 +W_DP_MFN_800_DIT: .word DP_MFN_800_DIT +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_665: .word DP_OP_665 +W_DP_MFD_665: .word DP_MFD_665 +W_DP_MFN_665: .word DP_MFN_665 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 14/08/2012 17:18, Benoît Thébaudeau wrote:
Coding style cleanup:
- Remove useless parentheses.
- Use tabs for indentations and alignments.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Changes for v2:
- Make patch description more detailed.
.../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 46 ++++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 683a7b5..a40b84f 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -36,9 +36,9 @@ /* reconfigure L2 cache aux control reg */ mov r0, #0xC0 /* tag RAM */ add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
- orr r0, r0, #1 << 24 /* disable write allocate delay */
- orr r0, r0, #1 << 23 /* disable write allocate combine */
- orr r0, r0, #1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51) ldr r1, =0x0 @@ -46,7 +46,7 @@ cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
- orrls r0, r0, #(1 << 25)
- orrls r0, r0, #1 << 25
#endif
mcr 15, 1, r0, c9, c0, 2 @@ -247,9 +247,9 @@ movhi r1, #0 #else mov r1, #0
#endif str r1, [r0, #CLKCTL_CACRR]
- /* Switch ARM back to PLL 1 */ mov r1, #0 str r1, [r0, #CLKCTL_CCSR]
@@ -288,9 +288,9 @@ /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145
- orr r1, r1, #(2 << 10)
- orr r1, r1, #(0 << 16)
- orr r1, r1, #(1 << 19)
orr r1, r1, #2 << 10
orr r1, r1, #0 << 16
orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
@@ -331,10 +331,10 @@ ENTRY(lowlevel_init) #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0]
- orr r1, r1, #(1 << 23)
- orr r1, r1, #1 << 23 str r1, [r0, #0x0] ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 23)
- orr r1, r1, #1 << 23 str r1, [r0, #0x4]
#endif
@@ -351,16 +351,16 @@ ENTRY(lowlevel_init) ENDPROC(lowlevel_init)
/* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 -W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +W_DP_OP_864: .word DP_OP_864 +W_DP_MFD_864: .word DP_MFD_864 +W_DP_MFN_864: .word DP_MFN_864 +W_DP_MFN_800_DIT: .word DP_MFN_800_DIT +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_665: .word DP_OP_665 +W_DP_MFD_665: .word DP_MFD_665 +W_DP_MFN_665: .word DP_MFN_665 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
participants (3)
-
Benoît Thébaudeau -
Otavio Salvador -
Stefano Babic