[PATCH 0/7] Qualcomm: add support for SC7280 and the RB3 Gen 2
Introduce support for the SC7280 platform and specifically the RB3 Gen 2 development board.
The RB3 Gen 2 is the latest robotics board from Qualcomm, featuring a QCM6490 SoC (the same SoC found in the Fairphone 5), 6GB of RAM, and 128GB of UFS storage, as well as a whole lot of I/O.
Most of the I/O is attached via a custom PCIe bridge chip, and as such is not yet supported. However it is possible to boot from USB via the Type-C port, which is hardcoded to host mode for this initial support.
USB support additionally requires this patch: https://lore.kernel.org/u-boot/20240423141551.2410199-1-caleb.connolly@linar...
--- Caleb Connolly (7): clk/qcom: add initial clock driver for sc7280 dts: qcs6490-rb3gen2-u-boot: add override dtsi dts: qcs6490-rb3gen2-u-boot: USB host mode iommu: qcom-smmu: add sc7280-smmu-500 compatible qcom_defconfig: enable SC7280 clocks configs: add qcm6490_defconfig doc: board/qualcomm: document rb3gen2 building/flashing
arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi | 28 +++++++ configs/qcm6490_defconfig | 18 +++++ configs/qcom_defconfig | 1 + doc/board/qualcomm/rb3gen2.rst | 53 +++++++++++++ drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-qcom.h | 1 + drivers/clk/qcom/clock-sc7280.c | 132 +++++++++++++++++++++++++++++++ drivers/iommu/qcom-hyp-smmu.c | 1 + 9 files changed, 243 insertions(+) --- change-id: 20240809-b4-rb3gen2-87bd866abde1 base-commit: 428e11e6e36aa0a13f85961c64af24751c4d1bb7
// Caleb (they/them)
We don't actually need any clocks to get UFS up and running, resets are useful though.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/clk/qcom/Kconfig | 8 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-qcom.h | 1 + drivers/clk/qcom/clock-sc7280.c | 132 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 142 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 45d63c6d6dbf..0d2c0ac225c5 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -85,7 +85,15 @@ config CLK_QCOM_SM8650 Say Y here to enable support for the Global Clock Controller on the Snapdragon SM8650 SoC. This driver supports the clocks and resets exposed by the GCC hardware block.
+config CLK_QCOM_SC7280 + bool "Qualcomm SC7280 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SC7280 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + endmenu
endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec20e4b5943..e223c131ee4d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -8,8 +8,9 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o +obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index f6445c8f566f..7aa6ca59aad5 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -10,8 +10,9 @@ #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) #define CFG_CLK_SRC_GPLL9 (2 << 8) +#define CFG_CLK_SRC_GPLL0_ODD (3 << 8) #define CFG_CLK_SRC_GPLL6 (4 << 8) #define CFG_CLK_SRC_GPLL7 (3 << 8) #define CFG_CLK_SRC_GPLL4 (5 << 8) #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c new file mode 100644 index 000000000000..5d343f120519 --- /dev/null +++ b/drivers/clk/qcom/clock-sc7280.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock drivers for Qualcomm sc7280 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-sc7280.h> + +#include "clock-qcom.h" + +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 + +static ulong sc7280_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate); + clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return rate; + case GCC_USB30_PRIM_MASTER_CLK: + WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); + clk_rcg_set_rate(priv->base, 0xf064, 0, 0); + return rate; + default: + return 0; + } +} + +static const struct gate_clk sc7280_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, 1), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, 1), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1), +}; + +static int sc7280_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, sc7280_clks[clk->id].name); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sc7280_gcc_resets[] = { + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_1_BCR] = { 0x8d000 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_SDCC1_BCR] = { 0x75000 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0xf000 }, + [GCC_USB30_SEC_BCR] = { 0x9e000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct qcom_power_map sc7280_gdscs[] = { + [GCC_UFS_PHY_GDSC] = { 0x77004 }, + [GCC_USB30_PRIM_GDSC] = { 0xf004 }, +}; + +static struct msm_clk_data qcs404_gcc_data = { + .resets = sc7280_gcc_resets, + .num_resets = ARRAY_SIZE(sc7280_gcc_resets), + .clks = sc7280_clks, + .num_clks = ARRAY_SIZE(sc7280_clks), + + .power_domains = sc7280_gdscs, + .num_power_domains = ARRAY_SIZE(sc7280_gdscs), + + .enable = sc7280_enable, + .set_rate = sc7280_set_rate, +}; + +static const struct udevice_id gcc_sc7280_of_match[] = { + { + .compatible = "qcom,gcc-sc7280", + .data = (ulong)&qcs404_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sc7280) = { + .name = "gcc_sc7280", + .id = UCLASS_NOP, + .of_match = gcc_sc7280_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +};
On 09/08/2024 02:48, Caleb Connolly wrote:
We don't actually need any clocks to get UFS up and running, resets are useful though.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org
drivers/clk/qcom/Kconfig | 8 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-qcom.h | 1 + drivers/clk/qcom/clock-sc7280.c | 132 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 142 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 45d63c6d6dbf..0d2c0ac225c5 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -85,7 +85,15 @@ config CLK_QCOM_SM8650 Say Y here to enable support for the Global Clock Controller on the Snapdragon SM8650 SoC. This driver supports the clocks and resets exposed by the GCC hardware block.
+config CLK_QCOM_SC7280
bool "Qualcomm SC7280 GCC"
select CLK_QCOM
help
Say Y here to enable support for the Global Clock Controlleron the Snapdragon SC7280 SoC. This driver supports the clocksand resets exposed by the GCC hardware block.endmenu
endif
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec20e4b5943..e223c131ee4d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -8,8 +8,9 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o +obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index f6445c8f566f..7aa6ca59aad5 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -10,8 +10,9 @@ #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) #define CFG_CLK_SRC_GPLL9 (2 << 8) +#define CFG_CLK_SRC_GPLL0_ODD (3 << 8) #define CFG_CLK_SRC_GPLL6 (4 << 8) #define CFG_CLK_SRC_GPLL7 (3 << 8) #define CFG_CLK_SRC_GPLL4 (5 << 8) #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c new file mode 100644 index 000000000000..5d343f120519 --- /dev/null +++ b/drivers/clk/qcom/clock-sc7280.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Clock drivers for Qualcomm sc7280
- (C) Copyright 2024 Linaro Ltd.
- */
+#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-sc7280.h>
+#include "clock-qcom.h"
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+static ulong sc7280_set_rate(struct clk *clk, ulong rate) +{
- struct msm_clk_priv *priv = dev_get_priv(clk->dev);
- if (clk->id < priv->data->num_clks)
debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);- switch (clk->id) {
- case GCC_USB30_PRIM_MOCK_UTMI_CLK:
WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);return rate;- case GCC_USB30_PRIM_MASTER_CLK:
WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);clk_rcg_set_rate(priv->base, 0xf064, 0, 0);return rate;- default:
return 0;- }
+}
+static const struct gate_clk sc7280_clks[] = {
- GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, 1),
- GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1),
- GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, 1),
- GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1),
- GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
- GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
- GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
+};
+static int sc7280_enable(struct clk *clk) +{
- struct msm_clk_priv *priv = dev_get_priv(clk->dev);
- if (priv->data->num_clks < clk->id) {
debug("%s: unknown clk id %lu\n", __func__, clk->id);return 0;- }
- debug("%s: clk %ld: %s\n", __func__, clk->id, sc7280_clks[clk->id].name);
- switch (clk->id) {
- case GCC_AGGRE_USB3_PRIM_AXI_CLK:
qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);fallthrough;- case GCC_USB30_PRIM_MASTER_CLK:
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);break;- }
- qcom_gate_clk_en(priv, clk->id);
- return 0;
+}
+static const struct qcom_reset_map sc7280_gcc_resets[] = {
- [GCC_PCIE_0_BCR] = { 0x6b000 },
- [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
- [GCC_PCIE_1_BCR] = { 0x8d000 },
- [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
- [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
- [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
- [GCC_SDCC1_BCR] = { 0x75000 },
- [GCC_SDCC2_BCR] = { 0x14000 },
- [GCC_SDCC4_BCR] = { 0x16000 },
- [GCC_UFS_PHY_BCR] = { 0x77000 },
- [GCC_USB30_PRIM_BCR] = { 0xf000 },
- [GCC_USB30_SEC_BCR] = { 0x9e000 },
- [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
- [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
- [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
- [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+static const struct qcom_power_map sc7280_gdscs[] = {
- [GCC_UFS_PHY_GDSC] = { 0x77004 },
- [GCC_USB30_PRIM_GDSC] = { 0xf004 },
+};
+static struct msm_clk_data qcs404_gcc_data = {
- .resets = sc7280_gcc_resets,
- .num_resets = ARRAY_SIZE(sc7280_gcc_resets),
- .clks = sc7280_clks,
- .num_clks = ARRAY_SIZE(sc7280_clks),
- .power_domains = sc7280_gdscs,
- .num_power_domains = ARRAY_SIZE(sc7280_gdscs),
- .enable = sc7280_enable,
- .set_rate = sc7280_set_rate,
+};
+static const struct udevice_id gcc_sc7280_of_match[] = {
- {
.compatible = "qcom,gcc-sc7280",.data = (ulong)&qcs404_gcc_data,- },
- { }
+};
+U_BOOT_DRIVER(gcc_sc7280) = {
- .name = "gcc_sc7280",
- .id = UCLASS_NOP,
- .of_match = gcc_sc7280_of_match,
- .bind = qcom_cc_bind,
- .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
Reviewed-by: Neil Armstrong neil.armstrong@linaro.org
For running U-Boot as primary bootloader we must define the memory layout statically.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi new file mode 100644 index 000000000000..c3ec4a317f7c --- /dev/null +++ b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Linaro Ltd. + */ +/ { + /* When running as the primary bootloader there is no prior + * stage to populate the memory layout for us. We *should* + * have two nodes here, but ABL does NOT like that. + * sooo we're stuck with this. + */ + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x3A800000>, + <0 0xC0000000 0 0x01800000>, + <0 0xC3400000 0 0x3CC00000>, + <1 0x00000000 1 0x00000000>; + }; +}; + +// RAM Entry 0 : Base 0x0080000000 Size 0x003A800000 +// RAM Entry 1 : Base 0x00C0000000 Size 0x0001800000 +// RAM Entry 2 : Base 0x00C3400000 Size 0x003CC00000 +// RAM Entry 3 : Base 0x0100000000 Size 0x0100000000
Adjust DTS so USB runs in host mode. The type-c port is the only supported port (since the others need PCIe). Booting from USB is possible with a powered type-c dock.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi index c3ec4a317f7c..fbe72595f5ac 100644 --- a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi +++ b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi @@ -16,8 +16,13 @@ <1 0x00000000 1 0x00000000>; }; };
+&usb_1_dwc3 { + dr_mode = "host"; + /delete-property/ usb-role-switch; +}; + // RAM Entry 0 : Base 0x0080000000 Size 0x003A800000 // RAM Entry 1 : Base 0x00C0000000 Size 0x0001800000 // RAM Entry 2 : Base 0x00C3400000 Size 0x003CC00000 // RAM Entry 3 : Base 0x0100000000 Size 0x0100000000
This soc doesn't have the generic compatible.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/iommu/qcom-hyp-smmu.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c index 7b646d840dd4..1b5a09bb7b39 100644 --- a/drivers/iommu/qcom-hyp-smmu.c +++ b/drivers/iommu/qcom-hyp-smmu.c @@ -380,8 +380,9 @@ static struct iommu_ops qcom_smmu_ops = { };
static const struct udevice_id qcom_smmu500_ids[] = { { .compatible = "qcom,sdm845-smmu-500" }, + { .compatible = "qcom,sc7280-smmu-500" }, { .compatible = "qcom,smmu-500", }, { /* sentinel */ } };
On 09/08/2024 02:48, Caleb Connolly wrote:
This soc doesn't have the generic compatible.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org
drivers/iommu/qcom-hyp-smmu.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c index 7b646d840dd4..1b5a09bb7b39 100644 --- a/drivers/iommu/qcom-hyp-smmu.c +++ b/drivers/iommu/qcom-hyp-smmu.c @@ -380,8 +380,9 @@ static struct iommu_ops qcom_smmu_ops = { };
static const struct udevice_id qcom_smmu500_ids[] = { { .compatible = "qcom,sdm845-smmu-500" },
- { .compatible = "qcom,sc7280-smmu-500" }, { .compatible = "qcom,smmu-500", }, { /* sentinel */ } };
Reviewed-by: Neil Armstrong neil.armstrong@linaro.org
Enable clocks on SC7280
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 24b71ba7be29..1a079264a554 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -44,8 +44,9 @@ CONFIG_CLK=y CONFIG_CLK_QCOM_APQ8016=y CONFIG_CLK_QCOM_APQ8096=y CONFIG_CLK_QCOM_QCM2290=y CONFIG_CLK_QCOM_QCS404=y +CONFIG_CLK_QCOM_SC7280=y CONFIG_CLK_QCOM_SDM845=y CONFIG_CLK_QCOM_SM6115=y CONFIG_CLK_QCOM_SM8250=y CONFIG_CLK_QCOM_SM8550=y
On 09/08/2024 02:48, Caleb Connolly wrote:
Enable clocks on SC7280
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org
configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 24b71ba7be29..1a079264a554 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -44,8 +44,9 @@ CONFIG_CLK=y CONFIG_CLK_QCOM_APQ8016=y CONFIG_CLK_QCOM_APQ8096=y CONFIG_CLK_QCOM_QCM2290=y CONFIG_CLK_QCOM_QCS404=y +CONFIG_CLK_QCOM_SC7280=y CONFIG_CLK_QCOM_SDM845=y CONFIG_CLK_QCOM_SM6115=y CONFIG_CLK_QCOM_SM8250=y CONFIG_CLK_QCOM_SM8550=y
Reviewed-by: Neil Armstrong neil.armstrong@linaro.org
Introduce a defconfig for the RB3 Gen 2 and other QCM6490 boards with a dedicated uefi partition. These can replace EDK2 entirely with U-Boot.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- configs/qcm6490_defconfig | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/configs/qcm6490_defconfig b/configs/qcm6490_defconfig new file mode 100644 index 000000000000..25413ac9ed5a --- /dev/null +++ b/configs/qcm6490_defconfig @@ -0,0 +1,18 @@ +# Configuration for building U-Boot to be flashed +# to the uefi partition of QCM6490 dev boards with +# the "Linux Embedded" partition layout (which have +# a dedicated "uefi" partition for edk2/U-Boot) + +#include "qcom_defconfig" + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0x994000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 + +# Address where U-Boot will be loaded +CONFIG_TEXT_BASE=0x9fc00000 +CONFIG_REMAKE_ELF=y + +CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs6490-rb3gen2"
The process here is almost identical to the Dragonboard 410c, we've come full circle!
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- doc/board/qualcomm/rb3gen2.rst | 53 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+)
diff --git a/doc/board/qualcomm/rb3gen2.rst b/doc/board/qualcomm/rb3gen2.rst new file mode 100644 index 000000000000..4240606224f5 --- /dev/null +++ b/doc/board/qualcomm/rb3gen2.rst @@ -0,0 +1,53 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Caleb Connolly caleb.connolly@linaro.org + +Qualcomm Robotics RB3 Gen 2 +=========================== + +The RB3 Gen 2 is a development board based on the Qualcomm QCM6490 SoC (a derivative +of SC7280). More information can be found on `Qualcomm's product page`_. + +U-Boot can be used as a replacement for Qualcomm's original EDK2 bootloader by +flashing it directly to the uefi_a (or _b) partition. + +.. _Qualcomm's product page: https://www.qualcomm.com/developer/hardware/rb3-gen-2-development-kit + +Installation +------------ +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``qcm6490``:: + + $ export CROSS_COMPILE=<aarch64 toolchain prefix> + $ make qcm6490_defconfig + $ make -j8 + +This will build ``u-boot.elf`` in the configured output directory. + +Although the RB3 Gen 2 does not have secure boot set up by default, +the firmware still expects firmware ELF images to be "signed". The signature +does not provide any security in this case, but it provides the firmware with +some required metadata. + +To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_:: + + $ qtestsign -v6 aboot -o u-boot.mbn u-boot.elf + +Then install the resulting ``u-boot.mbn`` to the ``uefi_a`` partition +on your device with ``fastboot flash uefi_a u-boot.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +Note that fastboot is not yet supported in U-Boot on this board, as a result, +to flash back the original firmware, or new versoins of the U-Boot, EDL mode +must be used. This can be accessed by pressing the EDL mode button as described +in the Qualcomm Linux documentation. A tool like bkerler's `edl`_ can be used +for flashing with the firehose loader binary appropriate for the board. + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign +.. _edl: https://github.com/bkerler/edl + +Usage +----- + +The USB Type-A ports are connected via a PCIe USB hub, which is not supported yet. +However, the Type-C port can be used with a powered USB dock to connect peripherals +like a USB stick.
participants (2)
-
Caleb Connolly -
Neil Armstrong