From: Ying Zhang b40530@freescale.com

The code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution.

The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled.

Signed-off-by: Ying Zhang b40530@freescale.com --- Change from v10: - No change. Change from v9: - Mofidy drivers/mmc/fsl_esdhc_spl.c, fix checkpatch warnings. Change from v8: - No change. Change from v7: - No change. Change from v6: - Split to the patch "Support booting from SD Card with SPL" and the patch. - "Enable P1022DS to boot from SD Card with SPL". this patch only support. - booting from SD Card with SPL. Change from v5: - Add new symbol CONFIG_SPL_ENV_IMPORT for contain the functionality. - env_import. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from "boot from SD card/SPI flash with SPL".

README | 4 + arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 5 + .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 4 + doc/README.mpc85xx-sd-spi-boot | 81 ++++++++++++ drivers/mmc/Makefile | 3 + drivers/mmc/fsl_esdhc_spl.c | 130 ++++++++++++++++++++ drivers/mmc/mmc.c | 2 + include/fsl_esdhc.h | 1 + spl/Makefile | 3 + 9 files changed, 233 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc85xx-sd-spi-boot create mode 100644 drivers/mmc/fsl_esdhc_spl.c

diff --git a/README b/README index 3918807..e7cca82 100644 --- a/README +++ b/README @@ -3075,6 +3075,10 @@ FIT uImage format: Support for NAND boot using simple NAND drivers that expose the cmd_ctrl() interface.

+ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT + Set for the SPL on PPC mpc8xxx targets, support for + arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary. + CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 08188d7..85ec74b 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -44,6 +44,11 @@ SECTIONS } _edata = .;

+ . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + . = ALIGN(8); __init_begin = .; __init_end = .; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index e958e13..56128a7 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -218,12 +218,16 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, if (dimm_params[i].n_ranks) { if (dimm_params[i].registered_dimm) { temp1 = 1; +#ifndef CONFIG_SPL_BUILD printf("Detected RDIMM %s\n", dimm_params[i].mpart); +#endif } else { temp2 = 1; +#ifndef CONFIG_SPL_BUILD printf("Detected UDIMM %s\n", dimm_params[i].mpart); +#endif } } } diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot new file mode 100644 index 0000000..d5043cc --- /dev/null +++ b/doc/README.mpc85xx-sd-spi-boot @@ -0,0 +1,81 @@ +---------------------------------------- +Booting from On-Chip ROM (eSDHC or eSPI) +---------------------------------------- + +boot_format is a tool to write SD bootable images to a filesystem and build +SD/SPI images to a binary file for writing later. + +When booting from an SD card/MMC, boot_format puts the configuration file and +the RAM-based U-Boot image on the card. +When booting from an EEPROM, boot_format generates a binary image that is used +to boot from this EEPROM. + +Where to get boot_format: +======================== + +you can browse it online at: +http://git.freescale.com/git/cgit.cgi/ppc/sdk/boot-format.git/ + +Building +======== + +Run the following to build this project + + $ make + +Execution +========= + +boot_format runs under a regular Linux machine and requires a super user mode +to run. Execute boot_format as follows. + +For building SD images by writing directly to a file system on SD media: + + $ boot_format $config u-boot.bin -sd $device + +Where $config is the included config.dat file for your platform and $device +is the target block device for the SD media on your computer. + +For build binary images directly a local file: + + $ boot_format $config u-boot.bin -spi $file + +Where $file is the target file. Also keep in mind the u-boot.bin file needs +to be the u-boot built for your particular platform and target media. + +Example: To generate a u-boot.bin for a P1022DS booting from SD, run the +following in the u-boot repository: + + $ make P1022DS_SDCARD + +Configuration Files +=================== + +Below are the configuration files to be used with a particular platform. Keep +in mind that some of these config files are tied to the platforms DDR speed. +Please see the SoC reference manual for more documentation. + +P1022DS config_sram_p1022ds.dat +P2020DS config_sram_p2020ds.dat +P2010DS config_sram_p2020ds.dat +P1020RDB config_ddr2_1g_p1020rdb_533M.dat +P1020RDB config_ddr2_1g_p1020rdb_667M.dat +P2020RDB config_ddr2_1g_p2020rdb_800M.dat +P2020RDB config_ddr2_1g_p2020rdb_667M.dat +P2020RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat +P2010RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat +P1020RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1011RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1010RDB config_ddr3_1gb_p1010rdb_800M.dat +P1014RDB config_ddr3_1gb_p1014rdb_800M.dat +P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1012RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1022DS config_ddr3_2gb_p1022ds.dat +P1013DS config_ddr3_2gb_p1022ds.dat +P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat +P1013RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat +P1025RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat +P1016RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat +P1020UTM config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1020MBG config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +MPC8536DS config_ddr2_512m_mpc8536ds_667M.dat diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 49e5cb9..bedf833 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -32,6 +32,9 @@ COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o COBJS-$(CONFIG_DWMMC) += dw_mmc.o COBJS-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o COBJS-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o +endif

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c new file mode 100644 index 0000000..25a1dff --- /dev/null +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -0,0 +1,130 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <mmc.h> +#include <malloc.h> + +/* + * The environment variables are written to just after the u-boot image + * on SDCard, so we must read the MBR to get the start address and code + * length of the u-boot image, then calculate the address of the env. + */ +#define ESDHC_BOOT_IMAGE_SIZE 0x48 +#define ESDHC_BOOT_IMAGE_ADDR 0x50 +#define MBRDBR_BOOT_SIG_55 0x1fe +#define MBRDBR_BOOT_SIG_AA 0x1ff +#define CONFIG_CFG_DATA_SECTOR 0 + +/* + * The main entry for mmc booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from mmc into SDRAM and starts it from there. + */ + +void __noreturn mmc_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + uint blk_start, blk_cnt, err; + u32 blklen; + uchar *tmp_buf; + uchar val; + uint i, byte_num; + u32 offset, code_len; + struct mmc *mmc; + + mmc = find_mmc_device(0); + if (!mmc) { + puts("spl: mmc device not found!!\n"); + hang(); + } + + blklen = mmc->read_bl_len; + tmp_buf = malloc(blklen); + if (!tmp_buf) { + puts("spl: malloc memory failed!!\n"); + hang(); + } + memset(tmp_buf, 0, blklen); + + /* + * Read source addr from sd card + */ + err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); + if (err != 1) { + puts("spl: mmc read failed!!\n"); + free(tmp_buf); + hang(); + } + + val = *(tmp_buf + MBRDBR_BOOT_SIG_55); + if (0x55 != val) { + puts("spl: mmc signature is not valid!!\n"); + free(tmp_buf); + hang(); + } + val = *(tmp_buf + MBRDBR_BOOT_SIG_AA); + if (0xAA != val) { + puts("spl: mmc signature is not valid!!\n"); + free(tmp_buf); + hang(); + } + + byte_num = 4; + offset = 0; + for (i = 0; i < byte_num; i++) { + val = *(tmp_buf + ESDHC_BOOT_IMAGE_ADDR + i); + offset = (offset << 8) + val; + } + offset += CONFIG_SYS_MMC_U_BOOT_OFFS; + /* Get the code size from offset 0x48 */ + byte_num = 4; + code_len = 0; + for (i = 0; i < byte_num; i++) { + val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i); + code_len = (code_len << 8) + val; + } + code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS; + /* + * Load U-Boot image from mmc into RAM + */ + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; + err = mmc->block_dev.block_read(0, blk_start, blk_cnt, + (uchar *)CONFIG_SYS_MMC_U_BOOT_DST); + if (err != blk_cnt) { + puts("spl: mmc read failed!!\n"); + free(tmp_buf); + hang(); + } + + /* + * Clean d-cache and invalidate i-cache, to + * make sure that no stale data is executed. + */ + flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE); + + /* + * Jump to U-Boot image + */ + uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START; + (*uboot)(); +} diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 4da8db9..5502675 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1483,7 +1483,9 @@ int mmc_initialize(bd_t *bis) if (board_mmc_init(bis) < 0) cpu_mmc_init(bis);

+#ifndef CONFIG_SPL_BUILD print_mmc_devices(','); +#endif

do_preinit(); return 0; diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 2c97398..89bcbd1 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -182,5 +182,6 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd); static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {} #endif /* CONFIG_FSL_ESDHC */ +void __noreturn mmc_boot(void);

#endif /* __FSL_ESDHC_H__ */ diff --git a/spl/Makefile b/spl/Makefile index 43db01f..383926f 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -50,6 +50,9 @@ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o endif ifeq ($(CPU),mpc85xx) LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o +ifdef CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o +endif endif ifeq ($(CPU),mpc86xx) LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o

From: Ying Zhang b40530@freescale.com

Enable p1022ds to start from eSDHC with SPL.

Signed-off-by: Ying Zhang b40530@freescale.com --- Change from v10: - Fix the warning from spl.c. Change from v9: - Mofidy board/freescale/p1022ds/spl.c, fix checkpatch warnings. Change from v8: - No change. Change from v7: - No change. Change from v6: - Split from the patch "powerpc/p1022ds: boot from SD Card with SPL". - this patch only enables p1022ds to boot from SD Card with SPL. Change from v5: - No change. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - No change.

README | 4 ++ board/freescale/common/Makefile | 2 - board/freescale/p1022ds/Makefile | 3 + board/freescale/p1022ds/spl.c | 110 ++++++++++++++++++++++++++++++++++++++ board/freescale/p1022ds/tlb.c | 23 +++++--- include/configs/P1022DS.h | 54 ++++++++++++++++--- 6 files changed, 179 insertions(+), 17 deletions(-) create mode 100644 board/freescale/p1022ds/spl.c

diff --git a/README b/README index e7cca82..23222d4 100644 --- a/README +++ b/README @@ -3079,6 +3079,10 @@ FIT uImage format: Set for the SPL on PPC mpc8xxx targets, support for arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.

+ CONFIG_SPL_COMMON_INIT_DDR + Set for common ddr init with serial presence detect in + SPL binary. + CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 457d1ad..f9550c4 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -45,9 +45,7 @@ COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o

COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o -ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_P1022DS) += ics307_clk.o -endif COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index cfc05f7..3bc4f43 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -21,6 +21,9 @@ ifdef MINIMAL COBJS-y += spl_minimal.o tlb.o law.o

else +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o +endif COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c new file mode 100644 index 0000000..71a0f85 --- /dev/null +++ b/board/freescale/p1022ds/spl.c @@ -0,0 +1,110 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <malloc.h> +#include <mmc.h> +#include <nand.h> +#include <i2c.h> +#include "../common/ngpixis.h" +#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +ulong get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, sys_clk, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#endif + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + env_init(); +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + /* relocate environment function pointers etc. */ + env_relocate(); + + i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + gd->ram_size = initdram(0); + puts("Second program loader running in sram...\n"); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#endif +} diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index 2eef6ad..e7ae2e2 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -71,25 +71,32 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1),

-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1), + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_1G, 1), + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1G, 1), #endif

#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16K, 1), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16K, 1), #endif

+#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) +#endif };

int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 5ca7f07..6db0c27 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -16,11 +16,32 @@ #endif

#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif

#ifdef CONFIG_SPIFLASH @@ -291,6 +312,24 @@ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)

/* + * Config the L2 Cache as L2 SRAM +*/ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#endif +#endif + +/* * Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -298,7 +337,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif

@@ -529,8 +568,9 @@ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_RAMBOOT_SDCARD) +#elif defined(CONFIG_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_NAND)

From: Ying Zhang b40530@freescale.com

This patch introduces SPL to enable a loader stub that being loaded by the code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution.

The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled.

Signed-off-by: Ying Zhang b40530@freescale.com --- Change from v10: - No change. Change from v9: - Modify drivers/mtd/spi/fsl_espi_spl.c, fix checkpatch warnings. Change from v8: - No change. Change from v7: - No change. Change from v6: - No change. Change from v5: - Split from "powerpc/p1022ds: boot from spi flash with SPL". - this patch add the capability starting from eSPI with SPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from "boot from SD card/SPI flash with SPL".

drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/fsl_espi_spl.c | 77 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi_flash.c | 2 + 3 files changed, 80 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spi/fsl_espi_spl.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index e537fcf..191138a 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -11,6 +11,7 @@ LIB := $(obj)libspi_flash.o

ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o +COBJS-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o endif

COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c new file mode 100644 index 0000000..9e216a6 --- /dev/null +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -0,0 +1,77 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <spi_flash.h> +#include <malloc.h> + +#define ESPI_BOOT_IMAGE_SIZE 0x48 +#define ESPI_BOOT_IMAGE_ADDR 0x50 +#define CONFIG_CFG_DATA_SECTOR 0 + +/* + * The main entry for SPI booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from SPI into SDRAM and starts it from there. + */ +void spi_boot(void) +{ + void (*uboot)(void) __noreturn; + u32 offset, code_len; + unsigned char *buf = NULL; + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (flash == NULL) { + puts("\nspi_flash_probe failed"); + hang(); + } + + /* + * Load U-Boot image from SPI flash into RAM + */ + buf = malloc(flash->page_size); + if (buf == NULL) { + puts("\nmalloc failed"); + hang(); + } + memset(buf, 0, flash->page_size); + + spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR, + flash->page_size, (void *)buf); + offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR); + /* Skip spl code */ + offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + /* Get the code size from offset 0x48 */ + code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); + /* Skip spl code */ + code_len = code_len - CONFIG_SPL_MAX_SIZE; + /* copy code to DDR */ + spi_flash_read(flash, offset, code_len, + (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST); + /* + * Jump to U-Boot image + */ + flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len); + uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START; + (*uboot)(); +} diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 9814395..5d5055f 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -555,12 +555,14 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, goto err_manufacturer_probe; } #endif +#ifndef CONFIG_SPL_BUILD printf("SF: Detected %s with page size ", flash->name); print_size(flash->sector_size, ", total "); print_size(flash->size, ""); if (flash->memory_map) printf(", mapped at %p", flash->memory_map); puts("\n"); +#endif #ifndef CONFIG_SPI_FLASH_BAR if (flash->size > SPI_FLASH_16MB_BOUN) { puts("SF: Warning - Only lower 16MiB accessible,");

From: Ying Zhang b40530@freescale.com

Enable p1022ds to start from eSPI with SPL.

Signed-off-by: Ying Zhang b40530@freescale.com --- Change from v10: - No change. Change from v9: - No change. Change from v8: - No change. Change from v7: - No change. Change from v6: - No longer changes the header file included by the file. - "board/freescale/p1022ds/spl.c". Change from v5: - Split from "powerpc/p1022ds: boot from spi flash with SPL". - this patch enable P1022DS to start from eSPI with SPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from "boot from SD card/SPI flash with SPL".

board/freescale/p1022ds/spl.c | 10 ++++++++++ include/configs/P1022DS.h | 36 +++++++++++++++++++++++++++++------- 2 files changed, 39 insertions(+), 7 deletions(-)

diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 71a0f85..7e89de2 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -27,6 +27,7 @@ #include <i2c.h> #include "../common/ngpixis.h" #include <fsl_esdhc.h> +#include <spi_flash.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -53,6 +54,11 @@ void board_init_f(ulong bootflag) setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);

+#ifdef CONFIG_SPL_SPI_BOOT + /* Enable the SPI */ + clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); +#endif + /* Read back the register to synchronize the write. */ in_be32(&gur->pmuxcr);

@@ -66,6 +72,8 @@ void board_init_f(ulong bootflag) bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); #endif

/* copy code to RAM and jump to it - this should not return */ @@ -106,5 +114,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)

#ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); #endif } diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 6db0c27..762b136 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -45,11 +45,33 @@ #endif

#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif

#define CONFIG_NAND_FSL_ELBC @@ -315,7 +337,7 @@ * Config the L2 Cache as L2 SRAM */ #if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) @@ -559,7 +581,7 @@ /* * Environment */ -#ifdef CONFIG_RAMBOOT_SPIFLASH +#ifdef CONFIG_SPIFLASH #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0

From: Ying Zhang b40530@freescale.com

Due to the nand SPL on some board(e.g. P1022DS)has a size limit, it can not be more than 4K. So, the SPL cannot initialize the DDR with the SPD code. This patch introduces TPL to enable a loader stub that is loaded by the code from the SPL. It initializes the DDR with the SPD or other operations.

The TPL's size is sizeable, the maximum size is decided by the memory's size that TPL runs. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are three stage uboot images: * spl_boot, * tpl_boot, * final uboot image

This patch is on top of the patch: SPL: Makefile: Build a separate autoconf.mk for SPL

Signed-off-by: Ying Zhang b40530@freescale.com --- Change from v10: - No change. Change from v9: - Move the part revision to the other patch. for example:fsl_elbc_spl.c. - Modify the Makefile. - Modify doc/README.TPL, fix checkpatch warnings. Change from v8: - Modify the doc/README.TPL. - Modify the Makefile. - Modify the drivers/mtd/nand/fsl_elbc_spl.c. - Modify the spl/Makefile. Change from v7: - Modify the doc/README.TPL - Modify the spl/Makefile. Change from v6: - Modify the description of the patch. - Add the separate the autoconf.mk for TPL. - Delete the file tpl/Makefile and the directory tpl. - Reuse the spl/Makefie in TPL. Change from v5: - Use ifdef to define "nand_load_image" to non-static for non-SPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from "powerpc/p1022ds: nand: introduce the TPL based on the SPL".

Makefile | 50 ++++++++++++++++++++++++++++++++++++++++++-------- README | 16 ++++++++++++++++ config.mk | 30 ++++++++++++++++++++++++++++-- doc/README.TPL | 45 +++++++++++++++++++++++++++++++++++++++++++++ spl/Makefile | 20 ++++++++++++++++---- 5 files changed, 147 insertions(+), 14 deletions(-) create mode 100644 doc/README.TPL

diff --git a/Makefile b/Makefile index 75df06a..7a8897d 100644 --- a/Makefile +++ b/Makefile @@ -102,10 +102,11 @@ endif # ifneq ($(BUILD_DIR),)

OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR)) SPLTREE := $(OBJTREE)/spl +TPLTREE := $(OBJTREE)/tpl SRCTREE := $(CURDIR) TOPDIR := $(SRCTREE) LNDIR := $(OBJTREE) -export TOPDIR SRCTREE OBJTREE SPLTREE +export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE

MKCONFIG := $(SRCTREE)/mkconfig export MKCONFIG @@ -397,6 +398,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin +ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin ifneq ($(CONFIG_SPL_TARGET),) ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET)) @@ -475,13 +477,25 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@

+# $@ is output, $(1) and $(2) are inputs, $(3) is padded intermediate, +# $(4) is pad-to +SPL_PAD_APPEND = \ + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(4) -I binary -O binary \ + $(1) $(obj)$(3); \ + cat $(obj)$(3) $(obj)$(2) > $@; \ + rm $(obj)$(3)

+ifdef CONFIG_TPL +SPL_PAYLOAD := $(obj)tpl/u-boot-with-tpl.bin +else +SPL_PAYLOAD := $(obj)u-boot.bin +endif

-$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ - -I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin - cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ - rm $(obj)spl/u-boot-spl-pad.bin +$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(SPL_PAYLOAD) + $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO)) + +$(obj)tpl/u-boot-with-tpl.bin: $(obj)tpl/u-boot-tpl.bin $(obj)u-boot.bin + $(call SPL_PAD_APPEND,$<,u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO))

$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \ @@ -607,6 +621,9 @@ $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all

+$(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend + $(MAKE) -C spl all CONFIG_TPL_BUILD=y + updater: $(MAKE) -C tools/updater all

@@ -614,6 +631,7 @@ updater: # parallel sub-makes creating .depend files simultaneously. depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \ $(obj)include/spl-autoconf.mk \ + $(obj)include/tpl-autoconf.mk \ $(obj)include/autoconf.mk \ $(obj)include/generated/generic-asm-offsets.h \ $(obj)include/generated/asm-offsets.h @@ -696,6 +714,15 @@ $(obj)include/autoconf.mk: $(obj)include/config.h mv $@.tmp $@

# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL) +$(obj)include/tpl-autoconf.mk: $(obj)include/config.h + @$(XECHO) Generating $@ ; \ + set -e ; \ + : Extract the config macros ; \ + $(CPP) $(CFLAGS) -DCONFIG_TPL_BUILD -DCONFIG_SPL_BUILD\ + -DDO_DEPS_ONLY -dM include/common.h | \ + sed -n -f tools/scripts/define2mk.sed > $@.tmp && \ + mv $@.tmp $@ + $(obj)include/spl-autoconf.mk: $(obj)include/config.h @$(XECHO) Generating $@ ; \ set -e ; \ @@ -706,12 +733,14 @@ $(obj)include/spl-autoconf.mk: $(obj)include/config.h

$(obj)include/generated/generic-asm-offsets.h: $(obj)include/autoconf.mk.dep \ $(obj)include/spl-autoconf.mk \ + $(obj)include/tpl-autoconf.mk \ $(obj)lib/asm-offsets.s @$(XECHO) Generating $@ tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@

$(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \ $(obj)include/spl-autoconf.mk \ + $(obj)include/tpl-autoconf.mk \ $(src)lib/asm-offsets.c @mkdir -p $(obj)lib $(CC) -DDO_DEPS_ONLY \ @@ -720,12 +749,14 @@ $(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \

$(obj)include/generated/asm-offsets.h: $(obj)include/autoconf.mk.dep \ $(obj)include/spl-autoconf.mk \ + $(obj)include/tpl-autoconf.mk \ $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s @$(XECHO) Generating $@ tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@

$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/autoconf.mk.dep \ - $(obj)include/spl-autoconf.mk + $(obj)include/spl-autoconf.mk \ + $(obj)include/tpl-autoconf.mk @mkdir -p $(obj)$(CPUDIR)/$(SOC) if [ -f $(src)$(CPUDIR)/$(SOC)/asm-offsets.c ];then \ $(CC) -DDO_DEPS_ONLY \ @@ -798,7 +829,8 @@ unconfig: @rm -f $(obj)include/config.h $(obj)include/config.mk \ $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \ $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep \ - $(obj)include/spl-autoconf.mk + $(obj)include/spl-autoconf.mk \ + $(obj)include/tpl-autoconf.mk

%_config:: unconfig @$(MKCONFIG) -A $(@:_config=) @@ -884,6 +916,8 @@ clobber: tidy @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} @rm -f $(obj)spl/u-boot-spl.lds + @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map} + @rm -f $(obj)tpl/u-boot-spl.lds @rm -f $(obj)MLO MLO.byteswap @rm -f $(obj)SPL @rm -f $(obj)tools/xway-swap-bytes diff --git a/README b/README index 23222d4..03fb7fd 100644 --- a/README +++ b/README @@ -3152,6 +3152,17 @@ FIT uImage format: option to re-enable it. This will affect the output of the bootm command when booting a FIT image.

+- TPL framework + CONFIG_TPL + Enable building of TPL globally. + + CONFIG_TPL_PAD_TO + Image offset to which the TPL should be padded before appending + the TPL payload. By default, this is defined as + CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined. + CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL + payload without any padding, or >= CONFIG_SPL_MAX_SIZE. + Modem Support: --------------

@@ -4189,6 +4200,11 @@ Low Level (hardware related) configuration options: that is executed before the actual U-Boot. E.g. when compiling a NAND SPL.

+- CONFIG_TPL_BUILD + Modifies the behaviour of start.S when compiling a loader + that is executed after the SPL and before the actual U-Boot. + It is loaded by the SPL. + - CONFIG_SYS_MPC85XX_NO_RESETVEC Only for 85xx systems. If this variable is specified, the section .resetvec is not kept and the section .bootpg is placed in the diff --git a/config.mk b/config.mk index 54e99f4..b3ecaa7 100644 --- a/config.mk +++ b/config.mk @@ -13,6 +13,12 @@ SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \

export SHELL

+ifeq ($(CONFIG_TPL_BUILD),y) +SPL_BIN := u-boot-tpl +else +SPL_BIN := u-boot-spl +endif + ifeq ($(CURDIR),$(SRCTREE)) dir := else @@ -22,7 +28,11 @@ endif ifneq ($(OBJTREE),$(SRCTREE)) # Create object files for SPL in a separate directory ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_TPL_BUILD),y) +obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/) +else obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) +endif else obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) endif @@ -32,8 +42,12 @@ $(shell mkdir -p $(obj)) else # Create object files for SPL in a separate directory ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_TPL_BUILD),y) +obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/) +else obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)

+endif $(shell mkdir -p $(obj)) else obj := @@ -145,6 +159,10 @@ CHECK = sparse #########################################################################

# Load generated board configuration +ifeq ($(CONFIG_TPL_BUILD),y) +# Include TPL autoconf +sinclude $(OBJTREE)/include/tpl-autoconf.mk +else ifeq ($(CONFIG_SPL_BUILD),y) # Include SPL autoconf sinclude $(OBJTREE)/include/spl-autoconf.mk @@ -152,6 +170,7 @@ else # Include normal autoconf sinclude $(OBJTREE)/include/autoconf.mk endif +endif sinclude $(OBJTREE)/include/config.mk

# Some architecture config.mk files need to know what CPUDIR is set to, @@ -221,12 +240,19 @@ ifneq ($(CONFIG_SPL_PAD_TO),) CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO) endif

+ifneq ($(CONFIG_TPL_PAD_TO),) +CPPFLAGS += -DCONFIG_TPL_PAD_TO=$(CONFIG_TPL_PAD_TO) +endif + ifneq ($(CONFIG_UBOOT_PAD_TO),) CPPFLAGS += -DCONFIG_UBOOT_PAD_TO=$(CONFIG_UBOOT_PAD_TO) endif

ifeq ($(CONFIG_SPL_BUILD),y) CPPFLAGS += -DCONFIG_SPL_BUILD +ifeq ($(CONFIG_TPL_BUILD),y) +CPPFLAGS += -DCONFIG_TPL_BUILD +endif endif

# Does this architecture support generic board init? @@ -298,9 +324,9 @@ ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) endif

-LDFLAGS_u-boot-spl += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL) +LDFLAGS_$(SPL_BIN) += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SPL_TEXT_BASE),) -LDFLAGS_u-boot-spl += -Ttext $(CONFIG_SPL_TEXT_BASE) +LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif

# Linus' kernel sanity checking tool diff --git a/doc/README.TPL b/doc/README.TPL new file mode 100644 index 0000000..1df03b9 --- /dev/null +++ b/doc/README.TPL @@ -0,0 +1,45 @@ +Generic TPL framework +===================== + +Overview +-------- + +TPL---Third Program Loader. + +Due to the SPL on some boards(powerpc mpc85xx) has a size limit and cannot +be compatible with all the external device(e.g. DDR). So add a tertiary +program loader (TPL) to enable a loader stub loaded by the code from the +SPL. It loads the final uboot image into DDR, then jump to it to begin +execution. Now, only the powerpc mpc85xx has this requirement and will +implemente it. + +Keep consistent with SPL, with this framework almost all source files for a +board can be reused. No code duplication or symlinking is necessary anymore. + +How it works +------------ + +There has been a directory TOPDIR/spl which contains only a Makefile. The +Makefile is shared by SPL and TPL. + +The object files are built separately for SPL/TPL and placed in the +directory spl/tpl. The final binaries which are generated are +u-boot-{spl|tpl}, u-boot-{spl|tpl}.bin and u-boot-{spl|tpl}.map. + +During the TPL build a variable named CONFIG_TPL_BUILD is exported in the +make environment and also appended to CPPFLAGS with -DCONFIG_TPL_BUILD. + +The SPL options are shared by SPL and TPL, the board config file should +determine which SPL options to choose based on whether CONFIG_TPL_BUILD +is set. Source files can be compiled for TPL with options choosed in the +board config file. + +For example: + +spl/Makefile: +LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o + +CONFIG_SPL_LIBCOMMON_SUPPORT is defined in board config file: +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#endif diff --git a/spl/Makefile b/spl/Makefile index 383926f..599f9c9 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -17,10 +17,22 @@ CONFIG_SPL_BUILD := y export CONFIG_SPL_BUILD

+ifeq ($(CONFIG_TPL_BUILD),y) +export CONFIG_TPL_BUILD +SPL_BIN := u-boot-tpl +else +SPL_BIN := u-boot-spl +endif + include $(TOPDIR)/config.mk

# We want the final binaries in this directory +ifeq ($(CONFIG_TPL_BUILD),y) +obj := $(OBJTREE)/tpl/ +SPLTREE := $(TPLTREE) +else obj := $(OBJTREE)/spl/ +endif

HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(SRCTREE)/board/$(VENDOR)/common/Makefile),y,n)

@@ -161,7 +173,7 @@ $(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin $(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@

-ALL-y += $(obj)u-boot-spl.bin +ALL-y += $(obj)$(SPL_BIN).bin

ifdef CONFIG_SAMSUNG ALL-y += $(obj)$(BOARD)-spl.bin @@ -175,15 +187,15 @@ $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin $(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin endif

-$(obj)u-boot-spl.bin: $(obj)u-boot-spl +$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@

GEN_UBOOT = \ cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ - -Map u-boot-spl.map -o u-boot-spl + -Map $(SPL_BIN).map -o $(SPL_BIN)

-$(obj)u-boot-spl: depend $(START) $(LIBS) $(obj)u-boot-spl.lds +$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds $(GEN_UBOOT)

$(START): depend

From: Ying Zhang b40530@freescale.com

TPL is introduced in the patch "NAND: TPL : introduce the TPL based on the SPL", here enable TPL for p1022ds nand boot.

Signed-off-by: Ying Zhang b40530@freescale.com --- Change from v10: - No change. Change from v9: - Modify drivers/mtd/nand/Makefile. - Modify drivers/mtd/nand/fsl_elbc_spl.c. - Modify include/configs/P1022DS.h, fix checkpatch warnings. Change from v8: - Add new symbol CONFIG_SPL_ENV_IN_NAND. Change from v7: - No change. Change from v6: - Delete the file "board/freescale/p1022ds/tpl.c". - Reuse the file "board/freescale/p1022ds/spl.c" in the TPL. Change from v5: - Change functionality nand_load_image to nand_load, it is called in TPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from "powerpc/p1022ds: nand: introduce the TPL based on the SPL".

board/freescale/p1022ds/spl.c | 16 +++++++ board/freescale/p1022ds/spl_minimal.c | 53 ++-------------------- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsl_elbc_spl.c | 27 +++++++++--- include/configs/P1022DS.h | 77 ++++++++++++++++++++++++++------- 5 files changed, 103 insertions(+), 71 deletions(-)

diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 7e89de2..358b2e3 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -100,21 +100,37 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); +#ifndef CONFIG_SPL_NAND_BOOT env_init(); +#endif #ifdef CONFIG_SPL_MMC_BOOT mmc_initialize(bd); #endif /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else env_relocate(); +#endif

i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("Tertiary program loader running in sram..."); +#else puts("Second program loader running in sram...\n"); +#endif

#ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); #endif } diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c index d150d95..8b34396 100644 --- a/board/freescale/p1022ds/spl_minimal.c +++ b/board/freescale/p1022ds/spl_minimal.c @@ -12,51 +12,6 @@ #include <asm/fsl_ddr_sdram.h>

-/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -void sdram_init(void) -{ - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); -#endif - __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - - __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); - - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, - &ddr->sdram_cfg); - - in_be32(&ddr->sdram_cfg); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - in_be32(&ddr->sdram_cfg); - - set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); -} - const static u32 sysclk_tbl[] = { 66666000, 7499900, 83332500, 8999900, 99999000, 11111000, 12499800, 13333200 @@ -68,6 +23,10 @@ void board_init_f(ulong bootflag) u32 plat_ratio, sys_clk, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;

+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif /* for FPGA */ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); @@ -83,9 +42,6 @@ void board_init_f(ulong bootflag)

puts("\nNAND boot... ");

- /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -96,6 +52,7 @@ void board_init_f(ulong bootflag)

void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); }

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index e27e0b7..366dee6 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -23,6 +23,7 @@ COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o +COBJS-$(CONFIG_SPL_NAND_INIT) += nand.o

else # not spl

diff --git a/drivers/mtd/nand/fsl_elbc_spl.c b/drivers/mtd/nand/fsl_elbc_spl.c index 7e5599a..a7476b4 100644 --- a/drivers/mtd/nand/fsl_elbc_spl.c +++ b/drivers/mtd/nand/fsl_elbc_spl.c @@ -34,7 +34,11 @@ static void nand_wait(void) } }

+#ifdef CONFIG_TPL_BUILD +int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) +#else static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) +#endif { fsl_lbc_t *regs = LBC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; @@ -114,6 +118,15 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) }

/* + * Defines a static function nand_load_image() here, because non-static makes + * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes) + */ +#ifndef CONFIG_TPL_BUILD +#define nand_spl_load_image(offs, uboot_size, vdst) \ + nand_load_image(offs, uboot_size, vdst) +#endif + +/* * The main entry for NAND booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image * from NAND into SDRAM and starts it from there. @@ -124,17 +137,17 @@ void nand_boot(void) /* * Load U-Boot image from NAND into RAM */ - nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (void *)CONFIG_SYS_NAND_U_BOOT_DST);

#ifdef CONFIG_NAND_ENV_DST - nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (void *)CONFIG_NAND_ENV_DST); + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (void *)CONFIG_NAND_ENV_DST);

#ifdef CONFIG_ENV_OFFSET_REDUND - nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, - (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); #endif #endif

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 762b136..edece1f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -78,22 +78,43 @@

#ifdef CONFIG_NAND #define CONFIG_SPL +#define CONFIG_TPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SYS_TEXT_BASE 0x00201000 -#define CONFIG_SPL_TEXT_BASE 0xfffff000 -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 4096 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif

/* High Level Configuration Options */ @@ -267,11 +288,11 @@ #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif

-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE

/* NAND flash config */ @@ -348,6 +369,25 @@ #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif #endif #endif

@@ -596,9 +636,14 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_NAND) -#define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (1024 * 1024) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */