[U-Boot] [PATCH 0/4] sunxi: Improve the SinA33 support
Hi all,
The SinA33 board is based on an Allwinner A33 SoC and features an external (and optional) LCD display and a 4GB Toshida eMMC.
This eMMC wasn't recognized by default in U-boot because it was failing to switch in high speed mode at the first attempt.
The first three patches are to enable the eMMC, the last one to enable the LCD.
Let me know what you think, Maxime
Maxime Ripard (4): mmc: Retry the switch command mmc: sunxi: Enable 8bits bus width for sun8i sunxi: sina33: Enable the eMMC sunxi: sina33: Enable the LCD
configs/Sinlinx_SinA33_defconfig | 5 +++++ drivers/mmc/mmc.c | 15 +++++++++++---- drivers/mmc/sunxi_mmc.c | 2 +- 3 files changed, 17 insertions(+), 5 deletions(-)
base-commit: d8bdfc80da39211d95f10d24e79f2e867305f71b
Some eMMC will fail at the first switch, but would succeed in a subsequent one.
Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com --- drivers/mmc/mmc.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 4380c7c195a6..d6b7e4f510c9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -494,6 +494,7 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) { struct mmc_cmd cmd; int timeout = 1000; + int retries = 3; int ret;
cmd.cmdidx = MMC_CMD_SWITCH; @@ -502,11 +503,17 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) (index << 16) | (value << 8);
- ret = mmc_send_cmd(mmc, &cmd, NULL); + while (retries > 0) { + ret = mmc_send_cmd(mmc, &cmd, NULL);
- /* Waiting for the ready status */ - if (!ret) - ret = mmc_send_status(mmc, timeout); + /* Waiting for the ready status */ + if (!ret) { + ret = mmc_send_status(mmc, timeout); + return ret; + } + + retries--; + }
return ret;
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
Some eMMC will fail at the first switch, but would succeed in a subsequent one.
Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Pantelis or Tom, can you pick this up please ?
Regards,
Hans
drivers/mmc/mmc.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 4380c7c195a6..d6b7e4f510c9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -494,6 +494,7 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) { struct mmc_cmd cmd; int timeout = 1000;
int retries = 3; int ret;
cmd.cmdidx = MMC_CMD_SWITCH;
@@ -502,11 +503,17 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) (index << 16) | (value << 8);
- ret = mmc_send_cmd(mmc, &cmd, NULL);
- while (retries > 0) {
ret = mmc_send_cmd(mmc, &cmd, NULL);
- /* Waiting for the ready status */
- if (!ret)
ret = mmc_send_status(mmc, timeout);
/* Waiting for the ready status */if (!ret) {ret = mmc_send_status(mmc, timeout);return ret;}retries--;}
return ret;
On Sun, Nov 13, 2016 at 07:50:53PM +0100, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
Some eMMC will fail at the first switch, but would succeed in a subsequent one.
Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Reviewed-by: Tom Rini trini@konsulko.com
Pantelis or Tom, can you pick this up please ?
Want to just pick it up with the rest of the series in the sunxi tree?
On 11/14/2016 07:50 AM, Tom Rini wrote:
On Sun, Nov 13, 2016 at 07:50:53PM +0100, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
Some eMMC will fail at the first switch, but would succeed in a subsequent one.
Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Reviewed-by: Tom Rini trini@konsulko.com
Pantelis or Tom, can you pick this up please ?
Want to just pick it up with the rest of the series in the sunxi tree?
Sorry for late..If you are ok, i will pick these on today. If you already picked this..let me know, plz.
Best Regards, Jaehoon Chung
Hi,
On 14-11-16 01:34, Jaehoon Chung wrote:
On 11/14/2016 07:50 AM, Tom Rini wrote:
On Sun, Nov 13, 2016 at 07:50:53PM +0100, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
Some eMMC will fail at the first switch, but would succeed in a subsequent one.
Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Reviewed-by: Tom Rini trini@konsulko.com
Pantelis or Tom, can you pick this up please ?
Want to just pick it up with the rest of the series in the sunxi tree?
Sorry for late..If you are ok, i will pick these on today.
Go ahead and pick these up please.
If you already picked this..let me know, plz.
Regards,
Hans
On 11/14/2016 06:56 PM, Hans de Goede wrote:
Hi,
On 14-11-16 01:34, Jaehoon Chung wrote:
On 11/14/2016 07:50 AM, Tom Rini wrote:
On Sun, Nov 13, 2016 at 07:50:53PM +0100, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
Some eMMC will fail at the first switch, but would succeed in a subsequent one.
Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Reviewed-by: Tom Rini trini@konsulko.com
Pantelis or Tom, can you pick this up please ?
Want to just pick it up with the rest of the series in the sunxi tree?
Sorry for late..If you are ok, i will pick these on today.
Go ahead and pick these up please.
Ok. I will pick these series.
Thanks!
Best Regards, Jaehoon Chung
If you already picked this..let me know, plz.
Regards,
Hans
On 11/14/2016 03:50 AM, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
Some eMMC will fail at the first switch, but would succeed in a subsequent one.
Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Pantelis or Tom, can you pick this up please ?
Applied on u-boot-mmc. Thanks!
Best Regards, Jaehoon Chung
Regards,
Hans
drivers/mmc/mmc.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 4380c7c195a6..d6b7e4f510c9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -494,6 +494,7 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) { struct mmc_cmd cmd; int timeout = 1000;
int retries = 3; int ret;
cmd.cmdidx = MMC_CMD_SWITCH;
@@ -502,11 +503,17 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) (index << 16) | (value << 8);
- ret = mmc_send_cmd(mmc, &cmd, NULL);
- while (retries > 0) {
ret = mmc_send_cmd(mmc, &cmd, NULL);
- /* Waiting for the ready status */
- if (!ret)
ret = mmc_send_status(mmc, timeout);
/* Waiting for the ready status */if (!ret) {ret = mmc_send_status(mmc, timeout);return ret;}retries--;}
return ret;
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com --- drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 6953accce123..b8716c93cb06 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT; -#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) if (sdc_no == 2) cfg->host_caps = MMC_MODE_8BIT; #endif
On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 6953accce123..b8716c93cb06 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT;-#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
8 come before 50. :)
Otherwise,
Reviewed-by: Chen-Yu Tsai wens@csie.org
if (sdc_no == 2) cfg->host_caps = MMC_MODE_8BIT;#endif
git-series 0.8.11
On Sat, Nov 05, 2016 at 09:34:25AM +0800, Chen-Yu Tsai wrote:
On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 6953accce123..b8716c93cb06 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT;-#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
8 come before 50. :)
But 5 comes before 8, and 0 before i :)
Otherwise,
Reviewed-by: Chen-Yu Tsai wens@csie.org
Thanks, Maxime
On Mon, Nov 7, 2016 at 1:15 AM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sat, Nov 05, 2016 at 09:34:25AM +0800, Chen-Yu Tsai wrote:
On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 6953accce123..b8716c93cb06 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT;-#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
8 come before 50. :)
But 5 comes before 8, and 0 before i :)
Indeed, though 8 and 50 are akin to a generation number, so it makes sense to sort them in natural order. :)
ChenYu
Otherwise,
Reviewed-by: Chen-Yu Tsai wens@csie.org
Thanks, Maxime
-- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
1;4600;0c On Mon, Nov 07, 2016 at 09:53:00AM +0800, Chen-Yu Tsai wrote:
On Mon, Nov 7, 2016 at 1:15 AM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sat, Nov 05, 2016 at 09:34:25AM +0800, Chen-Yu Tsai wrote:
On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 6953accce123..b8716c93cb06 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT;-#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
8 come before 50. :)
But 5 comes before 8, and 0 before i :)
Indeed, though 8 and 50 are akin to a generation number, so it makes sense to sort them in natural order. :)
I know, but it was one of the comments I had in Linux, and we used that ordering there. And we probably want to be consistent, but I don't really care.
Maxime
On Mon, Nov 7, 2016 at 4:39 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
1;4600;0c On Mon, Nov 07, 2016 at 09:53:00AM +0800, Chen-Yu Tsai wrote:
On Mon, Nov 7, 2016 at 1:15 AM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sat, Nov 05, 2016 at 09:34:25AM +0800, Chen-Yu Tsai wrote:
On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 6953accce123..b8716c93cb06 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT;-#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
8 come before 50. :)
But 5 comes before 8, and 0 before i :)
Indeed, though 8 and 50 are akin to a generation number, so it makes sense to sort them in natural order. :)
I know, but it was one of the comments I had in Linux, and we used that ordering there. And we probably want to be consistent, but I don't really care.
I see we have dictionary order in the ccu driver, natural order in pinctrl/sunxi/Kconfig, and ordered by SoC name (Axx) in pinctrl/sunxi/Makefile.
Anyway, no point in bikeshedding over this. Hans, please pick up this patch as is with my Reviewed-by, unless you have other concerns. :)
ChenYu
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Regards,
Hans
drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 6953accce123..b8716c93cb06 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT; -#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) if (sdc_no == 2) cfg->host_caps = MMC_MODE_8BIT; #endif
On 11/14/2016 03:51 AM, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Applied on u-boot-mmc. Thanks!
Best Regards, Jaehoon Chung
Regards,
Hans
drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 6953accce123..b8716c93cb06 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT;-#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) if (sdc_no == 2) cfg->host_caps = MMC_MODE_8BIT; #endif
The SinA33 has an 4GB Toshiba eMMC connected to the MMC2 controller. Enable it.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com --- configs/Sinlinx_SinA33_defconfig | 1 + 1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 2a5f985dd303..f4719db2d501 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
The SinA33 has an 4GB Toshiba eMMC connected to the MMC2 controller. Enable it.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
Reviewed-by: Chen-Yu Tsai wens@csie.org
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
The SinA33 has an 4GB Toshiba eMMC connected to the MMC2 controller. Enable it.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Regards,
Hans
configs/Sinlinx_SinA33_defconfig | 1 + 1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 2a5f985dd303..f4719db2d501 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
On 11/14/2016 03:51 AM, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
The SinA33 has an 4GB Toshiba eMMC connected to the MMC2 controller. Enable it.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Applied on u-boot-mmc. Thanks!
Best Regards, Jaehoon Chung
Regards,
Hans
configs/Sinlinx_SinA33_defconfig | 1 + 1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 2a5f985dd303..f4719db2d501 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
The SinA33 comes with an optional 7" display. Enable it in the configuration.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com --- configs/Sinlinx_SinA33_defconfig | 4 ++++ 1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index f4719db2d501..26b119a9b92f 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -6,6 +6,10 @@ CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y
Hi,
On Fri, Nov 4, 2016 at 11:18 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
The SinA33 comes with an optional 7" display. Enable it in the configuration.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
configs/Sinlinx_SinA33_defconfig | 4 ++++ 1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index f4719db2d501..26b119a9b92f 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -6,6 +6,10 @@ CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0"
I'm using the exact same panel with my SinA31s. The schematics show that these 2 pins aren't actually hooked up to the panel at all. Instead of BL_EN, the corresponding pin is pull-ed up to 3.3V by a resistor just before the LCD connector on the base board.
Please try it without these 2 pins set.
ChenYu
P.S. I've also a VGA converter board for the SinA33 which I've never tried.
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -- git-series 0.8.11
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
The SinA33 comes with an optional 7" display. Enable it in the configuration.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Regards,
Hans
configs/Sinlinx_SinA33_defconfig | 4 ++++ 1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index f4719db2d501..26b119a9b92f 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -6,6 +6,10 @@ CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y
Hi Hans,
On 11/14/2016 03:51 AM, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
The SinA33 comes with an optional 7" display. Enable it in the configuration.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
This patch is not on MMC side. But i picked with other patches. If there is other issue, let me know, plz.
Best Regards, Jaehoon Chung
Regards,
Hans
configs/Sinlinx_SinA33_defconfig | 4 ++++ 1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index f4719db2d501..26b119a9b92f 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -6,6 +6,10 @@ CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y
On 11/14/2016 03:51 AM, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
The SinA33 comes with an optional 7" display. Enable it in the configuration.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
LGTM:
Reviewed-by: Hans de Goede hdegoede@redhat.com
Applied on u-boot-mmc. Thanks!
Best Regards, Jaehoon Chung
Regards,
Hans
configs/Sinlinx_SinA33_defconfig | 4 ++++ 1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index f4719db2d501..26b119a9b92f 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -6,6 +6,10 @@ CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y
participants (5)
-
Chen-Yu Tsai -
Hans de Goede -
Jaehoon Chung -
Maxime Ripard -
Tom Rini