Fill in missing commit IDs and dates when the removal happened.

Signed-off-by: Marek Vasut marex@denx.de Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Simon Glass sjg@chromium.org Cc: Heiko Schocher hs@denx.de --- doc/README.scrapyard | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 1dcdcc7..18d2611 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,14 +12,14 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -MVBC_P powerpc mpc5xxx - - Andre Schwarz andre.schwarz@matrix-vision.de -MVSMR powerpc mpc5xxx - - Andre Schwarz andre.schwarz@matrix-vision.de -MERGERBOX powerpc mpc83xx - - Andre Schwarz andre.schwarz@matrix-vision.de -MVBLM7 powerpc mpc83xx - - Andre Schwarz andre.schwarz@matrix-vision.de -bluestone powerpc ppc4xx - - Tirumala Marri tmarri@apm.com -CRAYL1 powerpc ppc4xx - - David Updegraff dave@cray.com -KAREF powerpc ppc4xx - - Travis Sawyer travis.sawyer@sandburst.com -METROBOX powerpc ppc4xx - - Travis Sawyer travis.sawyer@sandburst.com +MVBC_P powerpc mpc5xxx af55e35d 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de +MVSMR powerpc mpc5xxx af55e35d 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de +MERGERBOX powerpc mpc83xx e7a56563 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de +MVBLM7 powerpc mpc83xx e7a56563 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de +bluestone powerpc ppc4xx 9ed3246e 2014-09-29 Tirumala Marri tmarri@apm.com +CRAYL1 powerpc ppc4xx 1521cdc5 2014-09-29 David Updegraff dave@cray.com +KAREF powerpc ppc4xx dc9617e0 2014-09-29 Travis Sawyer travis.sawyer@sandburst.com +METROBOX powerpc ppc4xx dc9617e0 2014-09-29 Travis Sawyer travis.sawyer@sandburst.com PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt smcnutt@psyent.com PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt smcnutt@psyent.com flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári Davíðsson kd@flaga.is

This board is the only user of CONFIG_SYS_EEPROM_X40430 , remove it so the EEPROM command code can be cleansed of the related code as well.

Signed-off-by: Marek Vasut marex@denx.de Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Simon Glass sjg@chromium.org Cc: Heiko Schocher hs@denx.de --- arch/powerpc/cpu/mpc8xx/Kconfig | 4 - arch/powerpc/cpu/mpc8xx/cpu_init.c | 1 - arch/powerpc/cpu/mpc8xx/fec.c | 40 +-- board/icu862/Kconfig | 9 - board/icu862/MAINTAINERS | 7 - board/icu862/Makefile | 8 - board/icu862/flash.c | 575 ------------------------------------- board/icu862/icu862.c | 199 ------------- board/icu862/pcmcia.c | 262 ----------------- board/icu862/u-boot.lds | 82 ------ board/icu862/u-boot.lds.debug | 122 -------- configs/ICU862_100MHz_defconfig | 4 - configs/ICU862_defconfig | 3 - doc/README.scrapyard | 1 + include/commproc.h | 10 - include/configs/ICU862.h | 443 ---------------------------- include/pcmcia.h | 2 - include/status_led.h | 19 -- 18 files changed, 2 insertions(+), 1789 deletions(-) delete mode 100644 board/icu862/Kconfig delete mode 100644 board/icu862/MAINTAINERS delete mode 100644 board/icu862/Makefile delete mode 100644 board/icu862/flash.c delete mode 100644 board/icu862/icu862.c delete mode 100644 board/icu862/pcmcia.c delete mode 100644 board/icu862/u-boot.lds delete mode 100644 board/icu862/u-boot.lds.debug delete mode 100644 configs/ICU862_100MHz_defconfig delete mode 100644 configs/ICU862_defconfig delete mode 100644 include/configs/ICU862.h

diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index f1dca90..171bee9 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -16,9 +16,6 @@ config TARGET_ESTEEM192E config TARGET_HERMES bool "Support hermes"

-config TARGET_ICU862 - bool "Support ICU862" - config TARGET_IP860 bool "Support IP860"

@@ -124,7 +121,6 @@ source "board/eltec/mhpc/Kconfig" source "board/emk/top860/Kconfig" source "board/esteem192e/Kconfig" source "board/hermes/Kconfig" -source "board/icu862/Kconfig" source "board/ip860/Kconfig" source "board/ivm/Kconfig" source "board/kup/kup4k/Kconfig" diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 90c7e61..b8dc14d 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -126,7 +126,6 @@ void cpu_init_f (volatile immap_t * immr) */

#if defined(CONFIG_HERMES) || \ - defined(CONFIG_ICU862) || \ defined(CONFIG_IP860) || \ defined(CONFIG_IVML24) || \ defined(CONFIG_IVMS8) || \ diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index d12b3df..22b8ec7 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -205,11 +205,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)

j = 0; while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { -#if defined(CONFIG_ICU862) - udelay(10); -#else udelay(1); -#endif j++; } if (j>=TOUT_LOOP) { @@ -424,7 +420,7 @@ static void fec_pin_init(int fecidx)

#endif /* !CONFIG_RMII */

-#elif !defined(CONFIG_ICU862) +#else /* * Configure all of port D for MII. */ @@ -437,42 +433,8 @@ static void fec_pin_init(int fecidx) immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ else immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ -#else - /* - * Configure port A for MII. - */ - -#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY) - - /* - * On the ICU862 board the MII-MDC pin is routed to PD8 pin - * * of CPU, so for this board we need to configure Utopia and - * * enable PD8 to MII-MDC function - */ - immr->im_ioport.iop_pdpar |= 0x4080; #endif

- /* - * Has Utopia been configured? - */ - if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { - /* - * YES - Use MUXED mode for UTOPIA bus. - * This frees Port A for use by MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode &= ~0x80; - } else { - /* - * NO - set SPLIT mode for UTOPIA bus. - * - * This doesn't really effect UTOPIA (which isn't - * enabled anyway) but just tells the 862 - * to use port A for MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode |= 0x80; - } -#endif /* !defined(CONFIG_ICU862) */ - #endif /* CONFIG_ETHER_ON_FEC1 */ } else if (fecidx == 1) {

diff --git a/board/icu862/Kconfig b/board/icu862/Kconfig deleted file mode 100644 index da11d7b..0000000 --- a/board/icu862/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_ICU862 - -config SYS_BOARD - default "icu862" - -config SYS_CONFIG_NAME - default "ICU862" - -endif diff --git a/board/icu862/MAINTAINERS b/board/icu862/MAINTAINERS deleted file mode 100644 index 7fe16d1..0000000 --- a/board/icu862/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -ICU862 BOARD -M: Wolfgang Denk wd@denx.de -S: Maintained -F: board/icu862/ -F: include/configs/ICU862.h -F: configs/ICU862_defconfig -F: configs/ICU862_100MHz_defconfig diff --git a/board/icu862/Makefile b/board/icu862/Makefile deleted file mode 100644 index 263f21b..0000000 --- a/board/icu862/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = icu862.o flash.o pcmcia.o diff --git a/board/icu862/flash.c b/board/icu862/flash.c deleted file mode 100644 index a84ab99..0000000 --- a/board/icu862/flash.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, - size_b0 >> 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - /* ICU862 Board has only one Flash Bank */ - flash_info[0].size = size_b0; - - return size_b0; - -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) { - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00040000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: puts ("AMD "); break; - case FLASH_MAN_FUJ: puts ("FUJITSU "); break; - case FLASH_MAN_BM: puts ("BRIGHT MICRO "); break; - default: puts ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: puts ("AM29LV033C (32 Mbit)\n"); - break; - default: puts ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - puts ("\n "); - } - - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - - puts ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; -#if 0 - ulong base = (ulong)addr; -#endif - uchar value; - - /* Write auto select command: read Manufacturer ID */ -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; -#endif - - value = addr[0]; - - switch (value + (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = addr[1]; /* device ID */ - - switch ((unsigned long)value) { - case AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV033C: - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - flash_get_offsets ((ulong)addr, &flash_info[0]); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); -#if 1 - /* We don't know why it happens, but on ICU Board * - * for AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if ( i == 32 ) { - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - } -#endif - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; -#if 0 - *addr = 0x00F000F0; /* reset bank */ -#else - *addr = 0xF0F0F0F0; /* reset bank */ -#endif - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - puts ("- missing\n"); - } else { - puts ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - puts ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - puts ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); -#if 0 - addr[0] = 0x00300030; -#else - addr[0] = 0x30303030; -#endif - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); -#if 0 - while ((addr[0] & 0x00800080) != 0x00800080) -#else - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) -#endif - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - puts ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#if 0 - addr[0] = 0x00F000F0; /* reset bank */ -#else - addr[0] = 0xF0F0F0F0; /* reset bank */ -#endif - - puts (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; -#endif - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); -#if 0 - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) -#else - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) -#endif - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c deleted file mode 100644 index 4c0e919..0000000 --- a/board/icu862/icu862.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <mpc8xx.h> - -/* - * Memory Controller Using - * - * CS0 - Flash memory (0x40000000) - * CS1 - SDRAM (0x00000000} - * CS2 - S/UNI Ultra ATM155 - * CS3 - IDT 77106 ATM25 - * CS4 - DSP HPI - * CS5 - E1/T1 Interface device - * CS6 - PCMCIA device - * CS7 - PCMCIA device - */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -const uint sdram_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* MRS initialization (offset 5) */ - - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: ICU862 Board\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - unsigned long reg; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 to the SDRAM bank at - * preliminary address - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (200); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c deleted file mode 100644 index dbe3c3c..0000000 --- a/board/icu862/pcmcia.c +++ /dev/null @@ -1,262 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "ICU862" - -static void cfg_port_B (void) -{ - volatile cpm8xx_t *cp; - uint reg; - - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* - * Configure Port B for TPS2205 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - reg = cp->cp_pbdat; - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */ - TPS2205_SHDN); /* enable switch */ - cp->cp_pbdat = reg; - - cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS); - - reg = cp->cp_pbdir & ~(TPS2205_INPUTS); - cp->cp_pbdir = reg | TPS2205_OUTPUTS; - - debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", - cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); -} - -int pcmcia_hardware_enable(int slot) -{ - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, pipr, mask; - int i; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */ - cfg_port_B (); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - reg = cp->cp_pbdat; - if ((pipr & mask) == mask) { - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC3); /* 3V off */ - reg &= ~(TPS2205_VCC5); /* 5V on */ - puts (" 5.0V card found: "); - } else { - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC5); /* 5V off */ - reg &= ~(TPS2205_VCC3); /* 3V on */ - puts (" 3.3V card found: "); - } - - debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n", - reg, - (reg & TPS2205_VCC3) ? "off" : "on", - (reg & TPS2205_VCC5) ? "off" : "on", - (reg & TPS2205_VPP_PGM) ? "off" : "on", - (reg & TPS2205_VPP_VCC) ? "off" : "on" ); - - cp->cp_pbdat = reg; - - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if ((cp->cp_pbdat & TPS2205_OC) == 0) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - cp->cp_pbdat &= ~(TPS2205_SHDN); - return (1); - } - udelay (100); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* Shut down */ - cp->cp_pbdat &= ~(TPS2205_SHDN); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_port_B (); /* Enables switch, but all in Hi-Z */ - - reg = cp->cp_pbdat; - - switch(vcc) { - case 0: break; /* Switch off */ - case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */ - case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */ - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - cp->cp_pbdat = reg; - -#ifdef DEBUG -{ - char *s; - - if ((reg & TPS2205_VCC3) == 0) { - s = "at 3.3V"; - } else if ((reg & TPS2205_VCC5) == 0) { - s = "at 5.0V"; - } else { - s = "down"; - } - printf ("PCMCIA powered %s\n", s); -} -#endif - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds deleted file mode 100644 index 00f63d2..0000000 --- a/board/icu862/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug deleted file mode 100644 index c7c6116..0000000 --- a/board/icu862/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/ICU862_100MHz_defconfig b/configs/ICU862_100MHz_defconfig deleted file mode 100644 index 72f0dfa..0000000 --- a/configs/ICU862_100MHz_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="100MHz" -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_ICU862=y diff --git a/configs/ICU862_defconfig b/configs/ICU862_defconfig deleted file mode 100644 index b58ea05..0000000 --- a/configs/ICU862_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_ICU862=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 18d2611..7ae18fb 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +ICU862 powerpc mpc8xx - - Wolfgang Denk wd@denx.de MVBC_P powerpc mpc5xxx af55e35d 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de MVSMR powerpc mpc5xxx af55e35d 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de MERGERBOX powerpc mpc83xx e7a56563 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de diff --git a/include/commproc.h b/include/commproc.h index 82a1a98..d481707 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -563,16 +563,6 @@ typedef struct scc_enet {

#endif /* CONFIG_HERMES */

-/*** ICU862 **********************************************************/ - -#if defined(CONFIG_ICU862) - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for EThernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -#endif /* CONFIG_ICU862 */ - /*** IP860 **********************************************************/

#if defined(CONFIG_IP860) diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h deleted file mode 100644 index 16af4bb..0000000 --- a/include/configs/ICU862.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <mpc8xx_irq.h> - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_ICU862 1 -#define CONFIG_MPC862 1 - -#define CONFIG_SYS_TEXT_BASE 0x40F00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#ifdef CONFIG_100MHz -#define MPC8XX_FACT 24 /* Multiply by 24 */ -#define MPC8XX_XIN 4165000 /* 4.165 MHz in */ -#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) - /* define if cant' use get_gclk_freq */ -#else -#if 1 /* for 50MHz version of processor */ -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */ -#else /* for 80MHz version of processor */ -#define MPC8XX_FACT 20 /* Multiply by 20 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */ -#endif -#endif - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 -#if 1 -#define CONFIG_SYS_DISCOVER_PHY 1 -#else -#undef CONFIG_SYS_DISCOVER_PHY -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if 0 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00F40000 - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */ -#define SCCR_MASK 0 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01) -#else /* up to 50 MHz we use a 1:1 clock */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 ) -#endif /* CONFIG_100MHz */ - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ -#define CONFIG_SYS_RCCR 0x0020 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * PCMCIA Power Switch - * - * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to - * control the voltages on the PCMCIA slot which is connected to Port B - *----------------------------------------------------------------------- - */ - /* Output pins */ -#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */ -#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */ -#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */ -#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */ -#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */ -#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \ - TPS2205_VPP_PGM | TPS2205_VPP_VCC | \ - TPS2205_SHDN) - - /* Input pins */ -#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */ -#define TPS2205_INPUTS ( TPS2205_OC ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */ -#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */ - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */ - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13a01114 - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - - -#endif /* __CONFIG_H */ diff --git a/include/pcmcia.h b/include/pcmcia.h index 4b667f4..00065b2 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -29,8 +29,6 @@ # define CONFIG_PCMCIA_SLOT_A #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ # define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */ -# define CONFIG_PCMCIA_SLOT_B #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */ # define CONFIG_PCMCIA_SLOT_B #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ diff --git a/include/status_led.h b/include/status_led.h index c1d2242..c5de894 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -114,25 +114,6 @@ void status_led_set (int led, int state); # define STATUS_LED_GREEN 1 # define STATUS_LED_BOOT 2 /* IDE LED used for boot status */

-/***** ICU862 ********************************************************/ -#elif defined(CONFIG_ICU862) - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING -# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */ -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ) -# define STATUS_LED_STATE1 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - /***** Someone else defines these *************************************/ #elif defined(STATUS_LED_PAR)

This board uses eeprom accessors in an incorrect way. The board is old and unsupported, just zap it.

Signed-off-by: Marek Vasut marex@denx.de Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Simon Glass sjg@chromium.org Cc: Heiko Schocher hs@denx.de --- arch/powerpc/cpu/mpc8xx/Kconfig | 4 - arch/powerpc/cpu/mpc8xx/cpu_init.c | 1 - board/eltec/mhpc/Kconfig | 12 - board/eltec/mhpc/MAINTAINERS | 6 - board/eltec/mhpc/Makefile | 8 - board/eltec/mhpc/flash.c | 414 --------------------------------- board/eltec/mhpc/mhpc.c | 465 ------------------------------------- board/eltec/mhpc/u-boot.lds.debug | 121 ---------- configs/MHPC_defconfig | 3 - doc/README.scrapyard | 1 + include/commproc.h | 22 -- include/configs/MHPC.h | 369 ----------------------------- 12 files changed, 1 insertion(+), 1425 deletions(-) delete mode 100644 board/eltec/mhpc/Kconfig delete mode 100644 board/eltec/mhpc/MAINTAINERS delete mode 100644 board/eltec/mhpc/Makefile delete mode 100644 board/eltec/mhpc/flash.c delete mode 100644 board/eltec/mhpc/mhpc.c delete mode 100644 board/eltec/mhpc/u-boot.lds.debug delete mode 100644 configs/MHPC_defconfig delete mode 100644 include/configs/MHPC.h

diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index 171bee9..4c150a8 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -40,9 +40,6 @@ config TARGET_RRVISION config TARGET_SPD823TS bool "Support SPD823TS"

-config TARGET_MHPC - bool "Support MHPC" - config TARGET_TOP860 bool "Support TOP860"

@@ -117,7 +114,6 @@ endchoice source "board/LEOX/elpt860/Kconfig" source "board/RRvision/Kconfig" source "board/cogent/Kconfig" -source "board/eltec/mhpc/Kconfig" source "board/emk/top860/Kconfig" source "board/esteem192e/Kconfig" source "board/hermes/Kconfig" diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index b8dc14d..60c401e 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -130,7 +130,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_IVML24) || \ defined(CONFIG_IVMS8) || \ defined(CONFIG_LWMON) || \ - defined(CONFIG_MHPC) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ defined(CONFIG_SPD823TS) diff --git a/board/eltec/mhpc/Kconfig b/board/eltec/mhpc/Kconfig deleted file mode 100644 index 5a4c884..0000000 --- a/board/eltec/mhpc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MHPC - -config SYS_BOARD - default "mhpc" - -config SYS_VENDOR - default "eltec" - -config SYS_CONFIG_NAME - default "MHPC" - -endif diff --git a/board/eltec/mhpc/MAINTAINERS b/board/eltec/mhpc/MAINTAINERS deleted file mode 100644 index 4d84a35..0000000 --- a/board/eltec/mhpc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MHPC BOARD -M: Frank Gottschling fgottschling@eltec.de -S: Maintained -F: board/eltec/mhpc/ -F: include/configs/MHPC.h -F: configs/MHPC_defconfig diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile deleted file mode 100644 index f3fcc2f..0000000 --- a/board/eltec/mhpc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mhpc.o flash.o diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c deleted file mode 100644 index ad89df9..0000000 --- a/board/eltec/mhpc/flash.c +++ /dev/null @@ -1,414 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <linux/byteorder/swab.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F640J5 : - printf ("28F640J5 \n"); break; - default: printf ("Unknown Chip Type=0x%lXh\n", - info->flash_id & FLASH_TYPEMASK); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0xAA00AA00; - addr[0x2AAA] = (FPW)0x55005500; - addr[0x5555] = (FPW)0x90009000; - - value = SWAP(addr[0]); - - switch (value) { - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0xFF00FF00; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = SWAP(addr[1]); /* device ID no swap !*/ - - switch (value) { - case (FPW)INTEL_ID_28F640J5 : - info->flash_id += FLASH_28F640J5 ; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0xFF00FF00; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rc = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x50005000; /* clear status register */ - *addr = (FPW)0x20002000; /* erase setup */ - *addr = (FPW)0xD000D000; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0xB000B000; /* suspend erase */ - *addr = (FPW)0xFF00FF00; /* reset to read mode */ - rc = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW)0xFF00FF00; /* reset to read mode */ - printf (" done\n"); - } - } - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i<port_width && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - while (cnt >= port_width) { - data = 0; - for (i=0; i<port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if ((wp & 0xfff) == 0) - { - printf("%08lX",wp); - printf("\x1b[8D"); - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_data(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%x)\n",(ulong)addr,*addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x40004000; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW)0xFF00FF00; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0xFF00FF00; /* restore read mode */ - - return (0); -} diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c deleted file mode 100644 index 5781b2a..0000000 --- a/board/eltec/mhpc/mhpc.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * (C) Copyright 2001 - * ELTEC Elektronik AG - * Frank Gottschling fgottschling@eltec.de - * - * Board specific routines for the miniHiPerCam - * - * - initialisation (eeprom) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <cli.h> -#include <linux/ctype.h> -#include <commproc.h> -#include "mpc8xx.h" -#include <video_fb.h> - -extern void eeprom_init (void); -extern int eeprom_read (unsigned dev_addr, unsigned offset, - unsigned char *buffer, unsigned cnt); -extern int eeprom_write (unsigned dev_addr, unsigned offset, - unsigned char *buffer, unsigned cnt); - -/* globals */ -void *video_hw_init (void); -void video_set_lut (unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ); - -GraphicDevice gdev; - -/* locals */ -static void video_circle (char *center, int radius, int color, int pitch); -static void video_test_image (void); -static void video_default_lut (unsigned int clut_type); - -/* revision info foer MHPC EEPROM offset 480 */ -typedef struct { - char board[12]; /* 000 - Board Revision information */ - char sensor; /* 012 - Sensor Type information */ - char serial[8]; /* 013 - Board serial number */ - char etheraddr[6]; /* 021 - Ethernet node addresse */ - char revision[2]; /* 027 - Revision code */ - char option[3]; /* 029 - resevered for options */ -} revinfo; - -/* ------------------------------------------------------------------------- */ - -static const unsigned int sdram_table[] = { - /* read single beat cycle */ - 0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00, - 0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35, - - /* read burst cycle */ - 0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00, - 0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* write single beat cycle */ - 0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* write burst cycle */ - 0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440, - 0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* periodic timer expired */ - 0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84, - 0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* exception */ - 0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04 -}; - -/* ------------------------------------------------------------------------- */ - -int board_early_init_f (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport); - - /* reset the port A s.a. cpm-routines */ - ip->iop_padat = 0x0000; - ip->iop_papar = 0x0000; - ip->iop_padir = 0x0800; - ip->iop_paodr = 0x0000; - - /* reset the port B for digital and LCD output */ - cp->cp_pbdat = 0x0300; - cp->cp_pbpar = 0x5001; - cp->cp_pbdir = 0x5301; - cp->cp_pbodr = 0x0000; - - /* reset the port C configured for SMC1 serial port and aqc. control */ - ip->iop_pcdat = 0x0800; - ip->iop_pcpar = 0x0000; - ip->iop_pcdir = 0x0e30; - ip->iop_pcso = 0x0000; - - /* Config port D for LCD output */ - ip->iop_pdpar = 0x1fff; - ip->iop_pddir = 0x1fff; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity - */ -int checkboard (void) -{ - puts ("Board: ELTEC miniHiperCam\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - revinfo mhpcRevInfo; - char nid[32]; - char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color", - "OMNIVISON OV7110 b&w", NULL - }; - char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, - 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 - }; - int i; - - /* check revision data */ - eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32); - - if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { - printf ("Enter revision number (0-9): %c ", - mhpcRevInfo.revision[0]); - if (0 != cli_readline(NULL)) { - mhpcRevInfo.revision[0] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter revision character (A-Z): %c ", - mhpcRevInfo.revision[1]); - if (1 == cli_readline(NULL)) { - mhpcRevInfo.revision[1] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter board name (V-XXXX-XXXX): %s ", - (char *) &mhpcRevInfo.board); - if (11 == cli_readline(NULL)) { - for (i = 0; i < 11; i++) { - mhpcRevInfo.board[i] = - (char) toupper (console_buffer[i]); - mhpcRevInfo.board[11] = '\0'; - } - } - - printf ("Supported sensor types:\n"); - i = 0; - do { - printf ("\n '%d' : %s\n", i, mhpcSensorTypes[i]); - } while (mhpcSensorTypes[++i] != NULL); - - do { - printf ("\nEnter sensor number (0-255): %d ", - (int) mhpcRevInfo.sensor); - if (0 != cli_readline(NULL)) { - mhpcRevInfo.sensor = - (unsigned char) - simple_strtoul (console_buffer, NULL, - 10); - } - } while (mhpcRevInfo.sensor >= i); - - printf ("Enter serial number: %s ", - (char *) &mhpcRevInfo.serial); - if (6 == cli_readline(NULL)) { - for (i = 0; i < 6; i++) { - mhpcRevInfo.serial[i] = console_buffer[i]; - } - mhpcRevInfo.serial[6] = '\0'; - } - - printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - if (12 == cli_readline(NULL)) { - for (i = 0; i < 12; i += 2) { - mhpcRevInfo.etheraddr[i >> 1] = - (char) (16 * - hex[toupper - (console_buffer[i]) - - '0'] + - hex[toupper - (console_buffer[i + 1]) - - '0']); - } - } - - /* setup new revision data */ - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, - 32); - } - - /* set environment */ - sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x", - mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], - mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], - mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - setenv ("ethaddr", nid); - - /* print actual board identification */ - printf ("Ident: %s %s Ser %s Rev %c%c\n", - mhpcRevInfo.board, - (mhpcRevInfo.sensor == 0 ? "color" : "b&w"), - (char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0], - mhpcRevInfo.revision[1]); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */ - memctl->memc_mptpr = MPTPR_PTP_DIV64; - memctl->memc_mar = 0x00008800; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - udelay (200); - - /* - * Map controller SDRAM bank 1 - */ - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (10000); - - /* leave place for framebuffers */ - return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE); -} - -/* ------------------------------------------------------------------------- */ - -static void video_circle (char *center, int radius, int color, int pitch) -{ - int x, y, d, dE, dSE; - - x = 0; - y = radius; - d = 1 - radius; - dE = 3; - dSE = -2 * radius + 5; - - *(center + x + y * pitch) = color; - *(center + y + x * pitch) = color; - *(center + y - x * pitch) = color; - *(center + x - y * pitch) = color; - *(center - x - y * pitch) = color; - *(center - y - x * pitch) = color; - *(center - y + x * pitch) = color; - *(center - x + y * pitch) = color; - while (y > x) { - if (d < 0) { - d += dE; - dE += 2; - dSE += 2; - x++; - } else { - d += dSE; - dE += 2; - dSE += 4; - x++; - y--; - } - *(center + x + y * pitch) = color; - *(center + y + x * pitch) = color; - *(center + y - x * pitch) = color; - *(center + x - y * pitch) = color; - *(center - x - y * pitch) = color; - *(center - y - x * pitch) = color; - *(center - y + x * pitch) = color; - *(center - x + y * pitch) = color; - } -} - -/* ------------------------------------------------------------------------- */ - -static void video_test_image (void) -{ - char *di; - int i, n; - - /* draw raster */ - for (i = 0; i < LCD_VIDEO_ROWS; i += 32) { - memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS), - LCD_VIDEO_FG, LCD_VIDEO_COLS); - for (n = i + 1; n < i + 32; n++) - memset ((char *) (LCD_VIDEO_ADDR + - n * LCD_VIDEO_COLS), LCD_VIDEO_BG, - LCD_VIDEO_COLS); - } - - for (i = 0; i < LCD_VIDEO_COLS; i += 32) { - for (n = 0; n < LCD_VIDEO_ROWS; n++) - *(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) = - LCD_VIDEO_FG; - } - - /* draw gray bar */ - di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 + - 97 * LCD_VIDEO_COLS); - for (n = 0; n < 63; n++) { - for (i = 0; i < 256; i++) { - *di++ = (char) i; - *(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255; - } - di += LCD_VIDEO_COLS - 256; - } - - video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 + - LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2, - LCD_VIDEO_FG, LCD_VIDEO_COLS); -} - -/* ------------------------------------------------------------------------- */ - -static void video_default_lut (unsigned int clut_type) -{ - unsigned int i; - unsigned char RGB[] = { - 0x00, 0x00, 0x00, /* black */ - 0x80, 0x80, 0x80, /* gray */ - 0xff, 0x00, 0x00, /* red */ - 0x00, 0xff, 0x00, /* green */ - 0x00, 0x00, 0xff, /* blue */ - 0x00, 0xff, 0xff, /* cyan */ - 0xff, 0x00, 0xff, /* magenta */ - 0xff, 0xff, 0x00, /* yellow */ - 0x80, 0x00, 0x00, /* dark red */ - 0x00, 0x80, 0x00, /* dark green */ - 0x00, 0x00, 0x80, /* dark blue */ - 0x00, 0x80, 0x80, /* dark cyan */ - 0x80, 0x00, 0x80, /* dark magenta */ - 0x80, 0x80, 0x00, /* dark yellow */ - 0xc0, 0xc0, 0xc0, /* light gray */ - 0xff, 0xff, 0xff, /* white */ - }; - - switch (clut_type) { - case 1: - for (i = 0; i < 240; i++) - video_set_lut (i, i, i, i); - for (i = 0; i < 16; i++) - video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1], - RGB[i * 3 + 2]); - break; - default: - for (i = 0; i < 256; i++) - video_set_lut (i, i, i, i); - } -} - -/* ------------------------------------------------------------------------- */ - -void *video_hw_init (void) -{ - unsigned int clut = 0; - unsigned char *penv; - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* enable video only on CLUT value */ - if ((penv = (uchar *)getenv ("clut")) != NULL) - clut = (u_int) simple_strtoul ((char *)penv, NULL, 10); - else - return NULL; - - /* disable graphic before write LCD regs. */ - immr->im_lcd.lcd_lccr = 0x96000866; - - /* config LCD regs. */ - immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR; - immr->im_lcd.lcd_lchcr = 0x010a0093; - immr->im_lcd.lcd_lcvcr = 0x900f0024; - - printf ("Video: 640x480 8Bit Index Lut %s\n", - (clut == 1 ? "240/16 (gray/vga)" : "256(gray)")); - - video_default_lut (clut); - - /* clear framebuffer */ - memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG, - LCD_VIDEO_ROWS * LCD_VIDEO_COLS); - - /* enable graphic */ - immr->im_lcd.lcd_lccr = 0x96000867; - - /* fill in Graphic Device */ - gdev.frameAdrs = LCD_VIDEO_ADDR; - gdev.winSizeX = LCD_VIDEO_COLS; - gdev.winSizeY = LCD_VIDEO_ROWS; - gdev.gdfBytesPP = 1; - gdev.gdfIndex = GDF__8BIT_INDEX; - - if (clut > 1) - /* return Graphic Device for console */ - return (void *) &gdev; - else - /* just graphic enabled - draw something beautiful */ - video_test_image (); - - return NULL; /* this disabels cfb - console */ -} - -/* ------------------------------------------------------------------------- */ - -void video_set_lut (unsigned int index, - unsigned char r, unsigned char g, unsigned char b) -{ - unsigned int lum; - unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00); - - /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */ - /* y = 0.299*R + 0.587*G + 0.114*B */ - lum = (2990 * r + 5870 * g + 1140 * b) / 10000; - pLut[index] = - ((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum & - 0x3f); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug deleted file mode 100644 index b0091db..0000000 --- a/board/eltec/mhpc/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/MHPC_defconfig b/configs/MHPC_defconfig deleted file mode 100644 index b05d3c4..0000000 --- a/configs/MHPC_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_MHPC=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 7ae18fb..4e99676 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +MHPC powerpc mpc8xx - - Frank Gottschling fgottschling@eltec.de ICU862 powerpc mpc8xx - - Wolfgang Denk wd@denx.de MVBC_P powerpc mpc5xxx af55e35d 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de MVSMR powerpc mpc5xxx af55e35d 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de diff --git a/include/commproc.h b/include/commproc.h index d481707..d78ab00 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -703,28 +703,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00250000) #endif /* CONFIG_KM8XX */

- -/*** MHPC ********************************************************/ - -#if defined(CONFIG_MHPC) -/* This ENET stuff is for the MHPC with ethernet on SCC2. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ -#endif /* CONFIG_MHPC */ - /*** NETVIA *******************************************************/

#if defined(CONFIG_NETVIA) diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h deleted file mode 100644 index d45be0f..0000000 --- a/include/configs/MHPC.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - * (C) Copyright 2001 - * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Configuation settings for the miniHiPerCam. - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_MHPC 1 /* on a miniHiPerCam */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */ -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#undef CONFIG_UCODE_PATCH - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE) -#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */ -#define LCD_VIDEO_COLS 640 -#define LCD_VIDEO_ROWS 480 -#define LCD_VIDEO_FG 255 -#define LCD_VIDEO_BG 0 - -#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */ -#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */ -#define CONFIG_VIDEO_LOGO - -#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */ -#define VIDEO_TSTC_FCT serial_stub_tstc -#define VIDEO_GETC_FCT serial_stub_getc - -#define CONFIG_BR0_WORKAROUND 1 - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_REGINFO - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfe000000 - -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=mhpc-0" -#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)" -*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */ -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 12-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define MPC8XX_SPEED 50000000L -#define MPC8XX_XIN 5000000L /* ref clk */ -#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */ -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001) - - -/*----------------------------------------------------------------------- - * MAMR settings for SDRAM - 16-14 - * => 0xC080200F - *----------------------------------------------------------------------- - * periodic timer for refresh - */ -#define CONFIG_SYS_MAMR_PTA 0xC0 -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK) - -/* - * BR0 and OR0 (FLASH) used to re-map FLASH - */ - -/* allow for max 8 MB of Flash */ -#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/ -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/ -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/ - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V ) - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ -#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */ - -/* SDRAM timing: drive GPL5 high on first cycle */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS) - -#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2/OR2 - DIMM - */ -#define CONFIG_SYS_OR2 (OR_ACS_DIV4) -#define CONFIG_SYS_BR2 (BR_MS_UPMA) - -/* - * BR3/OR3 - DIMM - */ -#define CONFIG_SYS_OR3 (OR_ACS_DIV4) -#define CONFIG_SYS_BR3 (BR_MS_UPMA) - -/* - * BR4/OR4 - */ -#define CONFIG_SYS_OR4 0 -#define CONFIG_SYS_BR4 0 - -/* - * BR5/OR5 - */ -#define CONFIG_SYS_OR5 0 -#define CONFIG_SYS_BR5 0 - -/* - * BR6/OR6 - */ -#define CONFIG_SYS_OR6 0 -#define CONFIG_SYS_BR6 0 - -/* - * BR7/OR7 - */ -#define CONFIG_SYS_OR7 0 -#define CONFIG_SYS_BR7 0 - - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -#endif /* __CONFIG_H */

Remove this board as this is the only one last user of eeprom_probe(), which is pretty non-standard stuff.

This patch also removes all the PHP, SQL and CSS stuff from U-Boot, which probably makes U-Boot a bit less IoT ;-)

Signed-off-by: Marek Vasut marex@denx.de Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Simon Glass sjg@chromium.org Cc: Heiko Schocher hs@denx.de --- arch/powerpc/cpu/mpc8260/Kconfig | 4 - arch/powerpc/cpu/mpc8260/ether_fcc.c | 27 +- arch/powerpc/cpu/mpc8260/interrupts.c | 10 +- arch/powerpc/cpu/mpc8260/start.S | 14 - arch/powerpc/cpu/mpc83xx/start.S | 11 - arch/powerpc/include/asm/u-boot.h | 3 - board/hymod/Kconfig | 9 - board/hymod/MAINTAINERS | 6 - board/hymod/Makefile | 8 - board/hymod/bsp.c | 387 ------------------ board/hymod/config.mk | 14 - board/hymod/eeprom.c | 678 ------------------------------- board/hymod/env.c | 221 ----------- board/hymod/fetch.c | 91 ----- board/hymod/flash.c | 490 ----------------------- board/hymod/flash.h | 140 ------- board/hymod/global_env | 145 ------- board/hymod/hymod.c | 521 ------------------------ board/hymod/hymod.h | 305 -------------- board/hymod/input.c | 91 ----- board/hymod/u-boot.lds | 132 ------ board/hymod/u-boot.lds.debug | 121 ------ configs/hymod_defconfig | 3 - doc/README.scrapyard | 1 + include/asm-generic/u-boot.h | 3 - include/common.h | 3 - include/configs/hymod.h | 728 ---------------------------------- tools/bddb/README | 116 ------ tools/bddb/badsubmit.php | 23 -- tools/bddb/bddb.css | 207 ---------- tools/bddb/brlog.php | 109 ----- tools/bddb/browse.php | 147 ------- tools/bddb/config.php | 16 - tools/bddb/create_tables.sql | 90 ----- tools/bddb/defs.php | 710 --------------------------------- tools/bddb/dodelete.php | 65 --- tools/bddb/dodellog.php | 57 --- tools/bddb/doedit.php | 186 --------- tools/bddb/doedlog.php | 76 ---- tools/bddb/donew.php | 230 ----------- tools/bddb/donewlog.php | 86 ---- tools/bddb/edit.php | 131 ------ tools/bddb/edlog.php | 86 ---- tools/bddb/execute.php | 33 -- tools/bddb/index.php | 38 -- tools/bddb/new.php | 120 ------ tools/bddb/newlog.php | 54 --- 47 files changed, 3 insertions(+), 6743 deletions(-) delete mode 100644 board/hymod/Kconfig delete mode 100644 board/hymod/MAINTAINERS delete mode 100644 board/hymod/Makefile delete mode 100644 board/hymod/bsp.c delete mode 100644 board/hymod/config.mk delete mode 100644 board/hymod/eeprom.c delete mode 100644 board/hymod/env.c delete mode 100644 board/hymod/fetch.c delete mode 100644 board/hymod/flash.c delete mode 100644 board/hymod/flash.h delete mode 100644 board/hymod/global_env delete mode 100644 board/hymod/hymod.c delete mode 100644 board/hymod/hymod.h delete mode 100644 board/hymod/input.c delete mode 100644 board/hymod/u-boot.lds delete mode 100644 board/hymod/u-boot.lds.debug delete mode 100644 configs/hymod_defconfig delete mode 100644 include/configs/hymod.h delete mode 100644 tools/bddb/README delete mode 100644 tools/bddb/badsubmit.php delete mode 100644 tools/bddb/bddb.css delete mode 100644 tools/bddb/brlog.php delete mode 100644 tools/bddb/browse.php delete mode 100644 tools/bddb/config.php delete mode 100644 tools/bddb/create_tables.sql delete mode 100644 tools/bddb/defs.php delete mode 100644 tools/bddb/dodelete.php delete mode 100644 tools/bddb/dodellog.php delete mode 100644 tools/bddb/doedit.php delete mode 100644 tools/bddb/doedlog.php delete mode 100644 tools/bddb/donew.php delete mode 100644 tools/bddb/donewlog.php delete mode 100644 tools/bddb/edit.php delete mode 100644 tools/bddb/edlog.php delete mode 100644 tools/bddb/execute.php delete mode 100644 tools/bddb/index.php delete mode 100644 tools/bddb/new.php delete mode 100644 tools/bddb/newlog.php

diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index 41e4e5f..7f246ff 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -28,9 +28,6 @@ config TARGET_EP82XXM config TARGET_GW8260 bool "Support gw8260"

-config TARGET_HYMOD - bool "Support hymod" - config TARGET_IPHASE4539 bool "Support IPHASE4539"

@@ -78,7 +75,6 @@ source "board/ep82xxm/Kconfig" source "board/freescale/mpc8266ads/Kconfig" source "board/funkwerk/vovpn-gw/Kconfig" source "board/gw8260/Kconfig" -source "board/hymod/Kconfig" source "board/ids/ids8247/Kconfig" source "board/iphase4539/Kconfig" source "board/keymile/km82xx/Kconfig" diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index d93a991..f9f15b5 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -645,32 +645,7 @@ eth_loopback_test (void)

/* 28.9 - (1-2): ioports have been set up already */

-#if defined(CONFIG_HYMOD) - /* - * Attention: this is board-specific - * 0, FCC1 - * 1, FCC2 - * 2, FCC3 - */ -# define FCC_START_LOOP 0 -# define FCC_END_LOOP 2 - - /* - * Attention: this is board-specific - * - FCC1 Rx-CLK is CLK10 - * - FCC1 Tx-CLK is CLK11 - * - FCC2 Rx-CLK is CLK13 - * - FCC2 Tx-CLK is CLK14 - * - FCC3 Rx-CLK is CLK15 - * - FCC3 Tx-CLK is CLK16 - */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\ - CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\ - CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16; -#elif defined(CONFIG_SACSng) +#if defined(CONFIG_SACSng) /* * Attention: this is board-specific * 1, FCC2 diff --git a/arch/powerpc/cpu/mpc8260/interrupts.c b/arch/powerpc/cpu/mpc8260/interrupts.c index 30125a7..41d2c04 100644 --- a/arch/powerpc/cpu/mpc8260/interrupts.c +++ b/arch/powerpc/cpu/mpc8260/interrupts.c @@ -142,15 +142,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) immr->im_intctl.ic_sipnrh = 0xffffffff; immr->im_intctl.ic_sipnrl = 0xffffffff;

-#ifdef CONFIG_HYMOD - /* - * ensure all external interrupt sources default to trigger on - * high-to-low transition (i.e. edge triggered active low) - */ - immr->im_intctl.ic_siexr = -1; -#endif - - return (0); + return 0; }

/****************************************************************************/ diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index d7eaf13..5f1e174 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -48,9 +48,6 @@ GOT_ENTRY(__init_end) GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) -#if defined(CONFIG_HYMOD) - GOT_ENTRY(environment) -#endif END_GOT

/* @@ -878,18 +875,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else lwz r4,GOT(__bss_end) -#endif

cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 36724e5..af75c63 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -958,18 +958,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else lwz r4,GOT(__bss_end) -#endif

cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index e1b566f..a61e998 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -77,9 +77,6 @@ typedef struct bd_info { unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ #endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif

#ifdef CONFIG_HAS_ETH1 unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ diff --git a/board/hymod/Kconfig b/board/hymod/Kconfig deleted file mode 100644 index fa162eb..0000000 --- a/board/hymod/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_HYMOD - -config SYS_BOARD - default "hymod" - -config SYS_CONFIG_NAME - default "hymod" - -endif diff --git a/board/hymod/MAINTAINERS b/board/hymod/MAINTAINERS deleted file mode 100644 index e27fe97..0000000 --- a/board/hymod/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HYMOD BOARD -M: Murray Jensen Murray.Jensen@csiro.au -S: Maintained -F: board/hymod/ -F: include/configs/hymod.h -F: configs/hymod_defconfig diff --git a/board/hymod/Makefile b/board/hymod/Makefile deleted file mode 100644 index b9080b0..0000000 --- a/board/hymod/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = hymod.o flash.o bsp.o eeprom.o fetch.o input.o env.o diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c deleted file mode 100644 index e54640f..0000000 --- a/board/hymod/bsp.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01 - */ - -#include <common.h> -#include <command.h> -#include <net.h> -#include <asm/iopin_8260.h> - -DECLARE_GLOBAL_DATA_PTR; - -/*----------------------------------------------------------------------- - * Board Special Commands: FPGA load/store, EEPROM erase - */ - -#if defined(CONFIG_CMD_BSP) - -#define LOAD_SUCCESS 0 -#define LOAD_FAIL_NOCONF 1 -#define LOAD_FAIL_NOINIT 2 -#define LOAD_FAIL_NODONE 3 - -#define STORE_SUCCESS 0 - -/* - * Programming the Hymod FPGAs - * - * The 8260 io port config table is set up so that the INIT pin is - * held Low (Open Drain output 0) - this will delay the automatic - * Power-On config until INIT is released (by making it an input). - * - * If the FPGA has been programmed before, then the assertion of PROGRAM - * will initiate configuration (i.e. it begins clearing the RAM). - * - * When the FPGA is ready to receive configuration data (either after - * releasing INIT after Power-On, or after asserting PROGRAM), it will - * pull INIT high. - * - * Notes from Paul Dunn: - * - * 1. program pin should be forced low for >= 300ns - * (about 20 bus clock cycles minimum). - * - * 2. then wait for init to go high, which signals - * that the FPGA has cleared its internal memory - * and is ready to load - * - * 3. perform load writes of entire config file - * - * 4. wait for done to go high, which should be - * within a few bus clock cycles. If done has not - * gone high after reasonable period, then load - * has not worked (wait several ms?) - */ - -int -fpga_load(int mezz, const uchar *addr, ulong size) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - xlx_info_t *fp; - xlx_iopins_t *fpgaio; - volatile uchar *fpgabase; - volatile uint cnt; - const uchar *eaddr = addr + size; - int result; - - if (mezz) - fp = &cp->mezz.xlx[0]; - else - fp = &cp->main.xlx[0]; - - if (!fp->mmap.prog.exists) - return (LOAD_FAIL_NOCONF); - - fpgabase = (uchar *)fp->mmap.prog.base; - fpgaio = &fp->iopins; - - /* set enable HIGH if required */ - if (fpgaio->enable_pin.flag) - iopin_set_high (&fpgaio->enable_pin); - - /* ensure INIT is released (set it to be an input) */ - iopin_set_in (&fpgaio->init_pin); - - /* toggle PROG Low then High (will already be Low after Power-On) */ - iopin_set_low (&fpgaio->prog_pin); - udelay (1); /* minimum 300ns - 1usec should do it */ - iopin_set_high (&fpgaio->prog_pin); - - /* wait for INIT High */ - cnt = 0; - while (!iopin_is_high (&fpgaio->init_pin)) - if (++cnt == 10000000) { - result = LOAD_FAIL_NOINIT; - goto done; - } - - /* write configuration data */ - while (addr < eaddr) - *fpgabase = *addr++; - - /* wait for DONE High */ - cnt = 0; - while (!iopin_is_high (&fpgaio->done_pin)) - if (++cnt == 100000000) { - result = LOAD_FAIL_NODONE; - goto done; - } - - /* success */ - result = LOAD_SUCCESS; - - done: - - if (fpgaio->enable_pin.flag) - iopin_set_low (&fpgaio->enable_pin); - - return (result); -} - -/* ------------------------------------------------------------------------- */ -int -do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - uchar *addr, *save_addr; - ulong size; - int mezz, arg, result; - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strcmp (argv[1], "info") == 0) { - printf ("\nHymod FPGA Info...\n"); - printf ("\t\t\t\tAddress\t\tSize\n"); - printf ("\tMain Configuration:\t0x%08x\t%d\n", - FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE); - printf ("\tMain Register:\t\t0x%08x\t%d\n", - FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE); - printf ("\tMain Port:\t\t0x%08x\t%d\n", - FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE); - printf ("\tMezz Configuration:\t0x%08x\t%d\n", - FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE); - return 0; - } - break; - - case 3: - if (strcmp (argv[1], "store") == 0) { - addr = (uchar *) simple_strtoul (argv[2], NULL, 16); - - save_addr = addr; -#if 0 - /* fpga readback unimplemented */ - while (more readback data) - *addr++ = *fpga; - result = error ? STORE_FAIL_XXX : STORE_SUCCESS; -#else - result = STORE_SUCCESS; -#endif - - if (result == STORE_SUCCESS) { - printf ("SUCCEEDED (%d bytes)\n", - addr - save_addr); - return 0; - } else - printf ("FAILED (%d bytes)\n", - addr - save_addr); - return 1; - } - break; - - case 4: - if (strcmp (argv[1], "tftp") == 0) { - copy_filename (BootFile, argv[2], sizeof (BootFile)); - load_addr = simple_strtoul (argv[3], NULL, 16); - NetBootFileXferSize = 0; - - if (NetLoop(TFTPGET) <= 0) { - printf ("tftp transfer failed - aborting " - "fgpa load\n"); - return 1; - } - - if (NetBootFileXferSize == 0) { - printf ("can't determine file size - " - "aborting fpga load\n"); - return 1; - } - - printf ("File transfer succeeded - " - "beginning fpga load..."); - - result = fpga_load (0, (uchar *) load_addr, - NetBootFileXferSize); - - if (result == LOAD_SUCCESS) { - printf ("SUCCEEDED\n"); - return 0; - } else if (result == LOAD_FAIL_NOCONF) - printf ("FAILED (no CONF)\n"); - else if (result == LOAD_FAIL_NOINIT) - printf ("FAILED (no INIT)\n"); - else - printf ("FAILED (no DONE)\n"); - return 1; - - } - /* fall through ... */ - - case 5: - if (strcmp (argv[1], "load") == 0) { - if (argc == 5) { - if (strcmp (argv[2], "main") == 0) - mezz = 0; - else if (strcmp (argv[2], "mezz") == 0) - mezz = 1; - else { - printf ("FPGA type must be either " - "`main' or `mezz'\n"); - return 1; - } - arg = 3; - } else { - mezz = 0; - arg = 2; - } - - addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16); - size = (ulong) simple_strtoul (argv[arg], NULL, 16); - - result = fpga_load (mezz, addr, size); - - if (result == LOAD_SUCCESS) { - printf ("SUCCEEDED\n"); - return 0; - } else if (result == LOAD_FAIL_NOCONF) - printf ("FAILED (no CONF)\n"); - else if (result == LOAD_FAIL_NOINIT) - printf ("FAILED (no INIT)\n"); - else - printf ("FAILED (no DONE)\n"); - return 1; - } - break; - - default: - break; - } - - return cmd_usage(cmdtp); -} -U_BOOT_CMD( - fpga, 6, 1, do_fpga, - "FPGA sub-system", - "load [type] addr size\n" - " - write the configuration data at memory address `addr',\n" - " size `size' bytes, into the FPGA of type `type' (either\n" - " `main' or `mezz', default `main'). e.g.\n" - " `fpga load 100000 7d8f'\n" - " loads the main FPGA with config data at address 100000\n" - " HEX, size 7d8f HEX (32143 DEC) bytes\n" - "fpga tftp file addr\n" - " - transfers `file' from the tftp server into memory at\n" - " address `addr', then writes the entire file contents\n" - " into the main FPGA\n" - "fpga store addr\n" - " - read configuration data from the main FPGA (the mezz\n" - " FPGA is write-only), into address `addr'. There must be\n" - " enough memory available at `addr' to hold all the config\n" - " data - the size of which is determined by VC:???\n" - "fpga info\n" - " - print information about the Hymod FPGA, namely the\n" - " memory addresses at which the four FPGA local bus\n" - " address spaces appear in the physical address space" -); -/* ------------------------------------------------------------------------- */ -int -do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - uchar data[HYMOD_EEPROM_SIZE]; - uint addr = CONFIG_SYS_I2C_EEPROM_ADDR; - - switch (argc) { - - case 1: - addr |= HYMOD_EEOFF_MAIN; - break; - - case 2: - if (strcmp (argv[1], "main") == 0) { - addr |= HYMOD_EEOFF_MAIN; - break; - } - if (strcmp (argv[1], "mezz") == 0) { - addr |= HYMOD_EEOFF_MEZZ; - break; - } - /* fall through ... */ - - default: - return cmd_usage(cmdtp); - } - - memset (data, 0, HYMOD_EEPROM_SIZE); - - eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE); - - return 0; -} -U_BOOT_CMD( - eeclear, 1, 0, do_eecl, - "Clear the eeprom on a Hymod board", - "[type]\n" - " - write zeroes into the EEPROM on the board of type `type'\n" - " (`type' is either `main' or `mezz' - default `main')\n" - " Note: the EEPROM write enable jumper must be installed" -); - -/* ------------------------------------------------------------------------- */ - -int -do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ -#if 0 - int rc; -#endif -#ifdef CONFIG_ETHER_LOOPBACK_TEST - extern void eth_loopback_test (void); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - - printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n"); - -#if 0 - /* Load FPGA with test program */ - - printf ("Loading test FPGA program ..."); - - rc = fpga_load (0, test_bitfile, sizeof (test_bitfile)); - - switch (rc) { - - case LOAD_SUCCESS: - printf (" SUCCEEDED\n"); - break; - - case LOAD_FAIL_NOCONF: - printf (" FAILED (no configuration space defined)\n"); - return 1; - - case LOAD_FAIL_NOINIT: - printf (" FAILED (timeout - no INIT signal seen)\n"); - return 1; - - case LOAD_FAIL_NODONE: - printf (" FAILED (timeout - no DONE signal seen)\n"); - return 1; - - default: - printf (" FAILED (unknown return code from fpga_load\n"); - return 1; - } - - /* run Local Bus <=> Xilinx tests */ - - /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */ - - /* run SDRAM test */ -#endif - -#ifdef CONFIG_ETHER_LOOPBACK_TEST - /* run Ethernet test */ - eth_loopback_test (); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - - return 0; -} - -#endif diff --git a/board/hymod/config.mk b/board/hymod/config.mk deleted file mode 100644 index 2eeea50..0000000 --- a/board/hymod/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# HYMOD boards -# - -PLATFORM_CPPFLAGS += -I$(srctree) - -OBJCOPYFLAGS = --remove-section=.ppcenv diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c deleted file mode 100644 index ffb0df1..0000000 --- a/board/hymod/eeprom.c +++ /dev/null @@ -1,678 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> - -/* imports from fetch.c */ -extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); - -/* imports from input.c */ -extern int hymod_get_serno (const char *); - -/* this is relative to the root of the server's tftp directory */ -static char *def_bddb_cfgdir = "/hymod/bddb"; - -static int -hymod_eeprom_load (int which, hymod_eeprom_t *ep) -{ - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - unsigned offset = 0; - uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp; - hymod_eehdr_t hdr; - ulong len, crc; - - memset (ep, 0, sizeof *ep); - - eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr)); - offset += sizeof (hdr); - - if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER || - (len = hdr.len) > HYMOD_EEPROM_MAXLEN) - return (0); - - eeprom_read (dev_addr, offset, data, len); - offset += len; - - eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong)); - offset += sizeof (ulong); - - if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc) - return (0); - - ep->ver = hdr.ver; - dp = data; edp = dp + len; - - for (;;) { - ulong rtyp; - uchar rlen, *rdat; - - rtyp = *dp++; - if ((rtyp & 0x80) == 0) - rlen = *dp++; - else { - uchar islarge = rtyp & 0x40; - - rtyp = ((rtyp & 0x3f) << 8) | *dp++; - if (islarge) { - rtyp = (rtyp << 8) | *dp++; - rtyp = (rtyp << 8) | *dp++; - } - - rlen = *dp++; - rlen = (rlen << 8) | *dp++; - if (islarge) { - rlen = (rlen << 8) | *dp++; - rlen = (rlen << 8) | *dp++; - } - } - - if (rtyp == 0) - break; - - rdat = dp; - dp += rlen; - - if (dp > edp) /* error? */ - break; - - switch (rtyp) { - - case HYMOD_EEREC_SERNO: /* serial number */ - if (rlen == sizeof (ulong)) - ep->serno = \ - ((ulong)rdat[0] << 24) | \ - ((ulong)rdat[1] << 16) | \ - ((ulong)rdat[2] << 8) | \ - (ulong)rdat[3]; - break; - - case HYMOD_EEREC_DATE: /* date */ - if (rlen == sizeof (hymod_date_t)) { - ep->date.year = ((ushort)rdat[0] << 8) | \ - (ushort)rdat[1]; - ep->date.month = rdat[2]; - ep->date.day = rdat[3]; - } - break; - - case HYMOD_EEREC_BATCH: /* batch */ - if (rlen <= HYMOD_MAX_BATCH) - memcpy (ep->batch, rdat, ep->batchlen = rlen); - break; - - case HYMOD_EEREC_TYPE: /* board type */ - if (rlen == 1) - ep->bdtype = *rdat; - break; - - case HYMOD_EEREC_REV: /* board revision */ - if (rlen == 1) - ep->bdrev = *rdat; - break; - - case HYMOD_EEREC_SDRAM: /* sdram size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) { - int i; - - for (i = 0; i < rlen; i++) - ep->sdramsz[i] = rdat[i]; - ep->nsdram = rlen; - } - break; - - case HYMOD_EEREC_FLASH: /* flash size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) { - int i; - - for (i = 0; i < rlen; i++) - ep->flashsz[i] = rdat[i]; - ep->nflash = rlen; - } - break; - - case HYMOD_EEREC_ZBT: /* zbt ram size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) { - int i; - - for (i = 0; i < rlen; i++) - ep->zbtsz[i] = rdat[i]; - ep->nzbt = rlen; - } - break; - - case HYMOD_EEREC_XLXTYP: /* xilinx fpga type(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].type = rdat[i]; - ep->nxlx = rlen; - } - break; - - case HYMOD_EEREC_XLXSPD: /* xilinx fpga speed(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].speed = rdat[i]; - } - break; - - case HYMOD_EEREC_XLXTMP: /* xilinx fpga temperature(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].temp = rdat[i]; - } - break; - - case HYMOD_EEREC_XLXGRD: /* xilinx fpga grade(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].grade = rdat[i]; - } - break; - - case HYMOD_EEREC_CPUTYP: /* CPU type */ - if (rlen == 1) - ep->mpc.type = *rdat; - break; - - case HYMOD_EEREC_CPUSPD: /* CPU speed */ - if (rlen == 1) - ep->mpc.cpuspd = *rdat; - break; - - case HYMOD_EEREC_CPMSPD: /* CPM speed */ - if (rlen == 1) - ep->mpc.cpmspd = *rdat; - break; - - case HYMOD_EEREC_BUSSPD: /* bus speed */ - if (rlen == 1) - ep->mpc.busspd = *rdat; - break; - - case HYMOD_EEREC_HSTYPE: /* hs-serial chip type */ - if (rlen == 1) - ep->hss.type = *rdat; - break; - - case HYMOD_EEREC_HSCHIN: /* num hs-serial input chans */ - if (rlen == 1) - ep->hss.nchin = *rdat; - break; - - case HYMOD_EEREC_HSCHOUT: /* num hs-serial output chans */ - if (rlen == 1) - ep->hss.nchout = *rdat; - break; - - default: /* ignore */ - break; - } - } - - return (1); -} - -/* maps an ascii "name=value" into a binary eeprom data record */ -typedef - struct _eerec_map { - char *name; - uint type; - uchar *(*handler) \ - (struct _eerec_map *, uchar *, uchar *, uchar *); - uint length; - uint maxlen; - } -eerec_map_t; - -static uchar * -uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - char *eval; - ulong lval; - - lval = simple_strtol ((char *)val, &eval, 10); - - if ((uchar *)eval == val || *eval != '\0') { - printf ("%s rec (%s) is not a valid uint\n", rp->name, val); - return (NULL); - } - - if (dp + 2 + rp->length > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = rp->length; - - switch (rp->length) { - - case 1: - if (lval >= 256) { - printf ("%s rec value (%lu) out of range (0-255)\n", - rp->name, lval); - return (NULL); - } - *dp++ = lval; - break; - - case 2: - if (lval >= 65536) { - printf ("%s rec value (%lu) out of range (0-65535)\n", - rp->name, lval); - return (NULL); - } - *dp++ = lval >> 8; - *dp++ = lval; - break; - - case 4: - *dp++ = lval >> 24; - *dp++ = lval >> 16; - *dp++ = lval >> 8; - *dp++ = lval; - break; - - default: - printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length); - return (NULL); - } - - return (dp); -} - -static uchar * -date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - hymod_date_t date; - char *p = (char *)val; - char *ep; - ulong lval; - - lval = simple_strtol (p, &ep, 10); - if (ep == p || *ep++ != '-') { -bad_date: - printf ("%s rec (%s) is not a valid date\n", rp->name, val); - return (NULL); - } - if (lval >= 65536) - goto bad_date; - date.year = lval; - - lval = simple_strtol (p = ep, &ep, 10); - if (ep == p || *ep++ != '-' || lval == 0 || lval > 12) - goto bad_date; - date.month = lval; - - lval = simple_strtol (p = ep, &ep, 10); - if (ep == p || *ep != '\0' || lval == 0 || lval > 31) - goto bad_date; - date.day = lval; - - if (dp + 2 + rp->length > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = rp->length; - *dp++ = date.year >> 8; - *dp++ = date.year; - *dp++ = date.month; - *dp++ = date.day; - - return (dp); -} - -static uchar * -string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - uint len; - - if ((len = strlen ((char *)val)) > rp->maxlen) { - printf ("%s rec (%s) string is too long (%d>%d)\n", - rp->name, val, len, rp->maxlen); - return (NULL); - } - - if (dp + 2 + len > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = len; - memcpy (dp, val, len); - dp += len; - - return (dp); -} - -static uchar * -bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - uchar bytes[HYMOD_MAX_BYTES], nbytes, *p; - char *ep; - - for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) { - ulong lval; - - lval = simple_strtol ((char *)p, &ep, 10); - if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \ - lval >= 256) { - printf ("%s rec (%s) byte array has invalid uint\n", - rp->name, val); - return (NULL); - } - if (nbytes >= HYMOD_MAX_BYTES) { - printf ("%s rec (%s) byte array too long\n", - rp->name, val); - return (NULL); - } - bytes[nbytes++] = lval; - - if (*ep != '\0') - ep++; - } - - if (dp + 2 + nbytes > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = nbytes; - memcpy (dp, bytes, nbytes); - dp += nbytes; - - return (dp); -} - -static eerec_map_t eerec_map[] = { - /* name type handler len max */ - { "serno", HYMOD_EEREC_SERNO, uint_handler, 4, 0 }, - { "date", HYMOD_EEREC_DATE, date_handler, 4, 0 }, - { "batch", HYMOD_EEREC_BATCH, string_handler, 0, HYMOD_MAX_BATCH }, - { "type", HYMOD_EEREC_TYPE, uint_handler, 1, 0 }, - { "rev", HYMOD_EEREC_REV, uint_handler, 1, 0 }, - { "sdram", HYMOD_EEREC_SDRAM, bytes_handler, 0, HYMOD_MAX_SDRAM }, - { "flash", HYMOD_EEREC_FLASH, bytes_handler, 0, HYMOD_MAX_FLASH }, - { "zbt", HYMOD_EEREC_ZBT, bytes_handler, 0, HYMOD_MAX_ZBT }, - { "xlxtyp", HYMOD_EEREC_XLXTYP, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxspd", HYMOD_EEREC_XLXSPD, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxtmp", HYMOD_EEREC_XLXTMP, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxgrd", HYMOD_EEREC_XLXGRD, bytes_handler, 0, HYMOD_MAX_XLX }, - { "cputyp", HYMOD_EEREC_CPUTYP, uint_handler, 1, 0 }, - { "cpuspd", HYMOD_EEREC_CPUSPD, uint_handler, 1, 0 }, - { "cpmspd", HYMOD_EEREC_CPMSPD, uint_handler, 1, 0 }, - { "busspd", HYMOD_EEREC_BUSSPD, uint_handler, 1, 0 }, - { "hstype", HYMOD_EEREC_HSTYPE, uint_handler, 1, 0 }, - { "hschin", HYMOD_EEREC_HSCHIN, uint_handler, 1, 0 }, - { "hschout", HYMOD_EEREC_HSCHOUT, uint_handler, 1, 0 }, -}; - -static int neerecs = sizeof eerec_map / sizeof eerec_map[0]; - -static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp; - -static int -eerec_callback (uchar *name, uchar *val) -{ - eerec_map_t *rp; - - for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++) - if (strcmp ((char *)name, rp->name) == 0) - break; - - if (rp >= &eerec_map[neerecs]) - return (0); - - if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL) - return (0); - - return (1); -} - -static int -hymod_eeprom_fetch(int which, char *filename, ulong addr) -{ - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0]; - ulong crc; - - memset (hp, 0, sizeof *hp); - hp->id = HYMOD_EEPROM_ID; - hp->ver = HYMOD_EEPROM_VER; - - dp = sdp = (uchar *)(hp + 1); - edp = dp + HYMOD_EEPROM_MAXLEN; - - if (fetch_and_parse (filename, addr, eerec_callback) == 0) - return (0); - - hp->len = dp - sdp; - - crc = crc32 (0, data, dp - data); - memcpy (dp, &crc, sizeof (ulong)); - dp += sizeof (ulong); - - eeprom_write (dev_addr, 0, data, dp - data); - - return (1); -} - -static char *type_vals[] = { - "NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY" -}; - -static char *xlxtyp_vals[] = { - "NONE", "XCV300E", "XCV400E", "XCV600E" -}; - -static char *xlxspd_vals[] = { - "NONE", "6", "7", "8" -}; - -static char *xlxtmp_vals[] = { - "NONE", "COM", "IND" -}; - -static char *xlxgrd_vals[] = { - "NONE", "NORMAL", "ENGSAMP" -}; - -static char *cputyp_vals[] = { - "NONE", "MPC8260" -}; - -static char *clk_vals[] = { - "NONE", "33", "66", "100", "133", "166", "200" -}; - -static char *hstype_vals[] = { - "NONE", "AMCC-S2064A" -}; - -static void -print_mem (char *l, char *s, uchar n, uchar a[]) -{ - if (n > 0) { - if (n == 1) - printf ("%s%dMB %s", s, 1 << (a[0] - 20), l); - else { - ulong t = 0; - int i; - - for (i = 0; i < n; i++) - t += 1 << (a[i] - 20); - - printf ("%s%luMB %s (%d banks:", s, t, l, n); - - for (i = 0; i < n; i++) - printf ("%dMB%s", - 1 << (a[i] - 20), - (i == n - 1) ? ")" : ","); - } - } - else - printf ("%sNO %s", s, l); -} - -void -hymod_eeprom_print (hymod_eeprom_t *ep) -{ - int i; - - printf (" Hymod %s board, rev %03d\n", - type_vals[ep->bdtype], ep->bdrev); - - printf (" serial #: %010lu, date %04d-%02d-%02d", - ep->serno, ep->date.year, ep->date.month, ep->date.day); - if (ep->batchlen > 0) - printf (", batch "%.*s"", ep->batchlen, ep->batch); - puts ("\n"); - - switch (ep->bdtype) { - - case HYMOD_BDTYPE_IO: - case HYMOD_BDTYPE_CLP: - case HYMOD_BDTYPE_DSP: - printf (" Motorola %s CPU, speeds: %s/%s/%s", - cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd], - clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]); - - print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz); - - print_mem ("FLASH", ", ", ep->nflash, ep->flashsz); - - puts ("\n"); - - print_mem ("ZBT", " ", ep->nzbt, ep->zbtsz); - - if (ep->nxlx > 0) { - hymod_xlx_t *xp; - - if (ep->nxlx == 1) { - xp = &ep->xlx[0]; - printf (", Xilinx %s FPGA (%s/%s/%s)", - xlxtyp_vals[xp->type], - xlxspd_vals[xp->speed], - xlxtmp_vals[xp->temp], - xlxgrd_vals[xp->grade]); - } - else { - printf (", %d Xilinx FPGAs (", ep->nxlx); - for (i = 0; i < ep->nxlx; i++) { - xp = &ep->xlx[i]; - printf ("%s[%s/%s/%s]%s", - xlxtyp_vals[xp->type], - xlxspd_vals[xp->speed], - xlxtmp_vals[xp->temp], - xlxgrd_vals[xp->grade], - (i == ep->nxlx - 1) ? ")" : ", "); - } - } - } - else - puts(", NO FPGAs"); - - puts ("\n"); - - if (ep->hss.type > 0) - printf (" High Speed Serial: " - "%s, %d input%s, %d output%s\n", - hstype_vals[ep->hss.type], - ep->hss.nchin, - (ep->hss.nchin == 1 ? "" : "s"), - ep->hss.nchout, - (ep->hss.nchout == 1 ? "" : "s")); - break; - - case HYMOD_BDTYPE_INPUT: - case HYMOD_BDTYPE_ALTINPUT: - case HYMOD_BDTYPE_DISPLAY: - break; - - default: - /* crap! */ - printf (" UNKNOWN BOARD TYPE: %d\n", ep->bdtype); - break; - } -} - -int -hymod_eeprom_read (int which, hymod_eeprom_t *ep) -{ - char *label = which ? "mezzanine" : "main"; - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - char filename[50], prompt[50], *dir; - int serno, count = 0, rc; - - rc = eeprom_probe (dev_addr, 0); - - if (rc > 0) { - printf ("*** probe for eeprom failed with code %d\n", rc); - return (0); - } - - if (rc < 0) - return (rc); - - sprintf (prompt, "Enter %s board serial number: ", label); - - if ((dir = getenv ("bddb_cfgdir")) == NULL) - dir = def_bddb_cfgdir; - - for (;;) { - int rc; - - if (hymod_eeprom_load (which, ep)) - return (1); - - printf ("*** %s board EEPROM contents are %sinvalid\n", - label, count == 0 ? "" : "STILL "); - - puts ("*** will fetch from server (Ctrl-C to abort)\n"); - - serno = hymod_get_serno (prompt); - - if (serno < 0) { - if (serno == -1) - puts ("\n*** interrupted!"); - else - puts ("\n*** timeout!"); - puts (" - ignoring eeprom contents\n"); - return (0); - } - - sprintf (filename, "%s/%010d.cfg", dir, serno); - - printf ("*** fetching %s board EEPROM contents from server\n", - label); - - rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR); - - if (rc == 0) { - puts ("*** fetch failed - ignoring eeprom contents\n"); - return (0); - } - - count++; - } -} diff --git a/board/hymod/env.c b/board/hymod/env.c deleted file mode 100644 index 66c5115..0000000 --- a/board/hymod/env.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/ctype.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* imports from fetch.c */ -extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); - -/* this is relative to the root of the server's tftp directory */ -static char *def_global_env_path = "/hymod/global_env"; - -static int -env_callback (uchar *name, uchar *value) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver; - int override = 1, append = 0, remove = 0, nnl, ovl, nvl; - - nn = (char *)name; - - if (*nn == '-') { - override = 0; - nn++; - } - - while (isblank(*nn)) - nn++; - - if ((nnl = strlen (nn)) == 0) { - printf ("Empty name in global env file\n"); - return (0); - } - - if ((c = nn[nnl - 1]) == '+' || c == '-') { - if (c == '+') - append = 1; - else - remove = 1; - nn[--nnl] = '\0'; - } - - while (nnl > 0 && isblank(nn[nnl - 1])) - nn[--nnl] = '\0'; - if (nnl == 0) { - printf ("Empty name in global env file\n"); - return (0); - } - - p = (char *)value; - q = nv; - - while (isblank(*p)) - p++; - - nvl = strlen (p); - while (nvl > 0 && isblank(p[nvl - 1])) - p[--nvl] = '\0'; - - while ((*q = *p++) != '\0') { - if (*q == '%') { - switch (*p++) { - - case '\0': /* whoops - back up */ - p--; - break; - - case '%': /* a single percent character */ - q++; - break; - - case 's': /* main board serial number as string */ - q += sprintf (q, "%010lu", - cp->main.eeprom.serno); - break; - - case 'S': /* main board serial number as number */ - q += sprintf (q, "%lu", cp->main.eeprom.serno); - break; - - default: /* ignore any others */ - break; - } - } - else - q++; - } - - if ((nvl = q - nv) == 0) { - setenv (nn, NULL); - return (1); - } - - if ((curver = getenv ("global_env_version")) == NULL) - curver = "unknown"; - - if ((newver = getenv ("new_genv_version")) == NULL || \ - strcmp (curver, newver) == 0) { - if (strcmp (nn, "version") == 0) - setenv ("new_genv_version", nv); - return (1); - } - - if ((p = getenv (nn)) != NULL) { - - strcpy (ov, p); - ovl = strlen (ov); - - if (append) { - - if (strstr (ov, nv) == NULL) { - - printf ("Appending '%s' to env var '%s'\n", - nv, nn); - - while (nvl >= 0) { - nv[ovl + 1 + nvl] = nv[nvl]; - nvl--; - } - - nv[ovl] = ' '; - - while (--ovl >= 0) - nv[ovl] = ov[ovl]; - - setenv (nn, nv); - } - - return (1); - } - - if (remove) { - - if (strstr (ov, nv) != NULL) { - - printf ("Removing '%s' from env var '%s'\n", - nv, nn); - - while ((p = strstr (ov, nv)) != NULL) { - q = p + nvl; - if (*q == ' ') - q++; - strcpy(p, q); - } - - setenv (nn, ov); - } - - return (1); - } - - if (!override || strcmp (ov, nv) == 0) - return (1); - - printf ("Re-setting env cmd '%s' from '%s' to '%s'\n", - nn, ov, nv); - } - else - printf ("Setting env cmd '%s' to '%s'\n", nn, nv); - - setenv (nn, nv); - return (1); -} - -void -hymod_check_env (void) -{ - char *p, *path, *curver, *newver; - int firsttime = 0, needsave = 0; - - if (getenv ("global_env_loaded") == NULL) { - puts ("*** global environment has never been loaded\n"); - puts ("*** fetching from server"); - firsttime = 1; - } - else if ((p = getenv ("always_check_env")) != NULL && - strcmp (p, "yes") == 0) - puts ("*** checking for updated global environment"); - else - return; - - puts (" (Control-C to Abort)\n"); - - if ((path = getenv ("global_env_path")) == NULL || *path == '\0') - path = def_global_env_path; - - if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) { - puts ("*** Fetch of global environment failed!\n"); - return; - } - - if ((newver = getenv ("new_genv_version")) == NULL) { - puts ("*** Version number not set - contents ignored!\n"); - return; - } - - if ((curver = getenv ("global_env_version")) == NULL || \ - strcmp (curver, newver) != 0) { - setenv ("global_env_version", newver); - needsave = 1; - } - else - printf ("*** Global environment up-to-date (ver %s)\n", curver); - - setenv ("new_genv_version", NULL); - - if (firsttime) { - setenv ("global_env_loaded", "yes"); - needsave = 1; - } - - if (needsave) - puts ("\n*** Remember to run the 'saveenv' " - "command to save the changes\n\n"); -} diff --git a/board/hymod/fetch.c b/board/hymod/fetch.c deleted file mode 100644 index da9373f..0000000 --- a/board/hymod/fetch.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <net.h> - -/* imports from input.c */ -extern int hymod_get_ethaddr (void); - -int -fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *)) -{ - char *ethaddr; - uchar *fp, *efp; - int rc, count = 0; - - while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') { - - printf ("*** Ethernet address is%s not set\n", - count == 0 ? "" : " STILL"); - - if ((rc = hymod_get_ethaddr ()) < 0) { - if (rc == -1) - puts ("\n*** interrupted!"); - else - puts ("\n*** timeout!"); - printf (" - fetch of '%s' aborted\n", fn); - return (0); - } - - count++; - } - - copy_filename (BootFile, fn, sizeof (BootFile)); - load_addr = addr; - NetBootFileXferSize = 0; - - if (NetLoop(TFTPGET) == 0) { - printf ("tftp transfer of file '%s' failed\n", fn); - return (0); - } - - if (NetBootFileXferSize == 0) { - printf ("can't determine size of file '%s'\n", fn); - return (0); - } - - fp = (uchar *)load_addr; - efp = fp + NetBootFileXferSize; - - do { - uchar *name, *value; - - if (*fp == '#' || *fp == '\n') { - /* skip this line */ - while (fp < efp && *fp++ != '\n') - ; - continue; - } - - name = fp; - - while (fp < efp && *fp != '=' && *fp != '\n') - fp++; - if (fp >= efp) - break; - if (*fp == '\n') { - fp++; - continue; - } - *fp++ = '\0'; - - value = fp; - - while (fp < efp && *fp != '\n') - fp++; - if (fp[-1] == '\r') - fp[-1] = '\0'; - *fp++ = '\0'; /* ok if we go off the end here */ - - if ((*cback)(name, value) == 0) - return (0); - - } while (fp < efp); - - return (1); -} diff --git a/board/hymod/flash.c b/board/hymod/flash.c deleted file mode 100644 index 02e519c..0000000 --- a/board/hymod/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 - */ - -#include <common.h> -#include <mpc8260.h> -#include <board/hymod/flash.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/*----------------------------------------------------------------------- - */ - -/* - * probe for flash bank at address "base" and store info about it - * in the flash_info entry "fip". Fatal error if nothing there. - */ -static void -bank_probe (flash_info_t *fip, volatile bank_addr_t base) -{ - volatile bank_addr_t addr; - bank_word_t word; - int i; - - /* reset the flash */ - *base = BANK_CMD_RST; - - /* put flash into read id mode */ - *base = BANK_CMD_RD_ID; - - /* check the manufacturer id - must be intel */ - word = *BANK_REG_MAN_CODE (base); - if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff)) - panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx", - (unsigned long)word, (unsigned long)base); - - /* check the device id */ - word = *BANK_REG_DEV_CODE (base); - switch (word) { - - case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5; - fip->sector_count = 32; - break; - - case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5; - fip->sector_count = 64; - break; - - case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A; - fip->sector_count = 32; - break; - - case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A; - fip->sector_count = 64; - break; - - case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A; - fip->sector_count = 128; - break; - - default: - panic ("\nbad device code (0x%08lx) at addr 0x%08lx", - (unsigned long)word, (unsigned long)base); - } - - if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT) - panic ("\ntoo many sectors (%d) in flash at address 0x%08lx", - fip->sector_count, (unsigned long)base); - - addr = base; - for (i = 0; i < fip->sector_count; i++) { - fip->start[i] = (unsigned long)addr; - fip->protect[i] = 0; - addr = BANK_ADDR_NEXT_BLK (addr); - } - - fip->size = (bank_size_t)addr - (bank_size_t)base; - - /* reset the flash */ - *base = BANK_CMD_RST; -} - -static void -bank_reset (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - -#ifdef FLASH_DEBUG - printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr); -#endif - - *addr = BANK_CMD_RST; -} - -static void -bank_erase_init (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - int flag; - -#ifdef FLASH_DEBUG - printf ("erasing sector %d, addr = 0x%08lx\n", - sect, (unsigned long)addr); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts (); - -#ifdef FLASH_DEBUG - printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr); -#endif - *addr = BANK_CMD_ERASE1; - *addr = BANK_CMD_ERASE2; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); -} - -static int -bank_erase_poll (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - bank_word_t stat = *addr; - -#ifdef FLASH_DEBUG - printf ("checking status at addr 0x%08lx [0x%08lx]\n", - (unsigned long)addr, (unsigned long)stat); -#endif - - if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) { - if ((stat & BANK_STAT_ERR) != 0) { - printf ("failed on sector %d [0x%08lx] at " - "address 0x%08lx\n", sect, - (unsigned long)stat, (unsigned long)addr); - *addr = BANK_CMD_CLR_STAT; - return (-1); - } - else - return (1); - } - else - return (0); -} - -static int -bank_write_word (volatile bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf ("flash program failed [0x%08lx] at address 0x%08lx\n", - (unsigned long)stat, (unsigned long)addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE); - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - (void)flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if defined(CONFIG_SYS_FLASH_ENV_ADDR) - (void)flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_ENV_ADDR, -#if defined(CONFIG_SYS_FLASH_ENV_BUF) - CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1, -#else - CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1, -#endif - &flash_info[0]); -#endif - - return flash_info[0].size; -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J5: printf ("28F320J5 (32 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F640J5: printf ("28F640J5 (64 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F320J3A: printf ("28F320J3A (32 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F128J3A: printf ("28F320J3A (128 Mbit, 2 x 16bit)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -/*----------------------------------------------------------------------- - */ - -int -flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - int rcode = 0; - -#ifdef FLASH_DEBUG - printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info (info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sector%s will not be erased\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init (info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer (start); - - do { - now = get_timer (start); - - if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - rcode = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll (info, sect); - - if (sectdone < 0) { - haderr = 1; - rcode = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset (info, sect); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Program failed - */ -static int -write_word (flash_info_t *info, ulong dest, ulong data) -{ - /* Check if Flash is (sufficiently) erased */ - if ((*(ulong *)dest & data) != data) - return (2); - - return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Program failed - */ - -int -write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/hymod/flash.h b/board/hymod/flash.h deleted file mode 100644 index 6ea2823..0000000 --- a/board/hymod/flash.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* Commands */ -#define ISF_CMD_RST 0xFF /* reset flash */ -#define ISF_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define ISF_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define ISF_CMD_RD_STAT 0x70 /* read the status register */ -#define ISF_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define ISF_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define ISF_CMD_PROG 0x40 /* program word command */ -#define ISF_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define ISF_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define ISF_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define ISF_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define ISF_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define ISF_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define ISF_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define ISF_STAT_DPS 0x02 /* Device Protect Status */ -#define ISF_STAT_VPPS 0x08 /* VPP Status */ -#define ISF_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define ISF_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define ISF_STAT_ESS 0x40 /* Erase Suspend Status */ -#define ISF_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define ISF_STAT_ERR (ISF_STAT_VPPS | ISF_STAT_DPS | \ - ISF_STAT_ECLBS | ISF_STAT_PSLBS) - -/* register addresses, valid only following an ISF_CMD_RD_ID command */ -#define ISF_REG_MAN_CODE 0x00 /* manufacturer code */ -#define ISF_REG_DEV_CODE 0x01 /* device code */ -#define ISF_REG_BLK_LCK 0x02 /* block lock configuration */ -#define ISF_REG_MST_LCK 0x03 /* master lock configuration */ - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * this code requires that the flash on any Hymod board appear as a bank - * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase - * sectors (or blocks), running in x16 bit mode and connected side-by-side - * to make a 32-bit wide bus. - */ - -typedef unsigned long bank_word_t; -typedef bank_word_t bank_blk_t[64 * 1024]; - -#define BANK_FILL_WORD(b) (((bank_word_t)(b) << 16) | (bank_word_t)(b)) - -#ifdef EXAMPLE - -/* theoretically the following examples should also work */ - -/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */ -typedef unsigned char bank_word_t; -typedef bank_word_t bank_blk_t[128 * 1024]; -#define BANK_FILL_WORD(b) ((bank_word_t)(b)) - -/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */ -typedef unsigned long long bank_word_t; -typedef bank_word_t bank_blk_t[32 * 1024]; -#define BANK_FILL_WORD(b) ( \ - ((bank_word_t)(b) << 48) \ - ((bank_word_t)(b) << 32) \ - ((bank_word_t)(b) << 16) \ - ((bank_word_t)(b) << 0) \ - ) - -#endif /* EXAMPLE */ - -/* the sizes of these two types should probably be the same */ -typedef bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(sizeof (bank_word_t) - 1))) -#define BANK_SIZE_WORD_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_word_t) - 1) \ - & ~(sizeof (bank_word_t) - 1)) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(sizeof (bank_blk_t) - 1))) -#define BANK_SIZE_BLK_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \ - & ~(sizeof (bank_blk_t) - 1)) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) ((bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o))) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - sizeof (bank_word_t)) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - sizeof (bank_blk_t)) - -/* get bank address of register r given a bank base address a and block num b */ -#define BANK_ADDR_REG(a, b, r) BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \ - (bank_size_t)(b) * sizeof (bank_blk_t)), \ - (bank_size_t)(r) * sizeof (bank_word_t)) - -/* make a bank word value for each StrataFlash value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(ISF_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(ISF_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(ISF_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(ISF_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(ISF_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(ISF_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(ISF_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(ISF_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(ISF_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(ISF_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(ISF_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(ISF_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(ISF_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(ISF_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(ISF_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(ISF_STAT_ERR) - -/* make a bank register address for each StrataFlash register address */ - -#define BANK_REG_MAN_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE) -#define BANK_REG_DEV_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE) -#define BANK_REG_BLK_LCK(a, b) BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK) -#define BANK_REG_MST_LCK(a) BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK) diff --git a/board/hymod/global_env b/board/hymod/global_env deleted file mode 100644 index ac12fd7..0000000 --- a/board/hymod/global_env +++ /dev/null @@ -1,145 +0,0 @@ -# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE - -# (C) Copyright 2001 -# Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au -# -# SPDX-License-Identifier: GPL-2.0+ - -# -# global_env -# -# file used by Hymod boards to initialise the u-boot non-volatile -# environment when u-boot is first run (it determines this by the -# absence of the environment variable "global_env_loaded") -# -# format of this file is: -# -# 1. blank lines and lines beginning with '#' are ignored -# 2. all other lines must have the form <name>=<value> -# 3. if a percent appears anywhere, it is replaced like so: -# -# %s serial number of the main board (10 digit zero filled) -# %S serial number of the main board (plain number) -# %% a percentage character -# ... otherwise the %x is discarded -# -# if first character in <name> is a dash ('-'), then an existing env var -# will not be overwritten (the dash is removed). i.e. it is only set if -# it does not exist -# -# if last character in <name> is a plus ('+'), then <value> will be appended -# to any existing env var (the plus is ignored). Duplicates of <value> are -# removed. -# -# similarly, if the last character in <name> is a minus ('-'), then any -# occurences of <value> in the current value of <name> will removed (the -# minus is ignored). -# -# leading and trailing whitespace is removed in both <name> and <value> -# (after processing any initial or final plus/minus in <name>). -# - -# MISCELLANEOUS PARAMETERS - -# version must always come first -version=4 - -# set the ip address based on the main board serial number -ipaddr=192.168.1.%S -serverip=192.168.1.254 - -# stop auto execute after tftp (not a very good name really) -autostart=no - -# setting this to "yes" forces the global_env file to be loaded and processed -# if the current version is different to the version in the file -always_check_env=no - -# BOOTING COMMANDS AND PARAMETERS - -# command to run when "auto-booting" -bootcmd=bootm 40080000 - -# how long the "countdown" to automatically running "bootcmd" is -bootdelay=2 - -# how long before it "times out" console input and attempts to run "bootcmd" -bootretry=5 - -# arguments passed to the boot program (i.e. linux kernel) via register 6 -# the linux kernel (v2.4) uses the following registers: -# r3 - address of board information structure -# r4 - address of initial ramdisk image (0 means no initrd) -# r5 - size of initial ramdisk image -# r6 - address of command line string --bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro - -# these four are for hymod linux integrated into our Sun network -bootargs+=serialno=%S -bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4 -bootargs+=nfsclient -bootargs+=automount - -# start a web server by default -bootargs+=webserver - -# give negotiation time to finish -bootargs+=netsleep=5 - -# then our ciscos don't pass packets for 25-30 secs after that, so -# pinging the server until it responds prevents network connections -# from failing... -bootargs+=netping - -# these are old bootargs - we don't need them anymore -bootargs-=preload=unix,i2c-cpm,i2c-dev -bootargs-=ramdisk_size=32768 -bootargs-=ramdisk_size=24576 - -# FLASH MANIPULATION COMMANDS - -# -# 16M flash, 64 x 256K sectors, mapped at address 0x40000000 -# -# Sector(s) Address Size Description -# -# 0 - 0 0x40000000 256K boot code -# 1 - 1 0x40040000 256K non volatile environment -# 2 - 4 0x40080000 768K linux kernel image -# 5 - 7 0x40140000 768K alternate linux kernel image -# 8 - 47 0x40200000 10M linux initial ramdisk image -# 48 - 63 0x40c00000 4M ramdisk image for applications -# - -fetchboot=tftp 100000 /hymod/u-boot.bin -eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0 -copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0 -cmpboot=cmp.b 100000 40000000 40000 -newboot=run fetchboot eraseboot copyboot cmpboot - -fetchlinux=tftp 100000 /hymod/linux.bin -eraselinux=erase 1:2-4 -copylinux=cp.b 100000 40080000 ${filesize} -cmplinux=cmp.b 100000 40080000 ${filesize} -newlinux=run fetchlinux eraselinux copylinux cmplinux - -fetchaltlinux=tftp 100000 /hymod/altlinux.bin -erasealtlinux=erase 1:5-7 -copyaltlinux=cp.b 100000 40140000 ${filesize} -cmpaltlinux=cmp.b 100000 40140000 ${filesize} -newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux - -fetchroot=tftp 100000 /hymod/root.bin -eraseroot=erase 1:8-47 -copyroot=cp.b 100000 40200000 ${filesize} -cmproot=cmp.b 100000 40200000 ${filesize} -newroot=run fetchroot eraseroot copyroot cmproot - -fetchard=tftp 100000 /hymod/apprd.bin -eraseard=erase 1:48-63 -copyard=cp.b 100000 40c00000 ${filesize} -cmpard=cmp.b 100000 40c00000 ${filesize} -newapprd=run fetchard eraseard copyard cmpard - -# pass above map to linux mtd driver -bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod) diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c deleted file mode 100644 index 0183f78..0000000 --- a/board/hymod/hymod.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 - */ - -#include <common.h> -#include <bootretry.h> -#include <cli.h> -#include <mpc8260.h> -#include <mpc8260_irq.h> -#include <ioports.h> -#include <i2c.h> -#include <asm/iopin_8260.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* imports from eeprom.c */ -extern int hymod_eeprom_read (int, hymod_eeprom_t *); -extern void hymod_eeprom_print (hymod_eeprom_t *); - -/* imports from env.c */ -extern void hymod_check_env (void); - -/* ------------------------------------------------------------------------- */ - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */ - { 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */ - { 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */ - { 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */ - { 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */ - { 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */ - { 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */ - { 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */ - { 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */ - { 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */ - { 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */ - { 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */ - { 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */ - { 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */ - { 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */ - { 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */ - { 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */ - { 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */ - { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */ - { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */ - { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */ - { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */ - }, - - /* Port B configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */ - { 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */ - { 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */ - { 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */ - { 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */ - { 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */ - { 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */ - { 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */ - { 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */ - { 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */ - { 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */ - { 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */ - { 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */ - { 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */ - { 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */ - }, - - /* Port C configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */ - { 0, 0, 0, 0, 0, 0 }, /* PC30: ? */ - { 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */ - { 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */ - { 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */ - { 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */ - { 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */ - { 0, 0, 0, 0, 0, 0 }, /* PC24: ? */ - { 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */ - { 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */ - { 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */ - { 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */ - { 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */ - { 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */ - { 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */ - { 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */ - { 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */ - { 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */ - { 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */ - { 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */ - { 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */ - { 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */ - { 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */ - { 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */ - { 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */ - { 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */ - { 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */ - }, - - /* Port D configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */ - { 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */ - { 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */ - { 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */ - { 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */ - { 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */ - { 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */ - { 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */ - { 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */ - { 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */ - { 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */ - { 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */ - { 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */ - { 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */ - { 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */ - { 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */ - { 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */ - { 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */ - { 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */ - { 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */ - { 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */ - { 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */ - { 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */ - { 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */ - { 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */ - { 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */ - { 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */ - { 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */ - { 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * AMI FS6377 Clock Generator configuration table - * - * the "fs6377_regs[]" table entries correspond to FS6377 registers - * 0 - 15 (total of 16 bytes). - * - * the data is written to the FS6377 via the i2c bus using address in - * "fs6377_addr" (address is 7 bits - R/W bit not included). - * - * The fs6377 has four clock outputs: A, B, C and D. - * - * Outputs C and D can each provide two different clock outputs C1/D1 or - * C2/D2 depending on the state of the SEL_CD input which is connected to - * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0) - * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2. - * - * PA11 defaults to output low (or 0) in the i/o port config table above. - * - * Output A provides a 100MHz for the High Speed Serial chips. Output B - * provides a 3.6864MHz clock for more accurate asynchronous serial bit - * rates. Output C is routed to the mezzanine connector but is currently - * unused - both C1 and C2 are set to 16MHz. Output D is used by both the - * alt-input and display mezzanine boards for their video chips. The - * alt-input board requires a clock of 24.576MHz and this is available on - * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this - * is available on D2 (PA11=SEL_CD=1). - * - * So the default is a clock suitable for the alt-input board. PA11 is toggled - * later in misc_init_r(), if a display board is detected. - */ - -uchar fs6377_addr = 0x5c; - -uchar fs6377_regs[16] = { - 12, 75, 64, 25, 144, 128, 25, 192, - 0, 16, 135, 192, 224, 64, 64, 192 -}; - -/* ------------------------------------------------------------------------- */ - -/* - * special board initialisation, after clocks and timebase have been - * set up but before environment and serial are initialised. - * - * added so that very early initialisations can be done using the i2c - * driver (which requires the clocks, to calculate the dividers, and - * the timebase, for udelay()) - */ - -int -board_postclk_init (void) -{ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* - * Initialise the FS6377 clock chip - * - * the secondary address is the register number from where to - * start the write - I want to write all the registers - * - * don't bother checking return status - we have no console yet - * to print it on, nor any RAM to store it in - it will be obvious - * if this doesn't work - */ - (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs, - sizeof (fs6377_regs)); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: Hardwired to HYMOD - */ - -int -checkboard (void) -{ - puts ("Board: HYMOD\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * miscellaneous (early - while running in flash) initialisations. - */ - -#define _NOT_USED_ 0xFFFFFFFF - -uint upmb_table[] = { - /* Read Single Beat (RSS) - offset 0x00 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Read Burst (RBS) - offset 0x08 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Single Beat (WSS) - offset 0x18 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Burst (WSS) - offset 0x20 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Refresh Timer (PTS) - offset 0x30 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Exception Condition (EXS) - offset 0x3c */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -uint upmc_table[] = { - /* Read Single Beat (RSS) - offset 0x00 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Read Burst (RBS) - offset 0x08 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Single Beat (WSS) - offset 0x18 */ - 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000, - 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Burst (WSS) - offset 0x20 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Refresh Timer (PTS) - offset 0x30 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Exception Condition (EXS) - offset 0x3c */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -int -misc_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - printf ("UPMs: "); - - upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]); - memctl->memc_mbmr = CONFIG_SYS_MBMR; - - upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]); - memctl->memc_mcmr = CONFIG_SYS_MCMR; - - printf ("configured\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t -initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); - ulong psdmr = CONFIG_SYS_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - return (CONFIG_SYS_SDRAM_SIZE << 20); -} - -/* ------------------------------------------------------------------------- */ -/* miscellaneous initialisations after relocation into ram (misc_init_r) */ -/* */ -/* loads the data in the main board and mezzanine board eeproms into */ -/* the hymod configuration struct stored in the board information area. */ -/* */ -/* if the contents of either eeprom is invalid, prompts for a serial */ -/* number (and an ethernet address if required) then fetches a file */ -/* containing information to be stored in the eeprom from the tftp server */ -/* (the file name is based on the serial number and a built-in path) */ - -int -last_stage_init (void) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - int rc; - - /* - * we use the cli_readline() function, but we also want - * command timeout enabled - */ - bootretry_init_cmd_timeout(); - - memset ((void *) cp, 0, sizeof (*cp)); - - /* set up main board config info */ - - rc = hymod_eeprom_read (0, &cp->main.eeprom); - - puts ("EEPROM:main..."); - if (rc < 0) - puts ("NOT PRESENT\n"); - else if (rc == 0) - puts ("INVALID\n"); - else { - cp->main.eeprom.valid = 1; - - printf ("OK (ver %u)\n", cp->main.eeprom.ver); - hymod_eeprom_print (&cp->main.eeprom); - - /* - * hard-wired assumption here: all hymod main boards will have - * one xilinx fpga, with the interrupt line connected to IRQ2 - * - * One day, this might be based on the board type - */ - - cp->main.xlx[0].mmap.prog.exists = 1; - cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE; - cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE; - - cp->main.xlx[0].mmap.reg.exists = 1; - cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE; - cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE; - - cp->main.xlx[0].mmap.port.exists = 1; - cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE; - cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE; - - cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT; - cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN; - cp->main.xlx[0].iopins.prog_pin.flag = 1; - cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT; - cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN; - cp->main.xlx[0].iopins.init_pin.flag = 1; - cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT; - cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN; - cp->main.xlx[0].iopins.done_pin.flag = 1; -#ifdef FPGA_MAIN_ENABLE_PORT - cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT; - cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN; - cp->main.xlx[0].iopins.enable_pin.flag = 1; -#endif - - cp->main.xlx[0].irq = FPGA_MAIN_IRQ; - } - - /* set up mezzanine board config info */ - - rc = hymod_eeprom_read (1, &cp->mezz.eeprom); - - puts ("EEPROM:mezz..."); - if (rc < 0) - puts ("NOT PRESENT\n"); - else if (rc == 0) - puts ("INVALID\n"); - else { - cp->main.eeprom.valid = 1; - - printf ("OK (ver %u)\n", cp->mezz.eeprom.ver); - hymod_eeprom_print (&cp->mezz.eeprom); - } - - cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc)); - - hymod_check_env (); - - return (0); -} - -#ifdef CONFIG_SHOW_ACTIVITY -void board_show_activity (ulong timebase) -{ -#ifdef CONFIG_SYS_HYMOD_DBLEDS - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8260_t *iop = &immr->im_ioport; - static int shift = 0; - - if ((timestamp % CONFIG_SYS_HZ) == 0) { - if (++shift > 3) - shift = 0; - iop->iop_pdatd = - (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift)); - } -#endif /* CONFIG_SYS_HYMOD_DBLEDS */ -} - -void show_activity(int arg) -{ -} -#endif /* CONFIG_SHOW_ACTIVITY */ diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h deleted file mode 100644 index 7024d8a..0000000 --- a/board/hymod/hymod.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _HYMOD_H_ -#define _HYMOD_H_ - -#ifdef CONFIG_MPC8260 -#include <asm/iopin_8260.h> -#endif - -/* - * hymod configuration data - passed by boot code via the board information - * structure (only U-Boot has support for this at the moment) - * - * there are three types of data passed up from the boot monitor. the first - * (type hymod_eeprom_t) is the eeprom data that was read off both the main - * (or mother) board and the mezzanine board (if any). this data defines how - * many Xilinx fpgas are on each board, and their types (among other things). - * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where - * in the physical address space the various Xilinx fpga access regions have - * been mapped by the boot rom. the third type of data (type xlx_iopins_t, - * one per Xilinx fpga) defines which io port pins are connected to the various - * signals required to program a Xilinx fpga. - * - * A ram/flash "bank" refers to memory controlled by the same chip select. - * - * the eeprom contents are defined as in technical note #2 - basically, - * a header, zero or more records in no particular order, and a 32 bit crc - * a record is 1 or more type bytes, a length byte and "length" bytes. - */ - -#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */ -#define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */ -#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */ - -/* eeprom header */ -typedef - struct { - unsigned char id; /* eeprom id byte */ - unsigned char :1; - unsigned char ver:7; /* eeprom contents version number */ - unsigned long len; /* total # of bytes btw hdr and crc */ - } -hymod_eehdr_t; - -/* maximum number of bytes available for eeprom data records */ -#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \ - - sizeof (hymod_eehdr_t) \ - - sizeof (unsigned long)) - -/* eeprom data record */ -typedef - union { - struct { - unsigned char topbit:1; - unsigned char type:7; - unsigned char len; - unsigned char data[1]; /* variable length */ - } small; - struct { - unsigned short topbit:1; - unsigned short nxtbit:1; - unsigned short type:14; - unsigned short len; - unsigned char data[1]; /* variable length */ - } medium; - struct { - unsigned long topbit:1; - unsigned long nxtbit:1; - unsigned long type:30; - unsigned long len; - unsigned char data[1]; /* variable length */ - } large; - } -hymod_eerec_t; - -#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */ -#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */ - -/* eeprom record types */ -#define HYMOD_EEREC_SERNO 1 /* serial number */ -#define HYMOD_EEREC_DATE 2 /* date */ -#define HYMOD_EEREC_BATCH 3 /* batch id */ -#define HYMOD_EEREC_TYPE 4 /* board type */ -#define HYMOD_EEREC_REV 5 /* revision number */ -#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */ -#define HYMOD_EEREC_FLASH 7 /* flash sizes */ -#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */ -#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */ -#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */ -#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */ -#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */ -#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */ -#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */ -#define HYMOD_EEREC_BUSSPD 15 /* bus speed */ -#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */ -#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */ -#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */ -#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */ - -/* some dimensions */ -#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */ -#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */ -#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */ -#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */ -#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */ - -#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */ - -/* board types */ -#define HYMOD_BDTYPE_NONE 0 /* information not present */ -#define HYMOD_BDTYPE_IO 1 /* I/O main board */ -#define HYMOD_BDTYPE_CLP 2 /* CLP main board */ -#define HYMOD_BDTYPE_DSP 3 /* DSP main board */ -#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */ -#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */ -#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */ -#define HYMOD_BDTYPE_MAX 7 /* first invalid value */ - -/* Xilinx fpga types */ -#define HYMOD_XTYP_NONE 0 /* information not present */ -#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */ -#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */ -#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */ -#define HYMOD_XTYP_MAX 4 /* first invalid value */ - -/* Xilinx fpga speeds */ -#define HYMOD_XSPD_NONE 0 /* information not present */ -#define HYMOD_XSPD_SIX 1 -#define HYMOD_XSPD_SEVEN 2 -#define HYMOD_XSPD_EIGHT 3 -#define HYMOD_XSPD_MAX 4 /* first invalid value */ - -/* Xilinx fpga temperatures */ -#define HYMOD_XTMP_NONE 0 /* information not present */ -#define HYMOD_XTMP_COM 1 -#define HYMOD_XTMP_IND 2 -#define HYMOD_XTMP_MAX 3 /* first invalid value */ - -/* Xilinx fpga grades */ -#define HYMOD_XTMP_NONE 0 /* information not present */ -#define HYMOD_XTMP_NORMAL 1 -#define HYMOD_XTMP_ENGSAMP 2 -#define HYMOD_XTMP_MAX 3 /* first invalid value */ - -/* CPU types */ -#define HYMOD_CPUTYPE_NONE 0 /* information not present */ -#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */ -#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */ - -/* CPU/BUS/CPM clock speeds */ -#define HYMOD_CLKSPD_NONE 0 /* information not present */ -#define HYMOD_CLKSPD_33MHZ 1 -#define HYMOD_CLKSPD_66MHZ 2 -#define HYMOD_CLKSPD_100MHZ 3 -#define HYMOD_CLKSPD_133MHZ 4 -#define HYMOD_CLKSPD_166MHZ 5 -#define HYMOD_CLKSPD_200MHZ 6 -#define HYMOD_CLKSPD_MAX 7 /* first invalid value */ - -/* high speed serial chip types */ -#define HYMOD_HSSTYPE_NONE 0 /* information not present */ -#define HYMOD_HSSTYPE_AMCC52064 1 -#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */ - -/* a date (yyyy-mm-dd) */ -typedef - struct { - unsigned short year; - unsigned char month; - unsigned char day; - } -hymod_date_t; - -/* describes a Xilinx fpga */ -typedef - struct { - unsigned char type; /* chip type */ - unsigned char speed; /* chip speed rating */ - unsigned char temp; /* chip temperature rating */ - unsigned char grade; /* chip grade */ - } -hymod_xlx_t; - -/* describes a Motorola embedded processor */ -typedef - struct { - unsigned char type; /* CPU type */ - unsigned char cpuspd; /* speed of the PowerPC core */ - unsigned char busspd; /* speed of the system and 60x bus */ - unsigned char cpmspd; /* speed of the CPM co-processor */ - } -hymod_mpc_t; - -/* info about high-speed (1Gbit) serial interface */ -typedef - struct { - unsigned char type; /* high-speed serial chip type */ - unsigned char nchin; /* number of input channels mounted */ - unsigned char nchout; /* number of output channels mounted */ - } -hymod_hss_t; - -/* - * this defines the contents of the serial eeprom that exists on every - * hymod board, including mezzanine boards (the serial eeprom will be - * faked for early development boards that don't have one) - */ - -typedef - struct { - unsigned char valid:1; /* contents of this struct is valid */ - unsigned char ver:7; /* eeprom contents version */ - unsigned char bdtype; /* board type */ - unsigned char bdrev; /* board revision */ - unsigned char batchlen; /* length of batch string below */ - unsigned long serno; /* serial number */ - hymod_date_t date; /* manufacture date */ - unsigned char batch[32]; /* manufacturer specific batch id */ - unsigned char nsdram; /* # of ram "banks" */ - unsigned char nflash; /* # of flash "banks" */ - unsigned char nzbt; /* # of ZBT rams */ - unsigned char nxlx; /* # of Xilinx fpgas */ - unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */ - unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */ - unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */ - hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */ - hymod_mpc_t mpc; /* Motorola MPC CPU info */ - hymod_hss_t hss; /* high-speed serial info */ - } -hymod_eeprom_t; - -/* - * this defines a region in the processor's physical address space - */ -typedef - struct { - unsigned long exists:1; /* 1 if the region exists, 0 if not */ - unsigned long size:31; /* size in bytes */ - unsigned long base; /* base address */ - } -xlx_prgn_t; - -/* - * this defines where the various Xilinx fpga access regions are mapped - * into the physical address space of the processor - */ -typedef - struct { - xlx_prgn_t prog; /* program access region */ - xlx_prgn_t reg; /* register access region */ - xlx_prgn_t port; /* port access region */ - } -xlx_mmap_t; - -/* - * this defines which 8260 i/o port pins are connected to the various - * signals required for programming a Xilinx fpga - */ -typedef - struct { - iopin_t prog_pin; /* assert for >= 300ns to program */ - iopin_t init_pin; /* goes high when fpga is cleared */ - iopin_t done_pin; /* goes high when program is done */ - iopin_t enable_pin; /* some fpgas need enabling */ - } -xlx_iopins_t; - -/* all info about one Xilinx chip */ -typedef - struct { - xlx_mmap_t mmap; - xlx_iopins_t iopins; - unsigned long irq:8; /* h/w intr req number for this fpga */ - } -xlx_info_t; - -/* all info about one hymod board */ -typedef - struct { - hymod_eeprom_t eeprom; - xlx_info_t xlx[HYMOD_MAX_XLX]; - } -hymod_board_t; - -/* - * this defines the configuration information of a hymod board-set - * (main board + possible mezzanine board). In future, there may be - * more than one mezzanine board (stackable?) - if so, add a "mezz2" - * field, and so on... or make mezz an array? - */ -typedef - struct { - unsigned long ver:8; /* version control */ - hymod_board_t main; /* main board info */ - hymod_board_t mezz; /* mezzanine board info */ - unsigned long crc; /* ensures kernel and boot prom agree */ - } -hymod_conf_t; - -#endif /* _HYMOD_H_ */ diff --git a/board/hymod/input.c b/board/hymod/input.c deleted file mode 100644 index a9035d3..0000000 --- a/board/hymod/input.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <bootretry.h> -#include <cli.h> - -int -hymod_get_serno (const char *prompt) -{ - for (;;) { - int n, serno; - char *p; - - bootretry_reset_cmd_timeout(); - - n = cli_readline(prompt); - - if (n < 0) - return (n); - - if (n == 0) - continue; - - serno = (int) simple_strtol (console_buffer, &p, 10); - - if (p > console_buffer && *p == '\0' && serno > 0) - return (serno); - - printf ("Invalid number (%s) - please re-enter\n", - console_buffer); - } -} - -int -hymod_get_ethaddr (void) -{ - for (;;) { - int n; - - bootretry_reset_cmd_timeout(); - - n = cli_readline("Enter board ethernet address: "); - - if (n < 0) - return (n); - - if (n == 0) - continue; - - if (n == 17) { - int i; - char *p, *q; - - /* see if it looks like an ethernet address */ - - p = console_buffer; - - for (i = 0; i < 6; i++) { - char term = (i == 5 ? '\0' : ':'); - - (void)simple_strtol (p, &q, 16); - - if ((q - p) != 2 || *q++ != term) - break; - - p = q; - } - - if (i == 6) { - /* it looks ok - set it */ - printf ("Setting ethernet addr to %s\n", - console_buffer); - - setenv ("ethaddr", console_buffer); - - puts ("Remember to do a 'saveenv' to " - "make it permanent\n"); - - return (0); - } - } - - printf ("Invalid ethernet addr (%s) - please re-enter\n", - console_buffer); - } -} diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds deleted file mode 100644 index 1dfd2b2..0000000 --- a/board/hymod/u-boot.lds +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8260/start.o (.text) -/* - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; -*/ - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug deleted file mode 100644 index b9c84c7..0000000 --- a/board/hymod/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/hymod_defconfig b/configs/hymod_defconfig deleted file mode 100644 index a6dc1d8..0000000 --- a/configs/hymod_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_HYMOD=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 4e99676..57eac91 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +hymod powerpc mpc8260 - - Murray Jensen Murray.Jensen@csiro.au MHPC powerpc mpc8xx - - Frank Gottschling fgottschling@eltec.de ICU862 powerpc mpc8xx - - Wolfgang Denk wd@denx.de MVBC_P powerpc mpc5xxx af55e35d 2014-09-29 Andre Schwarz andre.schwarz@matrix-vision.de diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 62cb1ea..aef39d7 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -79,9 +79,6 @@ typedef struct bd_info { unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ #endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif

#ifdef CONFIG_HAS_ETH1 unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ diff --git a/include/common.h b/include/common.h index d5020c8..c96b58e 100644 --- a/include/common.h +++ b/include/common.h @@ -69,9 +69,6 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_4xx #include <asm/ppc4xx.h> #endif -#ifdef CONFIG_HYMOD -#include <board/hymod/hymod.h> -#endif #ifdef CONFIG_ARM #define asmlinkage /* nothing */ #endif diff --git a/include/configs/hymod.h b/include/configs/hymod.h deleted file mode 100644 index c973365..0000000 --- a/include/configs/hymod.h +++ /dev/null @@ -1,728 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen Murray.Jensen@cmst.csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for Hymod board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_HYMOD 1 /* ...on a Hymod board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ -#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ - -#ifdef CONFIG_ETHER_ON_FCC - -#if (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK11 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ -# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ -# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ - -#elif (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ -# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) -#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) -#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ - else iop->pdat &= ~MDIO_DATA_PINMASK - -#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ - else iop->pdat &= ~MDIO_CLCK_PINMASK - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - - -/* other options */ -#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ -#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifdef DEBUG -#define CONFIG_8260_CLKIN 33333333 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 115200 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* default ip addresses - these will be overridden */ -#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ -#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ - -#define CONFIG_LAST_STAGE_INIT - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_XIMG - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ -#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press <SPACE> to stop\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 -#endif - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ -#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ -# if defined(CONFIG_KGDB_USE_EXTC) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -# else -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -# endif -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Hymod specific configurable options - */ -#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0x7e - -/* these are for the ST M24C02 2kbit serial i2c eeprom */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ - -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ - -/* - * standard dtt sensor configuration - bottom bit will determine local or - * remote sensor of the ADM1021, the rest determines index into - * CONFIG_SYS_DTT_ADM1021 array below. - * - * On HYMOD board, the remote sensor should be connected to the MPC8260 - * temperature diode thingy, but an errata said this didn't work and - * should be disabled - so it isn't connected. - */ -#if 0 -#define CONFIG_DTT_SENSORS { 0, 1 } -#else -#define CONFIG_DTT_SENSORS { 0 } -#endif - -/* - * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). - * there will be one entry in this array for each two (dummy) sensors in - * CONFIG_DTT_SENSORS. - * - * For HYMOD board: - * - only one ADM1021 - * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT ouput disabled - * - local temp sensor enabled, min set to 0 deg, max set to 85 deg - * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) - */ -#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#ifdef DEBUG -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0010) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0101) -#endif -/* no slaves so just duplicate the master hrcw */ -#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FPGA_BASE 0x80000000 -/* - * unfortunately, CONFIG_SYS_MONITOR_LEN must include the - * (very large i.e. 256kB) environment flash sector - */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#ifdef DEBUG -#define CONFIG_SYS_HID0_FINAL 0 -#else -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#endif -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#ifdef DEBUG -#define CONFIG_SYS_RMR 0 -#else -#define CONFIG_SYS_RMR RMR_CSRE -#endif - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ - SIUMCR_APPC10|SIUMCR_MMR11) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) - * 2 60x SDRAM 64 bit SDRAM - * 3 Local UPMC 8 bit Main Xilinx configuration - * 4 Local GPCM 32 bit Main Xilinx register mode - * 5 Local UPMB 32 bit Main Xilinx port mode - * 6 Local UPMC 8 bit Mezz Xilinx configuration - */ - -/* - * Bank 0 - FLASH - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The flash memory is two Intel StrataFlash chips, each configured for - * 16 bit operation and connected to give a 32 bit wide port." - * - * "The chip select logic is configured to respond to both *CS0 and *CS1. - * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. - * It is suggested that bank 0 be read-only and bank 1 be read/write. The - * FLASH will then appear as ROM during boot." - * - * Initially, we are only going to use bank 0 in read/write mode. - */ - -/* 32 bit, read-write, GPCM on 60x bus */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\ - BRx_PS_32|BRx_MS_GPCM_P|BRx_V) -/* up to 32 Mb */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) - -/* - * Bank 2 - SDRAM - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a - * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous - * dynamic random access memory organised as 4 banks by 4096 rows by 512 - * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." - * - * "The locations in SDRAM are accessed using multiplexed address pins to - * specify row and column. The pins also act to specify commands. The state - * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP - * pin may function as a row address or as the AUTO PRECHARGE control line, - * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 - * address lines to be configured to the required multiplexing scheme." - */ - -#define CONFIG_SYS_SDRAM_SIZE 64 - -/* 64 bit, read-write, SDRAM on 60x bus */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\ - BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) -/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\ - ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) - -/* - * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: - * - * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 - * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 - * as bank select, A7 is output on SDA10 during an ACTIVATE command, - * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, - * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE - * command is 2 clocks, earliest timing for PRECHARGE after last data - * was read is 1 clock, earliest timing for PRECHARGE after last data - * was written is 1 clock, CAS Latency is 2. - */ - -#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ - PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ - PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ - PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ - PSDMR_WRC_1C|PSDMR_CL_2) - -/* - * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh - * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register - * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer - * Prescaler, hence the P instead of the R). The refresh timer period is given - * by (note that there was a change in the 8260 UM Errata): - * - * TimerPeriod = (PSRT + 1) / Fmptc - * - * where Fmptc is the BusClock divided by PTP. i.e. - * - * TimerPeriod = (PSRT + 1) / (BusClock / PTP) - * - * or - * - * TImerPeriod = (PTP * (PSRT + 1)) / BusClock - * - * The requirement for the Toshiba TC59SM716FTL-10 is that there must be - * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 - * = 15.625 usecs. - * - * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 - * appear to be reasonable. - */ - -#ifdef DEBUG -#define CONFIG_SYS_PSRT 39 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 -#else -#define CONFIG_SYS_PSRT 31 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#endif - -/* - * Banks 3,4,5 and 6 - FPGA access - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made - * for configuring an optional FPGA on the mezzanine interface. - * - * Access to the FPGAs may be divided into several catagories: - * - * 1. Configuration - * 2. Register mode access - * 3. Port mode access - * - * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be - * configured only (mode 1). Consequently there are four access types. - * - * To improve interface performance and simplify software design, the four - * possible access types are separately mapped to different memory banks. - * - * All are accessed using the local bus." - * - * Device Mode Memory Bank Machine Port Size Access - * - * Main Configuration 3 UPMC 8bit R/W - * Main Register 4 GPCM 32bit R/W - * Main Port 5 UPMB 32bit R/W - * Mezzanine Configuration 6 UPMC 8bit W/O - * - * "Note that mezzanine mode 1 access is write-only." - */ - -/* all the bank sizes must be a power of two, greater or equal to 32768 */ -#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) -#define FPGA_MAIN_CFG_SIZE 32768 -#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) -#define FPGA_MAIN_REG_SIZE 32768 -#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) -#define FPGA_MAIN_PORT_SIZE 32768 -#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) -#define FPGA_MEZZ_CFG_SIZE 32768 - -/* 8 bit, read-write, UPMC */ -#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) - -/* 32 bit, read-write, GPCM */ -#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) -/* up to 32Kbyte */ -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) - -/* 32 bit, read-write, UPMB */ -#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) -/* up to 32Kbyte */ -#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) - -/* 8 bit, write-only, UPMC */ -#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) - -/*----------------------------------------------------------------------- - * MBMR - Machine B Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ - -/*----------------------------------------------------------------------- - * MCMR - Machine C Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ - -/* - * FPGA I/O Port/Bit information - */ - -#define FPGA_MAIN_PROG_PORT IOPIN_PORTA -#define FPGA_MAIN_PROG_PIN 4 /* PA4 */ -#define FPGA_MAIN_INIT_PORT IOPIN_PORTA -#define FPGA_MAIN_INIT_PIN 5 /* PA5 */ -#define FPGA_MAIN_DONE_PORT IOPIN_PORTA -#define FPGA_MAIN_DONE_PIN 6 /* PA6 */ - -#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA -#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ -#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA -#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ -#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA -#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ -#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA -#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ - -/* - * FPGA Interrupt configuration - */ -#define FPGA_MAIN_IRQ SIU_INT_IRQ2 - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/tools/bddb/README b/tools/bddb/README deleted file mode 100644 index 9bee59a..0000000 --- a/tools/bddb/README +++ /dev/null @@ -1,116 +0,0 @@ -Hymod Board Database - -(C) Copyright 2001 -Murray Jensen Murray.Jensen@csiro.au -CSIRO Manufacturing Science and Technology, Preston Lab - -25-Jun-01 - -This stuff is a set of PHP/MySQL scripts to implement a custom board -database. It will need *extensive* hacking to modify it to keep the -information about your custom boards that you want, however it is a good -starting point. - -How it is used: - - 1. a board has gone through all the hardware testing etc and is - ready to have the flash programmed for the first time - first you - go to a web page and fill in information about the board in a form - to register it in a database - - 2. the web stuff allocates a (unique) serial number and (optionally) - a (locally administered) ethernet address and stores the information - in a database using the serial number as the key (can do whole - batches of boards in one go and/or use a previously registered board - as defaults for the new board(s)) - - 3. it then creates a file in the tftp area of a server somewhere - containing the board information in a simple text format (one - per serial number) - - 4. all hymod boards have an i2c eeprom, and when U-Boot sees that - the eeprom is unitialised, it prompts for a serial number and - ethernet address (if not set), then transfers the file created - in step 3 from the server and initialises the eeprom from its - contents - -What this means is you can't boot the board until you have allocated a serial -number, but you don't have to type it all twice - you do it once on the web -and the board then finds the info it needs to initialise its eeprom. The -other side of the coin is the reading of the eeprom and how it gets passed -to Linux (or another O/S). - -To see how this is all done for the hymod boards look at the code in the -"board/hymod" directory and in the file "include/asm/hymod.h". Hymod boards -can have a mezzanine card which also have an eeprom that needs allocating, -the same process is used for these as well - just a different i2c address. - -Other forms provide the following functions: - - - browsing the board database - - editing board information (one at a time) - - maintaining/browsing a (simple) per board event log - -You will need: MySQL (I use version 3.23.7-alpha), PHP4 (with MySQL -support enabled) and a web server (I use Apache 1.3.x). - -I originally started by using phpMyBuilder (http://kyber.dk/phpMyBuilder) -but it soon got far more complicated than that could handle (but I left -the copyright messages in there anyway). Most of the code resides in the -common defs.php file, which shouldn't need much alteration - all the work -will be in shaping the front-end php files to your liking. - -Here's a quick summary of what needs doing to use it for your boards: - -1. get phpMyAdmin (http://phpwizard.net/projects/phpMyAdmin/) - it's an - invaluable tool for this sort of stuff (this step is optional of course) - -2. edit "bddb.css" to your taste, if you could be bothered - I have no - idea what is in there or what it does - I copied it from somewhere else - ("user.css" from the phpMyEdit (http://phpmyedit.sourcerforge.net) package, - I think) - I figure one day I'll see what sort of things I can change - in there. - -3. create a mysql database - call it whatever you like - -4. edit "create_tables.sql" and modify the "boards" table schema to - reflect the information you want to keep about your boards. It may or - may not be easier to do this and the next step in phpMyAdmin. Check out - the MySQL documentation at http://www.mysql.com/doc/ in particular the - column types at http://www.mysql.com/doc/C/o/Column_types.html - Note - there is only support for a few data types: - - int - presented as an html text input - char/text - presented as an html text input - date - presented as an html text input - enum - presented as an html radio input - - I also have what I call "enum_multi" which is a set of enums with the - same name, but suffixed with a number e.g. fred0, fred1, fred2. These - are presented as a number of html select's with a single label "fred" - this is useful for board characteristics that have multiple items of - the same type e.g. multiple banks of sdram. - -5. use the "create_tables.sql" file to create the "boards" table in the - database e.g. mysql dbname < create_tables.sql - -6. create a user and password for the web server to log into the MySQL - database with; give this user select, insert and update privileges - to the database created in 3 (and delete, if you want the "delete" - functions in the edit forms to work- I have this turned off). phpMyAdmin - helps in this step. - -7. edit "config.php" and set the variables: $mysql_user, $mysql_pw, $mysql_db, - $bddb_cfgdir and $bddb_label - keep the contents of this file secret - it - contains the web servers username and password (the three $mysql_* vars - are set from the previous step) - -8. edit "defs.php" and a. adjust the various enum value arrays and b. edit - the function "pg_foot()" to remove my email address :-) - -9. do major hacking on the following files: browse.php, doedit.php, donew.php, - edit.php and new.php to reflect your database schema - fortunately the - hacking is fairly straight-forward, but it is boring and time-consuming. - -These notes were written rather hastily - if you find any obvious problems -please let me know. diff --git a/tools/bddb/badsubmit.php b/tools/bddb/badsubmit.php deleted file mode 100644 index 5092a31..0000000 --- a/tools/bddb/badsubmit.php +++ /dev/null @@ -1,23 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - require("defs.php"); - pg_head("$bddb_label - Unknown Submit Type"); -?> -<center> - <font size="+4"> - <b> - The <?php echo "$bddb_label"; ?> form was submitted with an - unknown SUBMIT type <?php echo "(value was '$submit')" ?>. - <br></br> - Perhaps you typed the URL in directly? Click here to go to the - home page of the <a href="index.php"><?php echo "$bddb_label"; ?></a>. - </b> - </font> -</center> -<?php - pg_foot(); -?> diff --git a/tools/bddb/bddb.css b/tools/bddb/bddb.css deleted file mode 100644 index dee2b2e..0000000 --- a/tools/bddb/bddb.css +++ /dev/null @@ -1,207 +0,0 @@ -BODY { - background: #e0ffff; - color: #000000; - font-family: Arial, Verdana, Helvetica; -} -H1 { - font-family: "Copperplate Gothic Bold"; - background: transparent; - color: #993300; - text-align: center; -} -H2, H3, H4, H5 { - background: transparent; - color: #993300; - margin-top: 4%; - text-align: center; -} -Body.Plain Div.Abstract, Body.Plain P.Abstract { - background: #cccc99; - color: #333300; - border: white; - padding: 3%; - font-family: Times, Verdana; -} -TH.Nav { - background: #0000cc; - color: #ff9900; -} -TH.Menu { - background: #3366cc; - color: #ff9900; -} -A:hover { - color: #ff6600; -} -A.Menu:hover { - color: #ff6600; -} -A.HoMe:hover { - color: #ff6600; -} -A.Menu { - background: transparent; - color: #ffcc33; - font-family: Verdana, Helvetica, Arial; - font-size: smaller; - text-decoration: none; -} -A.Menu:visited { - background: transparent; - color: #ffcc99; -} -A.HoMe { - background: transparent; - color: #ffcc33; - font-family: Verdana, Helvetica, Arial; - text-decoration:none; -} -A.HoMe:visited { - background: transparent; - color: #ffcc99; -} -TH.Xmp { - background: #eeeeee; - color: #330066; - font-family: courier; - font-weight: normal; -} -TH.LuT { - background: #cccccc; - color: #000000; -} -TD.LuT { - background: #ffffcc; - color: #000000; - font-size: 85%; -} -TH.Info, TD.Info { - background: #ffffcc; - color: #660000; - font-family: "Comic Sans MS", Cursive, Verdana; - font-size: smaller; -} -Div.Info, P.Info { - background: #ffff99; - color: #990033; - text-align: left; - padding: 2%; - font-family: "Comic Sans MS", Cursive, Verdana; - font-size: 85%; - } -Div.Info A { - background: transparent; - color: #ff6600; -} -.HL { - background: #ffff99; - color: #000000; -} -TD.HL { - background: #ccffff; - color: #000000; -} -Div.Margins { - width: 512px; - text-align: center; -} -TD.Plain { - background: #ffffcc; - color: #000033; -} -.Type { - background: #cccccc; - color: #660000; -} -.Name { - background: #eeeeee; - color: #660000; - vertical-align: top; - text-align: right; -} -.Value { - background: #ffffee; - color: #000066; -} -.Drop { - background: #333366; - color: #ffcc33; - font-family: "Copperplate Gothic Light", Helvetica, Verdana, Arial; -} -A.Button:hover { - color: #ff6600; -} -A.Button { - text-decoration:none; - color: #003366; - background: #ffcc66; -} -.Button { - font-size: 9pt; - text-align: center; - text-decoration:none; - color: #003366; - background: #ffcc66; - margin-bottom: 2pt; - border-top: 2px solid #ffff99; - border-left: 2px solid #ffff99; - border-right: 2px solid #cc9933; - border-bottom: 2px solid #cc9933; - font-family: Verdana, Arial, "Comic Sans MS"; -} -.Banner { - width: 468; - font-size: 12pt; - text-align: center; - text-decoration:none; - color: #003366; - background: #ffcc66; - border-top: 4px solid #ffff99; - border-left: 4px solid #ffff99; - border-right: 4px solid #cc9933; - border-bottom: 4px solid #cc9933; - font-family: Verdana, Arial, "Comic Sans MS"; -} -TD.Nova, Body.Nova { - background: #000000; - font-family: "Times New Roman"; - font-weight: light; - color: #ffcc00; -} -Body.Nova A.Button { - background: gold; - color: #003366; -} -Body.Nova A.Banner { - background: transparent; - color: #003366; -} -Body.Nova A { - background: transparent; - text-decoration:none; - color: #ffd766; -} -Body.Nova H1, Body.Nova H2, Body.Nova H3, Body.Nova H4 { - background: transparent; - color: white; - margin-top: 4%; - text-align: center; - filter: Blur(Add=1, Direction=0, Strength=8); -} -Body.Nova Div.Abstract { - background: #000000; - color: #ffffff; - font-family: Times, Verdana; -} -Body.Nova A.Abstract { - background: transparent; - color: #ffeedd; -} -Body.Nova TH.LuT { - background: black; - color: #ffff99; -} -Body.Nova TD.LuT { - background: navy; - color: #ffff99; -} diff --git a/tools/bddb/brlog.php b/tools/bddb/brlog.php deleted file mode 100644 index fccfbd0..0000000 --- a/tools/bddb/brlog.php +++ /dev/null @@ -1,109 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // list page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Browse Board Log"); - - $serno=intval($serno); - if ($serno == 0) - die("serial number not specified or invalid!"); - - function print_cell($str) { - if ($str == '') - $str = '&nbsp;'; - echo "\t<td>$str</td>\n"; - } -?> -<table align=center border=1 cellpadding=10> -<tr> -<th>serno / edit</th> -<th>ethaddr</th> -<th>date</th> -<th>batch</th> -<th>type</th> -<th>rev</th> -<th>location</th> -</tr> -<?php - $r=mysql_query("select * from boards where serno=$serno"); - - while($row=mysql_fetch_array($r)){ - foreach ($columns as $key) { - if (!key_in_array($key, $row)) - $row[$key] = ''; - } - - echo "<tr>\n"; - print_cell("<a href=\"edit.php?serno=$row[serno]\">$row[serno]</a>"); - print_cell($row['ethaddr']); - print_cell($row['date']); - print_cell($row['batch']); - print_cell($row['type']); - print_cell($row['rev']); - print_cell($row['location']); - echo "</tr>\n"; - } - - mysql_free_result($r); -?> -</table> -<hr></hr> -<p></p> -<?php - $limit=abs(isset($_REQUEST['limit'])?$_REQUEST['limit']:20); - $offset=abs(isset($_REQUEST['offset'])?$_REQUEST['offset']:0); - $lr=mysql_query("select count(*) as n from log where serno=$serno"); - $lrow=mysql_fetch_array($lr); - if($lrow['n']>$limit){ - $preoffset=max(0,$offset-$limit); - $postoffset=$offset+$limit; - echo "<table width=\"100%\">\n<tr align=center>\n"; - printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"&lt;\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset); - printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"&gt;\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset); - echo "</tr>\n</table>\n"; - } - mysql_free_result($lr); -?> -<table width="100%" border=1 cellpadding=10> -<tr valign=top> -<th>logno / edit</th> -<th>date</th> -<th>who</th> -<th width="70%">details</th> -</tr> -<?php - $r=mysql_query("select * from log where serno=$serno order by logno limit $offset,$limit"); - - while($row=mysql_fetch_array($r)){ - echo "<tr>\n"; - print_cell("<a href=\"edlog.php?serno=$row[serno]&logno=$row[logno]\">$row[logno]</a>"); - print_cell($row['date']); - print_cell($row['who']); - print_cell("<pre>" . urldecode($row['details']) . "</pre>"); - echo "</tr>\n"; - } - - mysql_free_result($r); -?> -</table> -<hr></hr> -<p></p> -<table width="100%"> -<tr> - <td align=center> - <a href="newlog.php?serno=<?php echo "$serno"; ?>">Add to Log</a> - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/browse.php b/tools/bddb/browse.php deleted file mode 100644 index 675dfab..0000000 --- a/tools/bddb/browse.php +++ /dev/null @@ -1,147 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // list page (hymod_bddb / boards) - - require("defs.php"); - - $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:''; - - $verbose=isset($_REQUEST['verbose'])?intval($_REQUEST['verbose']):0; - - pg_head("$bddb_label - Browse database" . ($verbose?" (verbose)":"")); -?> -<p></p> -<?php - $limit=isset($_REQUEST['limit'])?abs(intval($_REQUEST['limit'])):20; - $offset=isset($_REQUEST['offset'])?abs(intval($_REQUEST['offset'])):0; - - if ($serno == '') { - - $lr=mysql_query("select count(*) as n from boards"); - $lrow=mysql_fetch_array($lr); - - if($lrow['n']>$limit){ - $preoffset=max(0,$offset-$limit); - $postoffset=$offset+$limit; - echo "<table width=\"100%\">\n<tr>\n"; - printf("<td align=left><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"&lt;\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset, $verbose); - printf("<td align=right><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"&gt;\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset, $offset); - echo "</tr>\n</table>\n"; - } - - mysql_free_result($lr); - } -?> -<table align=center border=1 cellpadding=10> -<tr> -<th></th> -<th>serno / edit</th> -<th>ethaddr</th> -<th>date</th> -<th>batch</th> -<th>type</th> -<th>rev</th> -<th>location</th> -<?php - if ($verbose) { - echo "<th>comments</th>\n"; - echo "<th>sdram</th>\n"; - echo "<th>flash</th>\n"; - echo "<th>zbt</th>\n"; - echo "<th>xlxtyp</th>\n"; - echo "<th>xlxspd</th>\n"; - echo "<th>xlxtmp</th>\n"; - echo "<th>xlxgrd</th>\n"; - echo "<th>cputyp</th>\n"; - echo "<th>cpuspd</th>\n"; - echo "<th>cpmspd</th>\n"; - echo "<th>busspd</th>\n"; - echo "<th>hstype</th>\n"; - echo "<th>hschin</th>\n"; - echo "<th>hschout</th>\n"; - } -?> -</tr> -<?php - $query = "select * from boards"; - if ($serno != '') { - $pre = " where "; - foreach (preg_split("/[\s,]+/", $serno) as $s) { - if (preg_match('/^[0-9]+$/',$s)) - $query .= $pre . "serno=" . $s; - else if (preg_match('/^([0-9]+)-([0-9]+)$/',$s,$m)) { - $m1 = intval($m[1]); $m2 = intval($m[2]); - if ($m2 <= $m1) - die("bad serial number range ($s)"); - $query .= $pre . "(serno>=$m[1] and serno<=$m[2])"; - } - else - die("illegal serial number ($s)"); - $pre = " or "; - } - } - $query .= " order by serno"; - if ($serno == '') - $query .= " limit $offset,$limit"; - - $r = mysql_query($query); - - function print_cell($str) { - if ($str == '') - $str = '&nbsp;'; - echo "\t<td>$str</td>\n"; - } - - while($row=mysql_fetch_array($r)){ - foreach ($columns as $key) { - if (!key_in_array($key, $row)) - $row[$key] = ''; - } - - echo "<tr>\n"; - print_cell("<a href=\"brlog.php?serno=$row[serno]\">Log</a>"); - print_cell("<a href=\"edit.php?serno=$row[serno]\">$row[serno]</a>"); - print_cell($row['ethaddr']); - print_cell($row['date']); - print_cell($row['batch']); - print_cell($row['type']); - print_cell($row['rev']); - print_cell($row['location']); - if ($verbose) { - print_cell("<pre>\n" . urldecode($row['comments']) . - "\n\t</pre>"); - print_cell(gather_enum_multi_print("sdram", 4, $row)); - print_cell(gather_enum_multi_print("flash", 4, $row)); - print_cell(gather_enum_multi_print("zbt", 16, $row)); - print_cell(gather_enum_multi_print("xlxtyp", 4, $row)); - print_cell(gather_enum_multi_print("xlxspd", 4, $row)); - print_cell(gather_enum_multi_print("xlxtmp", 4, $row)); - print_cell(gather_enum_multi_print("xlxgrd", 4, $row)); - print_cell($row['cputyp']); - print_cell($row['cpuspd']); - print_cell($row['cpmspd']); - print_cell($row['busspd']); - print_cell($row['hstype']); - print_cell($row['hschin']); - print_cell($row['hschout']); - } - echo "</tr>\n"; - } -?> -</table> -<p></p> -<table width="100%"> -<tr> - <td align=center><?php - printf("<a href=\"%s?submit=Browse&offset=%d&verbose=%d%s\">%s Listing</a>\n", $PHP_SELF, $offset, $verbose?0:1, $serno!=''?"&serno=$serno":'', $verbose?"Terse":"Verbose"); - ?></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/config.php b/tools/bddb/config.php deleted file mode 100644 index 6725757..0000000 --- a/tools/bddb/config.php +++ /dev/null @@ -1,16 +0,0 @@ -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // mysql database access info - $mysql_user="fred"; - $mysql_pw="apassword"; - $mysql_db="mydbname"; - - // where to put the eeprom config files - $bddb_cfgdir = '/tftpboot/bddb'; - - // what this database is called - $bddb_label = 'Hymod Board Database'; -?> diff --git a/tools/bddb/create_tables.sql b/tools/bddb/create_tables.sql deleted file mode 100644 index a2a5788..0000000 --- a/tools/bddb/create_tables.sql +++ /dev/null @@ -1,90 +0,0 @@ -# phpMyAdmin MySQL-Dump -# http://phpwizard.net/phpMyAdmin/ -# -# Host: localhost Database : hymod_bddb - -# (C) Copyright 2001 -# Murray Jensen Murray.Jensen@csiro.au -# CSIRO Manufacturing and Infrastructure Technology, Preston Lab - -# -------------------------------------------------------- -# -# Table structure for table 'boards' -# - -DROP TABLE IF EXISTS boards; -CREATE TABLE boards ( - serno int(10) unsigned zerofill NOT NULL auto_increment, - ethaddr char(17), - date date NOT NULL, - batch char(32), - type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') NOT NULL, - rev tinyint(3) unsigned zerofill NOT NULL, - location char(64), - comments text, - sdram0 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram1 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram2 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram3 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - flash0 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash1 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash2 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash3 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - zbt0 enum('512K','1M','2M','4M','8M','16M'), - zbt1 enum('512K','1M','2M','4M','8M','16M'), - zbt2 enum('512K','1M','2M','4M','8M','16M'), - zbt3 enum('512K','1M','2M','4M','8M','16M'), - zbt4 enum('512K','1M','2M','4M','8M','16M'), - zbt5 enum('512K','1M','2M','4M','8M','16M'), - zbt6 enum('512K','1M','2M','4M','8M','16M'), - zbt7 enum('512K','1M','2M','4M','8M','16M'), - zbt8 enum('512K','1M','2M','4M','8M','16M'), - zbt9 enum('512K','1M','2M','4M','8M','16M'), - zbta enum('512K','1M','2M','4M','8M','16M'), - zbtb enum('512K','1M','2M','4M','8M','16M'), - zbtc enum('512K','1M','2M','4M','8M','16M'), - zbtd enum('512K','1M','2M','4M','8M','16M'), - zbte enum('512K','1M','2M','4M','8M','16M'), - zbtf enum('512K','1M','2M','4M','8M','16M'), - xlxtyp0 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp1 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp2 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp3 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxspd0 enum('6','7','8','4','5','9','10','11','12'), - xlxspd1 enum('6','7','8','4','5','9','10','11','12'), - xlxspd2 enum('6','7','8','4','5','9','10','11','12'), - xlxspd3 enum('6','7','8','4','5','9','10','11','12'), - xlxtmp0 enum('COM','IND'), - xlxtmp1 enum('COM','IND'), - xlxtmp2 enum('COM','IND'), - xlxtmp3 enum('COM','IND'), - xlxgrd0 enum('NORMAL','ENGSAMP'), - xlxgrd1 enum('NORMAL','ENGSAMP'), - xlxgrd2 enum('NORMAL','ENGSAMP'), - xlxgrd3 enum('NORMAL','ENGSAMP'), - cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'), - cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - hstype enum('AMCC-S2064A','Xilinx-Rockets'), - hschin enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'), - hschout enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'), - PRIMARY KEY (serno), - KEY serno (serno), - UNIQUE serno_2 (serno) -); - -# -# Table structure for table 'log' -# - -DROP TABLE IF EXISTS log; -CREATE TABLE log ( - logno int(10) unsigned zerofill NOT NULL auto_increment, - serno int(10) unsigned zerofill NOT NULL, - date date NOT NULL, - details text NOT NULL, - PRIMARY KEY (logno), - KEY logno (logno, serno, date), - UNIQUE logno_2 (logno) -); diff --git a/tools/bddb/defs.php b/tools/bddb/defs.php deleted file mode 100644 index 0b50602..0000000 --- a/tools/bddb/defs.php +++ /dev/null @@ -1,710 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // contains mysql user id and password - keep secret - require("config.php"); - - if (isset($_REQUEST['logout'])) { - Header("status: 401 Unauthorized"); - Header("HTTP/1.0 401 Unauthorized"); - Header("WWW-authenticate: basic realm=\"$bddb_label\""); - - echo "<html><head><title>" . - "Access to '$bddb_label' Denied" . - "</title></head>\n"; - echo "<body bgcolor=#ffffff><br></br><br></br><center><h1>" . - "You must be an Authorised User " . - "to access the '$bddb_label'" . - "</h1>\n</center></body></html>\n"; - exit; - } - - // contents of the various enumerated types - if first item is - // empty ('') then the enum is allowed to be null (ie "not null" - // is not set on the column) - - // all column names in the database table - $columns = array( - 'serno','ethaddr','date','batch', - 'type','rev','location','comments', - 'sdram0','sdram1','sdram2','sdram3', - 'flash0','flash1','flash2','flash3', - 'zbt0','zbt1','zbt2','zbt3','zbt4','zbt5','zbt6','zbt7', - 'zbt8','zbt9','zbta','zbtb','zbtc','zbtd','zbte','zbtf', - 'xlxtyp0','xlxtyp1','xlxtyp2','xlxtyp3', - 'xlxspd0','xlxspd1','xlxspd2','xlxspd3', - 'xlxtmp0','xlxtmp1','xlxtmp2','xlxtmp3', - 'xlxgrd0','xlxgrd1','xlxgrd2','xlxgrd3', - 'cputyp','cpuspd','cpmspd','busspd', - 'hstype','hschin','hschout' - ); - - // board type - $type_vals = array('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY'); - - // Xilinx fpga types - $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'); - - // Xilinx fpga speeds - $xlxspd_vals = array('','6','7','8','4','5','9','10','11','12'); - - // Xilinx fpga temperatures (commercial or industrial) - $xlxtmp_vals = array('','COM','IND'); - - // Xilinx fpga grades (normal or engineering sample) - $xlxgrd_vals = array('','NORMAL','ENGSAMP'); - - // CPU types - $cputyp_vals = array('','MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'); - - // CPU/BUS/CPM clock speeds - $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'); - - // sdram sizes (nbits array is for eeprom config file) - $sdram_vals = array('','32M','64M','128M','256M','512M','1G','2G','4G'); - $sdram_nbits = array(0,25,26,27,28,29,30,31,32); - - // flash sizes (nbits array is for eeprom config file) - $flash_vals = array('','4M','8M','16M','32M','64M','128M','256M','512M','1G'); - $flash_nbits = array(0,22,23,24,25,26,27,28,29,30); - - // zbt ram sizes (nbits array is for write into eeprom config file) - $zbt_vals = array('','512K','1M','2M','4M','8M','16M'); - $zbt_nbits = array(0,19,20,21,22,23,24); - - // high-speed serial attributes - $hstype_vals = array('','AMCC-S2064A','Xilinx-Rockets'); - $hschin_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'); - $hschout_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'); - - // value filters - used when outputting html - function rev_filter($num) { - if ($num == 0) - return "001"; - else - return sprintf("%03d", $num); - } - - function text_filter($str) { - return urldecode($str); - } - - mt_srand(time() | getmypid()); - - // set up MySQL connection - mysql_connect("", $mysql_user, $mysql_pw) || die("cannot connect"); - mysql_select_db($mysql_db) || die("cannot select db"); - - // page header - function pg_head($title) - { - echo "<html>\n<head>\n"; - echo "<link rel=stylesheet href=\"bddb.css\" type=\"text/css\" title=\"style sheet\"></link>\n"; - echo "<title>$title</title>\n"; - echo "</head>\n"; - echo "<body>\n"; - echo "<center><h1>$title</h1></center>\n"; - echo "<hr></hr>\n"; - } - - // page footer - function pg_foot() - { - echo "<hr></hr>\n"; - echo "<table width=\"100%\"><tr><td align=left>\n<address>" . - "If you have any problems, email " . - "<a href=\"mailto:Murray.Jensen@csiro.au\">" . - "Murray Jensen" . - "</a></address>\n" . - "</td><td align=right>\n" . - "<a href=\"index.php?logout=true\">logout</a>\n" . - "</td></tr></table>\n"; - echo "<p><small><i>Made with " . - "<a href=\"http://kyber.dk/phpMyBuilder/\">" . - "Kyber phpMyBuilder</a></i></small></p>\n"; - echo "</body>\n"; - echo "</html>\n"; - } - - // some support functions - - if (!function_exists('array_search')) { - - function array_search($needle, $haystack, $strict = false) { - - if (is_array($haystack) && count($haystack)) { - - $ntype = gettype($needle); - - foreach ($haystack as $key => $value) { - - if ($value == $needle && (!$strict || - gettype($value) == $ntype)) - return $key; - } - } - - return false; - } - } - - if (!function_exists('in_array')) { - - function in_array($needle, $haystack, $strict = false) { - - if (is_array($haystack) && count($haystack)) { - - $ntype = gettype($needle); - - foreach ($haystack as $key => $value) { - - if ($value == $needle && (!$strict || - gettype($value) == $ntype)) - return true; - } - } - - return false; - } - } - - function key_in_array($key, $array) { - return in_array($key, array_keys($array), true); - } - - function enum_to_index($name, $vals) { - $index = array_search($GLOBALS[$name], $vals); - if ($vals[0] != '') - $index++; - return $index; - } - - // fetch a value from an array - return empty string is not present - function get_key_value($key, $array) { - if (key_in_array($key, $array)) - return $array[$key]; - else - return ''; - } - - function fprintf() { - $n = func_num_args(); - if ($n < 2) - return FALSE; - $a = func_get_args(); - $fp = array_shift($a); - $x = "\$s = sprintf"; - $sep = '('; - foreach ($a as $z) { - $x .= "$sep'$z'"; - $sep = ','; - } - $x .= ');'; - eval($x); - $l = strlen($s); - $r = fwrite($fp, $s, $l); - if ($r != $l) - return FALSE; - else - return TRUE; - } - - // functions to display (print) a database table and its columns - - function begin_table($ncols) { - global $table_ncols; - $table_ncols = $ncols; - echo "<table align=center width=\"100%\"" - . " border=1 cellpadding=4 cols=$table_ncols>\n"; - } - - function begin_field($name, $span = 0) { - global $table_ncols; - echo "<tr valign=top>\n"; - echo "\t<th align=center>$name</th>\n"; - if ($span <= 0) - $span = $table_ncols - 1; - if ($span > 1) - echo "\t<td colspan=$span>\n"; - else - echo "\t<td>\n"; - } - - function cont_field($span = 1) { - echo "\t</td>\n"; - if ($span > 1) - echo "\t<td colspan=$span>\n"; - else - echo "\t<td>\n"; - } - - function end_field() { - echo "\t</td>\n"; - echo "</tr>\n"; - } - - function end_table() { - echo "</table>\n"; - } - - function print_field($name, $array, $size = 0, $filt='') { - - begin_field($name); - - if (key_in_array($name, $array)) - $value = $array[$name]; - else - $value = ''; - - if ($filt != '') - $value = $filt($value); - - echo "\t\t<input name=$name value=\"$value\""; - if ($size > 0) - echo " size=$size maxlength=$size"; - echo "></input>\n"; - - end_field(); - } - - function print_field_multiline($name, $array, $cols, $rows, $filt='') { - - begin_field($name); - - if (key_in_array($name, $array)) - $value = $array[$name]; - else - $value = ''; - - if ($filt != '') - $value = $filt($value); - - echo "\t\t<textarea name=$name " . - "cols=$cols rows=$rows wrap=off>\n"; - echo "$value"; - echo "</textarea>\n"; - - end_field(); - } - - // print a mysql ENUM as an html RADIO INPUT - function print_enum($name, $array, $vals, $def = -1) { - - begin_field($name); - - if (key_in_array($name, $array)) - $chk = array_search($array[$name], $vals, FALSE); - else - $chk = $def; - - $nval = count($vals); - - for ($i = 0; $i < $nval; $i++) { - - $val = $vals[$i]; - if ($val == '') - $pval = "none"; - else - $pval = "$val"; - - printf("\t\t<input type=radio name=$name" - . " value=\"$val\"%s>$pval</input>\n", - $i == $chk ? " checked" : ""); - } - - end_field(); - } - - // print a mysql ENUM as an html SELECT INPUT - function print_enum_select($name, $array, $vals, $def = -1) { - - begin_field($name); - - echo "\t\t<select name=$name>\n"; - - if (key_in_array($name, $array)) - $chk = array_search($array[$name], $vals, FALSE); - else - $chk = $def; - - $nval = count($vals); - - for ($i = 0; $i < $nval; $i++) { - - $val = $vals[$i]; - if ($val == '') - $pval = "none"; - else - $pval = "$val"; - - printf("\t\t\t<option " . - "value=\"%s\"%s>%s</option>\n", - $val, $i == $chk ? " selected" : "", $pval); - } - - echo "\t\t</select>\n"; - - end_field(); - } - - // print a group of mysql ENUMs (e.g. name0,name1,...) as an html SELECT - function print_enum_multi($base, $array, $vals, $cnt, $defs, $grp = 0) { - - global $table_ncols; - - if ($grp <= 0) - $grp = $cnt; - $ncell = $cnt / $grp; - $span = ($table_ncols - 1) / $ncell; - - begin_field($base, $span); - - $nval = count($vals); - - for ($i = 0; $i < $cnt; $i++) { - - if ($i > 0 && ($i % $grp) == 0) - cont_field($span); - - $name = sprintf("%s%x", $base, $i); - - echo "\t\t<select name=$name>\n"; - - if (key_in_array($name, $array)) - $ai = array_search($array[$name], $vals, FALSE); - else { - if (key_in_array($i, $defs)) - $ai = $defs[$i]; - else - $ai = 0; - } - - for ($j = 0; $j < $nval; $j++) { - - $val = $vals[$j]; - if ($val == '') - $pval = "&nbsp;"; - else - $pval = "$val"; - - printf("\t\t\t<option " . - "value=\"%s\"%s>%s</option>\n", - $val, - $j == $ai ? " selected" : "", - $pval); - } - - echo "\t\t</select>\n"; - } - - end_field(); - } - - // functions to handle the form input - - // fetch all the parts of an "enum_multi" into a string suitable - // for a MySQL query - function gather_enum_multi_query($base, $cnt) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if (isset($_REQUEST[$name])) { - $retval .= sprintf(", %s='%s'", - $name, $_REQUEST[$name]); - } - } - - return $retval; - } - - // fetch all the parts of an "enum_multi" into a string suitable - // for a display e.g. in an html table cell - function gather_enum_multi_print($base, $cnt, $array) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if ($array[$name] != '') { - if ($retval != '') - $retval .= ','; - $retval .= $array[$name]; - } - } - - return $retval; - } - - // fetch all the parts of an "enum_multi" into a string suitable - // for writing to the eeprom data file - function gather_enum_multi_write($base, $cnt, $vals, $xfrm = array()) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if ($GLOBALS[$name] != '') { - if ($retval != '') - $retval .= ','; - $index = enum_to_index($name, $vals); - if ($xfrm != array()) - $retval .= $xfrm[$index]; - else - $retval .= $index; - } - } - - return $retval; - } - - // count how many parts of an "enum_multi" are actually set - function count_enum_multi($base, $cnt) { - - $retval = 0; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if (isset($_REQUEST[$name])) - $retval++; - } - - return $retval; - } - - // ethernet address functions - - // generate a (possibly not unique) random vendor ethernet address - // (setting bit 6 in the ethernet address - motorola wise i.e. bit 0 - // is the most significant bit - means it is not an assigned ethernet - // address - it is a "locally administered" address). Also, make sure - // it is NOT a multicast ethernet address (by setting bit 7 to 0). - // e.g. the first byte of all ethernet addresses generated here will - // have 2 in the bottom two bits (incidentally, these are the first - // two bits transmitted on the wire, since the octets in ethernet - // addresses are transmitted LSB first). - - function gen_eth_addr($serno) { - - $ethaddr_hgh = (mt_rand(0, 65535) & 0xfeff) | 0x0200; - $ethaddr_mid = mt_rand(0, 65535); - $ethaddr_low = mt_rand(0, 65535); - - return sprintf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx", - $ethaddr_hgh >> 8, $ethaddr_hgh & 0xff, - $ethaddr_mid >> 8, $ethaddr_mid & 0xff, - $ethaddr_low >> 8, $ethaddr_low & 0xff); - } - - // check that an ethernet address is valid - function eth_addr_is_valid($ethaddr) { - - $ethbytes = split(':', $ethaddr); - - if (count($ethbytes) != 6) - return FALSE; - - for ($i = 0; $i < 6; $i++) { - $ethbyte = $ethbytes[$i]; - if (!ereg('^[0-9a-f][0-9a-f]$', $ethbyte)) - return FALSE; - } - - return TRUE; - } - - // write a simple eeprom configuration file - function write_eeprom_cfg_file() { - - global $sernos, $nsernos, $bddb_cfgdir, $numerrs, $cfgerrs; - global $date, $batch, $type_vals, $rev; - global $sdram_vals, $sdram_nbits; - global $flash_vals, $flash_nbits; - global $zbt_vals, $zbt_nbits; - global $xlxtyp_vals, $xlxspd_vals, $xlxtmp_vals, $xlxgrd_vals; - global $cputyp, $cputyp_vals, $clk_vals; - global $hstype, $hstype_vals, $hschin, $hschout; - - $numerrs = 0; - $cfgerrs = array(); - - for ($i = 0; $i < $nsernos; $i++) { - - $serno = sprintf("%010d", $sernos[$i]); - - $wfp = @fopen($bddb_cfgdir . "/$serno.cfg", "w"); - if (!$wfp) { - $cfgerrs[$i] = 'file create fail'; - $numerrs++; - continue; - } - set_file_buffer($wfp, 0); - - if (!fprintf($wfp, "serno=%d\n", $sernos[$i])) { - $cfgerrs[$i] = 'cfg wr fail (serno)'; - fclose($wfp); - $numerrs++; - continue; - } - - if (!fprintf($wfp, "date=%s\n", $date)) { - $cfgerrs[$i] = 'cfg wr fail (date)'; - fclose($wfp); - $numerrs++; - continue; - } - - if ($batch != '') { - if (!fprintf($wfp, "batch=%s\n", $batch)) { - $cfgerrs[$i] = 'cfg wr fail (batch)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $typei = enum_to_index("type", $type_vals); - if (!fprintf($wfp, "type=%d\n", $typei)) { - $cfgerrs[$i] = 'cfg wr fail (type)'; - fclose($wfp); - $numerrs++; - continue; - } - - if (!fprintf($wfp, "rev=%d\n", $rev)) { - $cfgerrs[$i] = 'cfg wr fail (rev)'; - fclose($wfp); - $numerrs++; - continue; - } - - $s = gather_enum_multi_write("sdram", 4, - $sdram_vals, $sdram_nbits); - if ($s != '') { - $b = fprintf($wfp, "sdram=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (sdram)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("flash", 4, - $flash_vals, $flash_nbits); - if ($s != '') { - $b = fprintf($wfp, "flash=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (flash)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("zbt", 16, - $zbt_vals, $zbt_nbits); - if ($s != '') { - $b = fprintf($wfp, "zbt=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (zbt)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxtyp", 4, $xlxtyp_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxtyp=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxtyp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxspd", 4, $xlxspd_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxspd=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxspd)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxtmp", 4, $xlxtmp_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxtmp=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxtmp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxgrd", 4, $xlxgrd_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxgrd=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxgrd)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if ($cputyp != '') { - $cputypi = enum_to_index("cputyp",$cputyp_vals); - $cpuspdi = enum_to_index("cpuspd", $clk_vals); - $busspdi = enum_to_index("busspd", $clk_vals); - $cpmspdi = enum_to_index("cpmspd", $clk_vals); - $b = fprintf($wfp, "cputyp=%d\ncpuspd=%d\n" . - "busspd=%d\ncpmspd=%d\n", - $cputypi, $cpuspdi, $busspdi, $cpmspdi); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (cputyp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if ($hstype != '') { - $hstypei = enum_to_index("hstype",$hstype_vals); - $b = fprintf($wfp, "hstype=%d\n" . - "hschin=%s\nhschout=%s\n", - $hstypei, $hschin, $hschout); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (hstype)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if (!fclose($wfp)) { - $cfgerrs[$i] = 'file cls fail'; - $numerrs++; - } - } - - return $numerrs; - } -?> diff --git a/tools/bddb/dodelete.php b/tools/bddb/dodelete.php deleted file mode 100644 index 4839e36..0000000 --- a/tools/bddb/dodelete.php +++ /dev/null @@ -1,65 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // dodelete page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Delete Board Results"); - - if (!isset($_REQUEST['serno'])) - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - mysql_query("delete from boards where serno=$serno"); - - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - else { - echo "\t<font size=+2>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe board with serial number <b>$serno</b> was" - . " successfully deleted\n"; - mysql_query("delete from log where serno=$serno"); - if (mysql_errno()) { - $errstr = mysql_error(); - echo "\t\t\t<font size=+4>\n"; - echo "\t\t\t\t<p>\n"; - echo "\t\t\t\t\tBut the following error occurred " . - "when deleting the log entries:\n"; - echo "\t\t\t\t</p>\n"; - echo "\t\t\t\t<center>\n"; - printf("\t\t\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t\t\t</center>\n"; - echo "\t\t\t</font>\n"; - } - echo "\t\t</p>\n"; - echo "\t</font>\n"; - } -?> -<p> -<table width="100%"> -<tr> - <td align=center> - <a href="browse.php">Back to Browse</a> - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/dodellog.php b/tools/bddb/dodellog.php deleted file mode 100644 index 9dd78c1..0000000 --- a/tools/bddb/dodellog.php +++ /dev/null @@ -1,57 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // dodelete page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Delete Log Entry Results"); - - if (!isset($_REQUEST['serno'])) - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == 0) - die("the log entry number not specified!"); - $logno=$_REQUEST['logno']; - - mysql_query("delete from log where serno=$serno and logno=$logno"); - - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - else { - echo "\t<font size=+2>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe log entry with log number <b>$logno</b>\n"; - echo "\t\t\tand serial number <b>$serno</b> "; - echo "was successfully deleted\n"; - echo "\t\t</p>\n"; - echo "\t</font>\n"; - } -?> -<p> -<table width="100%"> -<tr> - <td align=center> - <a href="brlog.php?serno=<?php echo "$serno"; ?>">Back to Log</a> - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/doedit.php b/tools/bddb/doedit.php deleted file mode 100644 index 13fbb69..0000000 --- a/tools/bddb/doedit.php +++ /dev/null @@ -1,186 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - $query="update boards set"; - - if (isset($_REQUEST['ethaddr'])) { - $ethaddr=$_REQUEST['ethaddr']; - if (!eth_addr_is_valid($ethaddr)) - die("ethaddr is invalid ('$ethaddr')"); - $query.=" ethaddr='$ethaddr',"; - } - - if (isset($_REQUEST['date'])) { - $date=$_REQUEST['date']; - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', " . - "yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - } - - if (isset($_REQUEST['batch'])) { - $batch=$_REQUEST['batch']; - if (strlen($batch) > 32) - die("batch field too long (>32)"); - $query.=", batch='$batch'"; - } - - if (isset($_REQUEST['type'])) { - $type=$_REQUEST['type']; - if (!in_array($type, $type_vals)) - die("Invalid type ($type) specified"); - $query.=", type='$type'"; - } - - if (isset($_REQUEST['rev'])) { - $rev=$_REQUEST['rev']; - if (($rev = intval($rev)) <= 0 || $rev > 255) - die("Revision number is invalid ($rev)"); - $query.=sprintf(", rev=%d", $rev); - } - - if (isset($_REQUEST['location'])) { - $location=$_REQUEST['location']; - if (strlen($location) > 64) - die("location field too long (>64)"); - $query.=", location='$location'"; - } - - if (isset($_REQUEST['comments'])) - $comments=$_REQUEST['comments']; - $query.=", comments='" . rawurlencode($comments) . "'"; - - $query.=gather_enum_multi_query("sdram", 4); - - $query.=gather_enum_multi_query("flash", 4); - - $query.=gather_enum_multi_query("zbt", 16); - - $query.=gather_enum_multi_query("xlxtyp", 4); - $nxlx = count_enum_multi("xlxtyp", 4); - - $query.=gather_enum_multi_query("xlxspd", 4); - if (count_enum_multi("xlxspd", 4) != $nxlx) - die("number of xilinx speeds not same as number of types"); - - $query.=gather_enum_multi_query("xlxtmp", 4); - if (count_enum_multi("xlxtmp", 4) != $nxlx) - die("number of xilinx temps. not same as number of types"); - - $query.=gather_enum_multi_query("xlxgrd", 4); - if (count_enum_multi("xlxgrd", 4) != $nxlx) - die("number of xilinx grades not same as number of types"); - - if (isset($_REQUEST['cputyp'])) { - $cputyp=$_REQUEST['cputyp']; - $query.=", cputyp='$cputyp'"; - if (!isset($_REQUEST['cpuspd']) || $_REQUEST['cpuspd'] == '') - die("must specify cpu speed if cpu type is defined"); - $cpuspd=$_REQUEST['cpuspd']; - $query.=", cpuspd='$cpuspd'"; - if (!isset($_REQUEST['cpmspd']) || $_REQUEST['cpmspd'] == '') - die("must specify cpm speed if cpu type is defined"); - $cpmspd=$_REQUEST['cpmspd']; - $query.=", cpmspd='$cpmspd'"; - if (!isset($_REQUEST['busspd']) || $_REQUEST['busspd'] == '') - die("must specify bus speed if cpu type is defined"); - $busspd=$_REQUEST['busspd']; - $query.=", busspd='$busspd'"; - } - else { - if (isset($_REQUEST['cpuspd'])) - die("can't specify cpu speed if there is no cpu"); - if (isset($_REQUEST['cpmspd'])) - die("can't specify cpm speed if there is no cpu"); - if (isset($_REQUEST['busspd'])) - die("can't specify bus speed if there is no cpu"); - } - - if (isset($_REQUEST['hschin'])) { - $hschin=$_REQUEST['hschin']; - if (($hschin = intval($hschin)) < 0 || $hschin > 4) - die("Invalid number of hs input chans ($hschin)"); - } - else - $hschin = 0; - if (isset($_REQUEST['hschout'])) { - $hschout=$_REQUEST['hschout']; - if (($hschout = intval($hschout)) < 0 || $hschout > 4) - die("Invalid number of hs output chans ($hschout)"); - } - else - $hschout = 0; - if (isset($_REQUEST['hstype'])) { - $hstype=$_REQUEST['hstype']; - $query.=", hstype='$hstype'"; - } - else { - if ($_REQUEST['hschin'] != 0) - die("number of high-speed input channels must be zero" - . " if high-speed chip is not present"); - if ($_REQUEST['hschout'] != 0) - die("number of high-speed output channels must be zero" - . " if high-speed chip is not present"); - } - $query.=", hschin='$hschin'"; - $query.=", hschout='$hschout'"; - - $query.=" where serno=$serno"; - - mysql_query($query); - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - else { - $sernos = array($serno); - $nsernos = 1; - - write_eeprom_cfg_file(); - - echo "\t<font size=+2>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe board with serial number <b>$serno</b> was" - . " successfully updated"; - if ($numerrs > 0) { - $errstr = $cfgerrs[0]; - echo "<br>\n\t\t\t"; - echo "(but the cfg file update failed: $errstr)"; - } - echo "\n"; - echo "\t\t</p>\n"; - echo "\t</font>\n"; - } - -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center><a href="browse.php">Back to Browse</a></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/doedlog.php b/tools/bddb/doedlog.php deleted file mode 100644 index 7009aa7..0000000 --- a/tools/bddb/doedlog.php +++ /dev/null @@ -1,76 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Log Entry Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '') - die("log number not specified!"); - $logno=intval($_REQUEST['logno']); - - $query="update log set"; - - if (isset($_REQUEST['date'])) { - $date=$_REQUEST['date']; - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', " . - "yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - } - - if (isset($_REQUEST['who'])) { - $who=$_REQUEST['who']; - $query.=", who='" . $who . "'"; - } - - if (isset($_REQUEST['details'])) { - $details=$_REQUEST['details']; - $query.=", details='" . rawurlencode($details) . "'"; - } - - $query.=" where serno=$serno and logno=$logno"; - - mysql_query($query); - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - else { - echo "\t<font size=+2>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe log entry with log number <b>$logno</b> and\n"; - echo "\t\t\tserial number <b>$serno</b> "; - echo "was successfully updated\n"; - echo "\t\t</p>\n"; - echo "\t</font>\n"; - } - -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center><a href="brlog.php?serno=<?php echo "$serno"; ?>">Back to Log</a></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/donew.php b/tools/bddb/donew.php deleted file mode 100644 index 39b2c78..0000000 --- a/tools/bddb/donew.php +++ /dev/null @@ -1,230 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Board Registration Results"); - - if (isset($_REQUEST['serno'])) { - $serno=$_REQUEST['serno']; - die("serial number must not be set ($serno) when Creating!"); - } - - $query="update boards set"; - - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - - if ($batch != '') { - if (strlen($batch) > 32) - die("batch field too long (>32)"); - $query.=", batch='$batch'"; - } - - if (!in_array($type, $type_vals)) - die("Invalid type ($type) specified"); - $query.=", type='$type'"; - - if (($rev = intval($rev)) <= 0 || $rev > 255) - die("Revision number is invalid ($rev)"); - $query.=sprintf(", rev=%d", $rev); - - $query.=gather_enum_multi_query("sdram", 4); - - $query.=gather_enum_multi_query("flash", 4); - - $query.=gather_enum_multi_query("zbt", 16); - - $query.=gather_enum_multi_query("xlxtyp", 4); - $nxlx = count_enum_multi("xlxtyp", 4); - - $query.=gather_enum_multi_query("xlxspd", 4); - if (count_enum_multi("xlxspd", 4) != $nxlx) - die("number of xilinx speeds not same as number of types"); - - $query.=gather_enum_multi_query("xlxtmp", 4); - if (count_enum_multi("xlxtmp", 4) != $nxlx) - die("number of xilinx temps. not same as number of types"); - - $query.=gather_enum_multi_query("xlxgrd", 4); - if (count_enum_multi("xlxgrd", 4) != $nxlx) - die("number of xilinx grades not same as number of types"); - - if ($cputyp == '') { - if ($cpuspd != '') - die("can't specify cpu speed if there is no cpu"); - if ($cpmspd != '') - die("can't specify cpm speed if there is no cpu"); - if ($busspd != '') - die("can't specify bus speed if there is no cpu"); - } - else { - $query.=", cputyp='$cputyp'"; - if ($cpuspd == '') - die("must specify cpu speed if cpu type is defined"); - $query.=", cpuspd='$cpuspd'"; - if ($cpmspd == '') - die("must specify cpm speed if cpu type is defined"); - $query.=", cpmspd='$cpmspd'"; - if ($busspd == '') - die("must specify bus speed if cpu type is defined"); - $query.=", busspd='$busspd'"; - } - - if (($hschin = intval($hschin)) < 0 || $hschin > 4) - die("Invalid number of hs input chans ($hschin)"); - if (($hschout = intval($hschout)) < 0 || $hschout > 4) - die("Invalid number of hs output chans ($hschout)"); - if ($hstype == '') { - if ($hschin != 0) - die("number of high-speed input channels must be zero" - . " if high-speed chip is not present"); - if ($hschout != 0) - die("number of high-speed output channels must be zero" - . " if high-speed chip is not present"); - } - else - $query.=", hstype='$hstype'"; - $query.=", hschin='$hschin'"; - $query.=", hschout='$hschout'"; - - // echo "final query = '$query'<br>\n"; - - $quant = intval($quant); - if ($quant <= 0) $quant = 1; - - $sernos = array(); - if ($geneths) - $ethaddrs = array(); - - $sqlerr = ''; - - while ($quant-- > 0) { - - mysql_query("insert into boards (serno) values (null)"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - break; - } - - $serno = mysql_insert_id(); - if (!$serno) { - $sqlerr = "couldn't allocate new serial number"; - break; - } - - mysql_query($query . " where serno=$serno"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - break; - } - - array_push($sernos, $serno); - - if ($geneths) { - - $ethaddr = gen_eth_addr($serno); - - mysql_query("update boards set ethaddr='$ethaddr'" . - " where serno=$serno"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - - array_push($ethaddrs, - "<font color=#ff0000><b>" . - "db save fail" . - "</b></font>"); - break; - } - - array_push($ethaddrs, $ethaddr); - } - } - - $nsernos = count($sernos); - - if ($nsernos > 0) { - - write_eeprom_cfg_file(); - - echo "<font size=+2>\n"; - echo "\t<p>\n"; - echo "\t\tThe following board serial numbers were" - . " successfully allocated"; - if ($numerrs > 0) - echo " (but with $numerrs cfg file error" . - ($numerrs > 1 ? "s" : "") . ")"; - echo ":\n"; - echo "\t</p>\n"; - - echo "</font>\n"; - - echo "<table align=center width=\"100%\">\n"; - echo "<tr>\n"; - echo "\t<th>Serial Number</th>\n"; - if ($numerrs > 0) - echo "\t<th>Cfg File Errs</th>\n"; - if ($geneths) - echo "\t<th>Ethernet Address</th>\n"; - echo "</tr>\n"; - - for ($i = 0; $i < $nsernos; $i++) { - - $serno = sprintf("%010d", $sernos[$i]); - - echo "<tr>\n"; - - echo "\t<td align=center><font size=+2>" . - "<b>$serno</b></font></td>\n"; - - if ($numerrs > 0) { - if (($errstr = $cfgerrs[$i]) == '') - $errstr = '&nbsp;'; - echo "\t<td align=center>" . - "<font size=+2 color=#ff0000><b>" . - $errstr . - "</b></font></td>\n"; - } - - if ($geneths) { - echo "\t<td align=center>" . - "<font size=+2 color=#00ff00><b>" . - $ethaddrs[$i] . - "</b></font></td>\n"; - } - - echo "</tr>\n"; - } - - echo "</table>\n"; - } - - if ($sqlerr != '') { - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following SQL error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $sqlerr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center><a href="browse.php">Go to Browse</a></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/donewlog.php b/tools/bddb/donewlog.php deleted file mode 100644 index 7635d29..0000000 --- a/tools/bddb/donewlog.php +++ /dev/null @@ -1,86 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Add Log Entry Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified!"); - $serno=intval($_REQUEST['serno']); - - if (isset($_REQUEST['logno'])) { - $logno=$_REQUEST['logno']; - die("log number must not be set ($logno) when Creating!"); - } - - $query="update log set serno=$serno"; - - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')"); - $query.=", date='$date'"; - - if (isset($_REQUEST['who'])) { - $who=$_REQUEST['who']; - $query.=", who='" . $who . "'"; - } - - if (isset($_REQUEST['details'])) { - $details=$_REQUEST['details']; - $query.=", details='" . rawurlencode($details) . "'"; - } - - // echo "final query = '$query'<br>\n"; - - $sqlerr = ''; - - mysql_query("insert into log (logno) values (null)"); - if (mysql_errno()) - $sqlerr = mysql_error(); - else { - $logno = mysql_insert_id(); - if (!$logno) - $sqlerr = "couldn't allocate new serial number"; - else { - mysql_query($query . " where logno=$logno"); - if (mysql_errno()) - $sqlerr = mysql_error(); - } - } - - if ($sqlerr == '') { - echo "<font size=+2>\n"; - echo "\t<p>\n"; - echo "\t\tA log entry with log number '$logno' was " . - "added to the board with serial number '$serno'\n"; - echo "\t</p>\n"; - echo "</font>\n"; - } - else { - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following SQL error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $sqlerr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - -?> -<p></p> -<table width="100%"> -<tr> - <td align=center><a href="brlog.php?serno=<?php echo "$serno"; ?>">Go to Browse</a></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/edit.php b/tools/bddb/edit.php deleted file mode 100644 index dd8c26c..0000000 --- a/tools/bddb/edit.php +++ /dev/null @@ -1,131 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Registration"); - - if ($serno == 0) - die("serial number not specified or invalid!"); - - $pserno = sprintf("%010d", $serno); - - echo "<center><b><font size=+2>"; - echo "Board Serial Number: $pserno"; - echo "</font></b></center>\n"; - -?> -<p> -<form action=doedit.php method=POST> -<?php - echo "<input type=hidden name=serno value=$serno>\n"; - - $r=mysql_query("select * from boards where serno=$serno"); - $row=mysql_fetch_array($r); - if(!$row) die("no record of serial number '$serno' in database"); - - begin_table(5); - - // ethaddr char(17) - print_field("ethaddr", $row, 17); - - // date date - print_field("date", $row); - - // batch char(32) - print_field("batch", $row, 32); - - // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') - print_enum("type", $row, $type_vals); - - // rev tinyint(3) unsigned zerofill - print_field("rev", $row, 3, 'rev_filter'); - - // location char(64) - print_field("location", $row, 64); - - // comments text - print_field_multiline("comments", $row, 60, 10, 'text_filter'); - - // sdram[0-3] enum('32M','64M','128M','256M') - print_enum_multi("sdram", $row, $sdram_vals, 4, array()); - - // flash[0-3] enum('4M','8M','16M','32M','64M') - print_enum_multi("flash", $row, $flash_vals, 4, array()); - - // zbt[0-f] enum('512K','1M','2M','4M') - print_enum_multi("zbt", $row, $zbt_vals, 16, array()); - - // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E') - print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(), 1); - - // xlxspd[0-3] enum('6','7','8') - print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(), 1); - - // xlxtmp[0-3] enum('COM','IND') - print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(), 1); - - // xlxgrd[0-3] enum('NORMAL','ENGSAMP') - print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(), 1); - - // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)') - print_enum("cputyp", $row, $cputyp_vals); - - // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpuspd", $row, $clk_vals); - - // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpmspd", $row, $clk_vals); - - // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("busspd", $row, $clk_vals); - - // hstype enum('AMCC-S2064A') - print_enum("hstype", $row, $hstype_vals); - - // hschin enum('0','1','2','3','4') - print_enum("hschin", $row, $hschin_vals); - - // hschout enum('0','1','2','3','4') - print_enum("hschout", $row, $hschout_vals); - - end_table(); - - echo "<p>\n"; - echo "<center><b>"; - echo "<font color=#ff0000>WARNING: NO UNDO ON DELETE!</font>"; - echo "<br></br>\n"; - echo "<tt>[ <a href=\"dodelete.php?serno=$serno\">delete</a> ]</tt>"; - echo "</b></center>\n"; - echo "</p>\n"; -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center> - <input type=submit value=Edit> - </td> - <td> - &nbsp; - </td> - <td align=center> - <input type=reset value=Reset> - </td> - <td> - &nbsp; - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -</p> -</form> -<?php - pg_foot(); -?> diff --git a/tools/bddb/edlog.php b/tools/bddb/edlog.php deleted file mode 100644 index 8befd35..0000000 --- a/tools/bddb/edlog.php +++ /dev/null @@ -1,86 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Log Entry"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified!"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '') - die("log number not specified!"); - $logno=intval($_REQUEST['logno']); - - $pserno = sprintf("%010d", $serno); - $plogno = sprintf("%010d", $logno); - - echo "<center><b><font size=+2>"; - echo "Board Serial Number: $pserno, Log Number: $plogno"; - echo "</font></b></center>\n"; - -?> -<p> -<form action=doedlog.php method=POST> -<?php - echo "<input type=hidden name=serno value=$serno>\n"; - echo "<input type=hidden name=logno value=$logno>\n"; - - $r=mysql_query("select * from log where serno=$serno and logno=$logno"); - $row=mysql_fetch_array($r); - if(!$row) - die("no record of log entry with serial number '$serno' " . - "and log number '$logno' in database"); - - begin_table(3); - - // date date - print_field("date", $row); - - // who char(20) - print_field("who", $row); - - // details text - print_field_multiline("details", $row, 60, 10, 'text_filter'); - - end_table(); - - echo "<p>\n"; - echo "<center><b>"; - echo "<font color=#ff0000>WARNING: NO UNDO ON DELETE!</font>"; - echo "<br></br>\n"; - echo "<tt>[ <a href=\"dodellog.php?serno=$serno&logno=$logno\">delete</a> ]</tt>"; - echo "</b></center>\n"; - echo "</p>\n"; -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center> - <input type=submit value=Edit> - </td> - <td> - &nbsp; - </td> - <td align=center> - <input type=reset value=Reset> - </td> - <td> - &nbsp; - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -</p> -</form> -<?php - pg_foot(); -?> diff --git a/tools/bddb/execute.php b/tools/bddb/execute.php deleted file mode 100644 index 0b62882..0000000 --- a/tools/bddb/execute.php +++ /dev/null @@ -1,33 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:''; - - $submit=isset($_REQUEST['submit'])?$_REQUEST['submit']:"[NOT SET]"; - - switch ($submit) { - - case "New": - require("new.php"); - break; - - case "Edit": - require("edit.php"); - break; - - case "Browse": - require("browse.php"); - break; - - case "Log": - require("brlog.php"); - break; - - default: - require("badsubmit.php"); - break; - } -?> diff --git a/tools/bddb/index.php b/tools/bddb/index.php deleted file mode 100644 index 842aed5..0000000 --- a/tools/bddb/index.php +++ /dev/null @@ -1,38 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - require("defs.php"); - pg_head("$bddb_label"); -?> -<font size="+4"> - <form action=execute.php method=POST> - <table width="100%" cellspacing=10 cellpadding=10> - <tr> - <td align=center> - <input type=submit name=submit value="New"></input> - </td> - <td align=center> - <input type=submit name=submit value="Edit"></input> - </td> - <td align=center> - <input type=submit name=submit value="Browse"></input> - </td> - <td align=center> - <input type=submit name=submit value="Log"></input> - </td> - </tr> - <tr> - <td align=center colspan=4> - <b>Serial Number:</b> - <input type=text name=serno size=10 maxsize=10 value=""></input> - </td> - </tr> - </table> - </form> -</font> -<?php - pg_foot(); -?> diff --git a/tools/bddb/new.php b/tools/bddb/new.php deleted file mode 100644 index 30323ff..0000000 --- a/tools/bddb/new.php +++ /dev/null @@ -1,120 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - New Board Registration"); -?> -<form action=donew.php method=POST> -<p></p> -<?php - $serno=intval($serno); - // if a serial number was supplied, fetch the record - // and use its contents as defaults - if ($serno != 0) { - $r=mysql_query("select * from boards where serno=$serno"); - $row=mysql_fetch_array($r); - if(!$row)die("no record of serial number '$serno' in database"); - } - else - $row = array(); - - begin_table(5); - - // date date - print_field("date", array('date' => date("Y-m-d"))); - - // batch char(32) - print_field("batch", $row, 32); - - // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') - print_enum("type", $row, $type_vals, 0); - - // rev tinyint(3) unsigned zerofill - print_field("rev", $row, 3, 'rev_filter'); - - // sdram[0-3] enum('32M','64M','128M','256M') - print_enum_multi("sdram", $row, $sdram_vals, 4, array(2)); - - // flash[0-3] enum('4M','8M','16M','32M','64M') - print_enum_multi("flash", $row, $flash_vals, 4, array(2)); - - // zbt[0-f] enum('512K','1M','2M','4M') - print_enum_multi("zbt", $row, $zbt_vals, 16, array(2, 2)); - - // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E') - print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(1), 1); - - // xlxspd[0-3] enum('6','7','8') - print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(1), 1); - - // xlxtmp[0-3] enum('COM','IND') - print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(1), 1); - - // xlxgrd[0-3] enum('NORMAL','ENGSAMP') - print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(1), 1); - - // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)') - print_enum("cputyp", $row, $cputyp_vals, 1); - - // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpuspd", $row, $clk_vals, 4); - - // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpmspd", $row, $clk_vals, 4); - - // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("busspd", $row, $clk_vals, 2); - - // hstype enum('AMCC-S2064A') - print_enum("hstype", $row, $hstype_vals, 1); - - // hschin enum('0','1','2','3','4') - print_enum("hschin", $row, $hschin_vals, 4); - - // hschout enum('0','1','2','3','4') - print_enum("hschout", $row, $hschout_vals, 4); - - end_table(); -?> -<p></p> -<table width="100%"> -<tr> - <td align=center colspan=3> - Allocate - <input type=text name=quant size=2 maxlength=2 value=" 1"> - board serial number(s) - </td> -</tr> -<tr> - <td align=center colspan=3> - <input type=checkbox name=geneths checked> - Generate Ethernet Address(es) - </td> -</tr> -<tr> - <td colspan=3> - &nbsp; - </td> -</tr> -<tr> - <td align=center> - <input type=submit value="Register Board"> - </td> - <td> - &nbsp; - </td> - <td align=center> - <input type=reset value="Reset Form Contents"> - </td> -</tr> -</table> -</form> -<?php - pg_foot(); -?> diff --git a/tools/bddb/newlog.php b/tools/bddb/newlog.php deleted file mode 100644 index 609bb85..0000000 --- a/tools/bddb/newlog.php +++ /dev/null @@ -1,54 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - New Log Entry"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified or invalid!"); - $serno=intval($_REQUEST['serno']); - - if (isset($_REQUEST['logno'])) { - $logno=$_REQUEST['logno']; - die("log number must not be specified when adding! ($logno)"); - } -?> -<form action=donewlog.php method=POST> -<p></p> -<?php - echo "<input type=hidden name=serno value=$serno>\n"; - - begin_table(3); - - // date date - print_field("date", array('date' => date("Y-m-d"))); - - // who char(20) - print_field("who", array()); - - // details text - print_field_multiline("details", array(), 60, 10, 'text_filter'); - - end_table(); -?> -<p></p> -<table width="100%"> -<tr> - <td align=center> - <input type=submit value="Add Log Entry"> - </td> - <td align=center> - <input type=reset value="Reset Form Contents"> - </td> -</tr> -</table> -</form> -<?php - pg_foot(); -?>

This is the only used of CONFIG_SPI_X macro, just zap this.

Signed-off-by: Marek Vasut marex@denx.de Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Simon Glass sjg@chromium.org Cc: Heiko Schocher hs@denx.de --- arch/powerpc/cpu/mpc85xx/Kconfig | 4 - board/exmeritus/hww1u1a/Kconfig | 12 - board/exmeritus/hww1u1a/MAINTAINERS | 6 - board/exmeritus/hww1u1a/Makefile | 12 - board/exmeritus/hww1u1a/ddr.c | 34 --- board/exmeritus/hww1u1a/gpios.h | 56 ----- board/exmeritus/hww1u1a/hww1u1a.c | 268 --------------------- board/exmeritus/hww1u1a/law.c | 18 -- board/exmeritus/hww1u1a/tlb.c | 90 ------- configs/HWW1U1A_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/HWW1U1A.h | 460 ------------------------------------ 12 files changed, 1 insertion(+), 963 deletions(-) delete mode 100644 board/exmeritus/hww1u1a/Kconfig delete mode 100644 board/exmeritus/hww1u1a/MAINTAINERS delete mode 100644 board/exmeritus/hww1u1a/Makefile delete mode 100644 board/exmeritus/hww1u1a/ddr.c delete mode 100644 board/exmeritus/hww1u1a/gpios.h delete mode 100644 board/exmeritus/hww1u1a/hww1u1a.c delete mode 100644 board/exmeritus/hww1u1a/law.c delete mode 100644 board/exmeritus/hww1u1a/tlb.c delete mode 100644 configs/HWW1U1A_defconfig delete mode 100644 include/configs/HWW1U1A.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 8c1c01c..c0bb67b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -13,9 +13,6 @@ config TARGET_SBC8548 config TARGET_SOCRATES bool "Support socrates"

-config TARGET_HWW1U1A - bool "Support HWW1U1A" - config TARGET_B4860QDS bool "Support B4860QDS"

@@ -144,7 +141,6 @@ config TARGET_XPEDITE550X

endchoice

-source "board/exmeritus/hww1u1a/Kconfig" source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/board/exmeritus/hww1u1a/Kconfig b/board/exmeritus/hww1u1a/Kconfig deleted file mode 100644 index 7a76b43..0000000 --- a/board/exmeritus/hww1u1a/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_HWW1U1A - -config SYS_BOARD - default "hww1u1a" - -config SYS_VENDOR - default "exmeritus" - -config SYS_CONFIG_NAME - default "HWW1U1A" - -endif diff --git a/board/exmeritus/hww1u1a/MAINTAINERS b/board/exmeritus/hww1u1a/MAINTAINERS deleted file mode 100644 index b37f10b..0000000 --- a/board/exmeritus/hww1u1a/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HWW1U1A BOARD -#M: Kyle Moffett Kyle.D.Moffett@boeing.com -S: Orphan (since 2014-06) -F: board/exmeritus/hww1u1a/ -F: include/configs/HWW1U1A.h -F: configs/HWW1U1A_defconfig diff --git a/board/exmeritus/hww1u1a/Makefile b/board/exmeritus/hww1u1a/Makefile deleted file mode 100644 index d0cd878..0000000 --- a/board/exmeritus/hww1u1a/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += hww1u1a.o -obj-y += law.o -obj-y += tlb.o -obj-$(CONFIG_DDR_SPD) += ddr.o diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c deleted file mode 100644 index e1f6865..0000000 --- a/board/exmeritus/hww1u1a/ddr.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * We only support one DIMM, so according to the P2020 docs we should - * set the options as follows: - */ - popts->cs_local_opts[0].odt_rd_cfg = 0; - popts->cs_local_opts[0].odt_wr_cfg = 4; - popts->cs_local_opts[1].odt_rd_cfg = 0; - popts->cs_local_opts[1].odt_wr_cfg = 0; - popts->half_strength_driver_enable = 0; - - /* Manually configured for our static clock rate */ - popts->clk_adjust = 4; - popts->cpo_override = 4; - popts->write_data_delay = 2; - popts->twot_en = 0; -} diff --git a/board/exmeritus/hww1u1a/gpios.h b/board/exmeritus/hww1u1a/gpios.h deleted file mode 100644 index 499880f..0000000 --- a/board/exmeritus/hww1u1a/gpios.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2010 eXMeritus, A Boeing Company - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/mpc85xx_gpio.h> - -/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */ -#define GPIO_CPU_ID (1UL << (31 - 8)) -#define GPIO_BLUE_LED (1UL << (31 - 9)) -#define GPIO_DIMM_RESET (1UL << (31 - 10)) -#define GPIO_USB_RESET (1UL << (31 - 11)) -#define GPIO_UNUSED_12 (1UL << (31 - 12)) -#define GPIO_GETH0_RESET (1UL << (31 - 13)) -#define GPIO_RS422_RE (1UL << (31 - 14)) -#define GPIO_RS422_DE (1UL << (31 - 15)) -#define IRQ_I2CINT (1UL << (31 - 20)) -#define IRQ_FANINT (1UL << (31 - 21)) -#define IRQ_DIMM_EVENT (1UL << (31 - 22)) - -#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET) - -/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ -#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0)) -#define GPIO_CPUA_CPU_READY (1UL << (31 - 1)) -#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2)) -#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3)) -#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */ -#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */ -#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */ -#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */ -#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16)) -#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17)) -#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18)) -#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19)) - -/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ -#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0)) -#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1)) -#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2)) -#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3)) -#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4)) -#define GPIO_CPUB_CPU_READY (1UL << (31 - 5)) -#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6)) -#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7)) -#define IRQ_CPUB_SD_1A (1UL << (31 - 16)) -#define IRQ_CPUB_SD_2B (1UL << (31 - 17)) -#define IRQ_CPUB_SD_2A (1UL << (31 - 18)) -#define IRQ_CPUB_SD_1B (1UL << (31 - 19)) - -/* If it isn't CPU A then it's CPU B */ -static inline unsigned int hww1u1a_is_cpu_a(void) -{ - return !mpc85xx_gpio_get(GPIO_CPU_ID); -} diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c deleted file mode 100644 index 643ece1..0000000 --- a/board/exmeritus/hww1u1a/hww1u1a.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2009-2011 eXMeritus, A Boeing Company - * Copyright 2007-2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/io.h> -#include <miiphy.h> -#include <libfdt.h> -#include <linux/ctype.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <asm/fsl_law.h> -#include <netdev.h> -#include <malloc.h> -#include <i2c.h> -#include <pca953x.h> - -#include "gpios.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - unsigned int gpio_high = 0; - unsigned int gpio_low = 0; - unsigned int gpio_in = 0; - unsigned int i; - struct ccsr_ddr __iomem *ddr; - - puts("Board: HWW-1U-1A "); - - /* - * First just figure out which CPU we're on, then use that to - * configure the lists of other GPIOs to be programmed. - */ - mpc85xx_gpio_set_in(GPIO_CPU_ID); - if (hww1u1a_is_cpu_a()) { - puts("CPU A\n"); - - /* We want to turn on some LEDs */ - gpio_high |= GPIO_CPUA_CPU_READY; - gpio_low |= GPIO_CPUA_DEBUG_LED1; - gpio_low |= GPIO_CPUA_DEBUG_LED2; - - /* Disable the unused transmitters */ - gpio_low |= GPIO_CPUA_TDIS1A; - gpio_high |= GPIO_CPUA_TDIS1B; - gpio_low |= GPIO_CPUA_TDIS2A; - gpio_high |= GPIO_CPUA_TDIS2B; - } else { - puts("CPU B\n"); - - /* We want to turn on some LEDs */ - gpio_high |= GPIO_CPUB_CPU_READY; - gpio_low |= GPIO_CPUB_DEBUG_LED1; - gpio_low |= GPIO_CPUB_DEBUG_LED2; - - /* Enable the appropriate receivers */ - gpio_high |= GPIO_CPUB_RMUX_SEL0A; - gpio_high |= GPIO_CPUB_RMUX_SEL0B; - gpio_low |= GPIO_CPUB_RMUX_SEL1A; - gpio_low |= GPIO_CPUB_RMUX_SEL1B; - } - - /* These GPIOs are common */ - gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT; - gpio_low |= GPIO_RS422_RE; - gpio_high |= GPIO_RS422_DE; - - /* Ok, now go ahead and program all of those in one go */ - mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in, - gpio_high|gpio_low, - gpio_high); - - /* - * If things have been taken out of reset early (for example, by one - * of the BDI3000 debuggers), then we need to put them back in reset - * and delay a while before we continue. - */ - if (mpc85xx_gpio_get(GPIO_RESETS)) { - ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - - puts("Debugger detected... extra device reset enabled!\n"); - - /* Put stuff into reset and disable the DDR controller */ - mpc85xx_gpio_set_low(GPIO_RESETS); - out_be32(&ddr->sdram_cfg, 0x00000000); - - puts(" Waiting 1 sec for reset..."); - for (i = 0; i < 10; i++) { - udelay(100000); - puts("."); - } - puts("\n"); - } - - /* Now bring everything back out of reset again */ - mpc85xx_gpio_set_high(GPIO_RESETS); - return 0; -} - -/* - * This little shell function just returns whether or not it's CPU A. - * It can be used to select the right device-tree when booting, etc. - */ -int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - if (argc > 1) - cmd_usage(cmdtp); - - if (hww1u1a_is_cpu_a()) - return 0; - else - return 1; -} -U_BOOT_CMD( - test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a, - "Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board", - "" -); - -/* Create a prompt-like string: "uboot@HOSTNAME% " */ -#define PROMPT_PREFIX "uboot@exm" -#define PROMPT_SUFFIX "% " - -/* This function returns a PS1 prompt based on the serial number */ -static char *hww1u1a_prompt; -const char *hww1u1a_get_ps1(void) -{ - unsigned long len, i, j; - const char *serialnr; - - /* If our prompt was already set, just use that */ - if (hww1u1a_prompt) - return hww1u1a_prompt; - - /* Use our serial number if present, otherwise a default */ - serialnr = getenv("serial#"); - if (!serialnr || !serialnr[0]) - serialnr = "999999-X"; - - /* - * We will turn the serial number into a hostname by: - * (A) Delete all non-alphanumerics. - * (B) Lowercase all letters. - * (C) Prefix "exm". - * (D) Suffix "a" for CPU A and "b" for CPU B. - */ - for (i = 0, len = 0; serialnr[i]; i++) { - if (isalnum(serialnr[i])) - len++; - } - - len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */ - hww1u1a_prompt = malloc(len); - if (!hww1u1a_prompt) - return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX; - - /* Now actually fill it in */ - i = 0; - - /* Handle the prefix */ - for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++) - hww1u1a_prompt[i++] = PROMPT_PREFIX[j]; - - /* Now the serial# part of the hostname */ - for (j = 0; serialnr[j]; j++) - if (isalnum(serialnr[j])) - hww1u1a_prompt[i++] = tolower(serialnr[j]); - - /* Now the CPU id ("a" or "b") */ - hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b'; - - /* Finally the suffix */ - for (j = 0; j < sizeof(PROMPT_SUFFIX); j++) - hww1u1a_prompt[i++] = PROMPT_SUFFIX[j]; - - /* This should all have added up, but just in case */ - hww1u1a_prompt[len - 1] = '\0'; - - /* Now we're done */ - return hww1u1a_prompt; -} - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap bootflash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for FLASH */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - struct tsec_info_struct tsec_info[4]; - struct fsl_pq_mdio_info mdio_info; - - SET_STD_TSEC_INFO(tsec_info[0], 1); - SET_STD_TSEC_INFO(tsec_info[1], 2); - SET_STD_TSEC_INFO(tsec_info[2], 3); - - if (hww1u1a_is_cpu_a()) - tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA; - else - tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB; - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, 3); - return pci_eth_init(bis); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - FT_FSL_PCI_SETUP; -} diff --git a/board/exmeritus/hww1u1a/law.c b/board/exmeritus/hww1u1a/law.c deleted file mode 100644 index c7dc58d..0000000 --- a/board/exmeritus/hww1u1a/law.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/exmeritus/hww1u1a/tlb.c b/board/exmeritus/hww1u1a/tlb.c deleted file mode 100644 index 7f5a36f..0000000 --- a/board/exmeritus/hww1u1a/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Boot page */ - SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, - CONFIG_BPTR_VIRT_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, - CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* - * W**G* - FLASH (Will be *I*G* after relocation to RAM) - * - * This maps both SPI FLASH chips (128MByte per chip) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * *I*G* - PCI memory - * - * We have 1.5GB total PCI-E memory space to map and we want to use - * the minimum possible number of TLB entries. Since Book-E TLB - * entries are sized in powers of 4, we use 1GB + 256MB + 256MB. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, - CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* - * *I*G* - PCI I/O - * - * This one entry covers all 3 64k PCI-E I/O windows - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, - CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/HWW1U1A_defconfig b/configs/HWW1U1A_defconfig deleted file mode 100644 index 8947be2..0000000 --- a/configs/HWW1U1A_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_HWW1U1A=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 57eac91..19d0e9c 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +HWW1U1A powerpc mpc85xx - - Kyle Moffett Kyle.D.Moffett@boeing.com hymod powerpc mpc8260 - - Murray Jensen Murray.Jensen@csiro.au MHPC powerpc mpc8xx - - Frank Gottschling fgottschling@eltec.de ICU862 powerpc mpc8xx - - Wolfgang Denk wd@denx.de diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h deleted file mode 100644 index 6a3a11c..0000000 --- a/include/configs/HWW1U1A.h +++ /dev/null @@ -1,460 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * HardwareWall HWW-1U-1A airborne unit configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High-level system configuration options */ -#define CONFIG_BOOKE /* Power/PowerPC Book-E */ -#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */ -#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */ -#define CONFIG_FSL_LAW /* FreeScale Local Access Window */ -#define CONFIG_P2020 /* FreeScale P2020 */ -#define CONFIG_HWW1U1A /* eXMeritus HardwareWall HWW-1U-1A */ -#define CONFIG_MP /* Multiprocessing support */ -#define CONFIG_HWCONFIG /* Use hwconfig from environment */ - -#define CONFIG_L2_CACHE /* L2 cache enabled */ -#define CONFIG_BTB /* Branch predition enabled */ - -#define CONFIG_PANIC_HANG /* No board reset on panic */ -#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r() */ -#define CONFIG_CMD_REGINFO /* Dump various CPU regs */ - -/* - * Allow the use of 36-bit physical addresses. Device-trees with 64-bit - * addresses have known compatibility issues with some existing kernels. - */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */ - -/* Reserve plenty of RAM for malloc (we have 2GB+) */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* How much L2 cache do we map so we can use it as RAM */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -/* This is our temporary global data area just above the stack */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* The stack grows down from the global data area */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Enable IRQs and watchdog with a 1000Hz system decrementer */ -#define CONFIG_CMD_IRQ - -/* -------------------------------------------------------------------- */ - -/* - * Clock crystal configuration: - * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR) - * (2) CCB: Multiplier from SYS_CLK - * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock) - */ -#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/ -#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/ - - -/* -------------------------------------------------------------------- */ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM - * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1 - * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused) - * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3 - * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH - * 0xe800_0000 0xefff_ffff 128M Spansion FLASH - * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0) - * 0xffe0_0000 0xffef_ffff 1M CCSR - * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller - */ - -/* Virtual Memory Map */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */ - -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* Physical Memory Map */ -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf /* for ASM code */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000 /* for ASM code */ -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf /* for ASM code */ -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000 /* for ASM code */ - - -/* -------------------------------------------------------------------- */ - -/* U-Boot image (MONITOR_BASE == TEXT_BASE) */ -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc /* Top address in flash */ -#define CONFIG_SYS_TEXT_BASE 0xeff80000 /* Start of U-Boot image */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN 0x80000 /* 512kB (4 flash sectors) */ - -/* - * U-Boot Environment Image: The two sectors immediately below U-Boot - * form the U-Boot environment (regular and redundant). - */ -#define CONFIG_ENV_IS_IN_FLASH /* The environment image is stored in FLASH */ -#define CONFIG_ENV_OVERWRITE /* Allow "protected" variables to be erased */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (1 flash sector) */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) - -/* Only use 8kB of each environment sector for data */ -#define CONFIG_ENV_SIZE 0x2000 /* 8kB */ -#define CONFIG_ENV_SIZE_REDUND 0x2000 /* 8kB */ - - -/* -------------------------------------------------------------------- */ - -/* Serial Console Configuration */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Echo back characters received during a serial download */ -#define CONFIG_LOADS_ECHO - -/* Allow a serial-download to temporarily change baud */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - - -/* -------------------------------------------------------------------- */ - -/* PCI and PCI-Express Support */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCI_PNP /* Scan PCI busses */ -#define CONFIG_CMD_PCI /* Enable the "pci" command */ -#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */ -#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */ -#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */ - -/* Enable 2 of the 3 PCI-E controllers */ -#define CONFIG_PCIE3 -#undef CONFIG_PCIE2 -#define CONFIG_PCIE1 - -/* Display human-readable names when initializing */ -#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB" -#define CONFIG_SYS_PCIE2_NAME "Unused" -#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531" - -/* - * PCI bus addresses - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 - - -/* -------------------------------------------------------------------- */ - -/* Generic FreeScale hardware I2C support */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#define CONFIG_CMD_I2C - -/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */ -#define CONFIG_CMD_DATE -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 0 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* Turn off RTC square-wave output to save battery */ -#define CONFIG_SYS_RTC_DS1337_NOOSC - -/* - * AT24C128N EEPROM at I2C0-0x53. - * - * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages - * of 64 bytes per page. The chip uses 2-byte addresses and has a max write - * cycle time of 20ms according to the datasheet. - * - * NOTE: Our environment is stored on regular direct-attached FLASH, this - * chip is only used as a write-protected backup for certain key settings - * such as the serial# and macaddr values. (EG: "env import") - */ -#define CONFIG_CMD_EEPROM -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21 - -/* - * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554). You - * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command - * will not be able to access the chip. - */ -#define CONFIG_PCA953X -#define CONFIG_CMD_PCA953X -#define CONFIG_CMD_PCA953X_INFO -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f - - -/* -------------------------------------------------------------------- */ - -/* FreeScale DDR2/3 SDRAM Controller */ -#define CONFIG_SYS_FSL_DDR2 /* Our SDRAM slot is DDR2 */ -#define CONFIG_DDR_ECC /* Enable ECC by default */ -#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */ -#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */ -#define CONFIG_VERY_BIG_RAM /* Allow 2GB+ of RAM */ -#define CONFIG_CMD_SDRAM - -/* Standard P2020 DDR controller parameters */ -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* Make sure to tell the DDR controller to preinitialze all of RAM */ -#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER - - -/* -------------------------------------------------------------------- */ - -/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -/* Flash banks (2x 128MB) */ -#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull) -#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS } - -/* - * Flash access modes and timings (values are the defaults after a RESET). - * - * NOTE: These could probably be optimized but are more than sufficient for - * this particular system for the moment. - */ -#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V) -#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -/* Configure both flash banks */ -#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS)) -#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS)) -#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB) -#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB) - -/* Flash timeouts (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */ - -/* Quiet flash testing */ -#define CONFIG_SYS_FLASH_QUIET_TEST - -/* Make program/erase count down from 45/5 (9....8....7....) */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - - -/* -------------------------------------------------------------------- */ - -/* Ethernet Device Support */ -#define CONFIG_MII /* Enable MII PHY code */ -#define CONFIG_MII_DEFAULT_TSEC /* ??? Copied from P2020DS */ -#define CONFIG_PHY_GIGE /* Support Gigabit PHYs */ -#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */ - -/* Turn on various helpful networking commands */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING - -/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */ -#define CONFIG_TSEC_ENET -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 -#define CONFIG_TSEC3 -#define CONFIG_TSEC1_NAME "owt0" -#define CONFIG_TSEC2_NAME "owt1" -#define CONFIG_TSEC3_NAME "peer" -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 -#define TSEC3_PHY_ADDR 4 -#define TSEC3_PHY_ADDR_CPUA 4 -#define TSEC3_PHY_ADDR_CPUB 5 - -/* PCI-E dual-port E1000 (external ethernet ports) */ -#define CONFIG_E1000 -#define CONFIG_E1000_SPI -#define CONFIG_E1000_SPI_GENERIC -#define CONFIG_CMD_E1000 - -/* We need the SPI infrastructure to poke the E1000's EEPROM */ -#define CONFIG_SPI -#define CONFIG_SPI_X -#define CONFIG_CMD_SPI -#define MAX_SPI_BYTES 32 - - -/* -------------------------------------------------------------------- */ - -/* USB Thumbdrive Device Support */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_USB - -/* Partition and Filesystem support */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - - -/* -------------------------------------------------------------------- */ - -/* Command line configuration. */ -#define CONFIG_CMDLINE_EDITING /* Enable command editing */ -#define CONFIG_COMMAND_HISTORY /* Enable command history */ -#define CONFIG_AUTO_COMPLETE /* Enable command completion */ -#define CONFIG_SYS_LONGHELP /* Enable detailed command help */ -#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */ -#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */ -#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */ -#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */ -#define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */ - -/* A little extra magic here for the prompt */ -#define CONFIG_SYS_PROMPT hww1u1a_get_ps1() -#ifndef __ASSEMBLY__ -const char *hww1u1a_get_ps1(void); -#endif - -/* Include a bunch of default commands we probably want */ -#include <config_cmd_default.h> - -/* Other helpful shell-like commands */ -#define CONFIG_MD5 -#define CONFIG_SHA1 -#define CONFIG_CMD_MD5SUM -#define CONFIG_CMD_SHA1SUM -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SETEXPR - - -/* -------------------------------------------------------------------- */ - -/* Image manipulation and booting */ - -/* We use the OpenFirmware-esque "Flattened Device Tree" */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMD_ELF -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB */ - -/* This is the default address for commands with an optional address arg */ -#define CONFIG_LOADADDR 100000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 - -/* Test memory starting from the default load address to just below 2GB */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_END 0x7f000000 - -#define CONFIG_BOOTDELAY 20 -#define CONFIG_BOOTCOMMAND "echo Not yet flashed" -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1" - -/* Extra environment parameters */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethprime=e1000#0\0" \ - "ethrotate=no\0" \ - "setbootargs=setenv bootargs " \ - ""${bootargs} "CONFIG_BOOTARGS_DYNAMIC""\0" \ - "perf_mode=performance\0" \ - "hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=ulpi\0" \ - "flkernel=0xe8000000\0" \ - "flinitramfs=0xe8800000\0" \ - "fldevicetree=0xeff20000\0" \ - "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \ - "flboot=run preboot; run flbootm\0" \ - "restore_eeprom=i2c dev 0 && " \ - "eeprom read $loadaddr 0x0000 0x2000 && " \ - "env import -c $loadaddr 0x2000\0" - -#endif /* __CONFIG_H */

This board is old and is using CONFIG_I2C_X, which is wrong.

Signed-off-by: Marek Vasut marex@denx.de Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Simon Glass sjg@chromium.org Cc: Heiko Schocher hs@denx.de --- arch/powerpc/cpu/mpc8260/Kconfig | 4 - board/ids/ids8247/Kconfig | 12 - board/ids/ids8247/MAINTAINERS | 6 - board/ids/ids8247/Makefile | 11 - board/ids/ids8247/ids8247.c | 390 --------------------------------- configs/IDS8247_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/IDS8247.h | 462 --------------------------------------- 8 files changed, 1 insertion(+), 888 deletions(-) delete mode 100644 board/ids/ids8247/Kconfig delete mode 100644 board/ids/ids8247/MAINTAINERS delete mode 100644 board/ids/ids8247/Makefile delete mode 100644 board/ids/ids8247/ids8247.c delete mode 100644 configs/IDS8247_defconfig delete mode 100644 include/configs/IDS8247.h

diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index 7f246ff..7e28170 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -52,9 +52,6 @@ config TARGET_MPC8266ADS config TARGET_VOVPN_GW bool "Support VoVPN-GW"

-config TARGET_IDS8247 - bool "Support IDS8247" - config TARGET_KM82XX bool "Support km82xx"

@@ -75,7 +72,6 @@ source "board/ep82xxm/Kconfig" source "board/freescale/mpc8266ads/Kconfig" source "board/funkwerk/vovpn-gw/Kconfig" source "board/gw8260/Kconfig" -source "board/ids/ids8247/Kconfig" source "board/iphase4539/Kconfig" source "board/keymile/km82xx/Kconfig" source "board/muas3001/Kconfig" diff --git a/board/ids/ids8247/Kconfig b/board/ids/ids8247/Kconfig deleted file mode 100644 index bbab727..0000000 --- a/board/ids/ids8247/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IDS8247 - -config SYS_BOARD - default "ids8247" - -config SYS_VENDOR - default "ids" - -config SYS_CONFIG_NAME - default "IDS8247" - -endif diff --git a/board/ids/ids8247/MAINTAINERS b/board/ids/ids8247/MAINTAINERS deleted file mode 100644 index 3173cdf..0000000 --- a/board/ids/ids8247/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IDS8247 BOARD -M: Heiko Schocher hs@denx.de -S: Maintained -F: board/ids/ids8247/ -F: include/configs/IDS8247.h -F: configs/IDS8247_defconfig diff --git a/board/ids/ids8247/Makefile b/board/ids/ids8247/Makefile deleted file mode 100644 index 99c47b6..0000000 --- a/board/ids/ids8247/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Heiko Schocher, DENX Software Engineering, hs@denx.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ids8247.o diff --git a/board/ids/ids8247/ids8247.c b/board/ids/ids8247/ids8247.c deleted file mode 100644 index 1b2d0e0..0000000 --- a/board/ids/ids8247/ids8247.c +++ /dev/null @@ -1,390 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, hs@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <libfdt_env.h> -#include <fdt_support.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ - /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */ -#else /* normal I/O port pins */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ -#endif - /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ - /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ - /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ - /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */ - /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */ - /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */ - /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */ - /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */ - /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */ - /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */ - /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */ - /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */ - /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */ -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */ -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: IDS 8247\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - long psize; - - psize = 16 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2, - (uchar *) CONFIG_SYS_SDRAM_BASE); -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -int misc_init_r (void) -{ - gd->bd->bi_flashstart = 0xff800000; - return 0; -} - -#if defined(CONFIG_CMD_NAND) -#include <nand.h> -#include <linux/mtd/mtd.h> -#include <asm/io.h> - -static u8 hwctl; - -static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) { - hwctl |= 0x1; - writeb(0x00, (this->IO_ADDR_W + 0x0a)); - } else { - hwctl &= ~0x1; - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if ( ctrl & NAND_ALE ) { - hwctl |= 0x2; - writeb(0x00, (this->IO_ADDR_W + 0x09)); - } else { - hwctl &= ~0x2; - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if ( (ctrl & NAND_NCE) != NAND_NCE) - writeb(0x00, (this->IO_ADDR_W + 0x0c)); - else - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); - -} - -static u_char ids_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - - return readb(this->IO_ADDR_R); -} - -static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *nand = mtd->priv; - int i; - - for (i = 0; i < len; i++) { - if (hwctl & 0x1) - writeb(buf[i], (nand->IO_ADDR_W + 0x02)); - else if (hwctl & 0x2) - writeb(buf[i], (nand->IO_ADDR_W + 0x01)); - else - writeb(buf[i], nand->IO_ADDR_W); - } -} - -static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - int i; - - for (i = 0; i < len; i++) { - buf[i] = readb(this->IO_ADDR_R); - } -} - -static int ids_nand_dev_ready(struct mtd_info *mtd) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); - return 1; -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->ecc.mode = NAND_ECC_SOFT; - - /* Reference hardware control function */ - nand->cmd_ctrl = ids_nand_hwctrl; - nand->read_byte = ids_nand_read_byte; - nand->write_buf = ids_nand_write_buf; - nand->read_buf = ids_nand_read_buf; - nand->dev_ready = ids_nand_dev_ready; - nand->chip_delay = 12; - - return 0; -} - -#endif /* CONFIG_CMD_NAND */ - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup( blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/configs/IDS8247_defconfig b/configs/IDS8247_defconfig deleted file mode 100644 index b4dd23f..0000000 --- a/configs/IDS8247_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_IDS8247=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 19d0e9c..71dd621 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +IDS8247 powerpc mpc8260 - - Heiko Schocher hs@denx.de HWW1U1A powerpc mpc85xx - - Kyle Moffett Kyle.D.Moffett@boeing.com hymod powerpc mpc8260 - - Murray Jensen Murray.Jensen@csiro.au MHPC powerpc mpc8xx - - Frank Gottschling fgottschling@eltec.de diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h deleted file mode 100644 index 8ccb0ff..0000000 --- a/include/configs/IDS8247.h +++ /dev/null @@ -1,462 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, hs@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_IDS8247 1 -#define CPU_ID_STR "MPC8247" -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=ttyS0,115200\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/IDS8247/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ffa00000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000080) -#define I2C_TRISTATE (iop->pdir &= ~0x00000080) -#define I2C_READ ((iop->pdat & 0x00000080) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ - else iop->pdat &= ~0x00000080 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ - else iop->pdat &= ~0x00000100 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#if 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X -#endif - -/* - * select serial console configuration - * use the extern UART for the console - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 14745600 - -#define CONFIG_SYS_UART_BASE 0xE0000000 -#define CONFIG_SYS_UART_SIZE 0x10000 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000) - - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" - - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#define CONFIG_ETHER_ON_FCC1 -#define FCC_ENET - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK9 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH0_SIZE 8 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Environment in flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND0_BASE 0xE1000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -#endif /* CONFIG_CMD_NAND */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ - -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) -#define CONFIG_SYS_HID0_FINAL 0 -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR 0 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 16 bit FLASH - * 1 60x GPCM 8 bit NAND - * 2 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit UART - * - */ - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ - -#define CONFIG_SYS_MPTPR 0x6600 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_SCY_6_CLK ) - -#if defined(CONFIG_CMD_NAND) -/* Bank 1 - NAND Flash -*/ -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE -#define CONFIG_SYS_NAND_SIZE 0x8000 - -#define CONFIG_SYS_OR_TIMING_NAND 0x000036 - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND ) -#endif - -/* Bank 2 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 - -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2 - - -/* SDRAM initialization values -*/ -#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_2C |\ - PSDMR_WRC_3C |\ - PSDMR_CL_3) - -/* Bank 3 - UART -*/ - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) - -#endif /* __CONFIG_H */

This board is old and is using CONFIG_I2C_X, which is wrong.

Signed-off-by: Marek Vasut marex@denx.de Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Simon Glass sjg@chromium.org Cc: Heiko Schocher hs@denx.de --- arch/powerpc/cpu/mpc8260/Kconfig | 4 - board/tqc/tqm8260/Kconfig | 12 - board/tqc/tqm8260/MAINTAINERS | 16 - board/tqc/tqm8260/Makefile | 8 - board/tqc/tqm8260/README | 415 -------------------------- board/tqc/tqm8260/tqm8260.c | 352 ---------------------- configs/TQM8255_AA_defconfig | 4 - configs/TQM8260_AA_defconfig | 4 - configs/TQM8260_AB_defconfig | 4 - configs/TQM8260_AC_defconfig | 4 - configs/TQM8260_AD_defconfig | 4 - configs/TQM8260_AE_defconfig | 4 - configs/TQM8260_AF_defconfig | 4 - configs/TQM8260_AG_defconfig | 4 - configs/TQM8260_AH_defconfig | 4 - configs/TQM8260_AI_defconfig | 4 - configs/TQM8265_AA_defconfig | 4 - doc/README.scrapyard | 1 + include/configs/TQM8260.h | 620 --------------------------------------- 19 files changed, 1 insertion(+), 1471 deletions(-) delete mode 100644 board/tqc/tqm8260/Kconfig delete mode 100644 board/tqc/tqm8260/MAINTAINERS delete mode 100644 board/tqc/tqm8260/Makefile delete mode 100644 board/tqc/tqm8260/README delete mode 100644 board/tqc/tqm8260/tqm8260.c delete mode 100644 configs/TQM8255_AA_defconfig delete mode 100644 configs/TQM8260_AA_defconfig delete mode 100644 configs/TQM8260_AB_defconfig delete mode 100644 configs/TQM8260_AC_defconfig delete mode 100644 configs/TQM8260_AD_defconfig delete mode 100644 configs/TQM8260_AE_defconfig delete mode 100644 configs/TQM8260_AF_defconfig delete mode 100644 configs/TQM8260_AG_defconfig delete mode 100644 configs/TQM8260_AH_defconfig delete mode 100644 configs/TQM8260_AI_defconfig delete mode 100644 configs/TQM8265_AA_defconfig delete mode 100644 include/configs/TQM8260.h

diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index 7e28170..e28628f 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -55,9 +55,6 @@ config TARGET_VOVPN_GW config TARGET_KM82XX bool "Support km82xx"

-config TARGET_TQM8260 - bool "Support TQM8260" - config TARGET_TQM8272 bool "Support TQM8272"

@@ -79,7 +76,6 @@ source "board/pm826/Kconfig" source "board/pm828/Kconfig" source "board/ppmc8260/Kconfig" source "board/sacsng/Kconfig" -source "board/tqc/tqm8260/Kconfig" source "board/tqc/tqm8272/Kconfig"

endmenu diff --git a/board/tqc/tqm8260/Kconfig b/board/tqc/tqm8260/Kconfig deleted file mode 100644 index 90a96eb..0000000 --- a/board/tqc/tqm8260/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TQM8260 - -config SYS_BOARD - default "tqm8260" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM8260" - -endif diff --git a/board/tqc/tqm8260/MAINTAINERS b/board/tqc/tqm8260/MAINTAINERS deleted file mode 100644 index 266910f..0000000 --- a/board/tqc/tqm8260/MAINTAINERS +++ /dev/null @@ -1,16 +0,0 @@ -TQM8260 BOARD -M: Wolfgang Denk wd@denx.de -S: Maintained -F: board/tqc/tqm8260/ -F: include/configs/TQM8260.h -F: configs/TQM8255_AA_defconfig -F: configs/TQM8260_AA_defconfig -F: configs/TQM8260_AB_defconfig -F: configs/TQM8260_AC_defconfig -F: configs/TQM8260_AD_defconfig -F: configs/TQM8260_AE_defconfig -F: configs/TQM8260_AF_defconfig -F: configs/TQM8260_AG_defconfig -F: configs/TQM8260_AH_defconfig -F: configs/TQM8260_AI_defconfig -F: configs/TQM8265_AA_defconfig diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile deleted file mode 100644 index 6b8573d..0000000 --- a/board/tqc/tqm8260/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = tqm8260.o ../tqm8xx/load_sernum_ethaddr.o diff --git a/board/tqc/tqm8260/README b/board/tqc/tqm8260/README deleted file mode 100644 index 93b5506..0000000 --- a/board/tqc/tqm8260/README +++ /dev/null @@ -1,415 +0,0 @@ - -This file contains basic information on the port of U-Boot to TQM8260. -All the changes fit in the common U-Boot infrastructure, providing a -new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260, -type "make TQM8260_config", edit the "include/config_TQM8260.h" file -if necessary, then type "make". - - -Common file modifications: --------------------------- - -The following common files have been modified by this project: -(starting from the ppcboot-0.9.3/ directory) - -MAKEALL - TQM8260 entry added -Makefile - TQM8260_config entry added -arch/powerpc/cpu/mpc8260/Makefile - soft_i2c.o module added -arch/powerpc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious - bug fixed (fcr -> scr) -arch/powerpc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added -include/flash.h - added definitions for the AM29LV640D Flash chip - - -New files: ----------- - -The following new files have been added by this project: -(starting from the ppcboot-0.9.3/ directory) - -board/tqm8260/ - board-specific directory -board/tqm8260/Makefile - board-specific makefile -board/tqm8260/config.mk - config file -board/tqm8260/flash.c - flash driver (for AM29LV640D) -board/tqm8260/ppcboot.lds - linker script -board/tqm8260/tqm8260.c - ioport and memory initialization -arch/powerpc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver -include/config_TQM8260.h - main configuration file - - -New configuration options: --------------------------- - -CONFIG_TQM8260 - - Main board-specific option (should be defined for TQM8260). - -CONFIG_82xx_CONS_SMC1 - - If defined, SMC1 will be used as the console - -CONFIG_82xx_CONS_SMC2 - - If defined, SMC2 will be used as the console - -CONFIG_SYS_INIT_LOCAL_SDRAM - - If defined, the SDRAM on the local bus will be initialized and - mapped at BR2. - - -Acceptance criteria tests: --------------------------- - -The following tests have been conducted to validate the port of U-Boot -to TQM8260: - -1. Operation on serial console: - -With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file, -the U-Boot output appeared on the serial terminal connected to COM1 as -follows: - ------------------------------------------------------------------------------- -=> help -go - start application at address 'addr' -run - run commands in an environment variable -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -rarpboot- boot image via network using RARP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -loads - load S-Record file over serial line -loadb - load binary file over serial line (kermit mode) -md - memory display -mm - memory modify (auto-incrementing) -nm - memory modify (constant address) -mw - memory write (fill) -cp - memory copy -cmp - memory compare -crc32 - checksum calculation -base - print or set address offset -printenv- print environment variables -setenv - set environment variables -saveenv - save environment variables to persistent storage -protect - enable or disable FLASH write protection -erase - erase FLASH memory -flinfo - print FLASH memory information -bdinfo - print Board Info structure -iminfo - print header information for application image -coninfo - print console devices and informations -eeprom - EEPROM sub-system -loop - infinite loop on address range -mtest - simple RAM test -icache - enable or disable instruction cache -dcache - enable or disable data cache -reset - Perform RESET of the CPU -echo - echo args to console -version - print monitor version -help - print online help -? - alias for 'help' -=> ------------------------------------------------------------------------------- - - -2. Flash driver operation - -The following sequence was performed to test the "flinfo" command: - ------------------------------------------------------------------------------- -=> flinfo - -Bank # 1: AMD 29LV640D (64 M, uniform sector) - Size: 32 MB in 128 Sectors - Sector Start Addresses: - 40000000 40040000 (RO) 40080000 400C0000 40100000 - 40140000 40180000 401C0000 40200000 40240000 - 40280000 402C0000 40300000 40340000 40380000 - 403C0000 40400000 40440000 40480000 404C0000 - 40500000 40540000 40580000 405C0000 40600000 - 40640000 40680000 406C0000 40700000 40740000 - 40780000 407C0000 40800000 40840000 40880000 - 408C0000 40900000 40940000 40980000 409C0000 - 40A00000 40A40000 40A80000 40AC0000 40B00000 - 40B40000 40B80000 40BC0000 40C00000 40C40000 - 40C80000 40CC0000 40D00000 40D40000 40D80000 - 40DC0000 40E00000 40E40000 40E80000 40EC0000 - 40F00000 40F40000 40F80000 40FC0000 41000000 - 41040000 41080000 410C0000 41100000 41140000 - 41180000 411C0000 41200000 41240000 41280000 - 412C0000 41300000 41340000 41380000 413C0000 - 41400000 41440000 41480000 414C0000 41500000 - 41540000 41580000 415C0000 41600000 41640000 - 41680000 416C0000 41700000 41740000 41780000 - 417C0000 41800000 41840000 41880000 418C0000 - 41900000 41940000 41980000 419C0000 41A00000 - 41A40000 41A80000 41AC0000 41B00000 41B40000 - 41B80000 41BC0000 41C00000 41C40000 41C80000 - 41CC0000 41D00000 41D40000 41D80000 41DC0000 - 41E00000 41E40000 41E80000 41EC0000 41F00000 - 41F40000 41F80000 41FC0000 -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test the erase command: - ------------------------------------------------------------------------------- -=> cp 0 40080000 10 -Copy to Flash... done -=> erase 40080000 400bffff -Erase Flash from 0x40080000 to 0x400bffff -.. done -Erased 1 sectors -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> cp 0 40080000 10 -Copy to Flash... done -=> erase 1:2 -Erase Flash Sectors 2-2 in Bank # 1 -.. done -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> cp 0 40080000 10 -Copy to Flash... done -=> cp 0 400c0000 10 -Copy to Flash... done -=> erase 1:2-3 -Erase Flash Sectors 2-3 in Bank # 1 -... done -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> md 400c0000 -400c0000: ffffffff ffffffff ffffffff ffffffff ................ -400c0010: ffffffff ffffffff ffffffff ffffffff ................ -400c0020: ffffffff ffffffff ffffffff ffffffff ................ -400c0030: ffffffff ffffffff ffffffff ffffffff ................ -400c0040: ffffffff ffffffff ffffffff ffffffff ................ -400c0050: ffffffff ffffffff ffffffff ffffffff ................ -400c0060: ffffffff ffffffff ffffffff ffffffff ................ -400c0070: ffffffff ffffffff ffffffff ffffffff ................ -400c0080: ffffffff ffffffff ffffffff ffffffff ................ -400c0090: ffffffff ffffffff ffffffff ffffffff ................ -400c00a0: ffffffff ffffffff ffffffff ffffffff ................ -400c00b0: ffffffff ffffffff ffffffff ffffffff ................ -400c00c0: ffffffff ffffffff ffffffff ffffffff ................ -400c00d0: ffffffff ffffffff ffffffff ffffffff ................ -400c00e0: ffffffff ffffffff ffffffff ffffffff ................ -400c00f0: ffffffff ffffffff ffffffff ffffffff ................ -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test the Flash programming commands: - ------------------------------------------------------------------------------- -=> erase 40080000 400bffff -Erase Flash from 0x40080000 to 0x400bffff -.. done -Erased 1 sectors -=> cp 0 40080000 10 -Copy to Flash... done -=> md 0 -00000000: 00000000 00000104 61100200 01000000 ........a....... -00000010: 00000000 00000000 81140000 82000100 ................ -00000020: 01080000 00004000 22800000 00000600 ......@."....... -00000030: 00200800 00000000 10000100 00008000 . .............. -00000040: 00812000 00000200 00020000 80000000 .. ............. -00000050: 00028001 00001000 00040400 00000200 ................ -00000060: 20480000 00000000 20090000 00142000 H...... ..... . -00000070: 00000000 00004000 24210000 10000000 ......@.$!...... -00000080: 02440002 10000000 00200008 00000000 .D....... ...... -00000090: 02440900 00000000 30a40000 00004400 .D......0.....D. -000000a0: 04420800 00000000 00000040 00020000 .B.........@.... -000000b0: 05020000 00100000 00060000 00000000 ................ -000000c0: 00400000 00000000 00080000 00040000 .@.............. -000000d0: 10400000 00800004 00000000 00000200 .@.............. -000000e0: 80890000 00010004 00080000 00000020 ............... -000000f0: 08000000 10000000 00010000 00000000 ................ -=> md 40080000 -40080000: 00000000 00000104 61100200 01000000 ........a....... -40080010: 00000000 00000000 81140000 82000100 ................ -40080020: 01080000 00004000 22800000 00000600 ......@."....... -40080030: 00200800 00000000 10000100 00008000 . .............. -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test storage of the environment -variables in Flash: - ------------------------------------------------------------------------------- -=> setenv foo bar -=> saveenv -Un-Protected 1 sectors -Erasing Flash... -.. done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=> reset -... -=> printenv -bootdelay=CONFIG_BOOTDELAY -baudrate=9600 -ipaddr=192.168.4.7 -serverip=192.168.4.1 -ethaddr=66:55:44:33:22:11 -foo=bar -stdin=serial -stdout=serial -stderr=serial - -Environment size: 170/262140 bytes -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test image download and run over -Ethernet interface (both interfaces were tested): - ------------------------------------------------------------------------------- -=> tftpboot 40000 hello_world.bin -ARP broadcast 1 -TFTP from server 192.168.2.2; our IP address is 192.168.2.7 -Filename 'hello_world.bin'. -Load address: 0x40000 -Loading: ############# -done -Bytes transferred = 65912 (10178 hex) -=> go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "<NULL>" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test eeprom read/write commands: - ------------------------------------------------------------------------------- -=> md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|... -000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|... -000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L -000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=> eeprom write 40000 0 40 - -EEPROM write: addr 00040000 off 0000 count 64 ... done -=> mw 50000 0 1000 -=> eeprom read 50000 0 40 - -EEPROM read: addr 00050000 off 0000 count 64 ... done -=> md 50000 -00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00050010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x -00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00050040: 00000000 00000000 00000000 00000000 ................ -00050050: 00000000 00000000 00000000 00000000 ................ -00050060: 00000000 00000000 00000000 00000000 ................ -00050070: 00000000 00000000 00000000 00000000 ................ -00050080: 00000000 00000000 00000000 00000000 ................ -00050090: 00000000 00000000 00000000 00000000 ................ -000500a0: 00000000 00000000 00000000 00000000 ................ -000500b0: 00000000 00000000 00000000 00000000 ................ -000500c0: 00000000 00000000 00000000 00000000 ................ -000500d0: 00000000 00000000 00000000 00000000 ................ -000500e0: 00000000 00000000 00000000 00000000 ................ -000500f0: 00000000 00000000 00000000 00000000 ................ -=> ------------------------------------------------------------------------------- - - -Patch per Mon, 06 Aug 2001 17:57:27: - -- upgraded Flash support (added support for the following chips: - AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B) -- BCR tweakage for the 8260 bus mode -- SIUMCR tweakage enabling the MI interrupt (IRQ7) - -To simplify switching between the bus modes, a new configuration -option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h" -file. If it is defined, BCR will be configured for the 60x mode, -otherwise - for the 8260 mode. - -Concerning the SIUMCR modification: it's hard to predict whether it -will induce any problems on the other (60x mode) board. However, the -problems (if they appear) should be easy to notice - if the board -does not boot, it's most likely caused by the DPPC configuration in -SIUMCR. diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c deleted file mode 100644 index c361f18..0000000 --- a/board/tqc/tqm8260/tqm8260.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - - if (i < 0 || strncmp(buf, "TQM82", 5)) { - puts ("### No HW ID - assuming TQM8260\n"); - return (0); - } - - puts (buf); - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - long size8, size9; -#endif - long psize, lsize; - - psize = 16 * 1024 * 1024; - lsize = 0; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#if 0 /* Just for debugging */ -#define prt_br_or(brX,orX) do { \ - ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ - ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ - printf ("\n" \ - #brX " 0x%08x " #orX " 0x%08x " \ - "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ - memctl->memc_ ## brX, memctl->memc_ ## orX, \ - start, start+sizem, (sizem+1)>>20); \ - } while (0) - prt_br_or (br0, or0); - prt_br_or (br1, or1); - prt_br_or (br2, or2); - prt_br_or (br3, or3); -#endif - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - - /* Local SDRAM setup: - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CONFIG_SYS_LSRT; - size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) SDRAM_BASE2_PRELIM); - - if (size8 < size9) { - lsize = size9; - printf ("Local:9COL - %ld MB) using ", lsize >> 20); - } else { - lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - printf ("Local:8COL - %ld MB) using ", lsize >> 20); - } - -#if 0 - /* Set up BR2 so that the local SDRAM goes - * right after the 60x SDRAM - */ - memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | - (CONFIG_SYS_SDRAM_BASE + psize); -#endif -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -/* ------------------------------------------------------------------------- */ diff --git a/configs/TQM8255_AA_defconfig b/configs/TQM8255_AA_defconfig deleted file mode 100644 index a9f9f01..0000000 --- a/configs/TQM8255_AA_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8255,300MHz" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AA_defconfig b/configs/TQM8260_AA_defconfig deleted file mode 100644 index b762fe4..0000000 --- a/configs/TQM8260_AA_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AB_defconfig b/configs/TQM8260_AB_defconfig deleted file mode 100644 index 6ff8d17..0000000 --- a/configs/TQM8260_AB_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AC_defconfig b/configs/TQM8260_AC_defconfig deleted file mode 100644 index 6ff8d17..0000000 --- a/configs/TQM8260_AC_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AD_defconfig b/configs/TQM8260_AD_defconfig deleted file mode 100644 index 3f406a4..0000000 --- a/configs/TQM8260_AD_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AE_defconfig b/configs/TQM8260_AE_defconfig deleted file mode 100644 index 1077b19..0000000 --- a/configs/TQM8260_AE_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,266MHz" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AF_defconfig b/configs/TQM8260_AF_defconfig deleted file mode 100644 index 3f406a4..0000000 --- a/configs/TQM8260_AF_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AG_defconfig b/configs/TQM8260_AG_defconfig deleted file mode 100644 index b0d67fa..0000000 --- a/configs/TQM8260_AG_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AH_defconfig b/configs/TQM8260_AH_defconfig deleted file mode 100644 index 65c73e8..0000000 --- a/configs/TQM8260_AH_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,L2_CACHE,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AI_defconfig b/configs/TQM8260_AI_defconfig deleted file mode 100644 index 3f406a4..0000000 --- a/configs/TQM8260_AI_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8265_AA_defconfig b/configs/TQM8265_AA_defconfig deleted file mode 100644 index d8806c4..0000000 --- a/configs/TQM8265_AA_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8265,300MHz,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 71dd621..e9baa65 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +TQM8260 powerpc mpc8260 - - Wolfgang Denk wd@denx.de IDS8247 powerpc mpc8260 - - Heiko Schocher hs@denx.de HWW1U1A powerpc mpc85xx - - Kyle Moffett Kyle.D.Moffett@boeing.com hymod powerpc mpc8260 - - Murray Jensen Murray.Jensen@csiro.au diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h deleted file mode 100644 index 7fd12d3..0000000 --- a/include/configs/TQM8260.h +++ /dev/null @@ -1,620 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Imported from global configuration: - * CONFIG_MPC8255 - * CONFIG_MPC8265 - * CONFIG_200MHz - * CONFIG_266MHz - * CONFIG_300MHz - * CONFIG_L2_CACHE - * CONFIG_BUSMODE_60x - */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - - -#if 0 -#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ -#else -#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ -#endif - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=tqm8260/uImage\0" \ - "kernel_addr=400C0000\0" \ - "ramdisk_addr=40240000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ -#if (CONFIG_TQM8260 <= 100) - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00020000) -#define I2C_TRISTATE (iop->pdir &= ~0x00020000) -#define I2C_READ ((iop->pdat & 0x00020000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#else - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ -# ifndef CONFIG_300MHz -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -# else -# define CONFIG_8260_CLKIN 83333000 /* in Hz */ -# endif -#endif /* CONFIG_MPC8255 */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH0_SIZE 32 -#define CONFIG_SYS_FLASH1_SIZE 32 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x08000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else /* ! MPC8255 && !MPC8265 */ -# if defined(CONFIG_266MHz) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -# elif defined(CONFIG_300MHz) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) -# else -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__) -# endif -#endif /* CONFIG_MPC8255 */ - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_BUSMODE_60x -#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ - BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ -#else -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - - /* SDRAM on TQM8260 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - -/* Bank 2 - Local bus SDRAM - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL - -#define SDRAM_BASE2_PRELIM 0x80000000 - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */

This board is old and is using CONFIG_I2C_X, which is wrong.

Signed-off-by: Marek Vasut marex@denx.de Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Tom Rini trini@ti.com Cc: Wolfgang Denk wd@denx.de Cc: Simon Glass sjg@chromium.org Cc: Heiko Schocher hs@denx.de --- arch/powerpc/cpu/mpc8260/Kconfig | 4 - arch/powerpc/cpu/mpc8260/pci.c | 2 - board/tqc/tqm8272/Kconfig | 12 - board/tqc/tqm8272/MAINTAINERS | 6 - board/tqc/tqm8272/Makefile | 8 - board/tqc/tqm8272/nand.c | 264 ----------- board/tqc/tqm8272/tqm8272.c | 944 --------------------------------------- board/tqc/tqm8272/tqm8272.h | 37 -- configs/TQM8272_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/TQM8272.h | 735 ------------------------------ 11 files changed, 1 insertion(+), 2015 deletions(-) delete mode 100644 board/tqc/tqm8272/Kconfig delete mode 100644 board/tqc/tqm8272/MAINTAINERS delete mode 100644 board/tqc/tqm8272/Makefile delete mode 100644 board/tqc/tqm8272/nand.c delete mode 100644 board/tqc/tqm8272/tqm8272.c delete mode 100644 board/tqc/tqm8272/tqm8272.h delete mode 100644 configs/TQM8272_defconfig delete mode 100644 include/configs/TQM8272.h

diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index e28628f..2541400 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -55,9 +55,6 @@ config TARGET_VOVPN_GW config TARGET_KM82XX bool "Support km82xx"

-config TARGET_TQM8272 - bool "Support TQM8272" - endchoice

source "board/atc/Kconfig" @@ -76,6 +73,5 @@ source "board/pm826/Kconfig" source "board/pm828/Kconfig" source "board/ppmc8260/Kconfig" source "board/sacsng/Kconfig" -source "board/tqc/tqm8272/Kconfig"

endmenu diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c index 0a47fdc..f7bb05d 100644 --- a/arch/powerpc/cpu/mpc8260/pci.c +++ b/arch/powerpc/cpu/mpc8260/pci.c @@ -262,8 +262,6 @@ void pci_mpc8250_init (struct pci_controller *hose) | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11; -#elif defined(CONFIG_TQM8272) -/* nothing to do for this Board here */ #else /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), diff --git a/board/tqc/tqm8272/Kconfig b/board/tqc/tqm8272/Kconfig deleted file mode 100644 index 7b5cd8b..0000000 --- a/board/tqc/tqm8272/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TQM8272 - -config SYS_BOARD - default "tqm8272" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM8272" - -endif diff --git a/board/tqc/tqm8272/MAINTAINERS b/board/tqc/tqm8272/MAINTAINERS deleted file mode 100644 index 988d2b1..0000000 --- a/board/tqc/tqm8272/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TQM8272 BOARD -#M: - -S: Maintained -F: board/tqc/tqm8272/ -F: include/configs/TQM8272.h -F: configs/TQM8272_defconfig diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile deleted file mode 100644 index 8bf0241..0000000 --- a/board/tqc/tqm8272/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c deleted file mode 100644 index 7fb2dfa..0000000 --- a/board/tqc/tqm8272/nand.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -#include "tqm8272.h" - -/* UPM pattern for bus clock = 66.7 MHz */ -static const uint upmTable67[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 100 MHz */ -static const uint upmTable100[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 133.3 MHz */ -static const uint upmTable133[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -static int chipsel = 0; - -#if defined(CONFIG_CMD_NAND) - -#include <nand.h> -#include <linux/mtd/mtd.h> - -static u8 hwctl = 0; - -static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - - if (hwctl & 0x1) { - WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS); - } else if (hwctl & 0x2) { - WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS); - } else { - WRITE_NAND(byte, base); - } -} - -static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - } - if (cmd != NAND_CMD_NONE) - upmnand_write_byte (mtd, cmd); -} - -static u_char upmnand_read_byte(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - - return READ_NAND(base); -} - -static int tqm8272_dev_ready(struct mtd_info *mtdinfo) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); \ - return 1; -} - -#ifndef CONFIG_NAND_SPL -static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - buf[i] = *base; -} - -static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - *base = buf[i]; -} - -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i < len; i++) - if (buf[i] != *base) - return -1; - return 0; -} -#endif -#endif /* #ifndef CONFIG_NAND_SPL */ - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - chipsel = chip; -} - -int board_nand_init(struct nand_chip *nand) -{ - static int UpmInit = 0; - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - - if (hwinf.nand == 0) return -1; - - /* Setup the UPM */ - if (UpmInit == 0) { - switch (hwinf.busclk_real) { - case 100000000: - upmconfig (UPMB, (uint *) upmTable100, - sizeof (upmTable100) / sizeof (uint)); - break; - case 133333333: - upmconfig (UPMB, (uint *) upmTable133, - sizeof (upmTable133) / sizeof (uint)); - break; - default: - upmconfig (UPMB, (uint *) upmTable67, - sizeof (upmTable67) / sizeof (uint)); - break; - } - UpmInit = 1; - } - - /* Setup the memctrl */ - memctl->memc_or3 = CONFIG_SYS_NAND_OR; - memctl->memc_br3 = CONFIG_SYS_NAND_BR; - memctl->memc_mbmr = (MxMR_OP_NORM); - - nand->ecc.mode = NAND_ECC_SOFT; - - nand->cmd_ctrl = upmnand_hwcontrol; - nand->read_byte = upmnand_read_byte; - nand->dev_ready = tqm8272_dev_ready; - -#ifndef CONFIG_NAND_SPL - nand->write_buf = tqm8272_write_buf; - nand->read_buf = tqm8272_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = tqm8272_verify_buf; -#endif -#endif - - /* - * Select required NAND chip - */ - board_nand_select_device(nand, 0); - return 0; -} - -#endif diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c deleted file mode 100644 index d650868..0000000 --- a/board/tqc/tqm8272/tqm8272.c +++ /dev/null @@ -1,944 +0,0 @@ -/* - * (C) Copyright 2006 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -#include <command.h> -#include <netdev.h> -#ifdef CONFIG_PCI -#include <pci.h> -#include <asm/m8260_pci.h> -#endif -#include "tqm8272.h" - -#if 0 -#define deb_printf(fmt,arg...) \ - printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) -#else -#define deb_printf(fmt,arg...) \ - do { } while (0) -#endif - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -unsigned long board_get_cpu_clk_f (void); -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */ - /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* UPM pattern for slow init */ -static const uint upmTableSlow[] = -{ - /* Offset UPM Read Single RAM array entry */ - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, - /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry */ - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80, - /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for fast init */ -static const uint upmTableFast[] = -{ - /* Offset UPM Read Single RAM array entry */ - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, - /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry */ - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00, - /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - - puts ("Board: "); - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - puts (p); - } else { - puts ("No HWIB assuming TQM8272"); - } - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -static int get_cas_latency (void) -{ - /* get it from the option -ts in CIB */ - /* default is 3 */ - int ret = 3; - int pos = 0; - char *p = (char *) CIB_INFO_START_ADDR; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return ret; - } - if (*p == '-') { - if ((p[1] == 't') && (p[2] == 's')) { - return (p[4] - '0'); - } - } - p++; - pos++; - } - return ret; -} -#endif - -static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) -{ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - int clk = board_get_cpu_clk_f (); - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); - int cas; - - sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \ - PSDMR_BUFCMD); - if (busmode) { - switch (clk) { - case 66666666: - sdmr |= (PSDMR_RFRC_66MHZ_60X | \ - PSDMR_PRETOACT_66MHZ_60X | \ - PSDMR_WRC_66MHZ_60X | \ - PSDMR_BUFCMD_66MHZ_60X); - break; - case 100000000: - sdmr |= (PSDMR_RFRC_100MHZ_60X | \ - PSDMR_PRETOACT_100MHZ_60X | \ - PSDMR_WRC_100MHZ_60X | \ - PSDMR_BUFCMD_100MHZ_60X); - break; - - } - } else { - switch (clk) { - case 66666666: - sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \ - PSDMR_PRETOACT_66MHZ_SINGLE | \ - PSDMR_WRC_66MHZ_SINGLE | \ - PSDMR_BUFCMD_66MHZ_SINGLE); - break; - case 100000000: - sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \ - PSDMR_PRETOACT_100MHZ_SINGLE | \ - PSDMR_WRC_100MHZ_SINGLE | \ - PSDMR_BUFCMD_100MHZ_SINGLE); - break; - case 133333333: - sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \ - PSDMR_PRETOACT_133MHZ_SINGLE | \ - PSDMR_WRC_133MHZ_SINGLE | \ - PSDMR_BUFCMD_133MHZ_SINGLE); - break; - } - } - cas = get_cas_latency(); - sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK); - sdmr |= cas; - sdmr |= ((cas - 1) << 6); - return sdmr; -#else - return sdmr; -#endif -} - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base, int col) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - sdmr = set_sdram_timing (sdmr_ptr, sdmr, col); - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - long size8, size9; -#endif - long psize; - - psize = 16 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 8); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 9); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 8); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - - -static inline int scanChar (char *p, int len, unsigned long *number) -{ - int akt = 0; - - *number = 0; - while (akt < len) { - if ((*p >= '0') && (*p <= '9')) { - *number *= 10; - *number += *p - '0'; - p += 1; - } else { - if (*p == '-') return akt; - return -1; - } - akt ++; - } - return akt; -} - -static int dump_hwib(void) -{ - HWIB_INFO *hw = &hwinf; - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - if (i < 0) - buf[0] = '\0'; - - if (hw->OK) { - printf ("HWIB on %x\n", HWIB_INFO_START_ADDR); - printf ("serial : %s\n", buf); - printf ("ethaddr: %s\n", hw->ethaddr); - printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr); - printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs); - printf ("CPU : %lu\n", hw->cpunr); - printf ("CAN : %d\n", hw->can); - if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom); - else printf ("No EEprom\n"); - if (hw->nand) { - printf ("NAND : %x\n", hw->nand); - printf ("NAND CS: %d\n", hw->nand_cs); - } else { printf ("No NAND\n");} - printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII")); - printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \ - "60x" : "Single PQII")); - printf ("Option : %lx\n", hw->option); - printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no")); - printf ("CPM Clk: %d\n", hw->cpmcl); - printf ("CPU Clk: %d\n", hw->cpucl); - printf ("Bus Clk: %d\n", hw->buscl); - if (hw->busclk_real_ok) { - printf (" real Clk: %d\n", hw->busclk_real); - } - printf ("CAS : %d\n", get_cas_latency()); - } else { - printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR); - } - return 0; -} - -static inline int search_real_busclk (int *clk) -{ - int part = 0, pos = 0; - char *p = (char *) CIB_INFO_START_ADDR; - int ok = 0; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return 0; - } - switch (part) { - default: - if (*p == '-') { - ++part; - } - break; - case 3: - if (*p == '-') { - ++part; - break; - } - if (*p == 'b') { - ok = 1; - p++; - break; - } - if (ok) { - switch (*p) { - case '6': - *clk = 66666666; - return 1; - break; - case '1': - if (p[1] == '3') { - *clk = 133333333; - } else { - *clk = 100000000; - } - return 1; - break; - } - } - break; - } - p++; - } - return 0; -} - -int analyse_hwib (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int anz; - int part = 1, i = 0, pos = 0; - HWIB_INFO *hw = &hwinf; - - deb_printf(" %s pointer: %p\n", __FUNCTION__, p); - /* Head = TQM */ - if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - deb_printf("No HWIB\n"); - return -1; - } - p += 3; - if (scanChar (p, 4, &hw->cpunr) < 0) { - deb_printf("No CPU\n"); - return -2; - } - p +=4; - - hw->flash = 0x200000 << (*p - 'A'); - p++; - hw->flash_nr = *p - '0'; - p++; - - hw->ram = 0x2000000 << (*p - 'A'); - p++; - if (*p == '2') { - hw->ram_cs = 2; - p++; - } - - if (*p == 'A') hw->can = 1; - if (*p == 'B') hw->can = 2; - p +=1; - p +=1; /* connector */ - if (*p != '0') { - hw->eeprom = 0x1000 << (*p - 'A'); - } - p++; - - if ((*p < '0') || (*p > '9')) { - /* NAND before z-option */ - hw->nand = 0x8000000 << (*p - 'A'); - p++; - hw->nand_cs = *p - '0'; - p += 2; - } - /* z-option */ - anz = scanChar (p, 4, &hw->option); - if (anz < 0) { - deb_printf("No option\n"); - return -3; - } - if (hw->option & 0x8) hw->Bus = 1; - p += anz; - if (*p != '-') { - deb_printf("No -\n"); - return -4; - } - p++; - /* C option */ - if (*p == 'E') { - hw->SecEng = 1; - p++; - } - switch (*p) { - case 'M': hw->cpucl = 266666666; - break; - case 'P': hw->cpucl = 300000000; - break; - case 'T': hw->cpucl = 400000000; - break; - default: - deb_printf("No CPU Clk: %c\n", *p); - return -5; - break; - } - p++; - switch (*p) { - case 'I': hw->cpmcl = 200000000; - break; - case 'M': hw->cpmcl = 300000000; - break; - default: - deb_printf("No CPM Clk\n"); - return -6; - break; - } - p++; - switch (*p) { - case 'B': hw->buscl = 66666666; - break; - case 'E': hw->buscl = 100000000; - break; - case 'F': hw->buscl = 133333333; - break; - default: - deb_printf("No BUS Clk\n"); - return -7; - break; - } - p++; - - hw->OK = 1; - /* search MAC Address */ - while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return 0; - } - switch (part) { - default: - if (*p == ' ') { - ++part; - i = 0; - } - break; - case 3: /* Copy MAC address */ - if (*p == ' ') { - ++part; - i = 0; - break; - } - hw->ethaddr[i++] = *p; - if ((i % 3) == 2) - hw->ethaddr[i++] = ':'; - break; - - } - p++; - } - - hw->busclk_real_ok = search_real_busclk (&hw->busclk_real); - return 0; -} - -#if defined(CONFIG_GET_CPU_STR_F) -/* !! This routine runs from Flash */ -char get_cpu_str_f (char *buf) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int i = 0; - - buf[i++] = 'M'; - buf[i++] = 'P'; - buf[i++] = 'C'; - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - buf[i++] = *&p[3]; - buf[i++] = *&p[4]; - buf[i++] = *&p[5]; - buf[i++] = *&p[6]; - } else { - buf[i++] = '8'; - buf[i++] = '2'; - buf[i++] = '7'; - buf[i++] = 'x'; - } - buf[i++] = 0; - return 0; -} -#endif - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -/* !! This routine runs from Flash */ -unsigned long board_get_cpu_clk_f (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int i = 0; - - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - if (search_real_busclk (&i)) - return i; - } - return CONFIG_8260_CLKIN; -} -#endif - -#if CONFIG_BOARD_EARLY_INIT_R - -static int can_test (unsigned long off) -{ - volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); - - *(base + 0x17) = 'T'; - *(base + 0x18) = 'Q'; - *(base + 0x19) = 'M'; - if ((*(base + 0x17) != 'T') || - (*(base + 0x18) != 'Q') || - (*(base + 0x19) != 'M')) { - return 0; - } - return 1; -} - -static int can_config_one (unsigned long off) -{ - volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); - volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02); - volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f); - unsigned char temp; - - *cpu_if = 0x45; - temp = *ctrl; - temp |= 0x40; - *ctrl = temp; - *clkout = 0x20; - temp = *ctrl; - temp &= ~0x40; - *ctrl = temp; - return 0; -} - -static int can_config (void) -{ - int ret = 0; - can_config_one (0); - if (hwinf.can == 2) { - can_config_one (0x100); - } - /* make Test if they really there */ - ret += can_test (0); - ret += can_test (0x100); - return ret; -} - -static int init_can (void) -{ - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - int count = 0; - - if ((hwinf.OK) && (hwinf.can)) { - memctl->memc_or4 = CONFIG_SYS_CAN_OR; - memctl->memc_br4 = CONFIG_SYS_CAN_BR; - /* upm Init */ - upmconfig (UPMC, (uint *) upmTableFast, - sizeof (upmTableFast) / sizeof (uint)); - memctl->memc_mcmr = (MxMR_DSx_3_CYCL | - MxMR_GPL_x4DIS | - MxMR_RLFx_2X | - MxMR_WLFx_2X | - MxMR_OP_NORM); - /* can configure */ - count = can_config (); - printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE); - if (hwinf.can != count) printf("!!! difference to HWIB\n"); - } else { - printf ("CAN: No\n"); - } - return 0; -} - -int board_early_init_r(void) -{ - analyse_hwib (); - init_can (); - return 0; -} -#endif - -int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - dump_hwib (); - return 0; -} - -U_BOOT_CMD( - hwib, 1, 1, do_hwib_dump, - "dump HWIB'", - "" -); - -#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE -static int get_flash_timing (void) -{ - /* get it from the option -tf in CIB */ - /* default is 0x00000c84 */ - int ret = 0x00000c84; - int pos = 0; - int nr = 0; - char *p = (char *) CIB_INFO_START_ADDR; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return ret; - } - if (*p == '-') { - if ((p[1] == 't') && (p[2] == 'f')) { - p += 6; - ret = 0; - while (nr < 8) { - if ((*p >= '0') && (*p <= '9')) { - ret *= 0x10; - ret += *p - '0'; - p += 1; - nr ++; - } else if ((*p >= 'A') && (*p <= 'F')) { - ret *= 10; - ret += *p - '7'; - p += 1; - nr ++; - } else { - if (nr < 8) return 0x00000c84; - return ret; - } - } - } - } - p++; - pos++; - } - return ret; -} - -/* Update the Flash_Size and the Flash Timing */ -int update_flash_size (int flash_size) -{ - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - unsigned long reg; - unsigned long tim; - - /* I must use reg, otherwise the board hang */ - reg = memctl->memc_or0; - reg &= ~ORxU_AM_MSK; - reg |= MEG_TO_AM(flash_size >> 20); - tim = get_flash_timing (); - reg &= ~0xfff; - reg |= (tim & 0xfff); - memctl->memc_or0 = reg; - return 0; -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -int board_early_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; - return 0; -} - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm8272/tqm8272.h b/board/tqc/tqm8272/tqm8272.h deleted file mode 100644 index 1eeaf0e..0000000 --- a/board/tqc/tqm8272/tqm8272.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TQM8272_HEADER_H -#define _TQM8272_HEADER_H - -#define _NOT_USED_ 0xFFFFFFFF - -typedef struct{ - int Bus; - int flash; - int flash_nr; - int ram; - int ram_cs; - int nand; - int nand_cs; - int eeprom; - int can; - unsigned long cpunr; - unsigned long option; - int SecEng; - int cpucl; - int cpmcl; - int buscl; - int busclk_real_ok; - int busclk_real; - unsigned char OK; - unsigned char ethaddr[20]; -} HWIB_INFO; - -static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, - 0, 0, 0, 0, 0, 0}; -#endif /* __CONFIG_H */ diff --git a/configs/TQM8272_defconfig b/configs/TQM8272_defconfig deleted file mode 100644 index 0070baf..0000000 --- a/configs/TQM8272_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8272=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index e9baa65..330c74b 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +TQM8272 powerpc mpc8260 - - - TQM8260 powerpc mpc8260 - - Wolfgang Denk wd@denx.de IDS8247 powerpc mpc8260 - - Heiko Schocher hs@denx.de HWW1U1A powerpc mpc85xx - - Kyle Moffett Kyle.D.Moffett@boeing.com diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h deleted file mode 100644 index 9c7e163..0000000 --- a/include/configs/TQM8272.h +++ /dev/null @@ -1,735 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_TQM8272 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ -#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ - -#define STK82xx_150 1 /* on a STK82xx.150 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyCPM0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "hostname=tqm8272\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=$(consdev),$(baudrate)\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 300000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/tqm8272/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ - "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ - "cp.b 300000 40000000 40000;" \ - "setenv filesize;saveenv\0" \ - "cphwib=cp.b 4003fc00 33fc00 400\0" \ - "upd=run load cphwib update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_I2C 1 - -#if CONFIG_I2C -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_I2C_X - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -#else -#undef CONFIG_SYS_I2C -#undef CONFIG_HARD_I2C -#undef CONFIG_SYS_I2C_SOFT -#endif - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#define CONFIG_SYS_FCC_ETHERNET - -#if defined(CONFIG_SYS_FCC_ETHERNET) -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#else -#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#if STK82xx_150 -#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */ -#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */ -#endif - -#if STK82xx_100 -#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */ -#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */ -#endif - -#if 1 -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN -#else -#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;} - -#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;} -#endif - -#define MIIDELAY udelay(1) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#if CONFIG_I2C - #define CONFIG_CMD_I2C - #define CONFIG_CMD_DATE - #define CONFIG_CMD_DTT - #define CONFIG_CMD_EEPROM -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if 0 -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * CAN stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CAN_BASE 0x51000000 -#define CONFIG_SYS_CAN_SIZE 1 -#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMC |\ - BRx_V) - -#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI) - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */ - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_SYS_UPDATE_FLASH_SIZE - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND 0x20000 - -/* Where is the Hardwareinformation Block (from Monitor Sources) */ -#define MON_RES_LENGTH (0x0003FC00) -#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH) -#define HWIB_INFO_LEN 512 -#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) -#define CIB_INFO_LEN 512 - -#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND_CS_DIST 0x80 -#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20 -#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40 - -#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMB |\ - BRx_V) - -#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_8IDLE) - -#define CONFIG_SYS_NAND_SIZE 1 -#define CONFIG_SYS_NAND0_BASE 0x50000000 -#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) - -#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ - CONFIG_SYS_NAND2_BASE, \ - CONFIG_SYS_NAND3_BASE, \ - } - -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) -#define WRITE_NAND_UPM(d, adr, off) do \ -{ \ - volatile unsigned char *addr = (unsigned char *) (adr + off); \ - WRITE_NAND(d, addr); \ -} while(0) - -#endif /* CONFIG_CMD_NAND */ - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_PCI_SCAN_SHOW -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if 0 -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00) -#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00) -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 60x UPMB 8 bit NAND - * 3 60x UPMC 8 bit CAN - * - */ - -/* Initialize SDRAM - */ -#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ - -#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_8_CLK |\ - ORxG_TRLX) - -/* SDRAM on TQM8272 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 /* Low Value */ -/* #define CONFIG_SYS_PSRT 0x10 Fast Value */ -#define CONFIG_SYS_LSRT 0x20 /* Local Bus */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - -/* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - - -/* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A4 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ - PSDMR_SDAM_A17_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A4 |\ - PSDMR_RFRC_6_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ -#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ -#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ -#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ -#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ -#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ - -#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ -#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ -#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ -#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ -#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ -#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ - -#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ -#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ -#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ -#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ -#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ -#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ - -#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ -#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ -#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ -#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ -#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ -#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */

This is a reimplementation of the cmd_eeprom with the added bit where it can select I2C bus. Just remove this ugly duplication. If someone needs this code, there should be proper implementation submitted.

Signed-off-by: Marek Vasut marex@denx.de Cc: Andreas Bießmann andreas.biessmann@corscience.de Cc: Simon Glass sjg@chromium.org Cc: Tom Rini trini@ti.com Cc: Heiko Schocher hs@denx.de --- board/corscience/tricorder/Makefile | 2 +- board/corscience/tricorder/tricorder-eeprom.c | 251 -------------------------- board/corscience/tricorder/tricorder-eeprom.h | 41 ----- 3 files changed, 1 insertion(+), 293 deletions(-) delete mode 100644 board/corscience/tricorder/tricorder-eeprom.c delete mode 100644 board/corscience/tricorder/tricorder-eeprom.h

diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile index 266432d..c14ff07 100644 --- a/board/corscience/tricorder/Makefile +++ b/board/corscience/tricorder/Makefile @@ -8,4 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y := tricorder.o tricorder-eeprom.o led.o +obj-y := tricorder.o led.o diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c deleted file mode 100644 index 1c74a0f..0000000 --- a/board/corscience/tricorder/tricorder-eeprom.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * (C) Copyright 2013 - * Corscience GmbH & Co. KG, <www.corscience.de> - * Andreas Bießmann andreas.biessmann@corscience.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <i2c.h> - -#include "tricorder-eeprom.h" - -static inline void warn_wrong_value(const char *msg, unsigned int a, - unsigned int b) -{ - printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b); -} - -static int handle_eeprom_v0(struct tricorder_eeprom *eeprom) -{ - struct tricorder_eeprom_v0 { - uint32_t magic; - uint16_t length; - uint16_t version; - char board_name[TRICORDER_BOARD_NAME_LENGTH]; - char board_version[TRICORDER_BOARD_VERSION_LENGTH]; - char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; - uint32_t crc32; - } __packed eepromv0; - uint32_t crc; - - printf("Old EEPROM (v0), consider rewrite!\n"); - - if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) { - warn_wrong_value("length", sizeof(eepromv0), - be16_to_cpu(eeprom->length)); - return 1; - } - - memcpy(&eepromv0, eeprom, sizeof(eepromv0)); - - crc = crc32(0L, (unsigned char *)&eepromv0, - sizeof(eepromv0) - sizeof(eepromv0.crc32)); - if (be32_to_cpu(eepromv0.crc32) != crc) { - warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32), - crc); - return 1; - } - - /* Ok the content is correct, do the conversion */ - memset(eeprom->interface_version, 0x0, - TRICORDER_INTERFACE_VERSION_LENGTH); - crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); - eeprom->crc32 = cpu_to_be32(crc); - - return 0; -} - -static int handle_eeprom_v1(struct tricorder_eeprom *eeprom) -{ - uint32_t crc; - - if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) { - warn_wrong_value("length", TRICORDER_EEPROM_SIZE, - be16_to_cpu(eeprom->length)); - return 1; - } - - crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); - if (be32_to_cpu(eeprom->crc32) != crc) { - warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc); - return 1; - } - - return 0; -} - -int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom) -{ -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - unsigned int bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif - - memset(eeprom, 0, TRICORDER_EEPROM_SIZE); - - i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE); -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - i2c_set_bus_num(bus); -#endif - - if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) { - warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC, - be32_to_cpu(eeprom->magic)); - return 1; - } - - switch (be16_to_cpu(eeprom->version)) { - case 0: - return handle_eeprom_v0(eeprom); - case 1: - return handle_eeprom_v1(eeprom); - default: - warn_wrong_value("version", TRICORDER_EEPROM_VERSION, - be16_to_cpu(eeprom->version)); - return 1; - } -} - -#if !defined(CONFIG_SPL) -int tricorder_eeprom_read(unsigned devaddr) -{ - struct tricorder_eeprom eeprom; - int ret = tricorder_get_eeprom(devaddr, &eeprom); - - if (ret) - return ret; - - printf("Board type: %.*s\n", - sizeof(eeprom.board_name), eeprom.board_name); - printf("Board version: %.*s\n", - sizeof(eeprom.board_version), eeprom.board_version); - printf("Board serial: %.*s\n", - sizeof(eeprom.board_serial), eeprom.board_serial); - printf("Board interface version: %.*s\n", - sizeof(eeprom.interface_version), - eeprom.interface_version); - - return ret; -} - -int tricorder_eeprom_write(unsigned devaddr, const char *name, - const char *version, const char *serial, const char *interface) -{ - struct tricorder_eeprom eeprom, eeprom_verify; - size_t length; - uint32_t crc; - int ret; - unsigned char *p; - int i; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - unsigned int bus; -#endif - - memset(eeprom, 0, TRICORDER_EEPROM_SIZE); - memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE); - - eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC); - eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE); - eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION); - - length = min(sizeof(eeprom.board_name), strlen(name)); - strncpy(eeprom.board_name, name, length); - - length = min(sizeof(eeprom.board_version), strlen(version)); - strncpy(eeprom.board_version, version, length); - - length = min(sizeof(eeprom.board_serial), strlen(serial)); - strncpy(eeprom.board_serial, serial, length); - - if (interface) { - length = min(sizeof(eeprom.interface_version), - strlen(interface)); - strncpy(eeprom.interface_version, interface, length); - } - - crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE); - eeprom.crc32 = cpu_to_be32(crc); - -#if defined(DEBUG) - puts("Tricorder EEPROM content:\n"); - print_buffer(0, &eeprom, 1, sizeof(eeprom), 16); -#endif - -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif - - /* do page write to the eeprom */ - for (i = 0, p = (unsigned char *)&eeprom; - i < sizeof(eeprom); - i += 32, p += 32) { - ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min(sizeof(eeprom) - i, 32)); - if (ret) - break; - udelay(5000); /* 5ms write cycle timing */ - } - - ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify, - TRICORDER_EEPROM_SIZE); - - if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) { - printf("Tricorder: Could not verify EEPROM content!\n"); - ret = 1; - } - -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - i2c_set_bus_num(bus); -#endif - return ret; -} - -int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - if (argc == 3) { - ulong dev_addr = simple_strtoul(argv[2], NULL, 16); - eeprom_init(); - if (strcmp(argv[1], "read") == 0) { - int rcode; - - rcode = tricorder_eeprom_read(dev_addr); - - return rcode; - } - } else if (argc == 6 || argc == 7) { - ulong dev_addr = simple_strtoul(argv[2], NULL, 16); - char *name = argv[3]; - char *version = argv[4]; - char *serial = argv[5]; - char *interface = NULL; - eeprom_init(); - - if (argc == 7) - interface = argv[6]; - - if (strcmp(argv[1], "write") == 0) { - int rcode; - - rcode = tricorder_eeprom_write(dev_addr, name, version, - serial, interface); - - return rcode; - } - } - - return CMD_RET_USAGE; -} - -U_BOOT_CMD( - tricordereeprom, 7, 1, do_tricorder_eeprom, - "Tricorder EEPROM", - "read devaddr\n" - " - read Tricorder EEPROM at devaddr and print content\n" - "tricordereeprom write devaddr name version serial [interface]\n" - " - write Tricorder EEPROM at devaddr with 'name', 'version'" - "and 'serial'\n" - " optional add an HW interface parameter" -); -#endif /* CONFIG_SPL */ diff --git a/board/corscience/tricorder/tricorder-eeprom.h b/board/corscience/tricorder/tricorder-eeprom.h deleted file mode 100644 index 06ed9a5..0000000 --- a/board/corscience/tricorder/tricorder-eeprom.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2013 - * Corscience GmbH & Co. KG, <www.corscience.de> - * Andreas Bießmann andreas.biessmann@corscience.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef TRICORDER_EEPROM_H_ -#define TRICORDER_EEPROM_H_ - -#include <linux/compiler.h> - -#define TRICORDER_EEPROM_MAGIC 0xc2a94f52 -#define TRICORDER_EEPROM_VERSION 1 - -#define TRICORDER_BOARD_NAME_LENGTH 12 -#define TRICORDER_BOARD_VERSION_LENGTH 4 -#define TRICORDER_BOARD_SERIAL_LENGTH 12 -#define TRICORDER_INTERFACE_VERSION_LENGTH 4 - -struct tricorder_eeprom { - uint32_t magic; - uint16_t length; - uint16_t version; - char board_name[TRICORDER_BOARD_NAME_LENGTH]; - char board_version[TRICORDER_BOARD_VERSION_LENGTH]; - char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; - char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH]; - uint32_t crc32; -} __packed; - -#define TRICORDER_EEPROM_SIZE sizeof(struct tricorder_eeprom) -#define TRICORDER_EEPROM_CRC_SIZE (TRICORDER_EEPROM_SIZE - \ - sizeof(uint32_t)) - -/** - * @brief read eeprom information from a specific eeprom address - */ -int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom); - -#endif /* TRICORDER_EEPROM_H_ */