There are two types of PLL for all keystone platforms: Main PLL, Secondary PLL. Instead of duplicating the same definition for each secondary PLL, have a common function which does initialization for both PLLs. And also add proper register definitions.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/clock.c | 309 ++++++++++------------- arch/arm/mach-keystone/include/mach/clock-k2e.h | 1 + arch/arm/mach-keystone/include/mach/clock.h | 1 - arch/arm/mach-keystone/include/mach/clock_defs.h | 77 +++++- board/ti/ks2_evm/board.c | 1 - 5 files changed, 201 insertions(+), 188 deletions(-)

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 625907f..d8311ca 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -18,195 +18,157 @@ static void wait_for_completion(const struct pll_init_data *data) int i; for (i = 0; i < 100; i++) { sdelay(450); - if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0) + if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) break; } }

-void init_pll(const struct pll_init_data *data) +static inline void bypass_main_pll(const struct pll_init_data *data) +{ + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | + PLLCTL_PLLEN_MASK); + + /* 4 cycles of reference clock CLKIN*/ + sdelay(340); +} + +static void configure_mult_div(const struct pll_init_data *data) { - u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj; + u32 pllm, plld, bwadj;

pllm = data->pll_m - 1; - plld = (data->pll_d - 1) & PLL_DIV_MASK; - pllod = (data->pll_od - 1) & PLL_CLKOD_MASK; + plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;

- if (data->pll == MAIN_PLL) { - /* The requered delay before main PLL configuration */ - sdelay(210000); + /* Program Multiplier */ + if (data->pll == MAIN_PLL) + pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);

- tmp = pllctl_reg_read(data->pll, secctl); + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + CFG_PLLCTL0_PLLM_MASK, + pllm << CFG_PLLCTL0_PLLM_SHIFT); + + /* Program BWADJ */ + bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + CFG_PLLCTL0_BWADJ_MASK, + (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) & + CFG_PLLCTL0_BWADJ_MASK); + bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS; + clrsetbits_le32(keystone_pll_regs[data->pll].reg1, + CFG_PLLCTL1_BWADJ_MASK, bwadj); + + /* Program Divider */ + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + CFG_PLLCTL0_PLLD_MASK, plld); +}

- if (tmp & (PLLCTL_BYPASS)) { - setbits_le32(keystone_pll_regs[data->pll].reg1, - BIT(MAIN_ENSAT_OFFSET)); +void configure_main_pll(const struct pll_init_data *data) +{ + u32 tmp, pllod;

- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | - PLLCTL_PLLENSRC); - sdelay(340); + pllod = data->pll_od - 1;

- pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS); - pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN); - sdelay(21000); + /* 100 micro sec for stabilization */ + sdelay(210000);

- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN); - } else { - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | - PLLCTL_PLLENSRC); - sdelay(340); - } + tmp = pllctl_reg_read(data->pll, secctl);

- pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); + /* Check for Bypass */ + if (tmp & SECCTL_BYPASS_MASK) { + setbits_le32(keystone_pll_regs[data->pll].reg1, + CFG_PLLCTL1_ENSAT_MASK);

- clrsetbits_le32(keystone_pll_regs[data->pll].reg0, - PLLM_MULT_HI_SMASK, (pllm << 6)); - - /* Set the BWADJ (12 bit field) */ - tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */ - clrsetbits_le32(keystone_pll_regs[data->pll].reg0, - PLL_BWADJ_LO_SMASK, - (tmp_ctl << PLL_BWADJ_LO_SHIFT)); - clrsetbits_le32(keystone_pll_regs[data->pll].reg1, - PLL_BWADJ_HI_MASK, - (tmp_ctl >> 8)); - - /* - * Set the pll divider (6 bit field) * - * PLLD[5:0] is located in MAINPLLCTL0 - */ - clrsetbits_le32(keystone_pll_regs[data->pll].reg0, - PLL_DIV_MASK, plld); - - /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */ - pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK, - (pllod << PLL_CLKOD_SHIFT)); - wait_for_completion(data); - - pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1); - pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2); - pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3); - pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4); - pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5); - - pllctl_reg_setbits(data->pll, alnctl, 0x1f); - - /* - * Set GOSET bit in PLLCMD to initiate the GO operation - * to change the divide - */ - pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO); - sdelay(1500); /* wait for the phase adj */ - wait_for_completion(data); - - /* Reset PLL */ - pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST); - sdelay(21000); /* Wait for a minimum of 7 us*/ - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST); - sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ - - pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS); - - tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); + bypass_main_pll(data);

-#ifndef CONFIG_SOC_K2E - } else if (data->pll == TETRIS_PLL) { - bwadj = pllm >> 1; - /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ - setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); - /* - * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass) - * only applicable for Kepler - */ - clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); - /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */ - setbits_le32(keystone_pll_regs[data->pll].reg1 , - PLL_PLLRST | PLLCTL_ENSAT); - - /* - * 3 Program PLLM and PLLD in PLLCTL0 register - * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in - * PLLCTL1 register. BWADJ value must be set - * to ((PLLM + 1) >> 1) – 1) - */ - tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) | - (pllm << 6) | - (plld & PLL_DIV_MASK) | - (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS; - __raw_writel(tmp, keystone_pll_regs[data->pll].reg0); - - /* Set BWADJ[11:8] bits */ - tmp = __raw_readl(keystone_pll_regs[data->pll].reg1); - tmp &= ~(PLL_BWADJ_HI_MASK); - tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK); - __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); - /* - * 5 Wait for at least 5 us based on the reference - * clock (PLL reset time) - */ - sdelay(21000); /* Wait for a minimum of 7 us*/ - - /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */ - clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST); - /* - * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1) - * (PLL lock time) - */ - sdelay(105000); - /* 8 disable bypass */ - clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); - /* - * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass) - * only applicable for Kepler - */ - setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); -#endif - } else { - setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT); - /* - * process keeps state of Bypass bit while programming - * all other DDR PLL settings - */ - tmp = __raw_readl(keystone_pll_regs[data->pll].reg0); - tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */ - - /* - * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0, - * bypass disabled - */ - bwadj = pllm >> 1; - tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) | - (pllm << PLL_MULT_SHIFT) | - (plld & PLL_DIV_MASK) | - (pllod << PLL_CLKOD_SHIFT); - __raw_writel(tmp, keystone_pll_regs[data->pll].reg0); - - /* Set BWADJ[11:8] bits */ - tmp = __raw_readl(keystone_pll_regs[data->pll].reg1); - tmp &= ~(PLL_BWADJ_HI_MASK); - tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK); - - __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); - - /* Reset bit: bit 14 for both DDR3 & PASS PLL */ - tmp = PLL_PLLRST; - /* Set RESET bit = 1 */ - setbits_le32(keystone_pll_regs[data->pll].reg1, tmp); - /* Wait for a minimum of 7 us*/ + /* Powerdown and powerup Main Pll */ + pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK); + pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); + /* 5 micro sec */ sdelay(21000); - /* Clear RESET bit */ - clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp); - sdelay(105000);

- /* clear BYPASS (Enable PLL Mode) */ - clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); - sdelay(21000); /* Wait for a minimum of 7 us*/ + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); + } else { + bypass_main_pll(data); }

+ configure_mult_div(data); + + /* Program Output Divider */ + pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK, + ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK)); + + /* Program PLLDIVn */ + wait_for_completion(data); + pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1); + pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2); + pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3); + pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4); + pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5); + pllctl_reg_setbits(data->pll, alnctl, ALNCTL_ALN5_MASK); /* - * This is required to provide a delay between multiple - * consequent PPL configurations + * Set GOSET bit in PLLCMD to initiate the GO operation + * to change the divide */ - sdelay(210000); + pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK); + wait_for_completion(data); + + /* Reset PLL */ + pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK); + sdelay(21000); /* Wait for a minimum of 7 us*/ + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK); + sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ + + /* Enable PLL */ + pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK); + pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK); +} + +void configure_secondary_pll(const struct pll_init_data *data) +{ + int pllod = data->pll_od - 1; + + /* Enable Bypass mode */ + setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK); + setbits_le32(keystone_pll_regs[data->pll].reg0, + CFG_PLLCTL0_BYPASS_MASK); + + configure_mult_div(data); + + /* Program Output Divider */ + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + CFG_PLLCTL0_CLKOD_MASK, + (pllod << CFG_PLLCTL0_CLKOD_SHIFT) & + CFG_PLLCTL0_CLKOD_MASK); + + /* Reset PLL */ + setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); + /* Wait for 5 micro seconds */ + sdelay(21000); + + /* Select the Output of PASS PLL as input to PASS */ + if (data->pll == PASS_PLL) + setbits_le32(keystone_pll_regs[data->pll].reg1, + CFG_PLLCTL1_PAPLL_MASK); + + /* Select the Output of ARM PLL as input to ARM */ + if (data->pll == TETRIS_PLL) + setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); + + clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); + /* Wait for 500 * REFCLK cucles * (PLLD + 1) */ + sdelay(105000); + + /* Switch to PLL mode */ + clrbits_le32(keystone_pll_regs[data->pll].reg0, + CFG_PLLCTL0_BYPASS_MASK); +} + +void init_pll(const struct pll_init_data *data) +{ + if (data->pll == MAIN_PLL) + configure_main_pll(data); + else + configure_secondary_pll(data); }

void init_plls(int num_pll, struct pll_init_data *config) @@ -257,16 +219,3 @@ inline int get_max_dev_speed(void) { return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds); } - -void pass_pll_pa_clk_enable(void) -{ - u32 reg; - - reg = readl(keystone_pll_regs[PASS_PLL].reg1); - - reg |= PLLCTL_PAPLL; - writel(reg, keystone_pll_regs[PASS_PLL].reg1); - - /* wait till clock is enabled */ - sdelay(15000); -} diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h index d013b83..68e15ac 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2e.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h @@ -55,6 +55,7 @@ enum pll_type_e { CORE_PLL, PASS_PLL, DDR3_PLL, + TETRIS_PLL, };

enum { diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 9f6cfb2..7218230 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -58,7 +58,6 @@ void init_pll(const struct pll_init_data *data); unsigned long clk_get_rate(unsigned int clk); unsigned long clk_round_rate(unsigned int clk, unsigned long hz); int clk_set_rate(unsigned int clk, unsigned long hz); -void pass_pll_pa_clk_enable(void); int get_max_dev_speed(void); int get_max_arm_speed(void);

diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h index 85a046b..ff12689 100644 --- a/arch/arm/mach-keystone/include/mach/clock_defs.h +++ b/arch/arm/mach-keystone/include/mach/clock_defs.h @@ -69,7 +69,6 @@ static struct pllctl_regs *pllctl_regs[] = {

#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)

-/* PLLCTL Bits */ #define PLLCTL_BYPASS BIT(23) #define PLL_PLLRST BIT(14) #define PLLCTL_PAPLL BIT(13) @@ -102,10 +101,76 @@ static struct pllctl_regs *pllctl_regs[] = { #define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) #define PLL_BWADJ_HI_MASK 0xf

-#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) -#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) -#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) -#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) -#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) +/* PLLCTL Bits */ +#define PLLCTL_PLLENSRC_SHIF 5 +#define PLLCTL_PLLENSRC_MASK BIT(5) +#define PLLCTL_PLLRST_SHIFT 3 +#define PLLCTL_PLLRST_MASK BIT(3) +#define PLLCTL_PLLPWRDN_SHIFT 1 +#define PLLCTL_PLLPWRDN_MASK BIT(1) +#define PLLCTL_PLLEN_SHIFT 0 +#define PLLCTL_PLLEN_MASK BIT(0) + +/* SECCTL Bits */ +#define SECCTL_BYPASS_SHIFT 23 +#define SECCTL_BYPASS_MASK BIT(23) +#define SECCTL_OP_DIV_SHIFT 19 +#define SECCTL_OP_DIV_MASK (0xf << 19) + +/* PLLM Bits */ +#define PLLM_MULT_LO_SHIFT 0 +#define PLLM_MULT_LO_MASK 0x3f +#define PLLM_MULT_LO_BITS 6 + +/* PLLDIVn Bits */ +#define PLLDIV_ENABLE_SHIFT 15 +#define PLLDIV_ENABLE_MASK BIT(15) +#define PLLDIV_RATIO_SHIFT 0x0 +#define PLLDIV_RATIO_MASK 0xff + +/* PLLCMD Bits */ +#define PLLCMD_GOSET_SHIFT 0 +#define PLLCMD_GOSET_MASK BIT(0) + +/* PLLSTAT Bits */ +#define PLLSTAT_GOSTAT_SHIFT 0 +#define PLLSTAT_GOSTAT_MASK BIT(0) + +/* ALNCTL Bits */ +#define ALNCTL_ALNn_MASK 0xffff +#define ALNCTL_ALN5_MASK 0x1f + +/* Device Config PLLCTL0 */ +#define CFG_PLLCTL0_BWADJ_SHIFT 24 +#define CFG_PLLCTL0_BWADJ_MASK (0xff << 24) +#define CFG_PLLCTL0_BWADJ_BITS 8 +#define CFG_PLLCTL0_BYPASS_SHIFT 23 +#define CFG_PLLCTL0_BYPASS_MASK BIT(23) +#define CFG_PLLCTL0_CLKOD_SHIFT 19 +#define CFG_PLLCTL0_CLKOD_MASK (0xf << 19) +#define CFG_PLLCTL0_PLLM_HI_SHIFT 12 +#define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12) +#define CFG_PLLCTL0_PLLM_SHIFT 6 +#define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6) +#define CFG_PLLCTL0_PLLD_SHIFT 0 +#define CFG_PLLCTL0_PLLD_MASK 0x3f + +/* Device Config PLLCTL1 */ +#define CFG_PLLCTL1_RST_SHIFT 14 +#define CFG_PLLCTL1_RST_MASK BIT(14) +#define CFG_PLLCTL1_PAPLL_SHIFT 13 +#define CFG_PLLCTL1_PAPLL_MASK BIT(13) +#define CFG_PLLCTL1_ENSAT_SHIFT 6 +#define CFG_PLLCTL1_ENSAT_MASK BIT(6) +#define CFG_PLLCTL1_BWADJ_SHIFT 0 +#define CFG_PLLCTL1_BWADJ_MASK 0xf + +#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE_MASK | 0x0) +#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE_MASK | 0x0) +#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE_MASK | 0x1) +#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE_MASK | 0x4) +#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE_MASK | 0x17) + +#define MISC_CTL1_ARM_PLL_EN BIT(13)

#endif /* _CLOCK_DEFS_H_ */ diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 0cefb34..859a260 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -80,7 +80,6 @@ int board_eth_init(bd_t *bis) return -1; if (psc_enable_module(KS2_LPSC_CRYPTO)) return -1; - pass_pll_pa_clk_enable();

port_num = get_num_eth_ports();

As per the Documentation for K2HK[1], K2L[2], K2E[3], the definition of DEVSPEED register is same, only the supporting speeds are different. Hence use the same speed definition for all platforms, and read the DEVSPEED register to detect the supporting max speed.

[1] http://www.ti.com/lit/ds/symlink/66ak2h12.pdf [2] http://www.ti.com/lit/ds/symlink/66ak2l06.pdf [3] http://www.ti.com/lit/ds/symlink/am5k2e04.pdf

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/clock-k2e.c | 16 ------ arch/arm/mach-keystone/clock-k2hk.c | 32 ----------- arch/arm/mach-keystone/clock-k2l.c | 32 ----------- arch/arm/mach-keystone/clock.c | 71 ++++++++++++++---------- arch/arm/mach-keystone/include/mach/clock-k2e.h | 15 ++--- arch/arm/mach-keystone/include/mach/clock-k2hk.h | 14 ++--- arch/arm/mach-keystone/include/mach/clock-k2l.h | 14 ++--- arch/arm/mach-keystone/include/mach/clock.h | 9 +++ arch/arm/mach-keystone/include/mach/hardware.h | 7 +++ board/ti/ks2_evm/board_k2e.c | 1 - 10 files changed, 73 insertions(+), 138 deletions(-)

diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c index 31f6661..42092e1 100644 --- a/arch/arm/mach-keystone/clock-k2e.c +++ b/arch/arm/mach-keystone/clock-k2e.c @@ -17,22 +17,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = { [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, };

-int dev_speeds[] = { - SPD800, - SPD850, - SPD1000, - SPD1250, - SPD1350, - SPD1400, - SPD1500, - SPD1400, - SPD1350, - SPD1250, - SPD1000, - SPD850, - SPD800 -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c index 1591960..96a9f72 100644 --- a/arch/arm/mach-keystone/clock-k2hk.c +++ b/arch/arm/mach-keystone/clock-k2hk.c @@ -19,38 +19,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = { [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, };

-int dev_speeds[] = { - SPD800, - SPD1000, - SPD1200, - SPD800, - SPD800, - SPD800, - SPD800, - SPD800, - SPD1200, - SPD1000, - SPD800, - SPD800, - SPD800, -}; - -int arm_speeds[] = { - SPD800, - SPD1000, - SPD1200, - SPD1350, - SPD1400, - SPD800, - SPD1400, - SPD1350, - SPD1200, - SPD1000, - SPD800, - SPD800, - SPD800, -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c index 1c5e4d5..80c1f51 100644 --- a/arch/arm/mach-keystone/clock-k2l.c +++ b/arch/arm/mach-keystone/clock-k2l.c @@ -18,38 +18,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = { [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, };

-int dev_speeds[] = { - SPD800, - SPD1000, - SPD1200, - SPD800, - SPD800, - SPD800, - SPD800, - SPD800, - SPD1200, - SPD1000, - SPD800, - SPD800, - SPD800, -}; - -int arm_speeds[] = { - SPD800, - SPD1000, - SPD1200, - SPD1350, - SPD1400, - SPD800, - SPD1400, - SPD1350, - SPD1200, - SPD1000, - SPD800, - SPD800, - SPD800, -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index d8311ca..cad9ff3 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -11,7 +11,19 @@ #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h>

-#define MAX_SPEEDS 13 +/* DEV and ARM speed definitions as specified in DEVSPEED register */ +static int speeds[] = { + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD1500, + SPD1400, + SPD1350, + SPD1200, + SPD1000, + SPD800, +};

static void wait_for_completion(const struct pll_init_data *data) { @@ -179,43 +191,46 @@ void init_plls(int num_pll, struct pll_init_data *config) init_pll(&config[i]); }

-static int get_max_speed(u32 val, int *speeds) +static int get_max_speed(u32 val, u32 speed_supported) { - int j; + int speed;

- if (!val) - return speeds[0]; - - for (j = 1; j < MAX_SPEEDS; j++) { - if (val == 1) - return speeds[j]; - val >>= 1; + /* Left most setbit gives tess the speed */ + for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) { + if ((val & BIT(speed)) & speed_supported) + return speeds[speed]; }

+ /* If no bit is set, use SPD800 */ return SPD800; }

-#ifdef CONFIG_SOC_K2HK -static u32 read_efuse_bootrom(void) -{ - return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) : - __raw_readl(KS2_REV1_DEVSPEED); -} -#else -static inline u32 read_efuse_bootrom(void) +int get_max_arm_speed(void) { - return __raw_readl(KS2_EFUSE_BOOTROM); -} -#endif + int armspeed;

-#ifndef CONFIG_SOC_K2E -inline int get_max_arm_speed(void) -{ - return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds); + if (cpu_revision() > 0) + armspeed = __raw_readl(KS2_REV1_DEVSPEED); + else + armspeed = __raw_readl(KS2_EFUSE_BOOTROM); + + armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >> + DEVSPEED_ARMSPEED_SHIFT; + + return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS); } -#endif

-inline int get_max_dev_speed(void) +int get_max_dev_speed(void) { - return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds); + int devspeed; + + if (cpu_revision() > 0) + devspeed = __raw_readl(KS2_REV1_DEVSPEED); + else + devspeed = __raw_readl(KS2_EFUSE_BOOTROM); + + devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >> + DEVSPEED_DEVSPEED_SHIFT; + + return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS); } diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h index 68e15ac..42be2ca 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2e.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h @@ -58,17 +58,6 @@ enum pll_type_e { TETRIS_PLL, };

-enum { - SPD800, - SPD850, - SPD1000, - SPD1250, - SPD1350, - SPD1400, - SPD1500, - SPD_RSV -}; - #define CORE_PLL_800 {CORE_PLL, 16, 1, 2} #define CORE_PLL_850 {CORE_PLL, 17, 1, 2} #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} @@ -83,4 +72,8 @@ enum { #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}

+/* k2e DEV supports 800, 1000, 1200, 1350, 1400, 1500 MHz */ +#define DEV_SUPPORTED_SPEEDS 0x3FF +#define ARM_SUPPORTED_SPEEDS 0 + #endif diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h index f28d5f0..c41210c 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h @@ -64,15 +64,6 @@ enum pll_type_e { DDR3B_PLL, };

-enum { - SPD800, - SPD1000, - SPD1200, - SPD1350, - SPD1400, - SPD_RSV -}; - #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} #define CORE_PLL_999 {CORE_PLL, 122, 15, 1} @@ -100,4 +91,9 @@ enum { #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}

+/* k2h DEV supports 800, 1000, 1200 MHz */ +#define DEV_SUPPORTED_SPEEDS 0x383 +/* k2h ARM supportd 800, 1000, 1200, 1350, 1400 MHz */ +#define ARM_SUPPORTED_SPEEDS 0x3EF + #endif diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h index bb9a5c4..c145a1e 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2l.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h @@ -59,15 +59,6 @@ enum pll_type_e { DDR3_PLL, };

-enum { - SPD800, - SPD1000, - SPD1200, - SPD1350, - SPD1400, - SPD_RSV -}; - #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} #define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} @@ -92,4 +83,9 @@ enum { #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}

+/* k2l DEV supports 800, 1000, 1200 MHz */ +#define DEV_SUPPORTED_SPEEDS 0x383 +/* k2l ARM supportd 800, 1000, 1200, MHz */ +#define ARM_SUPPORTED_SPEEDS 0x383 + #endif diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 7218230..2192c0d 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -32,6 +32,15 @@ #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)

+enum { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD1500, +}; + enum clk_e { CLK_LIST(GENERATE_ENUM) }; diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 15c25b1..30022db 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -248,6 +248,13 @@ typedef volatile unsigned int *dv_reg_p; #define CPU_66AK2Ex 0xb9a6 #define CPU_66AK2Lx 0xb9a7

+/* DEVSPEED register */ +#define DEVSPEED_DEVSPEED_SHIFT 16 +#define DEVSPEED_DEVSPEED_MASK (0xfff << 16) +#define DEVSPEED_ARMSPEED_SHIFT 0 +#define DEVSPEED_ARMSPEED_MASK 0xfff +#define DEVSPEED_NUMSPDS 12 + #ifdef CONFIG_SOC_K2HK #include <asm/arch/hardware-k2hk.h> #endif diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 43dfc48..6d98b2a 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -28,7 +28,6 @@ unsigned int external_clk[ext_clk_count] = {

static struct pll_init_data core_pll_config[] = { CORE_PLL_800, - CORE_PLL_850, CORE_PLL_1000, CORE_PLL_1250, CORE_PLL_1350,

Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/clock-k2e.c | 6 ------ arch/arm/mach-keystone/clock-k2hk.c | 8 -------- arch/arm/mach-keystone/clock-k2l.c | 7 ------- arch/arm/mach-keystone/clock.c | 8 ++++++++ arch/arm/mach-keystone/include/mach/clock-k2e.h | 8 -------- arch/arm/mach-keystone/include/mach/clock-k2hk.h | 9 --------- arch/arm/mach-keystone/include/mach/clock-k2l.h | 8 -------- arch/arm/mach-keystone/include/mach/clock.h | 13 ++++++++++++- arch/arm/mach-keystone/include/mach/hardware-k2hk.h | 4 ---- arch/arm/mach-keystone/include/mach/hardware.h | 2 ++ 10 files changed, 22 insertions(+), 51 deletions(-)

diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c index 42092e1..b23d2a5 100644 --- a/arch/arm/mach-keystone/clock-k2e.c +++ b/arch/arm/mach-keystone/clock-k2e.c @@ -11,12 +11,6 @@ #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h>

-const struct keystone_pll_regs keystone_pll_regs[] = { - [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, - [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, - [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c index 96a9f72..2e36891 100644 --- a/arch/arm/mach-keystone/clock-k2hk.c +++ b/arch/arm/mach-keystone/clock-k2hk.c @@ -11,14 +11,6 @@ #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h>

-const struct keystone_pll_regs keystone_pll_regs[] = { - [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, - [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, - [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, - [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, - [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c index 80c1f51..0bd0fd6 100644 --- a/arch/arm/mach-keystone/clock-k2l.c +++ b/arch/arm/mach-keystone/clock-k2l.c @@ -11,13 +11,6 @@ #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h>

-const struct keystone_pll_regs keystone_pll_regs[] = { - [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, - [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, - [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, - [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, -}; - /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index cad9ff3..f60a0b8 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -25,6 +25,14 @@ static int speeds[] = { SPD800, };

+const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, + [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, + [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, +}; + static void wait_for_completion(const struct pll_init_data *data) { int i; diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h index 42be2ca..3bde6da 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2e.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h @@ -50,14 +50,6 @@ extern unsigned int external_clk[ext_clk_count];

#define KS2_CLK1_6 sys_clk0_6_clk

-/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - DDR3_PLL, - TETRIS_PLL, -}; - #define CORE_PLL_800 {CORE_PLL, 16, 1, 2} #define CORE_PLL_850 {CORE_PLL, 17, 1, 2} #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h index c41210c..366bf0e 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h @@ -55,15 +55,6 @@ extern unsigned int external_clk[ext_clk_count];

#define KS2_CLK1_6 sys_clk0_6_clk

-/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - TETRIS_PLL, - DDR3A_PLL, - DDR3B_PLL, -}; - #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} #define CORE_PLL_999 {CORE_PLL, 122, 15, 1} diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h index c145a1e..e3f005a 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2l.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h @@ -51,14 +51,6 @@ extern unsigned int external_clk[ext_clk_count];

#define KS2_CLK1_6 sys_clk0_6_clk

-/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - TETRIS_PLL, - DDR3_PLL, -}; - #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} #define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 2192c0d..dc3c56a 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -24,7 +24,8 @@ #include <asm/arch/clock-k2l.h> #endif

-#define MAIN_PLL CORE_PLL +#define CORE_PLL MAIN_PLL +#define DDR3_PLL DDR3A_PLL

#include <asm/types.h>

@@ -41,6 +42,16 @@ enum { SPD1500, };

+/* PLL identifiers */ +enum { + MAIN_PLL, + TETRIS_PLL, + PASS_PLL, + DDR3A_PLL, + DDR3B_PLL, + MAX_PLL_COUNT, +}; + enum clk_e { CLK_LIST(GENERATE_ENUM) }; diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h index 195c0d3..8c771dc 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h @@ -15,10 +15,6 @@ /* PA SS Registers */ #define KS2_PASS_BASE 0x02000000

-/* PLL control registers */ -#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) -#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) - /* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_MOD 0 #define KS2_LPSC_DUMMY1 1 diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 30022db..6d4015c 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -165,6 +165,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) #define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) #define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) +#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)

This is just a cosmetic change that makes the calling of pll init code looks much cleaner.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/clock.c | 12 ++++++--- arch/arm/mach-keystone/include/mach/clock.h | 3 ++- board/ti/ks2_evm/board_k2e.c | 33 +++++++++++++++-------- board/ti/ks2_evm/board_k2hk.c | 41 ++++++++++++++++++----------- board/ti/ks2_evm/board_k2l.c | 41 ++++++++++++++++++----------- 5 files changed, 84 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index f60a0b8..824a6ce 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -191,12 +191,16 @@ void init_pll(const struct pll_init_data *data) configure_secondary_pll(data); }

-void init_plls(int num_pll, struct pll_init_data *config) +void init_plls(void) { - int i; + struct pll_init_data *data; + int pll;

- for (i = 0; i < num_pll; i++) - init_pll(&config[i]); + for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) { + data = get_pll_init_data(pll); + if (data) + init_pll(data); + } }

static int get_max_speed(u32 val, u32 speed_supported) diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index dc3c56a..ea7d8bc 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -73,8 +73,9 @@ extern const struct keystone_pll_regs keystone_pll_regs[]; extern int dev_speeds[]; extern int arm_speeds[];

-void init_plls(int num_pll, struct pll_init_data *config); +void init_plls(void); void init_pll(const struct pll_init_data *data); +struct pll_init_data *get_pll_init_data(int pll); unsigned long clk_get_rate(unsigned int clk); unsigned long clk_round_rate(unsigned int clk, unsigned long hz); int clk_set_rate(unsigned int clk, unsigned long hz); diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 6d98b2a..82792ef 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -38,6 +38,26 @@ static struct pll_init_data core_pll_config[] = { static struct pll_init_data pa_pll_config = PASS_PLL_1000;

+struct pll_init_data *get_pll_init_data(int pll) +{ + int speed; + struct pll_init_data *data; + + switch (pll) { + case MAIN_PLL: + speed = get_max_dev_speed(); + data = &core_pll_config[speed]; + break; + case PASS_PLL: + data = &pa_pll_config; + break; + default: + data = NULL; + } + + return data; +} + #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET struct eth_priv_t eth_priv_cfg[] = { { @@ -107,24 +127,15 @@ int get_num_eth_ports(void) #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { - int speed; - - speed = get_max_dev_speed(); - init_pll(&core_pll_config[speed]); - - init_pll(&pa_pll_config); + init_plls();

return 0; } #endif

#ifdef CONFIG_SPL_BUILD -static struct pll_init_data spl_pll_config[] = { - CORE_PLL_800, -}; - void spl_init_keystone_plls(void) { - init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); + init_plls(); } #endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index ed181f4..cec6c02 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -46,6 +46,30 @@ static struct pll_init_data tetris_pll_config[] = { static struct pll_init_data pa_pll_config = PASS_PLL_983;

+struct pll_init_data *get_pll_init_data(int pll) +{ + int speed; + struct pll_init_data *data; + + switch (pll) { + case MAIN_PLL: + speed = get_max_dev_speed(); + data = &core_pll_config[speed]; + break; + case TETRIS_PLL: + speed = get_max_arm_speed(); + data = &tetris_pll_config[speed]; + break; + case PASS_PLL: + data = &pa_pll_config; + break; + default: + data = NULL; + } + + return data; +} + #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET struct eth_priv_t eth_priv_cfg[] = { { @@ -87,28 +111,15 @@ int get_num_eth_ports(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - int speed; - - speed = get_max_dev_speed(); - init_pll(&core_pll_config[speed]); - - init_pll(&pa_pll_config); - - speed = get_max_arm_speed(); - init_pll(&tetris_pll_config[speed]); + init_plls();

return 0; } #endif

#ifdef CONFIG_SPL_BUILD -static struct pll_init_data spl_pll_config[] = { - CORE_PLL_799, - TETRIS_PLL_500, -}; - void spl_init_keystone_plls(void) { - init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); + init_plls(); } #endif diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 729a193..1b4d086 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -42,6 +42,30 @@ static struct pll_init_data tetris_pll_config[] = { static struct pll_init_data pa_pll_config = PASS_PLL_983;

+struct pll_init_data *get_pll_init_data(int pll) +{ + int speed; + struct pll_init_data *data; + + switch (pll) { + case MAIN_PLL: + speed = get_max_dev_speed(); + data = &core_pll_config[speed]; + break; + case TETRIS_PLL: + speed = get_max_arm_speed(); + data = &tetris_pll_config[speed]; + break; + case PASS_PLL: + data = &pa_pll_config; + break; + default: + data = NULL; + } + + return data; +} + #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET struct eth_priv_t eth_priv_cfg[] = { { @@ -83,28 +107,15 @@ int get_num_eth_ports(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - int speed; - - speed = get_max_dev_speed(); - init_pll(&core_pll_config[speed]); - - init_pll(&pa_pll_config); - - speed = get_max_arm_speed(); - init_pll(&tetris_pll_config[speed]); + init_plls();

return 0; } #endif

#ifdef CONFIG_SPL_BUILD -static struct pll_init_data spl_pll_config[] = { - CORE_PLL_799, - TETRIS_PLL_491, -}; - void spl_init_keystone_plls(void) { - init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); + init_plls(); } #endif