[U-Boot] [PATCH v2 0/3] Add Beelink GS1 Board
This serie introduce the Beelink GS1 board with a patch for the reset on Allwinner H6.
Thanks to Jagan Teki most of the Beelink GS1 device-tree is taken from the Orange Pi boards.
Changes with v1: - Add bus-width for mmc2 node - Add sha1 in the sync dts commit
Clément Péron (3): arm: dts: h6: sync with dts with Linux sunxi arm: dts: h6: Add Beelink GS1 initial support arm: sunxi: h6: fix reset using r_wdog
arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 184 ++++++++++++++++++ arch/arm/dts/sun50i-h6-orangepi.dtsi | 2 - arch/arm/dts/sun50i-h6-pine-h64.dts | 4 - arch/arm/dts/sun50i-h6.dtsi | 16 +- .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 1 + arch/arm/mach-sunxi/board.c | 9 +- configs/beelink_gs1_defconfig | 15 ++ 8 files changed, 218 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig
There are some differences between U-Boot and Linux device tree files.
Sync only the minor changes.
6ba2e45d57af - arm64: dts: allwinner: h6: move MMC pinctrl to dtsi <Clément Péron> 54eac67bbe3a - arm64: dts: allwinner: Fix pinctrl node names <Maxime Ripard> 31af04cd60d3 - arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string <Rob Herring>
Signed-off-by: Clément Péron peron.clem@gmail.com --- arch/arm/dts/sun50i-h6-orangepi.dtsi | 2 -- arch/arm/dts/sun50i-h6-pine-h64.dts | 4 ---- arch/arm/dts/sun50i-h6.dtsi | 16 ++++++++++------ 3 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi index 0612c19cd9..3748dcaa70 100644 --- a/arch/arm/dts/sun50i-h6-orangepi.dtsi +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi @@ -24,8 +24,6 @@ };
&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; bus-width = <4>; diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts index ceffc40810..a26314c084 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts @@ -42,16 +42,12 @@ };
&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; status = "okay"; };
&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_cldo1>; vqmmc-supply = <®_bldo2>; non-removable; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index cfa5fffcf6..5f01314703 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -19,28 +19,28 @@ #size-cells = <0>;
cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0>; enable-method = "psci"; };
cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; };
cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; };
cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; enable-method = "psci"; @@ -143,7 +143,7 @@ bias-pull-up; };
- uart0_ph_pins: uart0-ph { + uart0_ph_pins: uart0-ph-pins { pins = "PH0", "PH1"; function = "uart0"; }; @@ -158,6 +158,8 @@ resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -186,6 +188,8 @@ resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -266,7 +270,7 @@ interrupt-controller; #interrupt-cells = <3>;
- r_i2c_pins: r-i2c { + r_i2c_pins: r-i2c-pins { pins = "PL0", "PL1"; function = "s_i2c"; };
Beelink GS1 is an Allwinner H6 based TV box, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 2GB LPDDR3 RAM - 16GB eMMC - AXP805 PMIC - 1Gbps GMAC via RTL8211E - USB 2.0 and 3.0 Host - HDMI port - S/PDIF port - 5V/2A DC power supply - Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS)
Signed-off-by: Clément Péron peron.clem@gmail.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 184 +++++++++++++++++++++++++ configs/beelink_gs1_defconfig | 15 ++ 3 files changed, 200 insertions(+) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 86a01c2c70..61e7156284 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -467,6 +467,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \ + sun50i-h6-beelink-gs1.dtb \ sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtb diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts new file mode 100644 index 0000000000..54b0882bed --- /dev/null +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2019 Clément Péron peron.clem@gmail.com + */ + +/dts-v1/; + +#include "sun50i-h6.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Beelink GS1"; + compatible = "azw,beelink-gs1", "allwinner,sun50i-h6"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "beelink:white:power"; + gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + default-state = "on"; + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC jack */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&mmc0 { + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; + non-removable; + cap-mmc-hw-reset; + bus-width = <8>; + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + regulator-enable-ramp-delay = <100000>; + }; + + reg_aldo3: aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc25-dram"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig new file mode 100644 index 0000000000..ef4dd29549 --- /dev/null +++ b/configs/beelink_gs1_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_PSCI_RESET is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" +CONFIG_LED=y +CONFIG_LED_GPIO=y
On Fri, Apr 12, 2019 at 7:45 PM Clément Péron peron.clem@gmail.com wrote:
Beelink GS1 is an Allwinner H6 based TV box, which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 2GB LPDDR3 RAM
- 16GB eMMC
- AXP805 PMIC
- 1Gbps GMAC via RTL8211E
- USB 2.0 and 3.0 Host
- HDMI port
- S/PDIF port
- 5V/2A DC power supply
- Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS)
Please dts sync commit details here.
Signed-off-by: Clément Péron peron.clem@gmail.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 184 +++++++++++++++++++++++++
Seems like this has part of required nodes, sync the complete dts.
configs/beelink_gs1_defconfig | 15 ++
Add entry on board/sunxi/MAINTAINERS
3 files changed, 200 insertions(+) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 86a01c2c70..61e7156284 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -467,6 +467,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \ sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtbdiff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts new file mode 100644 index 0000000000..54b0882bed --- /dev/null +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/*
- Copyright (C) 2019 Clément Péron peron.clem@gmail.com
- */
+/dts-v1/;
+#include "sun50i-h6.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
model = "Beelink GS1";compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";aliases {serial0 = &uart0;};chosen {stdout-path = "serial0:115200n8";};leds {compatible = "gpio-leds";power {label = "beelink:white:power";gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */default-state = "on";};};reg_vcc5v: vcc5v {/* board wide 5V supply directly from the DC jack */compatible = "regulator-fixed";regulator-name = "vcc-5v";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;};+};
+&mmc0 {
vmmc-supply = <®_cldo1>;cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;bus-width = <4>;status = "okay";+};
+&mmc2 {
vmmc-supply = <®_cldo1>;vqmmc-supply = <®_bldo2>;non-removable;cap-mmc-hw-reset;bus-width = <8>;status = "okay";+};
+&r_i2c {
status = "okay";axp805: pmic@36 {compatible = "x-powers,axp805", "x-powers,axp806";reg = <0x36>;interrupt-parent = <&r_intc>;interrupts = <0 IRQ_TYPE_LEVEL_LOW>;interrupt-controller;#interrupt-cells = <1>;x-powers,self-working-mode;vina-supply = <®_vcc5v>;vinb-supply = <®_vcc5v>;vinc-supply = <®_vcc5v>;vind-supply = <®_vcc5v>;vine-supply = <®_vcc5v>;aldoin-supply = <®_vcc5v>;bldoin-supply = <®_vcc5v>;cldoin-supply = <®_vcc5v>;regulators {reg_aldo1: aldo1 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-pl";};reg_aldo2: aldo2 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-ac200";regulator-enable-ramp-delay = <100000>;};reg_aldo3: aldo3 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc25-dram";};reg_bldo1: bldo1 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-bias-pll";};reg_bldo2: bldo2 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-efuse-pcie-hdmi-io";};reg_bldo3: bldo3 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-dcxoio";};bldo4 {/* unused */};reg_cldo1: cldo1 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-3v3";};reg_cldo2: cldo2 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-wifi-1";};reg_cldo3: cldo3 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-wifi-2";};reg_dcdca: dcdca {regulator-always-on;regulator-min-microvolt = <810000>;regulator-max-microvolt = <1080000>;regulator-name = "vdd-cpu";};reg_dcdcc: dcdcc {regulator-min-microvolt = <810000>;regulator-max-microvolt = <1080000>;regulator-name = "vdd-gpu";};reg_dcdcd: dcdcd {regulator-always-on;regulator-min-microvolt = <960000>;regulator-max-microvolt = <960000>;regulator-name = "vdd-sys";};reg_dcdce: dcdce {regulator-always-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-name = "vcc-dram";};sw {/* unused */};};};+};
+&uart0 {
pinctrl-names = "default";pinctrl-0 = <&uart0_ph_pins>;status = "okay";+}; diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig new file mode 100644 index 0000000000..ef4dd29549 --- /dev/null +++ b/configs/beelink_gs1_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_PSCI_RESET is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" +CONFIG_LED=y +CONFIG_LED_GPIO=y
Seems like most of Allwinner gpio's are gpio-leds. so select LED (since it's dm led core) in arch/arm/Kconfig if LED_GPIO. I'm thinking this could be proper assignment.
Hi,
On Sun, 14 Apr 2019 at 19:29, Jagan Teki jagan@amarulasolutions.com wrote:
On Fri, Apr 12, 2019 at 7:45 PM Clément Péron peron.clem@gmail.com wrote:
Beelink GS1 is an Allwinner H6 based TV box, which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 2GB LPDDR3 RAM
- 16GB eMMC
- AXP805 PMIC
- 1Gbps GMAC via RTL8211E
- USB 2.0 and 3.0 Host
- HDMI port
- S/PDIF port
- 5V/2A DC power supply
- Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS)
Please dts sync commit details here.
Signed-off-by: Clément Péron peron.clem@gmail.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 184 +++++++++++++++++++++++++
Seems like this has part of required nodes, sync the complete dts.
Ok so you want to add the complete dts from linux.
I think only IP used in U-boot are needed.
I will do that in v3
configs/beelink_gs1_defconfig | 15 ++
Add entry on board/sunxi/MAINTAINERS
Ok
3 files changed, 200 insertions(+) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 86a01c2c70..61e7156284 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -467,6 +467,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \ sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtbdiff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts new file mode 100644 index 0000000000..54b0882bed --- /dev/null +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/*
- Copyright (C) 2019 Clément Péron peron.clem@gmail.com
- */
+/dts-v1/;
+#include "sun50i-h6.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
model = "Beelink GS1";compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";aliases {serial0 = &uart0;};chosen {stdout-path = "serial0:115200n8";};leds {compatible = "gpio-leds";power {label = "beelink:white:power";gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */default-state = "on";};};reg_vcc5v: vcc5v {/* board wide 5V supply directly from the DC jack */compatible = "regulator-fixed";regulator-name = "vcc-5v";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;};+};
+&mmc0 {
vmmc-supply = <®_cldo1>;cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;bus-width = <4>;status = "okay";+};
+&mmc2 {
vmmc-supply = <®_cldo1>;vqmmc-supply = <®_bldo2>;non-removable;cap-mmc-hw-reset;bus-width = <8>;status = "okay";+};
+&r_i2c {
status = "okay";axp805: pmic@36 {compatible = "x-powers,axp805", "x-powers,axp806";reg = <0x36>;interrupt-parent = <&r_intc>;interrupts = <0 IRQ_TYPE_LEVEL_LOW>;interrupt-controller;#interrupt-cells = <1>;x-powers,self-working-mode;vina-supply = <®_vcc5v>;vinb-supply = <®_vcc5v>;vinc-supply = <®_vcc5v>;vind-supply = <®_vcc5v>;vine-supply = <®_vcc5v>;aldoin-supply = <®_vcc5v>;bldoin-supply = <®_vcc5v>;cldoin-supply = <®_vcc5v>;regulators {reg_aldo1: aldo1 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-pl";};reg_aldo2: aldo2 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-ac200";regulator-enable-ramp-delay = <100000>;};reg_aldo3: aldo3 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc25-dram";};reg_bldo1: bldo1 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-bias-pll";};reg_bldo2: bldo2 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-efuse-pcie-hdmi-io";};reg_bldo3: bldo3 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-dcxoio";};bldo4 {/* unused */};reg_cldo1: cldo1 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-3v3";};reg_cldo2: cldo2 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-wifi-1";};reg_cldo3: cldo3 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-wifi-2";};reg_dcdca: dcdca {regulator-always-on;regulator-min-microvolt = <810000>;regulator-max-microvolt = <1080000>;regulator-name = "vdd-cpu";};reg_dcdcc: dcdcc {regulator-min-microvolt = <810000>;regulator-max-microvolt = <1080000>;regulator-name = "vdd-gpu";};reg_dcdcd: dcdcd {regulator-always-on;regulator-min-microvolt = <960000>;regulator-max-microvolt = <960000>;regulator-name = "vdd-sys";};reg_dcdce: dcdce {regulator-always-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-name = "vcc-dram";};sw {/* unused */};};};+};
+&uart0 {
pinctrl-names = "default";pinctrl-0 = <&uart0_ph_pins>;status = "okay";+}; diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig new file mode 100644 index 0000000000..ef4dd29549 --- /dev/null +++ b/configs/beelink_gs1_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_PSCI_RESET is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" +CONFIG_LED=y +CONFIG_LED_GPIO=y
Seems like most of Allwinner gpio's are gpio-leds. so select LED (since it's dm led core) in arch/arm/Kconfig if LED_GPIO. I'm thinking this could be proper assignment.
We can't do that as LED_GPIO depends on LED.
On Mon, Apr 15, 2019 at 2:58 AM Clément Péron peron.clem@gmail.com wrote:
Hi,
On Sun, 14 Apr 2019 at 19:29, Jagan Teki jagan@amarulasolutions.com wrote:
On Fri, Apr 12, 2019 at 7:45 PM Clément Péron peron.clem@gmail.com wrote:
Beelink GS1 is an Allwinner H6 based TV box, which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 2GB LPDDR3 RAM
- 16GB eMMC
- AXP805 PMIC
- 1Gbps GMAC via RTL8211E
- USB 2.0 and 3.0 Host
- HDMI port
- S/PDIF port
- 5V/2A DC power supply
- Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS)
Please dts sync commit details here.
Signed-off-by: Clément Péron peron.clem@gmail.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 184 +++++++++++++++++++++++++
Seems like this has part of required nodes, sync the complete dts.
Ok so you want to add the complete dts from linux.
I think only IP used in U-boot are needed.
I will do that in v3
configs/beelink_gs1_defconfig | 15 ++
Add entry on board/sunxi/MAINTAINERS
Ok
3 files changed, 200 insertions(+) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 86a01c2c70..61e7156284 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -467,6 +467,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \ sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtbdiff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts new file mode 100644 index 0000000000..54b0882bed --- /dev/null +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/*
- Copyright (C) 2019 Clément Péron peron.clem@gmail.com
- */
+/dts-v1/;
+#include "sun50i-h6.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
model = "Beelink GS1";compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";aliases {serial0 = &uart0;};chosen {stdout-path = "serial0:115200n8";};leds {compatible = "gpio-leds";power {label = "beelink:white:power";gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */default-state = "on";};};reg_vcc5v: vcc5v {/* board wide 5V supply directly from the DC jack */compatible = "regulator-fixed";regulator-name = "vcc-5v";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;};+};
+&mmc0 {
vmmc-supply = <®_cldo1>;cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;bus-width = <4>;status = "okay";+};
+&mmc2 {
vmmc-supply = <®_cldo1>;vqmmc-supply = <®_bldo2>;non-removable;cap-mmc-hw-reset;bus-width = <8>;status = "okay";+};
+&r_i2c {
status = "okay";axp805: pmic@36 {compatible = "x-powers,axp805", "x-powers,axp806";reg = <0x36>;interrupt-parent = <&r_intc>;interrupts = <0 IRQ_TYPE_LEVEL_LOW>;interrupt-controller;#interrupt-cells = <1>;x-powers,self-working-mode;vina-supply = <®_vcc5v>;vinb-supply = <®_vcc5v>;vinc-supply = <®_vcc5v>;vind-supply = <®_vcc5v>;vine-supply = <®_vcc5v>;aldoin-supply = <®_vcc5v>;bldoin-supply = <®_vcc5v>;cldoin-supply = <®_vcc5v>;regulators {reg_aldo1: aldo1 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-pl";};reg_aldo2: aldo2 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-ac200";regulator-enable-ramp-delay = <100000>;};reg_aldo3: aldo3 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc25-dram";};reg_bldo1: bldo1 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-bias-pll";};reg_bldo2: bldo2 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-efuse-pcie-hdmi-io";};reg_bldo3: bldo3 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-dcxoio";};bldo4 {/* unused */};reg_cldo1: cldo1 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-3v3";};reg_cldo2: cldo2 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-wifi-1";};reg_cldo3: cldo3 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-wifi-2";};reg_dcdca: dcdca {regulator-always-on;regulator-min-microvolt = <810000>;regulator-max-microvolt = <1080000>;regulator-name = "vdd-cpu";};reg_dcdcc: dcdcc {regulator-min-microvolt = <810000>;regulator-max-microvolt = <1080000>;regulator-name = "vdd-gpu";};reg_dcdcd: dcdcd {regulator-always-on;regulator-min-microvolt = <960000>;regulator-max-microvolt = <960000>;regulator-name = "vdd-sys";};reg_dcdce: dcdce {regulator-always-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-name = "vcc-dram";};sw {/* unused */};};};+};
+&uart0 {
pinctrl-names = "default";pinctrl-0 = <&uart0_ph_pins>;status = "okay";+}; diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig new file mode 100644 index 0000000000..ef4dd29549 --- /dev/null +++ b/configs/beelink_gs1_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_PSCI_RESET is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" +CONFIG_LED=y +CONFIG_LED_GPIO=y
Seems like most of Allwinner gpio's are gpio-leds. so select LED (since it's dm led core) in arch/arm/Kconfig if LED_GPIO. I'm thinking this could be proper assignment.
We can't do that as LED_GPIO depends on LED.
True.
WDOG is broken for some H6 rev. The board is not reseted correctly.
Use the R_WDOG instead.
Signed-off-by: Clément Péron peron.clem@gmail.com --- arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 1 + arch/arm/mach-sunxi/board.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 41a9b0fc47..6392cb07b4 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -60,6 +60,7 @@ #define SUNXI_RTC_BASE 0x07000000 #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 +#define SUNXI_R_WDOG_BASE 0x07020400 #define SUNXI_R_PIO_BASE 0x07022000 #define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index b74eaf2a0e..1075b5ca54 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -287,9 +287,14 @@ void reset_cpu(ulong addr) writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) +#if defined(CONFIG_MACH_SUN50I_H6) + /* WDOG is broken for some H6 rev. use the R_WDOG instead */ static const struct sunxi_wdog *wdog = - ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; - + (struct sunxi_wdog *)SUNXI_R_WDOG_BASE; +#else + static const struct sunxi_wdog *wdog = + ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; +#endif /* Set the watchdog for its shortest interval (.5s) and wait */ writel(WDT_CFG_RESET, &wdog->cfg); writel(WDT_MODE_EN, &wdog->mode);
participants (2)
-
Clément Péron -
Jagan Teki