[U-Boot] [PATCH v4 0/5] Get socfpga gen5 SPL working again.
Socfpga gen5 SPL has been broken since moving to DM serial with v2018.07. Also, U-Boot console output has been broken since then. This series fixes this and makes some related small improvements.
Changes in v4: - dropped already merged patches 1, 3 and 4 - enable the env relocatation for all socfpga, not for gen5 only - rename socfpga_init_bus_mapping() to socfpga_sdram_remap_zero() and move socfpga_bridges_reset(1) out of that function
Changes in v3: - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board specific dts files since this can change per board - added patches 5-7 to boot SPL and U-Boot from fpga OnChip RAM - dropped Patch 5/6 "serial: ns16550: fix debug uart putc called before init" (this needs a more generic fix)
Changes in v2: - Improved comment on patch 1 - Removing gd->malloc_base assignment at the end of board_init_f() moved to an extra patch - don't change printf() to debug() in reset_manager_gen5.c socfpga_bridges_reset() (instead make debug uart handle this) - make ns16550 debug uart handle putc being called before init - removed the assignment of gd->malloc_limit from board_init()
Simon Goldschmidt (5): arm: socfpga: fix device trees to work with DM serial arm: socfpga: fix U-Boot running from fpga OnChip RAM arm: socfpga: gen5: combine some init code for SPL and U-Boot arm: socfpga: fix SPL booting from fpga OnChip RAM malloc_simple: calloc: don't call memset if malloc failed
arch/arm/dts/socfpga_arria5_socdk.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 +++ .../arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_is1.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_sockit.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_socrates.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 2 + arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 5 +++ arch/arm/mach-socfpga/Kconfig | 12 ++++++ arch/arm/mach-socfpga/include/mach/misc.h | 4 ++ arch/arm/mach-socfpga/misc_gen5.c | 38 ++++++++++++------- arch/arm/mach-socfpga/spl_gen5.c | 34 +++-------------- common/malloc_simple.c | 3 +- include/configs/socfpga_common.h | 11 ++++++ 17 files changed, 111 insertions(+), 43 deletions(-)
Device trees need to have the serial console device available before relocation and require a stdout-path in chosen at least for SPL to have a console.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board specific dts files since this can change per board Changes in v2: None
arch/arm/dts/socfpga_arria5_socdk.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_is1.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_sockit.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_socrates.dts | 5 +++++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 2 ++ arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 5 +++++ 11 files changed, 52 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 449ba9cbb9..6f4de2f563 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
memory { @@ -99,3 +100,7 @@ cdns,tslch-ns = <4>; }; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index aeb327dd5b..139a70f265 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
aliases { @@ -56,3 +57,7 @@ disable-over-current; status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index f4a98e4bb0..d504150edd 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
aliases { @@ -75,3 +76,7 @@ &usb1 { status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index 7da2d8b043..d4dd9e9bca 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -13,6 +13,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
aliases { @@ -65,3 +66,7 @@ &usb1 { status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index e6fadb4fc9..f62292284d 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
aliases { @@ -63,3 +64,7 @@ &usb1 { status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index aa1ce2c3e2..4e94d86114 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
memory { @@ -102,3 +103,7 @@ &usb1 { status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 55c70abb02..c28be67bb9 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
memory { @@ -113,3 +114,7 @@ &usb1 { status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts index 08d8356d80..c7a6cf2db8 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
aliases { @@ -93,3 +94,7 @@ &usb1 { status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 0d452ae300..8cde9906a0 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
aliases { @@ -84,3 +85,7 @@ disable-over-current; status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 341df7a3e7..86c61fe081 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
aliases { @@ -67,6 +68,7 @@
&uart0 { status = "okay"; + u-boot,dm-pre-reloc; };
&usb1 { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index 7a032af3a4..85ab56379f 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -11,6 +11,7 @@
chosen { bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; };
aliases { @@ -108,3 +109,7 @@ &usb1 { status = "okay"; }; + +&uart0 { + u-boot,dm-pre-reloc; +};
gd->env_addr points to pre-relocation address even after relocation. This leads to an abort in env_callback_init when loading the environment.
Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: enable this fix for all socfpga, not for gen5 only Changes in v3: this patch is new in v3 Changes in v2: None
include/configs/socfpga_common.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8ebf6b85fe..d1148b838b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START #endif
+/* When U-Boot is started from FPGA, prevent gd->env_addr to point into + * FPGA OnChip RAM after relocation + */ +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + /* Extra Environment */ #ifndef CONFIG_SPL_BUILD
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
gd->env_addr points to pre-relocation address even after relocation. This leads to an abort in env_callback_init when loading the environment.
Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Changes in v4: enable this fix for all socfpga, not for gen5 only Changes in v3: this patch is new in v3 Changes in v2: None
include/configs/socfpga_common.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8ebf6b85fe..d1148b838b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START #endif
+/* When U-Boot is started from FPGA, prevent gd->env_addr to point into
Multi-line comment should have this format /* * foo * bar */
- FPGA OnChip RAM after relocation
- */
+#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
What you don't explain in the commit message is this last line. Why is this needed ?
/* Extra Environment */ #ifndef CONFIG_SPL_BUILD
Marek Vasut marex@denx.de schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
gd->env_addr points to pre-relocation address even after relocation. This leads to an abort in env_callback_init when loading the environment.
Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Changes in v4: enable this fix for all socfpga, not for gen5 only Changes in v3: this patch is new in v3 Changes in v2: None
include/configs/socfpga_common.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/include/configs/socfpga_common.h
b/include/configs/socfpga_common.h
index 8ebf6b85fe..d1148b838b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START #endif
+/* When U-Boot is started from FPGA, prevent gd->env_addr to point into
Multi-line comment should have this format /*
- foo
- bar
*/
Right, of course. I wonder why patman didn't warm me about that...
- FPGA OnChip RAM after relocation
- */
+#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start
of monitor */
What you don't explain in the commit message is this last line. Why is this needed ?
The code enabled by CONFIG_SYS_EXTRA_ENV_RELOC used this to calculate the relocation offset. I do think that's a bit strange, but I wouldn't change it with this patchset, or should I?
Simon
/* Extra Environment */ #ifndef CONFIG_SPL_BUILD
-- Best regards, Marek Vasut
On 08/14/2018 08:09 AM, Simon Goldschmidt wrote:
Marek Vasut <marex@denx.de mailto:marex@denx.de> schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote: > gd->env_addr points to pre-relocation address even after > relocation. This leads to an abort in env_callback_init > when loading the environment. > > Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC. > > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com <mailto:simon.k.r.goldschmidt@gmail.com>> > --- > > Changes in v4: enable this fix for all socfpga, not for gen5 only > Changes in v3: this patch is new in v3 > Changes in v2: None > > include/configs/socfpga_common.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h > index 8ebf6b85fe..d1148b838b 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START > #endif > > +/* When U-Boot is started from FPGA, prevent gd->env_addr to point into Multi-line comment should have this format /* * foo * bar */Right, of course. I wonder why patman didn't warm me about that...
> + * FPGA OnChip RAM after relocation > + */ > +#define CONFIG_SYS_EXTRA_ENV_RELOC > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ What you don't explain in the commit message is this last line. Why is this needed ?The code enabled by CONFIG_SYS_EXTRA_ENV_RELOC used this to calculate the relocation offset. I do think that's a bit strange, but I wouldn't change it with this patchset, or should I?
You should document _why_ this is needed. Not "because the code enabled by foo needed this", but why that code enabled this and why setting it to SYS_TEXT_BASE is correct.
On Tue, Aug 14, 2018 at 10:37 AM Marek Vasut marex@denx.de wrote:
On 08/14/2018 08:09 AM, Simon Goldschmidt wrote:
Marek Vasut <marex@denx.de mailto:marex@denx.de> schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote: > gd->env_addr points to pre-relocation address even after > relocation. This leads to an abort in env_callback_init > when loading the environment. > > Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC. > > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com <mailto:simon.k.r.goldschmidt@gmail.com>> > --- > > Changes in v4: enable this fix for all socfpga, not for gen5 only > Changes in v3: this patch is new in v3 > Changes in v2: None > > include/configs/socfpga_common.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h > index 8ebf6b85fe..d1148b838b 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START > #endif > > +/* When U-Boot is started from FPGA, prevent gd->env_addr to point into Multi-line comment should have this format /* * foo * bar */Right, of course. I wonder why patman didn't warm me about that...
> + * FPGA OnChip RAM after relocation > + */ > +#define CONFIG_SYS_EXTRA_ENV_RELOC > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ What you don't explain in the commit message is this last line. Why is this needed ?The code enabled by CONFIG_SYS_EXTRA_ENV_RELOC used this to calculate the relocation offset. I do think that's a bit strange, but I wouldn't change it with this patchset, or should I?
You should document _why_ this is needed. Not "because the code enabled by foo needed this", but why that code enabled this and why setting it to SYS_TEXT_BASE is correct.
Yes, I wouldn't have sent a patch like that. I rather wanted to phrase that I don't know why this is needed for env relocation, as fdt relocation just uses gd->reloc_off. That might work for env relocation, too, but changing that seems out of scope for this patchset.
Simon
On 08/14/2018 10:19 PM, Simon Goldschmidt wrote:
On Tue, Aug 14, 2018 at 10:37 AM Marek Vasut marex@denx.de wrote:
On 08/14/2018 08:09 AM, Simon Goldschmidt wrote:
Marek Vasut <marex@denx.de mailto:marex@denx.de> schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote: > gd->env_addr points to pre-relocation address even after > relocation. This leads to an abort in env_callback_init > when loading the environment. > > Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC. > > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com <mailto:simon.k.r.goldschmidt@gmail.com>> > --- > > Changes in v4: enable this fix for all socfpga, not for gen5 only > Changes in v3: this patch is new in v3 > Changes in v2: None > > include/configs/socfpga_common.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h > index 8ebf6b85fe..d1148b838b 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START > #endif > > +/* When U-Boot is started from FPGA, prevent gd->env_addr to point into Multi-line comment should have this format /* * foo * bar */Right, of course. I wonder why patman didn't warm me about that...
> + * FPGA OnChip RAM after relocation > + */ > +#define CONFIG_SYS_EXTRA_ENV_RELOC > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ What you don't explain in the commit message is this last line. Why is this needed ?The code enabled by CONFIG_SYS_EXTRA_ENV_RELOC used this to calculate the relocation offset. I do think that's a bit strange, but I wouldn't change it with this patchset, or should I?
You should document _why_ this is needed. Not "because the code enabled by foo needed this", but why that code enabled this and why setting it to SYS_TEXT_BASE is correct.
Yes, I wouldn't have sent a patch like that. I rather wanted to phrase that I don't know why this is needed for env relocation, as fdt relocation just uses gd->reloc_off. That might work for env relocation, too, but changing that seems out of scope for this patchset.
Maybe the comment in board_r.c explains why?
143 #ifdef CONFIG_SYS_EXTRA_ENV_RELOC 144 /* 145 * Some systems need to relocate the env_addr pointer early because the 146 * location it points to will get invalidated before env_relocate is 147 * called. One example is on systems that might use a L2 or L3 cache 148 * in SRAM mode and initialize that cache from SRAM mode back to being 149 * a cache in cpu_init_r. 150 */ 151 gd->env_addr += gd->relocaddr - CONFIG_SYS_MONITOR_BASE; 152 #endif
But then the env shouldn't point to pre-reloc address after relocation according to the comment ?
Some of the code for low level system initialization in SPL's board_init_f() and U-Boot's arch_early_init_r() is the same, so let's combine it into a single function called from both.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: - rename socfpga_init_bus_mapping() to socfpga_sdram_remap_zero() and move socfpga_bridges_reset(1) out of that function Changes in v3: this patch is new in v3 Changes in v2: None
arch/arm/mach-socfpga/include/mach/misc.h | 4 ++++ arch/arm/mach-socfpga/misc_gen5.c | 29 +++++++++++++---------- arch/arm/mach-socfpga/spl_gen5.c | 28 +--------------------- 3 files changed, 22 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 7fe77ac8d8..218dd6b6e7 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -27,6 +27,10 @@ unsigned int shared_uart_com_port(const void *blob); unsigned int uart_com_port(const void *blob); #endif
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5 +void socfpga_sdram_remap_zero(void); +#endif + void do_bridge_reset(int enable);
#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 848551c73f..429c3d6cd5 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -175,6 +175,22 @@ static void socfpga_nic301_slave_ns(void) writel(0x1, &nic301_regs->sdrdata); }
+void socfpga_sdram_remap_zero(void) +{ + socfpga_nic301_slave_ns(); + + /* + * Private components security: + * U-Boot : configure private timer, global timer and cpu component + * access as non secure for kernel stage (as required by Linux) + */ + setbits_le32(&scu_regs->sacr, 0xfff); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + writel(0x1, &pl310->pl310_addr_filter_start); +} + static u32 iswgrp_handoff[8];
int arch_early_init_r(void) @@ -195,18 +211,7 @@ int arch_early_init_r(void)
socfpga_bridges_reset(1);
- socfpga_nic301_slave_ns(); - - /* - * Private components security: - * U-Boot : configure private timer, global timer and cpu component - * access as non secure for kernel stage (as required by Linux) - */ - setbits_le32(&scu_regs->sacr, 0xfff); - - /* Configure the L2 controller to make SDRAM start at 0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ - writel(0x1, &pl310->pl310_addr_filter_start); + socfpga_sdram_remap_zero();
/* Add device descriptor to FPGA device table */ socfpga_fpga_add(); diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 0e685f6ee5..be318cc0d9 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -5,7 +5,6 @@
#include <common.h> #include <asm/io.h> -#include <asm/pl310.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <image.h> @@ -17,8 +16,6 @@ #include <asm/arch/misc.h> #include <asm/arch/scan_manager.h> #include <asm/arch/sdram.h> -#include <asm/arch/scu.h> -#include <asm/arch/nic301.h> #include <asm/sections.h> #include <debug_uart.h> #include <fdtdec.h> @@ -26,12 +23,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; -static struct scu_registers *scu_regs = - (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; -static struct nic301_registers *nic301_regs = - (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
@@ -72,16 +63,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif
-static void socfpga_nic301_slave_ns(void) -{ - writel(0x1, &nic301_regs->lwhps2fpgaregs); - writel(0x1, &nic301_regs->hps2fpgaregs); - writel(0x1, &nic301_regs->acp); - writel(0x1, &nic301_regs->rom); - writel(0x1, &nic301_regs->ocram); - writel(0x1, &nic301_regs->sdrdata); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -103,14 +84,7 @@ void board_init_f(ulong dummy)
memset(__bss_start, 0, __bss_end - __bss_start);
- socfpga_nic301_slave_ns(); - - /* Configure ARM MPU SNSAC register. */ - setbits_le32(&scu_regs->sacr, 0xfff); - - /* Remap SDRAM to 0x0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ - writel(0x1, &pl310->pl310_addr_filter_start); + socfpga_sdram_remap_zero();
debug("Freezing all I/O banks\n"); /* freeze all IO banks */
To boot from fpga OnChip RAM, some changes are required in SPL to ensure the code is linked to the correct address (in contrast to QSPI and MMC boot, FPGA boot executes SPL in place instead of copying it to SRAM) and that fpga OnChip RAM stays accessible while SPL runs (don't disable fpga bridges).
This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) for socfpga gen5 boards.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: Adapted to changed previous patch Changes in v3: this patch is new in v3 Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- include/configs/socfpga_common.h | 5 +++++ 4 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..a909395aac 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif + +if TARGET_SOCFPGA_GEN5 + +config SPL_SOCFPGA_BOOT_FROM_FPGA + bool "Allow booting SPL from FPGA OnChip RAM" + default n + help + Boot from FPGA: this changes the linker address for SPL code to run + from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAM + stays accessible while SPL runs. + +endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..c82c3584dc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) { + /* remap.mpuzero, keep fpga bridge enabled */ + writel(0x9, &nic301_regs->remap); + } else { + /* remap.mpuzero */ + writel(0x1, &nic301_regs->remap); + } writel(0x1, &pl310->pl310_addr_filter_start); }
@@ -209,7 +215,8 @@ int arch_early_init_r(void) for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
- socfpga_bridges_reset(1); + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) + socfpga_bridges_reset(1);
socfpga_sdram_remap_zero();
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..0c7f6a8c84 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); /* Put FPGA bridges into reset too. */ - socfpga_bridges_reset(1); + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) + socfpga_bridges_reset(1);
socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); @@ -163,5 +164,6 @@ void board_init_f(ulong dummy) hang(); }
- socfpga_bridges_reset(1); + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) + socfpga_bridges_reset(1); } diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d1148b838b..99c5e39086 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * 0xFFEz_zzzz ...... Malloc area (grows up to top) * 0xFFE3_FFFF ...... End of SRAM (top) */ +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA +/* SPL executed from FPGA */ +#define CONFIG_SPL_TEXT_BASE 0xC0000000 +#else #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
To boot from fpga OnChip RAM, some changes are required in SPL to ensure the code is linked to the correct address (in contrast to QSPI and MMC boot, FPGA boot executes SPL in place instead of copying it to SRAM) and that fpga OnChip RAM stays accessible while SPL runs (don't disable fpga bridges).
This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) for socfpga gen5 boards.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Changes in v4: Adapted to changed previous patch Changes in v3: this patch is new in v3 Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- include/configs/socfpga_common.h | 5 +++++ 4 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..a909395aac 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
+if TARGET_SOCFPGA_GEN5
+config SPL_SOCFPGA_BOOT_FROM_FPGA
- bool "Allow booting SPL from FPGA OnChip RAM"
- default n
- help
Boot from FPGA: this changes the linker address for SPL code to runfrom FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAMstays accessible while SPL runs.+endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..c82c3584dc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
- writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
- if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
/* remap.mpuzero, keep fpga bridge enabled */writel(0x9, &nic301_regs->remap);- } else {
/* remap.mpuzero */writel(0x1, &nic301_regs->remap);- } writel(0x1, &pl310->pl310_addr_filter_start);
}
@@ -209,7 +215,8 @@ int arch_early_init_r(void) for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
- socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
socfpga_bridges_reset(1);socfpga_sdram_remap_zero();
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..0c7f6a8c84 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); /* Put FPGA bridges into reset too. */
- socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
socfpga_bridges_reset(1);socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
@@ -163,5 +164,6 @@ void board_init_f(ulong dummy) hang(); }
- socfpga_bridges_reset(1);
- if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
socfpga_bridges_reset(1);} diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d1148b838b..99c5e39086 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
- 0xFFEz_zzzz ...... Malloc area (grows up to top)
- 0xFFE3_FFFF ...... End of SRAM (top)
*/ +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA +/* SPL executed from FPGA */ +#define CONFIG_SPL_TEXT_BASE 0xC0000000 +#else #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on the previous version of the patch ?
Marek Vasut marex@denx.de schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
To boot from fpga OnChip RAM, some changes are required in SPL to ensure the code is linked to the correct address (in contrast to QSPI and MMC boot, FPGA boot executes SPL in place instead of copying it to SRAM) and that fpga OnChip RAM stays accessible while SPL runs (don't disable fpga bridges).
This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) for socfpga gen5 boards.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Changes in v4: Adapted to changed previous patch Changes in v3: this patch is new in v3 Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- include/configs/socfpga_common.h | 5 +++++ 4 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig
b/arch/arm/mach-socfpga/Kconfig
index 5c1df2cf1f..a909395aac 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
+if TARGET_SOCFPGA_GEN5
+config SPL_SOCFPGA_BOOT_FROM_FPGA
bool "Allow booting SPL from FPGA OnChip RAM"default nhelpBoot from FPGA: this changes the linker address for SPL code torun
from FPGA OnChip memory instead of SRAM and ensures FPGA OnChipRAM
stays accessible while SPL runs.+endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 429c3d6cd5..c82c3584dc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {/* remap.mpuzero, keep fpga bridge enabled */writel(0x9, &nic301_regs->remap);} else {/* remap.mpuzero */writel(0x1, &nic301_regs->remap);} writel(0x1, &pl310->pl310_addr_filter_start);}
@@ -209,7 +215,8 @@ int arch_early_init_r(void) for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_sdram_remap_zero();diff --git a/arch/arm/mach-socfpga/spl_gen5.c
b/arch/arm/mach-socfpga/spl_gen5.c
index be318cc0d9..0c7f6a8c84 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); /* Put FPGA bridges into reset too. */
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0);@@ -163,5 +164,6 @@ void board_init_f(ulong dummy) hang(); }
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1);} diff --git a/include/configs/socfpga_common.h
b/include/configs/socfpga_common.h
index d1148b838b..99c5e39086 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
- 0xFFEz_zzzz ...... Malloc area (grows up to top)
- 0xFFE3_FFFF ...... End of SRAM (top)
*/ +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA +/* SPL executed from FPGA */ +#define CONFIG_SPL_TEXT_BASE 0xC0000000 +#else #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on the previous version of the patch ?
D'oh! That slipped through. Sorry for reminding.
Simon
On Tue, Aug 14, 2018 at 8:12 AM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
Marek Vasut marex@denx.de schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
To boot from fpga OnChip RAM, some changes are required in SPL to ensure the code is linked to the correct address (in contrast to QSPI and MMC boot, FPGA boot executes SPL in place instead of copying it to SRAM) and that fpga OnChip RAM stays accessible while SPL runs (don't disable fpga bridges).
This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) for socfpga gen5 boards.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Changes in v4: Adapted to changed previous patch Changes in v3: this patch is new in v3 Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- include/configs/socfpga_common.h | 5 +++++ 4 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..a909395aac 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
+if TARGET_SOCFPGA_GEN5
+config SPL_SOCFPGA_BOOT_FROM_FPGA
bool "Allow booting SPL from FPGA OnChip RAM"default nhelpBoot from FPGA: this changes the linker address for SPL code to runfrom FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAMstays accessible while SPL runs.+endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..c82c3584dc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {/* remap.mpuzero, keep fpga bridge enabled */writel(0x9, &nic301_regs->remap);} else {/* remap.mpuzero */writel(0x1, &nic301_regs->remap);} writel(0x1, &pl310->pl310_addr_filter_start);}
@@ -209,7 +215,8 @@ int arch_early_init_r(void) for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_sdram_remap_zero();diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..0c7f6a8c84 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); /* Put FPGA bridges into reset too. */
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0);@@ -163,5 +164,6 @@ void board_init_f(ulong dummy) hang(); }
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1);} diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d1148b838b..99c5e39086 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
- 0xFFEz_zzzz ...... Malloc area (grows up to top)
- 0xFFE3_FFFF ...... End of SRAM (top)
*/ +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA +/* SPL executed from FPGA */ +#define CONFIG_SPL_TEXT_BASE 0xC0000000 +#else #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on the previous version of the patch ?
Revisiting that request again, it seems like I would touch tons of files in include/configs (and maybe tons of defconfigs). Is this really the right series to do so?
Or did you think of a config option scoped to mach-socfpga only?
Simon
On 08/14/2018 10:26 PM, Simon Goldschmidt wrote:
On Tue, Aug 14, 2018 at 8:12 AM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
Marek Vasut marex@denx.de schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
To boot from fpga OnChip RAM, some changes are required in SPL to ensure the code is linked to the correct address (in contrast to QSPI and MMC boot, FPGA boot executes SPL in place instead of copying it to SRAM) and that fpga OnChip RAM stays accessible while SPL runs (don't disable fpga bridges).
This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) for socfpga gen5 boards.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Changes in v4: Adapted to changed previous patch Changes in v3: this patch is new in v3 Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- include/configs/socfpga_common.h | 5 +++++ 4 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..a909395aac 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
+if TARGET_SOCFPGA_GEN5
+config SPL_SOCFPGA_BOOT_FROM_FPGA
bool "Allow booting SPL from FPGA OnChip RAM"default nhelpBoot from FPGA: this changes the linker address for SPL code to runfrom FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAMstays accessible while SPL runs.+endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..c82c3584dc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {/* remap.mpuzero, keep fpga bridge enabled */writel(0x9, &nic301_regs->remap);} else {/* remap.mpuzero */writel(0x1, &nic301_regs->remap);} writel(0x1, &pl310->pl310_addr_filter_start);}
@@ -209,7 +215,8 @@ int arch_early_init_r(void) for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_sdram_remap_zero();diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..0c7f6a8c84 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); /* Put FPGA bridges into reset too. */
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0);@@ -163,5 +164,6 @@ void board_init_f(ulong dummy) hang(); }
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1);} diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d1148b838b..99c5e39086 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
- 0xFFEz_zzzz ...... Malloc area (grows up to top)
- 0xFFE3_FFFF ...... End of SRAM (top)
*/ +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA +/* SPL executed from FPGA */ +#define CONFIG_SPL_TEXT_BASE 0xC0000000 +#else #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on the previous version of the patch ?
Revisiting that request again, it seems like I would touch tons of files in include/configs (and maybe tons of defconfigs). Is this really the right series to do so?
If you run moveconfig.py on it, does it seems like much work is left after moveconfig did it's job ? I'd like to prevent the ifdeffery.
Or did you think of a config option scoped to mach-socfpga only?
I'd like to see a generic one, since this is generic config option. Try adding the Kconfig entry, then run moveconfig and see if there's much to be done. Maybe it'll be easier than it looks at first.
Simon
On Wed, Aug 15, 2018 at 10:57 AM Marek Vasut marex@denx.de wrote:
On 08/14/2018 10:26 PM, Simon Goldschmidt wrote:
On Tue, Aug 14, 2018 at 8:12 AM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
Marek Vasut marex@denx.de schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
To boot from fpga OnChip RAM, some changes are required in SPL to ensure the code is linked to the correct address (in contrast to QSPI and MMC boot, FPGA boot executes SPL in place instead of copying it to SRAM) and that fpga OnChip RAM stays accessible while SPL runs (don't disable fpga bridges).
This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) for socfpga gen5 boards.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Changes in v4: Adapted to changed previous patch Changes in v3: this patch is new in v3 Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- include/configs/socfpga_common.h | 5 +++++ 4 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..a909395aac 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
+if TARGET_SOCFPGA_GEN5
+config SPL_SOCFPGA_BOOT_FROM_FPGA
bool "Allow booting SPL from FPGA OnChip RAM"default nhelpBoot from FPGA: this changes the linker address for SPL code to runfrom FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAMstays accessible while SPL runs.+endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..c82c3584dc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {/* remap.mpuzero, keep fpga bridge enabled */writel(0x9, &nic301_regs->remap);} else {/* remap.mpuzero */writel(0x1, &nic301_regs->remap);} writel(0x1, &pl310->pl310_addr_filter_start);}
@@ -209,7 +215,8 @@ int arch_early_init_r(void) for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_sdram_remap_zero();diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..0c7f6a8c84 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); /* Put FPGA bridges into reset too. */
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0);@@ -163,5 +164,6 @@ void board_init_f(ulong dummy) hang(); }
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1);} diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d1148b838b..99c5e39086 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
- 0xFFEz_zzzz ...... Malloc area (grows up to top)
- 0xFFE3_FFFF ...... End of SRAM (top)
*/ +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA +/* SPL executed from FPGA */ +#define CONFIG_SPL_TEXT_BASE 0xC0000000 +#else #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on the previous version of the patch ?
Revisiting that request again, it seems like I would touch tons of files in include/configs (and maybe tons of defconfigs). Is this really the right series to do so?
If you run moveconfig.py on it, does it seems like much work is left after moveconfig did it's job ? I'd like to prevent the ifdeffery.
Or did you think of a config option scoped to mach-socfpga only?
I'd like to see a generic one, since this is generic config option. Try adding the Kconfig entry, then run moveconfig and see if there's much to be done. Maybe it'll be easier than it looks at first.
I didn't want to say it's not easy. I wanted to say it produces a really big patch, as almost every board is affected. Which does not seem to fit into this series...
But I do have some problems: defconfigs for nds32 and sandbox are failing. I got sh and riscv working by editing ~/.buildman. Is this expected?
Simon
On 08/15/2018 09:23 PM, Simon Goldschmidt wrote:
On Wed, Aug 15, 2018 at 10:57 AM Marek Vasut marex@denx.de wrote:
On 08/14/2018 10:26 PM, Simon Goldschmidt wrote:
On Tue, Aug 14, 2018 at 8:12 AM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
Marek Vasut marex@denx.de schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
To boot from fpga OnChip RAM, some changes are required in SPL to ensure the code is linked to the correct address (in contrast to QSPI and MMC boot, FPGA boot executes SPL in place instead of copying it to SRAM) and that fpga OnChip RAM stays accessible while SPL runs (don't disable fpga bridges).
This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) for socfpga gen5 boards.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Changes in v4: Adapted to changed previous patch Changes in v3: this patch is new in v3 Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- include/configs/socfpga_common.h | 5 +++++ 4 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..a909395aac 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
+if TARGET_SOCFPGA_GEN5
+config SPL_SOCFPGA_BOOT_FROM_FPGA
bool "Allow booting SPL from FPGA OnChip RAM"default nhelpBoot from FPGA: this changes the linker address for SPL code to runfrom FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAMstays accessible while SPL runs.+endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..c82c3584dc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {/* remap.mpuzero, keep fpga bridge enabled */writel(0x9, &nic301_regs->remap);} else {/* remap.mpuzero */writel(0x1, &nic301_regs->remap);} writel(0x1, &pl310->pl310_addr_filter_start);}
@@ -209,7 +215,8 @@ int arch_early_init_r(void) for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_sdram_remap_zero();diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..0c7f6a8c84 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); /* Put FPGA bridges into reset too. */
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1); socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0);@@ -163,5 +164,6 @@ void board_init_f(ulong dummy) hang(); }
socfpga_bridges_reset(1);
if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))socfpga_bridges_reset(1);} diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d1148b838b..99c5e39086 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
- 0xFFEz_zzzz ...... Malloc area (grows up to top)
- 0xFFE3_FFFF ...... End of SRAM (top)
*/ +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA +/* SPL executed from FPGA */ +#define CONFIG_SPL_TEXT_BASE 0xC0000000 +#else #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on the previous version of the patch ?
Revisiting that request again, it seems like I would touch tons of files in include/configs (and maybe tons of defconfigs). Is this really the right series to do so?
If you run moveconfig.py on it, does it seems like much work is left after moveconfig did it's job ? I'd like to prevent the ifdeffery.
Or did you think of a config option scoped to mach-socfpga only?
I'd like to see a generic one, since this is generic config option. Try adding the Kconfig entry, then run moveconfig and see if there's much to be done. Maybe it'll be easier than it looks at first.
I didn't want to say it's not easy. I wanted to say it produces a really big patch, as almost every board is affected. Which does not seem to fit into this series...
I agree the patch will be huge. And it'd be a nice cleanup. Would you mind postponing this booting from FPGA patch series for after the release ? I'd like to get the fixes for the standard booting paths into the release, but the next into the next one.
But I do have some problems: defconfigs for nds32 and sandbox are failing. I got sh and riscv working by editing ~/.buildman. Is this expected?
Possibly. Try running it through travis-ci to see what broke. No need to build everything locally.
On Thu, Aug 16, 2018 at 1:33 AM Marek Vasut marex@denx.de wrote:
On 08/15/2018 09:23 PM, Simon Goldschmidt wrote:
On Wed, Aug 15, 2018 at 10:57 AM Marek Vasut marex@denx.de wrote:
On 08/14/2018 10:26 PM, Simon Goldschmidt wrote:
On Tue, Aug 14, 2018 at 8:12 AM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
Marek Vasut marex@denx.de schrieb am Mo., 13. Aug. 2018, 22:36:
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote: > To boot from fpga OnChip RAM, some changes are required in SPL > to ensure the code is linked to the correct address (in contrast > to QSPI and MMC boot, FPGA boot executes SPL in place instead of > copying it to SRAM) and that fpga OnChip RAM stays accessible while > SPL runs (don't disable fpga bridges). > > This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) > for socfpga gen5 boards. > > Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com > --- > > Changes in v4: Adapted to changed previous patch > Changes in v3: this patch is new in v3 > Changes in v2: None > > arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ > arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- > arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- > include/configs/socfpga_common.h | 5 +++++ > 4 files changed, 30 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig > index 5c1df2cf1f..a909395aac 100644 > --- a/arch/arm/mach-socfpga/Kconfig > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME > default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA > > endif > + > +if TARGET_SOCFPGA_GEN5 > + > +config SPL_SOCFPGA_BOOT_FROM_FPGA > + bool "Allow booting SPL from FPGA OnChip RAM" > + default n > + help > + Boot from FPGA: this changes the linker address for SPL code to run > + from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAM > + stays accessible while SPL runs. > + > +endif > diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c > index 429c3d6cd5..c82c3584dc 100644 > --- a/arch/arm/mach-socfpga/misc_gen5.c > +++ b/arch/arm/mach-socfpga/misc_gen5.c > @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) > setbits_le32(&scu_regs->sacr, 0xfff); > > /* Configure the L2 controller to make SDRAM start at 0 */ > - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ > + if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) { > + /* remap.mpuzero, keep fpga bridge enabled */ > + writel(0x9, &nic301_regs->remap); > + } else { > + /* remap.mpuzero */ > + writel(0x1, &nic301_regs->remap); > + } > writel(0x1, &pl310->pl310_addr_filter_start); > } > > @@ -209,7 +215,8 @@ int arch_early_init_r(void) > for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ > iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); > > - socfpga_bridges_reset(1); > + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) > + socfpga_bridges_reset(1); > > socfpga_sdram_remap_zero(); > > diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c > index be318cc0d9..0c7f6a8c84 100644 > --- a/arch/arm/mach-socfpga/spl_gen5.c > +++ b/arch/arm/mach-socfpga/spl_gen5.c > @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) > /* Put everything into reset but L4WD0. */ > socfpga_per_reset_all(); > /* Put FPGA bridges into reset too. */ > - socfpga_bridges_reset(1); > + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) > + socfpga_bridges_reset(1); > > socfpga_per_reset(SOCFPGA_RESET(SDR), 0); > socfpga_per_reset(SOCFPGA_RESET(UART0), 0); > @@ -163,5 +164,6 @@ void board_init_f(ulong dummy) > hang(); > } > > - socfpga_bridges_reset(1); > + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) > + socfpga_bridges_reset(1); > } > diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h > index d1148b838b..99c5e39086 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > * 0xFFEz_zzzz ...... Malloc area (grows up to top) > * 0xFFE3_FFFF ...... End of SRAM (top) > */ > +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA > +/* SPL executed from FPGA */ > +#define CONFIG_SPL_TEXT_BASE 0xC0000000 > +#else > #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR > +#endif > #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE > > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on the previous version of the patch ?
Revisiting that request again, it seems like I would touch tons of files in include/configs (and maybe tons of defconfigs). Is this really the right series to do so?
If you run moveconfig.py on it, does it seems like much work is left after moveconfig did it's job ? I'd like to prevent the ifdeffery.
Or did you think of a config option scoped to mach-socfpga only?
I'd like to see a generic one, since this is generic config option. Try adding the Kconfig entry, then run moveconfig and see if there's much to be done. Maybe it'll be easier than it looks at first.
I didn't want to say it's not easy. I wanted to say it produces a really big patch, as almost every board is affected. Which does not seem to fit into this series...
I agree the patch will be huge. And it'd be a nice cleanup. Would you mind postponing this booting from FPGA patch series for after the release ? I'd like to get the fixes for the standard booting paths into the release, but the next into the next one.
Yes, let's leave SPL-from-FPGA for the next release then. But can we still merge the gd->ev_addr relocation patch for U-Boot? I'll send a V5 with fixed comments.
Simon
But I do have some problems: defconfigs for nds32 and sandbox are failing. I got sh and riscv working by editing ~/.buildman. Is this expected?
Possibly. Try running it through travis-ci to see what broke. No need to build everything locally.
-- Best regards, Marek Vasut
On 08/16/2018 09:26 AM, Simon Goldschmidt wrote:
On Thu, Aug 16, 2018 at 1:33 AM Marek Vasut marex@denx.de wrote:
On 08/15/2018 09:23 PM, Simon Goldschmidt wrote:
On Wed, Aug 15, 2018 at 10:57 AM Marek Vasut marex@denx.de wrote:
On 08/14/2018 10:26 PM, Simon Goldschmidt wrote:
On Tue, Aug 14, 2018 at 8:12 AM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
Marek Vasut marex@denx.de schrieb am Mo., 13. Aug. 2018, 22:36: > > On 08/13/2018 09:34 PM, Simon Goldschmidt wrote: >> To boot from fpga OnChip RAM, some changes are required in SPL >> to ensure the code is linked to the correct address (in contrast >> to QSPI and MMC boot, FPGA boot executes SPL in place instead of >> copying it to SRAM) and that fpga OnChip RAM stays accessible while >> SPL runs (don't disable fpga bridges). >> >> This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA) >> for socfpga gen5 boards. >> >> Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com >> --- >> >> Changes in v4: Adapted to changed previous patch >> Changes in v3: this patch is new in v3 >> Changes in v2: None >> >> arch/arm/mach-socfpga/Kconfig | 12 ++++++++++++ >> arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++-- >> arch/arm/mach-socfpga/spl_gen5.c | 6 ++++-- >> include/configs/socfpga_common.h | 5 +++++ >> 4 files changed, 30 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig >> index 5c1df2cf1f..a909395aac 100644 >> --- a/arch/arm/mach-socfpga/Kconfig >> +++ b/arch/arm/mach-socfpga/Kconfig >> @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME >> default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA >> >> endif >> + >> +if TARGET_SOCFPGA_GEN5 >> + >> +config SPL_SOCFPGA_BOOT_FROM_FPGA >> + bool "Allow booting SPL from FPGA OnChip RAM" >> + default n >> + help >> + Boot from FPGA: this changes the linker address for SPL code to run >> + from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAM >> + stays accessible while SPL runs. >> + >> +endif >> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c >> index 429c3d6cd5..c82c3584dc 100644 >> --- a/arch/arm/mach-socfpga/misc_gen5.c >> +++ b/arch/arm/mach-socfpga/misc_gen5.c >> @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void) >> setbits_le32(&scu_regs->sacr, 0xfff); >> >> /* Configure the L2 controller to make SDRAM start at 0 */ >> - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ >> + if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) { >> + /* remap.mpuzero, keep fpga bridge enabled */ >> + writel(0x9, &nic301_regs->remap); >> + } else { >> + /* remap.mpuzero */ >> + writel(0x1, &nic301_regs->remap); >> + } >> writel(0x1, &pl310->pl310_addr_filter_start); >> } >> >> @@ -209,7 +215,8 @@ int arch_early_init_r(void) >> for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ >> iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); >> >> - socfpga_bridges_reset(1); >> + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) >> + socfpga_bridges_reset(1); >> >> socfpga_sdram_remap_zero(); >> >> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c >> index be318cc0d9..0c7f6a8c84 100644 >> --- a/arch/arm/mach-socfpga/spl_gen5.c >> +++ b/arch/arm/mach-socfpga/spl_gen5.c >> @@ -93,7 +93,8 @@ void board_init_f(ulong dummy) >> /* Put everything into reset but L4WD0. */ >> socfpga_per_reset_all(); >> /* Put FPGA bridges into reset too. */ >> - socfpga_bridges_reset(1); >> + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) >> + socfpga_bridges_reset(1); >> >> socfpga_per_reset(SOCFPGA_RESET(SDR), 0); >> socfpga_per_reset(SOCFPGA_RESET(UART0), 0); >> @@ -163,5 +164,6 @@ void board_init_f(ulong dummy) >> hang(); >> } >> >> - socfpga_bridges_reset(1); >> + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) >> + socfpga_bridges_reset(1); >> } >> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h >> index d1148b838b..99c5e39086 100644 >> --- a/include/configs/socfpga_common.h >> +++ b/include/configs/socfpga_common.h >> @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); >> * 0xFFEz_zzzz ...... Malloc area (grows up to top) >> * 0xFFE3_FFFF ...... End of SRAM (top) >> */ >> +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA >> +/* SPL executed from FPGA */ >> +#define CONFIG_SPL_TEXT_BASE 0xC0000000 >> +#else >> #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR >> +#endif >> #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE >> >> #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on > the previous version of the patch ?
Revisiting that request again, it seems like I would touch tons of files in include/configs (and maybe tons of defconfigs). Is this really the right series to do so?
If you run moveconfig.py on it, does it seems like much work is left after moveconfig did it's job ? I'd like to prevent the ifdeffery.
Or did you think of a config option scoped to mach-socfpga only?
I'd like to see a generic one, since this is generic config option. Try adding the Kconfig entry, then run moveconfig and see if there's much to be done. Maybe it'll be easier than it looks at first.
I didn't want to say it's not easy. I wanted to say it produces a really big patch, as almost every board is affected. Which does not seem to fit into this series...
I agree the patch will be huge. And it'd be a nice cleanup. Would you mind postponing this booting from FPGA patch series for after the release ? I'd like to get the fixes for the standard booting paths into the release, but the next into the next one.
Yes, let's leave SPL-from-FPGA for the next release then. But can we still merge the gd->ev_addr relocation patch for U-Boot? I'll send a V5 with fixed comments.
Yes, thanks
malloc_simple() can return 0 if out of memory. Don't call memset from calloc() in this case but rely on the caller checking the return value.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Reviewed-by: Marek Vasut marex@denx.de
---
Changes in v4: None Changes in v3: None Changes in v2: None
common/malloc_simple.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/malloc_simple.c b/common/malloc_simple.c index c14f8b59c1..871b5444bd 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -57,7 +57,8 @@ void *calloc(size_t nmemb, size_t elem_size) void *ptr;
ptr = malloc(size); - memset(ptr, '\0', size); + if (ptr) + memset(ptr, '\0', size);
return ptr; }
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
malloc_simple() can return 0 if out of memory. Don't call memset from calloc() in this case but rely on the caller checking the return value.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Reviewed-by: Marek Vasut marex@denx.de
Separate this from the patchset, this has nothing to do with socfpga .
Changes in v4: None Changes in v3: None Changes in v2: None
common/malloc_simple.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/malloc_simple.c b/common/malloc_simple.c index c14f8b59c1..871b5444bd 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -57,7 +57,8 @@ void *calloc(size_t nmemb, size_t elem_size) void *ptr;
ptr = malloc(size);
- memset(ptr, '\0', size);
if (ptr)
memset(ptr, '\0', size);return ptr;
}
malloc_simple() can return 0 if out of memory. Don't call memset from calloc() in this case but rely on the caller checking the return value.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Reviewed-by: Marek Vasut marex@denx.de
---
Changes in v1: - extracted this patch from series "Get socfpga gen5 SPL working again" as it is not socfpga specific
common/malloc_simple.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/malloc_simple.c b/common/malloc_simple.c index c14f8b59c1..871b5444bd 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -57,7 +57,8 @@ void *calloc(size_t nmemb, size_t elem_size) void *ptr;
ptr = malloc(size); - memset(ptr, '\0', size); + if (ptr) + memset(ptr, '\0', size);
return ptr; }
On Thu, Aug 16, 2018 at 09:50:32AM +0200, Simon Goldschmidt wrote:
malloc_simple() can return 0 if out of memory. Don't call memset from calloc() in this case but rely on the caller checking the return value.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Reviewed-by: Marek Vasut marex@denx.de
Applied to u-boot/master, thanks!
participants (3)
-
Marek Vasut -
Simon Goldschmidt -
Tom Rini