This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com ---

drivers/serial/Kconfig | 5 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_msm.c | 204 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 210 insertions(+) create mode 100644 drivers/serial/serial_msm.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1fc287e..f28c093 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -223,4 +223,9 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N.

+config MSM_SERIAL + bool "Qualcomm on-chip UART" + depends on DM_SERIAL + help + Support Data Mover UART used on Qualcomm Snapdragon SoCs. endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..d052175 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o +obj-$(CONFIG_MSM_SERIAL) += serial_msm.o

ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c new file mode 100644 index 0000000..13dad33 --- /dev/null +++ b/drivers/serial/serial_msm.c @@ -0,0 +1,204 @@ +/* + * Qualcomm UART driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * UART will work in Data Mover mode. + * Based on Linux driver. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <errno.h> +#include <linux/compiler.h> +#include <serial.h> +#include <watchdog.h> + +/* Serial registers - this driver works in uartdm mode*/ + +#define UARTDM_DMRX 0x34 /* Max RX transfer length */ +#define UARTDM_NCF_TX 0x40 /* Number of chars to TX */ + +#define UARTDM_RXFS 0x50 /* RX channel status register */ +#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */ +#define UARTDM_RXFS_BUF_MASK 0x7 + +#define UARTDM_SR 0xA4 /* Status register */ +#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */ +#define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */ +#define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */ + +#define UARTDM_CR 0xA8 /* Command register */ +#define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */ +#define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */ +#define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/ +#define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */ +#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */ + +#define UARTDM_IMR 0xB0 /* Interrupt mask register */ +#define UARTDM_ISR 0xB4 /* Interrupt status register */ +#define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */ + +#define UARTDM_TF 0x100 /* UART Transmit FIFO register */ +#define UARTDM_RF 0x140 /* UART Receive FIFO register */ + + +DECLARE_GLOBAL_DATA_PTR; + +struct msm_serial_data { + phys_addr_t base; + unsigned chars_cnt; /* number of buffered chars */ + uint32_t chars_buf; /* buffered chars */ +}; + +static int msm_serial_getc(struct udevice *dev) +{ + struct msm_serial_data *p = dev_get_priv(dev); + unsigned sr; + char c; + + /* There was something buffered */ + if (p->chars_cnt) { + c = p->chars_buf & 0xFF; + p->chars_buf >>= 8; + p->chars_cnt--; + return c; + } + + /* Clear error in case of buffer overrun */ + if (readl(p->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) + writel(UARTDM_CR_CMD_RESET_ERR, p->base + UARTDM_CR); + + /* We need to fetch new character */ + sr = readl(p->base + UARTDM_SR); + + /* There are at least 4 bytes in fifo */ + if (sr & UARTDM_SR_RX_READY) { + p->chars_buf = readl(p->base + UARTDM_RF); + c = p->chars_buf & 0xFF; + p->chars_cnt = 3; /* 4 - one read */ + p->chars_buf >>= 8; + return c; + } + + /* Check if there is anything in fifo */ + p->chars_cnt = readl(p->base + UARTDM_RXFS); + /* Extract number of characters in UART packing buffer */ + p->chars_cnt = (p->chars_cnt >> UARTDM_RXFS_BUF_SHIFT) & + UARTDM_RXFS_BUF_MASK; + if (!p->chars_cnt) + return -EAGAIN; + + /* There is at least one charcter, move it to fifo */ + writel(UARTDM_CR_CMD_FORCE_STALE, p->base + UARTDM_CR); + + p->chars_buf = readl(p->base + UARTDM_RF); + writel(UARTDM_CR_CMD_RESET_STALE_INT, p->base + UARTDM_CR); + writel(0xFFFFFF, p->base + UARTDM_DMRX); + + c = p->chars_buf & 0xFF; + p->chars_buf >>= 8; + p->chars_cnt--; + + return c; +} + +static int msm_serial_putc(struct udevice *dev, const char ch) +{ + struct msm_serial_data *p = dev_get_priv(dev); + + if (!(readl(p->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) && + !(readl(p->base + UARTDM_ISR) & UARTDM_ISR_TX_READY)) + return -EAGAIN; + + writel(UARTDM_CR_CMD_RESET_TX_READY, p->base + UARTDM_CR); + + writel(1, p->base + UARTDM_NCF_TX); + writel(ch, p->base + UARTDM_TF); + return 0; +} + +static int msm_serial_pending(struct udevice *dev, bool input) +{ + struct msm_serial_data *p = dev_get_priv(dev); + + if (input) { + if (p->chars_cnt) + return 1; + if (readl(p->base + UARTDM_SR) & UARTDM_SR_RX_READY) + return 1; + if (readl(p->base + UARTDM_RXFS)) + return 1; + } + return 0; +} + +static const struct dm_serial_ops msm_serial_ops = { + .putc = msm_serial_putc, + .pending = msm_serial_pending, + .getc = msm_serial_getc, +}; + +static int msm_uart_clk_init(struct udevice *dev) +{ + uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "clock-frequency", 115200); + uint clkd[2]; /* clk_id and clk_no */ + fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, 2); + clkd[0] = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); + + struct udevice *clk = NULL; + uclass_get_device_by_of_offset(UCLASS_CLK, clkd[0], &clk); + if (clk) + clk_set_periph_rate(clk, clkd[1], clk_rate); + + return 0; +} + +static int msm_serial_probe(struct udevice *dev) +{ + struct msm_serial_data *p = dev_get_priv(dev); + + msm_uart_clk_init(dev); + + if (readl(p->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) + writel(UARTDM_CR_CMD_RESET_ERR, p->base + UARTDM_CR); + + writel(0, p->base + UARTDM_IMR); + writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, p->base + UARTDM_CR); + writel(0xFFFFFF, p->base + UARTDM_DMRX); + + p->chars_buf = 0; + p->chars_cnt = 0; + return 0; +} + +static int msm_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct msm_serial_data *p = dev_get_priv(dev); + + p->base = dev_get_addr(dev); + if (p->base == FDT_ADDR_T_NONE) + return -EINVAL; + return 0; +} + +static const struct udevice_id msm_serial_ids[] = { + { .compatible = "qcom,msm-uartdm-v1.4" }, + { } +}; + +U_BOOT_DRIVER(serial_msm) = { + .name = "serial_msm", + .id = UCLASS_SERIAL, + .of_match = msm_serial_ids, + .ofdata_to_platdata = msm_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct msm_serial_data), + .probe = msm_serial_probe, + .ops = &msm_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +};

Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com ---

drivers/gpio/Kconfig | 7 +++ drivers/gpio/Makefile | 2 +- drivers/gpio/msm_gpio.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 drivers/gpio/msm_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e60e9fd..1d9443b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -46,6 +46,13 @@ config LPC32XX_GPIO help Support for the LPC32XX GPIO driver.

+config MSM_GPIO + bool "Qualcomm GPIO driver" + depends on DM_GPIO + default n + help + Support GPIO controllers on Qualcomm Snapdragon family of SoCs. + config ROCKCHIP_GPIO bool "Rockchip GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb4fd25..9520b1e 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o - +obj-$(CONFIG_MSM_GPIO) += msm_gpio.o diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c new file mode 100644 index 0000000..9bb9e89 --- /dev/null +++ b/drivers/gpio/msm_gpio.c @@ -0,0 +1,115 @@ +/* + * Qualcomm GPIO driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct msm_gpio_bank { + phys_addr_t base; +}; + +static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio); + + /* Disable OE bit */ + writel((readl(reg) & ~GPIO_OE_MASK) | GPIO_OE_DISABLE , reg); + return 0; +} + +static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + + value = !!value; + /* set value */ + writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio)); + return 0; +} + +static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio); + + value = !!value; + /* set value */ + writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio)); + /* switch direction */ + writel((readl(reg) & ~GPIO_OE_MASK) | GPIO_OE_ENABLE , reg); + return 0; +} + +static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + + return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN); +} + +static int msm_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + + if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE) + return GPIOF_OUTPUT; + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops gpio_msm_ops = { + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get_value = msm_gpio_get_value, + .set_value = msm_gpio_set_value, + .get_function = msm_gpio_get_function, +}; + +static int msm_gpio_probe(struct udevice *dev) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + return priv->base == FDT_ADDR_T_NONE; +} + +static int msm_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "gpio-count", 0); + uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, + "gpio-bank-name", NULL); + if (uc_priv->bank_name == NULL) + uc_priv->bank_name = "soc"; + return 0; +} + +static const struct udevice_id msm_gpio_ids[] = { + { .compatible = "qcom,msm8916-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(gpio_msm) = { + .name = "gpio_msm", + .id = UCLASS_GPIO, + .of_match = msm_gpio_ids, + .ofdata_to_platdata = msm_gpio_ofdata_to_platdata, + .probe = msm_gpio_probe, + .ops = &gpio_msm_ops, + .priv_auto_alloc_size = sizeof(struct msm_gpio_bank), +}; + +

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com ---

drivers/mmc/Kconfig | 6 ++ drivers/mmc/Makefile | 1 + drivers/mmc/msm_sdhci.c | 149 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 drivers/mmc/msm_sdhci.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index ceae7bc..3f75fa7 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -16,6 +16,12 @@ config DM_MMC appear as block devices in U-Boot and can support filesystems such as EXT4 and FAT.

+config MSM_SDHCI + bool "Qualcomm SDHCI controller" + depends on DM_MMC + help + Enables support for SDHCI 2.0 controller manufactured by Qualcomm. + config ROCKCHIP_DWMMC bool "Rockchip SD/MMC controller support" depends on DM_MMC && OF_CONTROL diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 5d35705..f4fdfca 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -49,3 +49,4 @@ else obj-$(CONFIG_GENERIC_MMC) += mmc_write.o endif

+obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c new file mode 100644 index 0000000..96119f0 --- /dev/null +++ b/drivers/mmc/msm_sdhci.c @@ -0,0 +1,149 @@ +/* + * Qualcomm SDHCI driver - SD/eMMC controller + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * Based on Linux driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <common.h> +#include <dm.h> +#include <linux/bitops.h> +#include <sdhci.h> +#include <clk.h> + +/* Non-standard registers needed for SDHCI startup */ +#define SDCC_MCI_POWER 0x0 +#define SDCC_MCI_POWER_SW_RST BIT(7) + +/* This is undocumented register */ +#define SDCC_MCI_VERSION 0x50 +#define SDCC_MCI_VERSION_MAJOR_SHIFT 28 +#define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT) +#define SDCC_MCI_VERSION_MINOR_MASK 0xff + +#define SDCC_MCI_HC_MODE 0x78 + +/* Offset to SDHCI registers */ +#define SDCC_SDHCI_OFFSET 0x900 + +/* Non standard (?) SDHCI register */ +#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c + +struct msm_sdhc { + struct sdhci_host host; + phys_addr_t base; + unsigned width; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static int msm_sdc_clk_init(struct udevice *dev) +{ + uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "clock-frequency", 400000); + uint clkd[2]; /* clk_id and clk_no */ + fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, 2); + clkd[0] = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); + + struct udevice *clk = NULL; + uclass_get_device_by_of_offset(UCLASS_CLK, clkd[0], &clk); + if (clk) + clk_set_periph_rate(clk, clkd[1], clk_rate); + + return 0; +} + +static int msm_sdc_probe(struct udevice *dev) +{ + struct msm_sdhc *prv = dev_get_priv(dev); + struct sdhci_host *host = &prv->host; + u32 core_version, core_minor, core_major; + + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; + + /* Init clocks */ + if (msm_sdc_clk_init(dev)) + return -EIO; + + /* Reset the core and Enable SDHC mode */ + writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST, + prv->base + SDCC_MCI_POWER); + + /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ + mdelay(2); + + if (readl(prv->base + SDCC_MCI_POWER) & SDCC_MCI_POWER_SW_RST) { + printf("msm_sdhci: stuck in reset\n"); + return -1; + } + + /* Enable host-controller mode */ + writel(1, prv->base + SDCC_MCI_HC_MODE); + + core_version = readl(prv->base + SDCC_MCI_VERSION); + + core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK); + core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT; + + core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK; + + /* + * Support for some capabilities is not advertised by newer + * controller versions and must be explicitly enabled. + */ + if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { + u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES); + caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; + writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); + } + + /* Set host controller version */ + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + + /* automatically detect max and min speed */ + return add_sdhci(host, 0, 0); +} + +static int msm_sdc_remove(struct udevice *dev) +{ + struct msm_sdhc *priv = dev_get_priv(dev); + /* Disable host-controller mode */ + writel(0, priv->base + SDCC_MCI_HC_MODE); + return 0; +} + +static int msm_ofdata_to_platdata(struct udevice *dev) +{ + struct msm_sdhc *priv = dev_get_priv(dev); + struct sdhci_host *host = &priv->host; + + host->name = strdup(dev->name); + host->ioaddr = (void *)dev_get_addr(dev); + host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); + host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0); + priv->base = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, + dev->parent->of_offset, + dev->of_offset, "reg", + 1, NULL); + return 0; +} + +static const struct udevice_id msm_mmc_ids[] = { + { .compatible = "qcom,sdhci-msm-v4" }, + { } +}; + +U_BOOT_DRIVER(msm_sdc_drv) = { + .name = "msm_sdc", + .id = UCLASS_MMC, + .of_match = msm_mmc_ids, + .ofdata_to_platdata = msm_ofdata_to_platdata, + .probe = msm_sdc_probe, + .remove = msm_sdc_remove, + .priv_auto_alloc_size = sizeof(struct msm_sdhc), +};

This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com ---

drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-msm.c | 198 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/usb/host/ehci-msm.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0096a2f..5a63475 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -66,6 +66,14 @@ config USB_EHCI_MX6 ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs.

+config USB_EHCI_MSM + bool "Support for Qualcomm on-chip EHCI USB controller" + depends on DM_USB + default n + ---help--- + Enables support for the on-chip EHCI controller on Qualcomm + Snapdragon SoCs. + config USB_EHCI_UNIPHIER bool "Support for UniPhier on-chip EHCI USB controller" depends on ARCH_UNIPHIER && OF_CONTROL diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 0b4b458..d4a556a 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o +obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c new file mode 100644 index 0000000..d17a29a --- /dev/null +++ b/drivers/usb/host/ehci-msm.c @@ -0,0 +1,198 @@ +/* + * Qualcomm EHCI driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * Based on Linux driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm-generic/errno.h> +#include <linux/compat.h> +#include <dm.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <asm/io.h> +#include <usb.h> +#include <usb/ulpi.h> +#include "ehci.h" + +#ifndef CONFIG_USB_ULPI_VIEWPORT +#error Please enable CONFIG_USB_ULPI_VIEWPORT +#endif + +#define MSM_USB_ULPI_OFFSET 0x170 /* ULPI viewport (PHY) */ +#define MSM_USB_EHCI_OFFSET 0x100 /* Start of EHCI registers */ + +/* PHY viewport regs */ +#define ULPI_MISC_A_READ 0x96 +#define ULPI_MISC_A_SET 0x97 +#define ULPI_MISC_A_CLEAR 0x98 +#define ULPI_MISC_A_VBUSVLDEXTSEL (1 << 1) +#define ULPI_MISC_A_VBUSVLDEXT (1 << 0) + +/* qcom specific registers (OTG) */ +#define USB_GENCONFIG_2 0x00A0 +#define GEN2_SESS_VLD_CTRL_EN (1 << 7) + +#define USB_USBCMD (0x0140) +#define SESS_VLD_CTRL (1 << 25) +#define USBCMD_RESET 2 +#define USBCMD_ATTACH 1 + +/* USB2_HSIC_USB_OTG_HS_BASE_USB_OTG_HS_PORTSC */ +#define USB_PORTSC 0x0184 +#define USB_SBUSCFG 0x0090 +#define USB_AHB_MODE 0x0098 + +#define USB_USBMODE 0x01A8 +#define USBMODE_DEVICE 2 +#define USBMODE_HOST 3 + +struct msm_ehci_priv { + struct ehci_ctrl ctrl; /* Needed by EHCI */ + phys_addr_t base; + phys_addr_t ehci_base; + u32 ulpi_base; + u32 ulpi_port; +}; + +int __weak board_prepare_usb(enum usb_init_type type) +{ + return 0; +} + +static void setup_usb_phy(struct msm_ehci_priv *priv) +{ + struct ulpi_viewport ulpi_vp = {.port_num = priv->ulpi_port, + .viewport_addr = priv->ulpi_base}; + + /* Select and enable external configuration with USB PHY */ + ulpi_write(&ulpi_vp, (u8 *)ULPI_MISC_A_SET, + ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT); +} + +static void reset_usb_phy(struct msm_ehci_priv *priv) +{ + struct ulpi_viewport ulpi_vp = {.port_num = priv->ulpi_port, + .viewport_addr = priv->ulpi_base}; + + /* Disable VBUS mimicing in the controller. */ + ulpi_write(&ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR, + ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT); +} + + +static int msm_init_after_reset(struct ehci_ctrl *dev) +{ + struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv, ctrl); + uint32_t val; + + /* select ULPI phy */ + writel(0x80000000, p->base + USB_PORTSC); + setup_usb_phy(p); + + /* Enable sess_vld */ + val = readl(p->base + USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN; + writel(val, p->base + USB_GENCONFIG_2); + + /* Enable external vbus configuration in the LINK */ + val = readl(p->base + USB_USBCMD); + val |= SESS_VLD_CTRL; + writel(val, p->base + USB_USBCMD); + + /* USB_OTG_HS_AHB_BURST */ + writel(0x0, p->base + USB_SBUSCFG); + + /* USB_OTG_HS_AHB_MODE: HPROT_MODE */ + /* Bus access related config. */ + writel(0x08, p->base + USB_AHB_MODE); + + /* set mode to host controller */ + writel(USBMODE_HOST, p->base + USB_USBMODE); + + return 0; +} + +static const struct ehci_ops msm_ehci_ops = { + .init_after_reset = msm_init_after_reset +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct msm_ehci_priv *p = dev_get_priv(dev); + struct ehci_hccr *cr; + struct ehci_hcor *or; + int ret; + + cr = (struct ehci_hccr *)p->ehci_base; + or = (struct ehci_hcor *)(p->ehci_base + + HC_LENGTH(readl(p->ehci_base))); + + ret = board_prepare_usb(USB_INIT_HOST); + if (ret < 0) + return ret; + + + return ehci_register(dev, cr, or, &msm_ehci_ops, 0, USB_INIT_HOST); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + struct msm_ehci_priv *p = dev_get_priv(dev); + phys_addr_t reg = p->base + USB_USBCMD; + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + /* Stop controller. */ + writel(readl(reg) & ~USBCMD_ATTACH, reg); + + reset_usb_phy(p); + + ret = board_prepare_usb(USB_INIT_DEVICE); /* Board specific hook */ + if (ret < 0) + return ret; + + /* Reset controller */ + writel(0x00080002, reg); /* reset usb */ + mdelay(20); + /* Wait for completion */ + while (readl(reg) & 2) + ; + + return 0; +} + +static int ehci_usb_ofdata_to_platdata(struct udevice *dev) +{ + struct msm_ehci_priv *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + priv->ehci_base = priv->base + MSM_USB_EHCI_OFFSET; + priv->ulpi_base = priv->base + MSM_USB_ULPI_OFFSET; + priv->ulpi_port = 0; + return 0; +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "qcom,ehci-host", }, + { } +}; + +U_BOOT_DRIVER(usb_ehci) = { + .name = "ehci_msm", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .priv_auto_alloc_size = sizeof(struct msm_ehci_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +};

Support SPMI arbiter on Qualcomm Snapdragon devices.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com ---

drivers/spmi/Kconfig | 6 ++ drivers/spmi/Makefile | 1 + drivers/spmi/spmi-msm.c | 183 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 190 insertions(+) create mode 100644 drivers/spmi/spmi-msm.c

diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index 2d8d78b..4f17df0 100644 --- a/drivers/spmi/Kconfig +++ b/drivers/spmi/Kconfig @@ -7,4 +7,10 @@ config DM_SPMI Select this to enable to support SPMI bus. SPMI (System Power Management Interface) bus is used to connect PMIC devices on various SoCs. + +config SPMI_MSM + boolean "Support Qualcomm SPMI bus" + depends on DM_SPMI + ---help--- + Support SPMI implementation found on Qualcomm Snapdragon SoCs. endmenu diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile index 2015b1a..419fe1d 100644 --- a/drivers/spmi/Makefile +++ b/drivers/spmi/Makefile @@ -5,3 +5,4 @@ #

obj-$(CONFIG_DM_SPMI) += spmi-uclass.o +obj-$(CONFIG_SPMI_MSM) += spmi-msm.o diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c new file mode 100644 index 0000000..6781a92 --- /dev/null +++ b/drivers/spmi/spmi-msm.c @@ -0,0 +1,183 @@ +/* + * Qualcomm SPMI bus driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * Loosely based on Little Kernel driver + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm/io.h> +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <spmi/spmi.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ARB_CHANNEL_OFFSET(n) (0x800 + 0x4 * (n)) +#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000) + +#define SPMI_REG_CMD0 0x0 +#define SPMI_REG_CONFIG 0x4 +#define SPMI_REG_STATUS 0x8 +#define SPMI_REG_WDATA 0x10 +#define SPMI_REG_RDATA 0x18 + +#define SPMI_CMD_OPCODE_SHIFT 27 +#define SPMI_CMD_SLAVE_ID_SHIFT 20 +#define SPMI_CMD_ADDR_SHIFT 12 +#define SPMI_CMD_ADDR_OFFSET_SHIFT 4 +#define SPMI_CMD_BYTE_CNT_SHIFT 0 + +#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00 +#define SPMI_CMD_EXT_REG_READ_LONG 0x01 + +#define SPMI_STATUS_DONE 0x1 + +#define SPMI_MAX_CHANNELS 128 +#define SPMI_MAX_SLAVES 16 +#define SPMI_MAX_PERIPH 256 + +struct msm_spmi_priv { + phys_addr_t arb_core; /* ARB Core base */ + phys_addr_t spmi_core; /* SPMI core */ + phys_addr_t spmi_obs; /* SPMI observer */ + /* SPMI channel map */ + uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH]; +}; + +static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off, + uint8_t val) +{ + struct msm_spmi_priv *p = dev_get_priv(dev); + unsigned channel; + uint32_t reg = 0; + + if (usid >= SPMI_MAX_SLAVES) + return -EIO; + if (pid >= SPMI_MAX_PERIPH) + return -EIO; + + channel = p->channel_map[usid][pid]; + + /* Disable IRQ mode for the current channel*/ + writel(0x0, p->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG); + + /* Write single byte */ + writel(val, p->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA); + + /* Prepare write command */ + reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT; + reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT); + reg |= (pid << SPMI_CMD_ADDR_SHIFT); + reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT); + reg |= 1; /* byte count */ + + /* Send write command */ + writel(reg, p->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0); + + /* Wait till CMD DONE status */ + reg = 0; + while (!reg) { + reg = readl(p->spmi_core + SPMI_CH_OFFSET(channel) + + SPMI_REG_STATUS); + } + + if (reg ^ SPMI_STATUS_DONE) { + printf("SPMI write failure.\n"); + return -EIO; + } + + return 0; +} + +static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off) +{ + struct msm_spmi_priv *p = dev_get_priv(dev); + unsigned channel; + uint32_t reg = 0; + + if (usid >= SPMI_MAX_SLAVES) + return -EIO; + if (pid >= SPMI_MAX_PERIPH) + return -EIO; + + channel = p->channel_map[usid][pid]; + + /* Disable IRQ mode for the current channel*/ + writel(0x0, p->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG); + + /* Prepare read command */ + reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT; + reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT); + reg |= (pid << SPMI_CMD_ADDR_SHIFT); + reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT); + reg |= 1; /* byte count */ + + /* Request read */ + writel(reg, p->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0); + + /* Wait till CMD DONE status */ + reg = 0; + while (!reg) { + reg = readl(p->spmi_obs + SPMI_CH_OFFSET(channel) + + SPMI_REG_STATUS); + } + + if (reg ^ SPMI_STATUS_DONE) { + printf("SPMI read failure.\n"); + return -EIO; + } + + /* Read the data */ + return readl(p->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_RDATA) & + 0xFF; +} + +static struct dm_spmi_ops msm_spmi_ops = { + .read = msm_spmi_read, + .write = msm_spmi_write, +}; + +static int msm_spmi_probe(struct udevice *dev) +{ + struct msm_spmi_priv *priv = dev_get_priv(dev); + int i; + + priv->arb_core = dev_get_addr(dev); + priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, + dev->parent->of_offset, + dev->of_offset, "reg", + 1, NULL); + priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, + dev->parent->of_offset, + dev->of_offset, "reg", + 2, NULL); + + /* Scan peripherals connected to each SPMI channel */ + for (i = 0; i < SPMI_MAX_CHANNELS ; i++) { + uint32_t periph = readl(priv->arb_core + ARB_CHANNEL_OFFSET(i)); + uint8_t slave_id = (periph & 0xf0000) >> 16; + uint8_t pid = (periph & 0xff00) >> 8; + + priv->channel_map[slave_id][pid] = i; + } + return 0; +} + +static const struct udevice_id msm_spmi_ids[] = { + { .compatible = "qcom,spmi-pmic-arb" }, + { } +}; + +U_BOOT_DRIVER(msm_spmi) = { + .name = "msm_spmi", + .id = UCLASS_SPMI, + .of_match = msm_spmi_ids, + .ops = &msm_spmi_ops, + .probe = msm_spmi_probe, + .priv_auto_alloc_size = sizeof(struct msm_spmi_priv), +};

This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification. Features (present out of the box): - 4x Cortex A53 (ARMv8) - 2x USB Host port - 1x USB Device port - 4x LEDs - 1x HDMI connector - 1x uSD connector - 3x buttons (Power, Vol+, Vol-/Reset) - WIFI, Bluetooth with integrated antenna - 8GiB eMMC

U-Boot boots chained with fastboot in 64-bit mode. For detailed build instructions see readme.txt in board directory.

This is code is cleaned-up version of code I did last month that is already used by some people: https://github.com/hallor/u-boot

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com ---

arch/arm/dts/Makefile | 2 + arch/arm/dts/dragonboard410c.dts | 157 +++++++++++++++++++ arch/arm/mach-snapdragon/Kconfig | 9 ++ board/qualcomm/dragonboard410c/Kconfig | 15 ++ board/qualcomm/dragonboard410c/Makefile | 8 + board/qualcomm/dragonboard410c/dragonboard410c.c | 111 ++++++++++++++ board/qualcomm/dragonboard410c/head.S | 20 +++ board/qualcomm/dragonboard410c/readme.txt | 40 +++++ board/qualcomm/dragonboard410c/u-boot.lds | 90 +++++++++++ configs/dragonboard410c_defconfig | 29 ++++ include/configs/dragonboard410c.h | 184 +++++++++++++++++++++++ 11 files changed, 665 insertions(+) create mode 100644 arch/arm/dts/dragonboard410c.dts create mode 100644 board/qualcomm/dragonboard410c/Kconfig create mode 100644 board/qualcomm/dragonboard410c/Makefile create mode 100644 board/qualcomm/dragonboard410c/dragonboard410c.c create mode 100644 board/qualcomm/dragonboard410c/head.S create mode 100644 board/qualcomm/dragonboard410c/readme.txt create mode 100644 board/qualcomm/dragonboard410c/u-boot.lds create mode 100644 configs/dragonboard410c_defconfig create mode 100644 include/configs/dragonboard410c.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 521aa4c..1154993 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -95,6 +95,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \ fsl-ls1043a-rdb.dtb

+dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb + dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts new file mode 100644 index 0000000..04ad9eb --- /dev/null +++ b/arch/arm/dts/dragonboard410c.dts @@ -0,0 +1,157 @@ +/dts-v1/; + +#include "skeleton64.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Dragonboard 410c"; + compatible = "qcom,dragonboard", "qcom,apq8016-sbc"; + qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>; + qcom,board-id = <0x10018 0x0>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x3da00000>; + }; + + chosen { + stdout-path = "/soc/serial@78b0000"; + }; + + + soc { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0x0 0xffffffff>; + compatible = "simple-bus"; + + clkc: qcom,gcc@1800000 { + compatible = "qcom,gcc-msm8916"; + reg = <0x1800000 0x80000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4"; + reg = <0x78b0000 0x200>; + u-boot,dm-pre-reloc; + clock = <&clkc 4>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; + + soc_gpios: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x1000000 0x300000>; + gpio-controller; + gpio-count = <122>; + gpio-bank-name="soc"; + #gpio-cells = <1>; + }; + + ehci@78d9000 { + compatible = "qcom,ehci-host"; + reg = <0x78d9000 0x400>; + }; + + sdhci@07824000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7824900 0x11c 0x7824000 0x800>; + bus-width = <0x8>; + index = <0x0>; + non-removable; + clock = <&clkc 0>; + clock-frequency = <100000000>; + }; + + sdhci@07864000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7864900 0x11c 0x7864000 0x800>; + index = <0x1>; + bus-width = <0x4>; + clock = <&clkc 1>; + clock-frequency = <200000000>; + }; + + spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000 0x2400000 0x400000 0x2c00000 0x400000 0x3800000 0x200000 0x200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + #address-cells = <0x1>; + #size-cells = <0x1>; + pm8916@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x2>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + pmic_pon: pon@800 { + compatible = "qcom,pm8916-pwrkey"; + reg = <0x800 0x96>; + #gpio-cells = <2>; + gpio-controller; + }; + + pmic_gpios: gpios@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000 0x400>; + gpio-controller; + gpio-count = <4>; + #gpio-cells = <2>; + gpio-bank-name="pmic"; + }; + }; + + pm8916@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + user1 { + label = "green:user1"; + gpios = <&soc_gpios 21 0>; + }; + + user2 { + label = "green:user2"; + gpios = <&soc_gpios 120 0>; + }; + + user3 { + label = "green:user3"; + gpios = <&pmic_gpios 0 0>; + }; + + user4 { + label = "green:user4"; + gpios = <&pmic_gpios 1 0>; + }; + }; + + usb_hub_reset_n_pm { + gpios = <&pmic_gpios 2 0>; + }; + + usb_sw_sel_pm { + gpios = <&pmic_gpios 3 0>; + }; + + key_vol_down { + gpios = <&pmic_pon 1 0>; + }; + + key_power { + gpios = <&pmic_pon 0 0>; + }; +}; diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 156e733..61e0e9e 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -3,4 +3,13 @@ if ARCH_SNAPDRAGON config SYS_SOC default "snapdragon"

+choice + prompt "Snapdragon board select" + +config TARGET_DRAGONBOARD410C + bool "96Boards Dragonboard 410C" +endchoice + +source "board/qualcomm/dragonboard410c/Kconfig" + endif diff --git a/board/qualcomm/dragonboard410c/Kconfig b/board/qualcomm/dragonboard410c/Kconfig new file mode 100644 index 0000000..03bd7ae --- /dev/null +++ b/board/qualcomm/dragonboard410c/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DRAGONBOARD410C + +config SYS_BOARD + default "dragonboard410c" + +config SYS_VENDOR + default "qualcomm" + +config SYS_SOC + default "apq8016" + +config SYS_CONFIG_NAME + default "dragonboard410c" + +endif diff --git a/board/qualcomm/dragonboard410c/Makefile b/board/qualcomm/dragonboard410c/Makefile new file mode 100644 index 0000000..cd67808 --- /dev/null +++ b/board/qualcomm/dragonboard410c/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := dragonboard410c.o +extra-y += head.o diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c new file mode 100644 index 0000000..7057a2c --- /dev/null +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -0,0 +1,111 @@ +/* + * Board init file for Dragonboard 410C + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <usb.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +static struct gpio_desc hub_reset, usb_sel; + +int board_prepare_usb(enum usb_init_type type) +{ + int ret = 0, node; + + /* Try to request gpios needed to start usb host on dragonboard */ + if (!dm_gpio_is_valid(&hub_reset)) { + node = fdt_subnode_offset(gd->fdt_blob, 0, + "usb_hub_reset_n_pm"); + if (node < 0) { + printf("Failed to find usb_hub_reset_n_pm dt node.\n"); + return node; + } + ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, + &hub_reset, 0); + if (ret < 0) { + printf("Failed to request usb_hub_reset_n_pm gpio.\n"); + return ret; + } + } + + if (!dm_gpio_is_valid(&usb_sel)) { + node = fdt_subnode_offset(gd->fdt_blob, 0, "usb_sw_sel_pm"); + if (node < 0) { + printf("Failed to find usb_sw_sel_pm dt node.\n"); + return 0; + } + ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, + &usb_sel, 0); + if (ret < 0) { + printf("Failed to request usb_sw_sel_pm gpio.\n"); + return ret; + } + } + + if (type == USB_INIT_HOST) { + /* Start USB Hub */ + dm_gpio_set_dir_flags(&hub_reset, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + mdelay(100); + /* Switch usb to host connectors */ + dm_gpio_set_dir_flags(&usb_sel, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + mdelay(100); + } else { /* Device */ + /* Disable hub */ + dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT); + /* Switch back to device connector */ + dm_gpio_set_dir_flags(&usb_sel, GPIOD_IS_OUT); + } + return 0; +} + +int board_init(void) +{ + return 0; +} + +/* Check for vol- button - if pressed - stop autoboot */ +int misc_init_r(void) +{ + int node; + struct gpio_desc resin; + + node = fdt_subnode_offset(gd->fdt_blob, 0, "key_vol_down"); + if (node < 0) { + printf("Failed to find key_vol_down node. Check device tree\n"); + return 0; + } + + if (gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, &resin, + 0)) { + printf("Failed to request key_vol_down button.\n"); + return 0; + } + + if (dm_gpio_get_value(&resin)) { + setenv("bootdelay", "-1"); + printf("Power button pressed - dropping to console.\n"); + } + + return 0; +} diff --git a/board/qualcomm/dragonboard410c/head.S b/board/qualcomm/dragonboard410c/head.S new file mode 100644 index 0000000..00d6d97 --- /dev/null +++ b/board/qualcomm/dragonboard410c/head.S @@ -0,0 +1,20 @@ +#include <config.h> + +.global _fastboot_header +_fastboot_header: + b _start + add x13, x18, #0x16 + // Image load offset from start of RAM, little-endian + .quad CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1 + // Effective size of kernel image, little-endian + .quad 0 //0x60000 + // Informative flags, little-endian + .quad 0 + .quad 0 // reserved + .quad 0 // reserved + .quad 0 // reserved + .byte 0x41 // Magic number, "ARM\x64" + .byte 0x52 + .byte 0x4d + .byte 0x64 + .word 0 // reserved diff --git a/board/qualcomm/dragonboard410c/readme.txt b/board/qualcomm/dragonboard410c/readme.txt new file mode 100644 index 0000000..0f575db --- /dev/null +++ b/board/qualcomm/dragonboard410c/readme.txt @@ -0,0 +1,40 @@ +# +# (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Build & Run instructions: + +1) Install mkbootimg from git://codeaurora.org/quic/kernel/skales (15ece94f09 worked for me) +2) Setup CROSS_COMPILE to aarch64 compiler +3) make dragonboard410c_config +4) make +5) generate fake, empty ramdisk (can have 0 bytes) +$ touch rd + +6) generate qualcomm device tree, use dtbTool to generate it +$ dtbTool -o dt.img arch/arm/dts + +7) generate image with mkbootimg: +$ mkbootimg --kernel=u-boot-dtb.bin --output=u-boot.img --dt=dt.img --pagesize 2048 --base 0x80000000 --ramdisk=rd --cmdline="" + +Boot it with fastboot: +fastboot boot u-boot.img +or flash as kernel: +fastboot flash boot u-boot.img +fastboot reboot + + +What is working: +- UART +- GPIO (SoC) +- SD +- eMMC +- Reset +- USB in EHCI mode (usb starts does switch device->host, usb stop does the opposite) +- PMIC GPIOS (but not in generic subsystem) +- PMIC "special" buttons (power, vol-) + +What is not working / known bugs: +- SDHCI is slow (~2.5MiB/s for SD and eMMC) diff --git a/board/qualcomm/dragonboard410c/u-boot.lds b/board/qualcomm/dragonboard410c/u-boot.lds new file mode 100644 index 0000000..3fb4235 --- /dev/null +++ b/board/qualcomm/dragonboard410c/u-boot.lds @@ -0,0 +1,90 @@ +/* + * Override linker script for fastboot-readable images + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_fastboot_header) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(8); + .text : + { + *(.__image_copy_start) + board/qualcomm/dragonboard410c/head.o (.text*) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(8); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(8); + .data : { + *(.data*) + } + + . = ALIGN(8); + + . = .; + + . = ALIGN(8); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(8); + + .image_copy_end : + { + *(.__image_copy_end) + } + + . = ALIGN(8); + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rela.dyn : { + *(.rela*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + . = ALIGN(8); + + .bss_start : { + KEEP(*(.__bss_start)); + } + + .bss : { + *(.bss*) + . = ALIGN(8); + } + + .bss_end : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig new file mode 100644 index 0000000..7dd9aae --- /dev/null +++ b/configs/dragonboard410c_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_ARM64=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_TARGET_DRAGONBOARD410C=y + +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="dragonboard410c => " +CONFIG_CMD_USB=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c" + +CONFIG_CLK=y +CONFIG_MSM_GPIO=y +CONFIG_PM8916_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_RESET=y +CONFIG_DM_MMC=y +CONFIG_MSM_SDHCI=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PM8916=y +CONFIG_SPMI_MSM=y +CONFIG_MSM_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h new file mode 100644 index 0000000..132ed75 --- /dev/null +++ b/include/configs/dragonboard410c.h @@ -0,0 +1,184 @@ +/* + * Board configuration file for Dragonboard 410C + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIGS_DRAGONBOARD410C_H +#define __CONFIGS_DRAGONBOARD410C_H + +#include <linux/sizes.h> +#include <asm/arch/sysmap-apq8016.h> + +#define CONFIG_IDENT_STRING "\nQualcomm-DragonBoard 410C" + +#define CONFIG_MISC_INIT_R /* To stop autoboot */ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x80000000 +/* 1008 MB (the last ~30Mb are secured for TrustZone by ATF*/ +#define PHYS_SDRAM_1_SIZE 0x3da00000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_TEXT_BASE 0x80080000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */ + +/* UART */ +#define CONFIG_BAUDRATE 115200 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 19000000 + +/* This are needed to have proper mmc support */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI + +#define CONFIG_SYS_LDSCRIPT "board/qualcomm/dragonboard410c/u-boot.lds" + +/* Fixup - in init code we switch from device to host mode, + * it has to be done after each HCD reset */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +/* Needed for Host Controller driver */ +#define CONFIG_USB_ULPI_VIEWPORT + +#define CONFIG_USB_HOST_ETHER /* Enable USB Networking */ + +/* Support all possible USB ethernet dongles */ +#define CONFIG_USB_ETHER_DM9601 +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_ASIX88179 +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX + +/* Libraries */ +#define CONFIG_MD5 + +/* Extra Commands */ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GPT +#define CONFIG_CMD_MD5SUM +#define CONFIG_CMD_MEMINFO /* meminfo */ +#define CONFIG_CMD_MMC +/* Enable that for switching of boot partitions */ +/* Disabled by default as some sub-commands can brick eMMC */ +/*#define CONFIG_SUPPORT_EMMC_BOOT */ +#define CONFIG_CMD_PART +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO /* Register dump */ +#define CONFIG_CMD_TFTP +#define CONFIG_CMD_TIMER +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_BOOTI + +/* Command line configuration */ +#define CONFIG_MENU +#define CONFIG_SYS_LONGHELP + +/* Partition table support */ +#define HAVE_BLOCK_DEVICE /* Needed for partition commands */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Environment - Boot*/ +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ + +#define CONFIG_NFSBOOTCOMMAND "" +#define CONFIG_BOOTCOMMAND "usb start && dhcp && tftp && usb stop && bootm" +#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8" + +/* Does what recovery does */ +#define REFLASH(file, part) \ +"part start mmc 0 "#part" start && "\ +"part size mmc 0 "#part" size && "\ +"tftp $loadaddr "#file" &&" \ +"mmc write $loadaddr $start $size &&" + + +#define CONFIG_ENV_REFLASH \ +"mmc dev 0 &&"\ +"usb start &&"\ +"dhcp &&"\ +"tftp $loadaddr dragonboard/rescue/gpt_both0.bin && "\ +"mmc write $loadaddr 0 43 &&" \ +"mmc rescan &&"\ +REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)\ +REFLASH(dragonboard/rescue/sbl1.mbn, 2)\ +REFLASH(dragonboard/rescue/rpm.mbn, 3)\ +REFLASH(dragonboard/rescue/tz.mbn, 4)\ +REFLASH(dragonboard/rescue/hyp.mbn, 5)\ +REFLASH(dragonboard/rescue/sec.dat, 6)\ +REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)\ +REFLASH(dragonboard/u-boot.img, 8)\ +"usb stop &&"\ +"echo Reflash completed" + +#define CONFIG_UBOOT_REFLASH \ +"mmc dev 0 &&"\ +"usb start &&"\ +"dhcp &&"\ +"part start mmc 0 8 start && "\ +"setenv size 0x800 &&"\ +"tftp $loadaddr dragonboard/u-boot.img &&" \ +"mmc write $loadaddr $start $size &&"\ +"usb stop &&"\ +"echo Reflash completed &&" \ +"reset" + +/* Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "reflash="CONFIG_ENV_REFLASH"\0"\ + "reflash_uboot="CONFIG_UBOOT_REFLASH"\0"\ + "loadaddr=0x81000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "linux_image=dragonboard/Image\0" \ + "linux_addr=0x81000000\0"\ + "fdt_image=dragonboard/apq8016-sbc.dtb\0" \ + "fdt_addr=0x83000000\0"\ + "ramdisk_addr=0x84000000\0"\ + "ramdisk_image=dragonboard/initrd.img\0" \ + "dl_uboot=tftp $loadaddr dragonboard/u-boot.img\0"\ + "dl_kernel=tftp $linux_addr $linux_image " \ + "&& tftp $fdt_addr $fdt_image\0"\ + "dl_ramdisk=tftp $ramdisk_addr $ramdisk_image\0"\ + "nboot_nord=usb start && run dl_kernel && usb stop && " \ + "booti $linux_addr - $fdt_addr\0"\ + "nboot_rd=usb start && run dl_kernel && run dl_ramdisk && "\ + "booti $linux_addr $ramdisk_addr $fdt_addr\0" + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_SYS_NO_FLASH + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + + +#endif