From: Patrice Chotard patrice.chotard@st.com

Use the same clocks macro than the one used by kernel DT.

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- arch/arm/dts/stm32f746.dtsi | 30 ++++---- include/dt-bindings/clock/stm32fx-clock.h | 59 ++++++++++++++++ include/dt-bindings/mfd/stm32f7-rcc.h | 112 ++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+), 14 deletions(-) create mode 100644 include/dt-bindings/clock/stm32fx-clock.h create mode 100644 include/dt-bindings/mfd/stm32f7-rcc.h

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 54f5bc7..783d4e7 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -47,6 +47,8 @@

#include "armv7-m.dtsi" #include <dt-bindings/pinctrl/stm32f746-pinfunc.h> +#include <dt-bindings/clock/stm32fx-clock.h> +#include <dt-bindings/mfd/stm32f7-rcc.h>

/ { clocks { @@ -74,7 +76,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; reg = <0xA0000000 0x1000>; - clocks = <&rcc 0 64>; + clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; u-boot,dm-pre-reloc; };

@@ -86,14 +88,14 @@ reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = <92>; spi-max-frequency = <108000000>; - clocks = <&rcc 0 65>; + clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; status = "disabled"; }; usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; - clocks = <&rcc 0 164>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; status = "disabled"; u-boot,dm-pre-reloc; }; @@ -119,7 +121,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x0 0x400>; - clocks = <&rcc 0 0>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; st,bank-name = "GPIOA"; u-boot,dm-pre-reloc; }; @@ -129,7 +131,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x400 0x400>; - clocks = <&rcc 0 1>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; st,bank-name = "GPIOB"; u-boot,dm-pre-reloc; }; @@ -140,7 +142,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x800 0x400>; - clocks = <&rcc 0 2>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; st,bank-name = "GPIOC"; u-boot,dm-pre-reloc; }; @@ -150,7 +152,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0xc00 0x400>; - clocks = <&rcc 0 3>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; st,bank-name = "GPIOD"; u-boot,dm-pre-reloc; }; @@ -160,7 +162,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x1000 0x400>; - clocks = <&rcc 0 4>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; st,bank-name = "GPIOE"; u-boot,dm-pre-reloc; }; @@ -170,7 +172,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x1400 0x400>; - clocks = <&rcc 0 5>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; st,bank-name = "GPIOF"; u-boot,dm-pre-reloc; }; @@ -180,7 +182,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x1800 0x400>; - clocks = <&rcc 0 6>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; st,bank-name = "GPIOG"; u-boot,dm-pre-reloc; }; @@ -190,7 +192,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x1c00 0x400>; - clocks = <&rcc 0 7>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; st,bank-name = "GPIOH"; u-boot,dm-pre-reloc; }; @@ -200,7 +202,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x2000 0x400>; - clocks = <&rcc 0 8>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; st,bank-name = "GPIOI"; u-boot,dm-pre-reloc; }; @@ -210,7 +212,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x2400 0x400>; - clocks = <&rcc 0 9>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; st,bank-name = "GPIOJ"; u-boot,dm-pre-reloc; }; @@ -220,7 +222,7 @@ #gpio-cells = <2>; compatible = "st,stm32-gpio"; reg = <0x2800 0x400>; - clocks = <&rcc 0 10>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; st,bank-name = "GPIOK"; u-boot,dm-pre-reloc; }; diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h new file mode 100644 index 0000000..49bb3c2 --- /dev/null +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -0,0 +1,59 @@ +/* + * stm32fx-clock.h + * + * Copyright (C) 2016 STMicroelectronics + * Author: Gabriel Fernandez for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +/* + * List of clocks wich are not derived from system clock (SYSCLOCK) + * + * The index of these clocks is the secondary index of DT bindings + * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) + * + * e.g: + <assigned-clocks = <&rcc 1 CLK_LSE>; +*/ + +#ifndef _DT_BINDINGS_CLK_STMFX_H +#define _DT_BINDINGS_CLK_STMFX_H + +#define SYSTICK 0 +#define FCLK 1 +#define CLK_LSI 2 +#define CLK_LSE 3 +#define CLK_HSE_RTC 4 +#define CLK_RTC 5 +#define PLL_VCO_I2S 6 +#define PLL_VCO_SAI 7 +#define CLK_LCD 8 +#define CLK_I2S 9 +#define CLK_SAI1 10 +#define CLK_SAI2 11 +#define CLK_I2SQ_PDIV 12 +#define CLK_SAIQ_PDIV 13 + +#define END_PRIMARY_CLK 14 + +#define CLK_HSI 14 +#define CLK_SYSCLK 15 +#define CLK_HDMI_CEC 16 +#define CLK_SPDIF 17 +#define CLK_USART1 18 +#define CLK_USART2 19 +#define CLK_USART3 20 +#define CLK_UART4 21 +#define CLK_UART5 22 +#define CLK_USART6 23 +#define CLK_UART7 24 +#define CLK_UART8 25 +#define CLK_I2C1 26 +#define CLK_I2C2 27 +#define CLK_I2C3 28 +#define CLK_I2C4 29 +#define CLK_LPTIMER 30 + +#define END_PRIMARY_CLK_F7 31 + +#endif diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h new file mode 100644 index 0000000..e36cc69 --- /dev/null +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -0,0 +1,112 @@ +/* + * This header provides constants for the STM32F7 RCC IP + */ + +#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H +#define _DT_BINDINGS_MFD_STM32F7_RCC_H + +/* AHB1 */ +#define STM32F7_RCC_AHB1_GPIOA 0 +#define STM32F7_RCC_AHB1_GPIOB 1 +#define STM32F7_RCC_AHB1_GPIOC 2 +#define STM32F7_RCC_AHB1_GPIOD 3 +#define STM32F7_RCC_AHB1_GPIOE 4 +#define STM32F7_RCC_AHB1_GPIOF 5 +#define STM32F7_RCC_AHB1_GPIOG 6 +#define STM32F7_RCC_AHB1_GPIOH 7 +#define STM32F7_RCC_AHB1_GPIOI 8 +#define STM32F7_RCC_AHB1_GPIOJ 9 +#define STM32F7_RCC_AHB1_GPIOK 10 +#define STM32F7_RCC_AHB1_CRC 12 +#define STM32F7_RCC_AHB1_BKPSRAM 18 +#define STM32F7_RCC_AHB1_DTCMRAM 20 +#define STM32F7_RCC_AHB1_DMA1 21 +#define STM32F7_RCC_AHB1_DMA2 22 +#define STM32F7_RCC_AHB1_DMA2D 23 +#define STM32F7_RCC_AHB1_ETHMAC 25 +#define STM32F7_RCC_AHB1_ETHMACTX 26 +#define STM32F7_RCC_AHB1_ETHMACRX 27 +#define STM32FF_RCC_AHB1_ETHMACPTP 28 +#define STM32F7_RCC_AHB1_OTGHS 29 +#define STM32F7_RCC_AHB1_OTGHSULPI 30 + +#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) +#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) + + +/* AHB2 */ +#define STM32F7_RCC_AHB2_DCMI 0 +#define STM32F7_RCC_AHB2_CRYP 4 +#define STM32F7_RCC_AHB2_HASH 5 +#define STM32F7_RCC_AHB2_RNG 6 +#define STM32F7_RCC_AHB2_OTGFS 7 + +#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) +#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) + +/* AHB3 */ +#define STM32F7_RCC_AHB3_FMC 0 +#define STM32F7_RCC_AHB3_QSPI 1 + +#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) +#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) + +/* APB1 */ +#define STM32F7_RCC_APB1_TIM2 0 +#define STM32F7_RCC_APB1_TIM3 1 +#define STM32F7_RCC_APB1_TIM4 2 +#define STM32F7_RCC_APB1_TIM5 3 +#define STM32F7_RCC_APB1_TIM6 4 +#define STM32F7_RCC_APB1_TIM7 5 +#define STM32F7_RCC_APB1_TIM12 6 +#define STM32F7_RCC_APB1_TIM13 7 +#define STM32F7_RCC_APB1_TIM14 8 +#define STM32F7_RCC_APB1_LPTIM1 9 +#define STM32F7_RCC_APB1_WWDG 11 +#define STM32F7_RCC_APB1_SPI2 14 +#define STM32F7_RCC_APB1_SPI3 15 +#define STM32F7_RCC_APB1_SPDIFRX 16 +#define STM32F7_RCC_APB1_UART2 17 +#define STM32F7_RCC_APB1_UART3 18 +#define STM32F7_RCC_APB1_UART4 19 +#define STM32F7_RCC_APB1_UART5 20 +#define STM32F7_RCC_APB1_I2C1 21 +#define STM32F7_RCC_APB1_I2C2 22 +#define STM32F7_RCC_APB1_I2C3 23 +#define STM32F7_RCC_APB1_I2C4 24 +#define STM32F7_RCC_APB1_CAN1 25 +#define STM32F7_RCC_APB1_CAN2 26 +#define STM32F7_RCC_APB1_CEC 27 +#define STM32F7_RCC_APB1_PWR 28 +#define STM32F7_RCC_APB1_DAC 29 +#define STM32F7_RCC_APB1_UART7 30 +#define STM32F7_RCC_APB1_UART8 31 + +#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) +#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) + +/* APB2 */ +#define STM32F7_RCC_APB2_TIM1 0 +#define STM32F7_RCC_APB2_TIM8 1 +#define STM32F7_RCC_APB2_USART1 4 +#define STM32F7_RCC_APB2_USART6 5 +#define STM32F7_RCC_APB2_ADC1 8 +#define STM32F7_RCC_APB2_ADC2 9 +#define STM32F7_RCC_APB2_ADC3 10 +#define STM32F7_RCC_APB2_SDMMC1 11 +#define STM32F7_RCC_APB2_SPI1 12 +#define STM32F7_RCC_APB2_SPI4 13 +#define STM32F7_RCC_APB2_SYSCFG 14 +#define STM32F7_RCC_APB2_TIM9 16 +#define STM32F7_RCC_APB2_TIM10 17 +#define STM32F7_RCC_APB2_TIM11 18 +#define STM32F7_RCC_APB2_SPI5 20 +#define STM32F7_RCC_APB2_SPI6 21 +#define STM32F7_RCC_APB2_SAI1 22 +#define STM32F7_RCC_APB2_SAI2 23 +#define STM32F7_RCC_APB2_LTDC 26 + +#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) +#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) + +#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */

From: Patrice Chotard patrice.chotard@st.com

Also remove its declaration from stm32.h which is no more needed.

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- arch/arm/include/asm/arch-stm32f7/stm32.h | 1 - drivers/clk/clk_stm32f7.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index 14e3398..d4c834e 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -114,7 +114,6 @@ struct stm32_pwr_regs { }; #define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)

-int configure_clocks(void); unsigned long clock_get(enum clock clck); void stm32_flash_latency_cfg(int latency);

diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index fcdc3c0..aff8ad3 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -104,7 +104,7 @@ struct pll_psc sys_pll_psc = { #endif #endif

-int configure_clocks(void) +static int configure_clocks(void) { /* Reset RCC configuration */ setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);

From: Patrice Chotard patrice.chotard@st.com

Retrieve RCC base address from DT, this will prepare the ground for future STM32 SoCs support.

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- drivers/clk/clk_stm32f7.c | 57 +++++++++++++++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 19 deletions(-)

diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index aff8ad3..7dd91b6 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -83,6 +83,10 @@ struct pll_psc { #define APB_PSC_8 0x6 #define APB_PSC_16 0x7

+struct stm32_clk { + struct stm32_rcc_regs *base; +}; + #if !defined(CONFIG_STM32_HSE_HZ) #error "CONFIG_STM32_HSE_HZ not defined!" #else @@ -104,23 +108,26 @@ struct pll_psc sys_pll_psc = { #endif #endif

-static int configure_clocks(void) +static int configure_clocks(struct udevice *dev) { + struct stm32_clk *priv = dev_get_priv(dev); + struct stm32_rcc_regs *regs = priv->base; + /* Reset RCC configuration */ - setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); - writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ - clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON + setbits_le32(&regs->cr, RCC_CR_HSION); + writel(0, &regs->cfgr); /* Reset CFGR */ + clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON)); - writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */ - clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); - writel(0, &STM32_RCC->cir); /* Disable all interrupts */ + writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */ + clrbits_le32(&regs->cr, RCC_CR_HSEBYP); + writel(0, &regs->cir); /* Disable all interrupts */

/* Configure for HSE+PLL operation */ - setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); - while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) + setbits_le32(&regs->cr, RCC_CR_HSEON); + while (!(readl(&regs->cr) & RCC_CR_HSERDY)) ;

- setbits_le32(&STM32_RCC->cfgr, (( + setbits_le32(&regs->cfgr, (( sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); @@ -132,15 +139,15 @@ static int configure_clocks(void) pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; - writel(pllcfgr, &STM32_RCC->pllcfgr); + writel(pllcfgr, &regs->pllcfgr);

/* Enable the main PLL */ - setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); - while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) + setbits_le32(&regs->cr, RCC_CR_PLLON); + while (!(readl(&regs->cr) & RCC_CR_PLLRDY)) ;

/* Enable high performance mode, System frequency up to 200 MHz */ - setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); + setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN); setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN); /* Infinite wait! */ while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY)) @@ -152,10 +159,10 @@ static int configure_clocks(void) ;

stm32_flash_latency_cfg(5); - clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); - setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); + clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); + setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);

- while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != + while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) ;

@@ -215,12 +222,14 @@ unsigned long clock_get(enum clock clck)

static int stm32_clk_enable(struct clk *clk) { + struct stm32_clk *priv = dev_get_priv(clk->dev); + struct stm32_rcc_regs *regs = priv->base; u32 offset = clk->id / 32; u32 bit_index = clk->id % 32;

debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", __func__, clk->id, offset, bit_index); - setbits_le32(&STM32_RCC->ahb1enr + offset, BIT(bit_index)); + setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));

return 0; } @@ -247,7 +256,17 @@ void clock_setup(int peripheral) static int stm32_clk_probe(struct udevice *dev) { debug("%s: stm32_clk_probe\n", __func__); - configure_clocks(); + + struct stm32_clk *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (struct stm32_rcc_regs *)addr; + + configure_clocks(dev);

return 0; }

From: Patrice Chotard patrice.chotard@st.com

Add clock framework .get_rate callback. This step will allow to convert all drivers which was using proprietary clock_get() to use clock framework .get_rate().

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- arch/arm/include/asm/arch-stm32f7/rcc.h | 2 ++ drivers/clk/clk_stm32f7.c | 62 +++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+)

diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h index 0f8d50b..cc9b57f 100644 --- a/arch/arm/include/asm/arch-stm32f7/rcc.h +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h @@ -8,6 +8,8 @@ #ifndef _STM32_RCC_H #define _STM32_RCC_H

+#include <dt-bindings/mfd/stm32f7-rcc.h> + /* * RCC AHB1ENR specific definitions */ diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index 7dd91b6..5e20b0c 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -12,6 +12,8 @@ #include <asm/arch/stm32.h> #include <asm/arch/stm32_periph.h>

+#include <dt-bindings/mfd/stm32f7-rcc.h> + #define RCC_CR_HSION BIT(0) #define RCC_CR_HSEON BIT(16) #define RCC_CR_HSERDY BIT(17) @@ -220,6 +222,65 @@ unsigned long clock_get(enum clock clck) } }

+static unsigned long stm32_clk_get_rate(struct clk *clk) +{ + struct stm32_clk *priv = dev_get_priv(clk->dev); + struct stm32_rcc_regs *regs = priv->base; + u32 sysclk = 0; + u32 shift = 0; + /* Prescaler table lookups for clock computation */ + u8 ahb_psc_table[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 + }; + u8 apb_psc_table[8] = { + 0, 0, 0, 0, 1, 2, 3, 4 + }; + + if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) == + RCC_CFGR_SWS_PLL) { + u16 pllm, plln, pllp; + pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); + plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) + >> RCC_PLLCFGR_PLLN_SHIFT); + pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) + >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); + sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; + } else { + return -EINVAL; + } + + switch (clk->id) { + /* + * AHB CLOCK: 3 x 32 bits consecutive registers are used : + * AHB1, AHB2 and AHB3 + */ + case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI): + shift = ahb_psc_table[( + (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) + >> RCC_CFGR_HPRE_SHIFT)]; + return sysclk >>= shift; + break; + /* APB1 CLOCK */ + case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): + shift = apb_psc_table[( + (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK) + >> RCC_CFGR_PPRE1_SHIFT)]; + return sysclk >>= shift; + break; + /* APB2 CLOCK */ + case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): + shift = apb_psc_table[( + (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK) + >> RCC_CFGR_PPRE2_SHIFT)]; + return sysclk >>= shift; + break; + default: + error("clock index %ld out of range\n", clk->id); + return -EINVAL; + break; + } +} + static int stm32_clk_enable(struct clk *clk) { struct stm32_clk *priv = dev_get_priv(clk->dev); @@ -291,6 +352,7 @@ static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) static struct clk_ops stm32_clk_ops = { .of_xlate = stm32_clk_of_xlate, .enable = stm32_clk_enable, + .get_rate = stm32_clk_get_rate, };

static const struct udevice_id stm32_clk_ids[] = {

From: Patrice Chotard patrice.chotard@st.com

clean the code by removing unused enums, structs and defines related to clocks

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- arch/arm/include/asm/arch-stm32f7/rcc.h | 22 ---------------------- arch/arm/include/asm/arch-stm32f7/stm32.h | 6 ------ arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 15 --------------- drivers/clk/clk_stm32f7.c | 3 --- 4 files changed, 46 deletions(-)

diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h index cc9b57f..a33f8cf 100644 --- a/arch/arm/include/asm/arch-stm32f7/rcc.h +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h @@ -13,41 +13,19 @@ /* * RCC AHB1ENR specific definitions */ -#define RCC_AHB1ENR_GPIO_A_EN BIT(0) -#define RCC_AHB1ENR_GPIO_B_EN BIT(1) -#define RCC_AHB1ENR_GPIO_C_EN BIT(2) -#define RCC_AHB1ENR_GPIO_D_EN BIT(3) -#define RCC_AHB1ENR_GPIO_E_EN BIT(4) -#define RCC_AHB1ENR_GPIO_F_EN BIT(5) -#define RCC_AHB1ENR_GPIO_G_EN BIT(6) -#define RCC_AHB1ENR_GPIO_H_EN BIT(7) -#define RCC_AHB1ENR_GPIO_I_EN BIT(8) -#define RCC_AHB1ENR_GPIO_J_EN BIT(9) -#define RCC_AHB1ENR_GPIO_K_EN BIT(10) #define RCC_AHB1ENR_ETHMAC_EN BIT(25) #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) -#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28) - -/* - * RCC AHB3ENR specific definitions - */ -#define RCC_AHB3ENR_FMC_EN BIT(0) -#define RCC_AHB3ENR_QSPI_EN BIT(1)

/* * RCC APB1ENR specific definitions */ #define RCC_APB1ENR_TIM2EN BIT(0) -#define RCC_APB1ENR_USART2EN BIT(17) -#define RCC_APB1ENR_USART3EN BIT(18) #define RCC_APB1ENR_PWREN BIT(28)

/* * RCC APB2ENR specific definitions */ -#define RCC_APB2ENR_USART1EN BIT(4) -#define RCC_APB2ENR_USART6EN BIT(5) #define RCC_APB2ENR_SYSCFGEN BIT(14)

#endif diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index d4c834e..12efee5 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -58,7 +58,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { };

enum clock { - CLOCK_CORE, CLOCK_AHB, CLOCK_APB1, CLOCK_APB2 @@ -101,11 +100,6 @@ struct stm32_rcc_regs { }; #define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)

-struct stm32_rcc_ext_f7_regs { - u32 dckcfgr2; /* dedicated clocks configuration register */ -}; -#define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs))) - struct stm32_pwr_regs { u32 cr1; /* power control register 1 */ u32 csr1; /* power control/status register 2 */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h index 3c5604a..9c1ec02 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -21,24 +21,9 @@ enum periph_id { };

enum periph_clock { - USART1_CLOCK_CFG = 0, - USART2_CLOCK_CFG, - GPIO_A_CLOCK_CFG, - GPIO_B_CLOCK_CFG, - GPIO_C_CLOCK_CFG, - GPIO_D_CLOCK_CFG, - GPIO_E_CLOCK_CFG, - GPIO_F_CLOCK_CFG, - GPIO_G_CLOCK_CFG, - GPIO_H_CLOCK_CFG, - GPIO_I_CLOCK_CFG, - GPIO_J_CLOCK_CFG, - GPIO_K_CLOCK_CFG, SYSCFG_CLOCK_CFG, TIMER2_CLOCK_CFG, - FMC_CLOCK_CFG, STMMAC_CLOCK_CFG, - QSPI_CLOCK_CFG, };

#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index 5e20b0c..5bc650a 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -195,9 +195,6 @@ unsigned long clock_get(enum clock clck) }

switch (clck) { - case CLOCK_CORE: - return sysclk; - break; case CLOCK_AHB: shift = ahb_psc_table[( (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)

From: Patrice Chotard patrice.chotard@st.com

This allow to remove include/dm/platform_data/serial_stm32x7.h which was included in the past by stm32x7 driver and by stm32f746-disco.c board file. Since patch 42bf5e7c27 "serial: stm32f7: add device tree support" this file is no more needed in board file.

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- board/st/stm32f746-disco/stm32f746-disco.c | 1 - drivers/serial/serial_stm32x7.c | 1 - drivers/serial/serial_stm32x7.h | 5 +++++ include/dm/platform_data/serial_stm32x7.h | 17 ----------------- 4 files changed, 5 insertions(+), 19 deletions(-) delete mode 100644 include/dm/platform_data/serial_stm32x7.h

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index fc4c60c..e3b662b 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -14,7 +14,6 @@ #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> #include <asm/arch/fmc.h> -#include <dm/platform_data/serial_stm32x7.h> #include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_defs.h> #include <asm/arch/syscfg.h> diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index 61e8167..05c73da 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -11,7 +11,6 @@ #include <asm/io.h> #include <serial.h> #include <asm/arch/stm32.h> -#include <dm/platform_data/serial_stm32x7.h> #include "serial_stm32x7.h"

DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h index facfdba..42b05f1 100644 --- a/drivers/serial/serial_stm32x7.h +++ b/drivers/serial/serial_stm32x7.h @@ -22,6 +22,11 @@ struct stm32_usart { u32 tx_dr; };

+/* Information about a serial port */ +struct stm32x7_serial_platdata { + struct stm32_usart *base; /* address of registers in physical memory */ + unsigned int clock; +};

#define USART_CR1_OVER8 (1 << 15) #define USART_CR1_TE (1 << 3) diff --git a/include/dm/platform_data/serial_stm32x7.h b/include/dm/platform_data/serial_stm32x7.h deleted file mode 100644 index 328a8a3..0000000 --- a/include/dm/platform_data/serial_stm32x7.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2016 - * Vikas Manocha, vikas.manocha@st.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SERIAL_STM32x7_H -#define __SERIAL_STM32x7_H - -/* Information about a serial port */ -struct stm32x7_serial_platdata { - struct stm32_usart *base; /* address of registers in physical memory */ - unsigned int clock; -}; - -#endif /* __SERIAL_STM32x7_H */

From: Patrice Chotard patrice.chotard@st.com

Replace proprietary clock_get() by clk_get_rate() The stm32x7 serial driver is now "generic" and can be used by other STM32 SoCs.

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- drivers/serial/serial_stm32x7.c | 17 ++++++++--------- drivers/serial/serial_stm32x7.h | 2 +- 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index 05c73da..bf118a7 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -19,16 +19,9 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate) { struct stm32x7_serial_platdata *plat = dev->platdata; struct stm32_usart *const usart = plat->base; - u32 clock, int_div, mantissa, fraction, oversampling; + u32 int_div, mantissa, fraction, oversampling;

- if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE) - clock = clock_get(CLOCK_APB1); - else if (((u32)usart & STM32_BUS_MASK) == APB2_PERIPH_BASE) - clock = clock_get(CLOCK_APB2); - else - return -EINVAL; - - int_div = DIV_ROUND_CLOSEST(clock, baudrate); + int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);

if (int_div < 16) { oversampling = 8; @@ -101,6 +94,12 @@ static int stm32_serial_probe(struct udevice *dev) } #endif

+ plat->clock_rate = clk_get_rate(&clk); + if (plat->clock_rate < 0) { + clk_disable(&clk); + return plat->clock_rate; + }; + /* Disable usart-> disable overrun-> enable usart */ clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); setbits_le32(&usart->cr3, USART_CR3_OVRDIS); diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h index 42b05f1..9fe37af 100644 --- a/drivers/serial/serial_stm32x7.h +++ b/drivers/serial/serial_stm32x7.h @@ -25,7 +25,7 @@ struct stm32_usart { /* Information about a serial port */ struct stm32x7_serial_platdata { struct stm32_usart *base; /* address of registers in physical memory */ - unsigned int clock; + unsigned long int clock_rate; };

#define USART_CR1_OVER8 (1 << 15)

From: Patrice Chotard patrice.chotard@st.com

Replace proprietary clock_get() by clk_get_rate() The stm32_qspi is now "generic" and can be used by other STM32 SoCs.

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- drivers/spi/stm32_qspi.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index f0434a4..ef2b64e 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -165,6 +165,7 @@ struct stm32_qspi_platdata {

struct stm32_qspi_priv { struct stm32_qspi_regs *regs; + ulong clock_rate; u32 max_hz; u32 mode;

@@ -471,6 +472,13 @@ static int stm32_qspi_probe(struct udevice *bus) dev_err(bus, "failed to enable clock\n"); return ret; } + + priv->clock_rate = clk_get_rate(&clk); + if (priv->clock_rate < 0) { + clk_disable(&clk); + return priv->clock_rate; + } + #endif

setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); @@ -536,7 +544,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed) if (speed > plat->max_hz) speed = plat->max_hz;

- u32 qspi_clk = clock_get(CLOCK_AHB); + u32 qspi_clk = priv->clock_rate; u32 prescaler = 255; if (speed > 0) { prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;

From: Patrice Chotard patrice.chotard@st.com

All drivers which was using clock_get() are now using clk_get_rate() from clock framework, now it's safe to remove clock_get().

Signed-off-by: Patrice Chotard patrice.chotard@st.com Acked-by: Vikas MANOCHA vikas.manocha@st.com --- arch/arm/include/asm/arch-stm32f7/stm32.h | 6 ---- drivers/clk/clk_stm32f7.c | 48 ------------------------------- 2 files changed, 54 deletions(-)

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index 12efee5..87aee60 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -57,11 +57,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [5 ... 7] = 256 * 1024 };

-enum clock { - CLOCK_AHB, - CLOCK_APB1, - CLOCK_APB2 -}; #define STM32_BUS_MASK GENMASK(31, 16)

struct stm32_rcc_regs { @@ -108,7 +103,6 @@ struct stm32_pwr_regs { }; #define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)

-unsigned long clock_get(enum clock clck); void stm32_flash_latency_cfg(int latency);

#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index 5bc650a..255a583 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -171,54 +171,6 @@ static int configure_clocks(struct udevice *dev) return 0; }

-unsigned long clock_get(enum clock clck) -{ - u32 sysclk = 0; - u32 shift = 0; - /* Prescaler table lookups for clock computation */ - u8 ahb_psc_table[16] = { - 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 - }; - u8 apb_psc_table[8] = { - 0, 0, 0, 0, 1, 2, 3, 4 - }; - - if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == - RCC_CFGR_SWS_PLL) { - u16 pllm, plln, pllp; - pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); - plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) - >> RCC_PLLCFGR_PLLN_SHIFT); - pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) - >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); - sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; - } - - switch (clck) { - case CLOCK_AHB: - shift = ahb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) - >> RCC_CFGR_HPRE_SHIFT)]; - return sysclk >>= shift; - break; - case CLOCK_APB1: - shift = apb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) - >> RCC_CFGR_PPRE1_SHIFT)]; - return sysclk >>= shift; - break; - case CLOCK_APB2: - shift = apb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) - >> RCC_CFGR_PPRE2_SHIFT)]; - return sysclk >>= shift; - break; - default: - return 0; - break; - } -} - static unsigned long stm32_clk_get_rate(struct clk *clk) { struct stm32_clk *priv = dev_get_priv(clk->dev);