[U-Boot] [PATCH 1/4] 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields
Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match the 86xx user's manual and other Freescale architectures
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 4 ++-- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 6 +++--- board/sbc8641d/sbc8641d.c | 12 ++++++------ cpu/mpc86xx/ddr-8641.c | 4 ++-- include/asm-ppc/immap_86xx.h | 4 ++-- 5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index a85ebea..419b2c1 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -154,7 +154,7 @@ phys_size_t fixed_sdram(void) ddr->timing_cfg_0 = 0x00260802; ddr->timing_cfg_1 = 0x3935d322; ddr->timing_cfg_2 = 0x14904cc8; - ddr->sdram_mode_1 = 0x00480432; + ddr->sdram_mode = 0x00480432; ddr->sdram_mode_2 = 0x00000000; ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ ddr->sdram_data_init = 0xDEADBEEF; @@ -170,7 +170,7 @@ phys_size_t fixed_sdram(void)
udelay(500);
- ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ + ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 7422e6b..545997c 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -91,7 +91,7 @@ fixed_sdram(void) ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; @@ -109,9 +109,9 @@ fixed_sdram(void)
#if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; #endif asm("sync; isync"); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index c39d2c0..f118a6e 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -127,9 +127,9 @@ long int fixed_sdram (void) ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A; + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A; ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; @@ -140,7 +140,7 @@ long int fixed_sdram (void)
udelay (500);
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B; + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B; asm ("sync; isync");
udelay (500); @@ -158,9 +158,9 @@ long int fixed_sdram (void) ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A; + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A; ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; @@ -171,7 +171,7 @@ long int fixed_sdram (void)
udelay (500);
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B; + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B; asm ("sync; isync");
udelay (500); diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c index 51d0102..b8f2c93 100644 --- a/cpu/mpc86xx/ddr-8641.c +++ b/cpu/mpc86xx/ddr-8641.c @@ -56,7 +56,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); @@ -74,7 +74,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, udelay(200); asm volatile("sync;isync");
- out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg); + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
/* * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index a839834..fdfc654 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -114,9 +114,9 @@ typedef struct ccsr_ddr { uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ - uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ + uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */ uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ - uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ + uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
This is in preparation for adding one common 8xxx board_add_ram_info() fuction for all 8xxx boards
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- board/xes/common/fsl_8xxx_ddr.c | 53 --------------------------------------- 1 files changed, 0 insertions(+), 53 deletions(-)
diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c index ec64efa..81ee70d 100644 --- a/board/xes/common/fsl_8xxx_ddr.c +++ b/board/xes/common/fsl_8xxx_ddr.c @@ -44,56 +44,3 @@ phys_size_t initdram(int board_type)
return dram_size; } - -#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1) -void board_add_ram_info(int use_default) -{ -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) -#if defined(CONFIG_MPC85xx) - volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); -#elif defined(CONFIG_MPC86xx) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; -#endif -#endif - - puts(" ("); - -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) - /* Print interleaving information */ - if (ddr1->cs0_config & 0x20000000) { - switch ((ddr1->cs0_config >> 24) & 0xf) { - case 0: - puts("cache line"); - break; - case 1: - puts("page"); - break; - case 2: - puts("bank"); - break; - case 3: - puts("super-bank"); - break; - default: - puts("invalid"); - break; - } - } else { - puts("no"); - } - - puts(" interleaving"); -#endif - -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC) - puts(", "); -#endif - -#if defined(CONFIG_DDR_ECC) - puts("ECC enabled"); -#endif - - puts(")"); -} -#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */
On Jul 17, 2009, at 10:14 AM, Peter Tyser wrote:
This is in preparation for adding one common 8xxx board_add_ram_info() fuction for all 8xxx boards
Signed-off-by: Peter Tyser ptyser@xes-inc.com
board/xes/common/fsl_8xxx_ddr.c | 53
1 files changed, 0 insertions(+), 53 deletions(-)
applied
- k
This is in preparation for adding one common 8xxx board_add_ram_info() function for all 8xxx boards
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- board/tqc/tqm85xx/sdram.c | 33 +++------------------------------ 1 files changed, 3 insertions(+), 30 deletions(-)
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 6d73a88..503c5e5 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -374,31 +374,6 @@ long int sdram_setup (int casl) return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; }
-void board_add_ram_info (int use_default) -{ - int casl; - - if (use_default) - casl = CONFIG_DDR_DEFAULT_CL; - else - casl = cas_latency (); - - puts (" (CL="); - switch (casl) { - case 20: - puts ("2)"); - break; - - case 25: - puts ("2.5)"); - break; - - case 30: - puts ("3)"); - break; - } -} - phys_size_t initdram (int board_type) { long dram_size = 0; @@ -438,11 +413,9 @@ phys_size_t initdram (int board_type) /* * Try again with default CAS latency */ - puts ("Problem with CAS lantency"); - board_add_ram_info (1); - puts (", using default CL!\n"); - casl = CONFIG_DDR_DEFAULT_CL; - dram_size = sdram_setup (casl); + printf ("Problem with CAS lantency, using default CL %d/10!\n", + CONFIG_DDR_DEFAULT_CL); + dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL); puts (" "); }
On Jul 17, 2009, at 10:14 AM, Peter Tyser wrote:
This is in preparation for adding one common 8xxx board_add_ram_info() function for all 8xxx boards
Signed-off-by: Peter Tyser ptyser@xes-inc.com
board/tqc/tqm85xx/sdram.c | 33 +++------------------------------ 1 files changed, 3 insertions(+), 30 deletions(-)
applied
- k
Previously, 85xx and 86xx boards would display DRAM information on bootup such as:
... I2C: ready DRAM: Memory controller interleaving enabled: Bank interleaving! 2 GB FLASH: 256 MB ...
This patch moves the printing of the DRAM controller configuration to a common board_add_ram_info() function which prints out DDR type, width, CAS latency, and ECC mode. It also makes the DDR interleaving information print out in a more sane manner:
... I2C: ready DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on) DDR Controller Interleaving Mode: bank FLASH: 256 MB ...
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- cpu/mpc8xxx/ddr/main.c | 43 +-------------------- cpu/mpc8xxx/ddr/util.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+), 41 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c index 6dae26b..faa1af9 100644 --- a/cpu/mpc8xxx/ddr/main.c +++ b/cpu/mpc8xxx/ddr/main.c @@ -162,28 +162,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, j++; } } - if (j == 2) { + if (j == 2) *memctl_interleaving = 1;
- printf("\nMemory controller interleaving enabled: "); - - switch (pinfo->memctl_opts[0].memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - printf("Cache-line interleaving!\n"); - break; - case FSL_DDR_PAGE_INTERLEAVING: - printf("Page interleaving!\n"); - break; - case FSL_DDR_BANK_INTERLEAVING: - printf("Bank interleaving!\n"); - break; - case FSL_DDR_SUPERBANK_INTERLEAVING: - printf("Super bank interleaving\n"); - default: - break; - } - } - /* Check that all controllers are rank interleaving. */ j = 0; for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { @@ -191,29 +172,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, j++; } } - if (j == 2) { + if (j == 2) *rank_interleaving = 1;
- printf("Bank(chip-select) interleaving enabled: "); - - switch (pinfo->memctl_opts[0].ba_intlv_ctl & - FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - printf("CS0+CS1+CS2+CS3\n"); - break; - case FSL_DDR_CS0_CS1: - printf("CS0+CS1\n"); - break; - case FSL_DDR_CS2_CS3: - printf("CS2+CS3\n"); - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - printf("CS0+CS1 and CS2+CS3\n"); - default: - break; - } - } - if (*memctl_interleaving) { unsigned long long addr, total_mem_per_ctlr = 0; /* diff --git a/cpu/mpc8xxx/ddr/util.c b/cpu/mpc8xxx/ddr/util.c index 70dbee0..61c0af8 100644 --- a/cpu/mpc8xxx/ddr/util.c +++ b/cpu/mpc8xxx/ddr/util.c @@ -107,3 +107,99 @@ __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); + +void board_add_ram_info(int use_default) +{ +#if defined(CONFIG_MPC85xx) + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); +#elif defined(CONFIG_MPC86xx) + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR); +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + uint32_t cs0_config = in_be32(&ddr->cs0_config); +#endif + uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); + int cas_lat; + + puts(" (DDR"); + switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> + SDRAM_CFG_SDRAM_TYPE_SHIFT) { + case SDRAM_TYPE_DDR1: + puts("1"); + break; + case SDRAM_TYPE_DDR2: + puts("2"); + break; + case SDRAM_TYPE_DDR3: + puts("3"); + break; + default: + puts("?"); + break; + } + + if (sdram_cfg & SDRAM_CFG_32_BE) + puts(", 32-bit"); + else + puts(", 64-bit"); + + /* Calculate CAS latency based on timing cfg values */ + cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; + if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) + cas_lat += (8 << 1); + printf(", CL=%d", cas_lat >> 1); + if (cas_lat & 0x1) + puts(".5"); + + if (sdram_cfg & SDRAM_CFG_ECC_EN) + puts(", ECC on)"); + else + puts(", ECC off)"); + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + if (cs0_config & 0x20000000) { + puts("\n"); + puts(" DDR Controller Interleaving Mode: "); + + switch ((cs0_config >> 24) & 0xf) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + puts("cache line"); + break; + case FSL_DDR_PAGE_INTERLEAVING: + puts("page"); + break; + case FSL_DDR_BANK_INTERLEAVING: + puts("bank"); + break; + case FSL_DDR_SUPERBANK_INTERLEAVING: + puts("super-bank"); + break; + default: + puts("invalid"); + break; + } + } +#endif + + if ((sdram_cfg >> 8) & 0x7f) { + puts("\n"); + puts(" DDR Chip-Select Interleaving Mode: "); + switch(sdram_cfg >> 8 & 0x7f) { + case FSL_DDR_CS0_CS1_CS2_CS3: + puts("CS0+CS1+CS2+CS3"); + break; + case FSL_DDR_CS0_CS1: + puts("CS0+CS1"); + break; + case FSL_DDR_CS2_CS3: + puts("CS2+CS3"); + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + puts("CS0+CS1 and CS2+CS3"); + break; + default: + puts("invalid"); + break; + } + } +}
On Jul 17, 2009, at 10:14 AM, Peter Tyser wrote:
Previously, 85xx and 86xx boards would display DRAM information on bootup such as:
... I2C: ready DRAM: Memory controller interleaving enabled: Bank interleaving! 2 GB FLASH: 256 MB ...
This patch moves the printing of the DRAM controller configuration to a common board_add_ram_info() function which prints out DDR type, width, CAS latency, and ECC mode. It also makes the DDR interleaving information print out in a more sane manner:
... I2C: ready DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on) DDR Controller Interleaving Mode: bank FLASH: 256 MB ...
Signed-off-by: Peter Tyser ptyser@xes-inc.com
cpu/mpc8xxx/ddr/main.c | 43 +-------------------- cpu/mpc8xxx/ddr/util.c | 96 +++++++++++++++++++++++++++++++++++++++ +++++++++ 2 files changed, 98 insertions(+), 41 deletions(-)
applied
- k
On Jul 17, 2009, at 10:14 AM, Peter Tyser wrote:
Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match the 86xx user's manual and other Freescale architectures
Signed-off-by: Peter Tyser ptyser@xes-inc.com
board/freescale/mpc8610hpcd/mpc8610hpcd.c | 4 ++-- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 6 +++--- board/sbc8641d/sbc8641d.c | 12 ++++++------ cpu/mpc86xx/ddr-8641.c | 4 ++-- include/asm-ppc/immap_86xx.h | 4 ++-- 5 files changed, 15 insertions(+), 15 deletions(-)
applied
- k
participants (2)
-
Kumar Gala -
Peter Tyser