[U-Boot] [PATCH 00/32] Massive x86 Update - Bring x86 in line with ARM and PPC
This patch series marks a considerably significant milestone in the x86 port of U-Boot - Running the initial init sequence from Flash using the CPU on-die cache as a temporary stack.
Prior to this patch series, the low-level assembler code running in Flash was responsible for initialising SDRAM and getting the C environment (the stack) set up. The C code would then simply copy the U-Boot image to RAM, do some relocation adjustments and jump into the in-RAM copy - only then would the init sequence run.
Thank to the assistance of Juergen Beisert (who had done a Cache-As-RAM implementation for the sc520 quite some time ago), the x86 boot sequence is more 'standard': - Initialise Cache-As-RAM (CAR) - Setup a restricted 'C' environment - Setup initial global data in CAR - Run init sequence from Flash - Copy global data to a newly malloc'd block - Jump to RAM
This patch does have three 'negative' impacts: - Boot time is slightly slower due to running the init sequence from Flash rather than SDRAM - The image is no longer position independent - If you want to create a warm-boot u-boot image, you need to link it to a different address - You can no longer do a warm-boot to a new u-boot image from SDARM (SDRAM is always re-initialised during the init sequence)
Regards,
Graeme
Changes since RFC: - Ran checkpatch.pl and fixed (most) errors and warnings (a few long lines remain for readability and sc520_enable_ecc() in arch\i386\cpu\sc520 contains raw asm which is #ifdef'd out - This is ECC initialisation copied from the original asm file which is retained in case someone with ECC capable hardware (which I do not have) would care to implement properly - Merged some patches that logically belonged together - Added a code tidy-up for eNET - #defined all 'magic numbers' in the eNET configuration file - rebased to u-boot/master
Graeme Russ (32): x86: Fix definition of global_data struct for asm-offsets.c x86: Align config.mk and linker scripts with other arches eNET: Create distinct board configurations x86: Parametize values used in linker script sc520: Sort Makefile x86: Fix mangled umlauts x86: Add stack dump to register dump x86: Move Global Descriptor Table defines to processor.h x86: Add processor flags header from linux x86: Call early_board_init when warm booting x86: Make cpu init functions weak sc520: Define MMCR address in include file sc520: Move board specific settings to board init function sc520: Remove printf calls from cpu_init_f eNET: Fix eNET Interrupt Setup for Linux eNET: Add RTC support to eNET eNET: Define MMCR values in config.h eNET: Rearrange PAR assignments eNET: General code cleanup x86: Move initial gd to fixed location x86: Use Cache-As-RAM for initial stack sc520: Move RAM sizing code from asm to C x86: Defer setup of final stack x86: Move call to dram_init_f into board_init_f x86: Move test for cold boot into init functions x86: Move console initialisation into board_init_f x86: Fix incorrect usage of relocation offset x86: Split board_init_f() into init_fnc_t compatible functions x86: Rearrange function calls in board_init_f x86: Convert board_init_f to use an init_sequence sc520: Release CAR and enable caching eNET: Move initial Global Data into CAR
arch/i386/config.mk | 14 +- arch/i386/cpu/config.mk | 10 +- arch/i386/cpu/cpu.c | 35 +- arch/i386/cpu/interrupts.c | 19 +- arch/i386/cpu/sc520/Makefile | 5 +- arch/i386/cpu/sc520/sc520.c | 148 +------- arch/i386/cpu/sc520/sc520_asm.S | 615 ---------------------------- arch/i386/cpu/sc520/sc520_car.S | 94 +++++ arch/i386/cpu/sc520/sc520_sdram.c | 532 ++++++++++++++++++++++++ arch/i386/cpu/start.S | 107 +++--- arch/i386/cpu/start16.S | 5 +- arch/i386/cpu/u-boot.lds | 96 +++++ arch/i386/include/asm/global_data.h | 21 +- arch/i386/include/asm/ic/sc520.h | 93 ++++- arch/i386/include/asm/processor-flags.h | 100 +++++ arch/i386/include/asm/processor.h | 9 +- arch/i386/include/asm/u-boot-i386.h | 3 + arch/i386/lib/board.c | 144 ++++--- arch/i386/lib/realmode.c | 8 +- board/eNET/config.mk | 6 +- board/eNET/eNET.c | 192 +++++---- board/eNET/eNET_start.S | 7 - board/eNET/eNET_start16.S | 15 +- board/eNET/u-boot.lds | 104 ----- boards.cfg | 3 +- drivers/rtc/mc146818.c | 6 + include/configs/eNET.h | 678 +++++++++++++++++++++++-------- 27 files changed, 1786 insertions(+), 1283 deletions(-) delete mode 100644 arch/i386/cpu/sc520/sc520_asm.S create mode 100644 arch/i386/cpu/sc520/sc520_car.S create mode 100644 arch/i386/cpu/sc520/sc520_sdram.c create mode 100644 arch/i386/cpu/u-boot.lds create mode 100644 arch/i386/include/asm/processor-flags.h delete mode 100644 board/eNET/u-boot.lds
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/include/asm/global_data.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index e3f8a25..e9000c3 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -35,7 +35,7 @@
#ifndef __ASSEMBLY__
-typedef struct { +typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long baudrate;
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/include/asm/global_data.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/config.mk | 13 ++++-- arch/i386/cpu/config.mk | 4 +- arch/i386/cpu/u-boot.lds | 104 ++++++++++++++++++++++++++++++++++++++++++++++ board/eNET/config.mk | 4 -- board/eNET/u-boot.lds | 104 ---------------------------------------------- 5 files changed, 114 insertions(+), 115 deletions(-) create mode 100644 arch/i386/cpu/u-boot.lds delete mode 100644 board/eNET/u-boot.lds
diff --git a/arch/i386/config.mk b/arch/i386/config.mk index 3fb97c1..77a33dd 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -21,8 +21,6 @@ # MA 02111-1307 USA #
-CROSS_COMPILE ?= i386-linux- - STANDALONE_LOAD_ADDR = 0x40000
PLATFORM_CPPFLAGS += -fno-strict-aliasing @@ -33,8 +31,13 @@ PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding) PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time)) PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector) PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) -PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ +PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm + +PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden + +PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
LDFLAGS += --cref -LDFLAGS_u-boot += --gc-sections -PLATFORM_RELFLAGS += -ffunction-sections +LDFLAGS_u-boot += --gc-sections -pie +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds + diff --git a/arch/i386/cpu/config.mk b/arch/i386/cpu/config.mk index 16a160d..ec1d102 100644 --- a/arch/i386/cpu/config.mk +++ b/arch/i386/cpu/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA #
-PLATFORM_RELFLAGS += +CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -march=i386 -Werror +PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror diff --git a/arch/i386/cpu/u-boot.lds b/arch/i386/cpu/u-boot.lds new file mode 100644 index 0000000..3eeb2a2 --- /dev/null +++ b/arch/i386/cpu/u-boot.lds @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + . = ALIGN(4); + __u_boot_cmd_end = .; + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = ALIGN(4); + .dynsym : { *(.dynsym*) } + + . = ALIGN(4); + .hash : { *(.hash*) } + + . = ALIGN(4); + .got : { *(.got*) } + + . = ALIGN(4); + __data_end = .; + + . = ALIGN(4); + __bss_start = ABSOLUTE(.); + .bss (NOLOAD) : { *(.bss) } + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + + . = ALIGN(4); + __rel_dyn_start = .; + .rel.dyn : { *(.rel.dyn) } + __rel_dyn_end = .; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + + /* 16bit realmode trampoline code */ + .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) } + + __realmode_start = LOADADDR(.realmode); + __realmode_size = SIZEOF(.realmode); + + /* 16bit BIOS emulation code (just enough to boot Linux) */ + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) } + + __bios_start = LOADADDR(.bios); + __bios_size = SIZEOF(.bios); + + /* The load addresses below assumes that the flash + * will be mapped so that 0x387f0000 == 0xffff0000 + * at reset time + * + * The fe00 and ff00 offsets of the start32 and start16 + * segments are arbitrary, the just have to be mapped + * at reset and the code have to fit. + * The fff0 offset of resetvec is important, however. + */ + . = 0xfffffe00; + .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } + + . = 0xf800; + .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } + + . = 0xfff0; + .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } +} diff --git a/board/eNET/config.mk b/board/eNET/config.mk index c4242ad..ce575ab 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -22,7 +22,3 @@ #
CONFIG_SYS_TEXT_BASE = 0x06000000 -CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing -PLATFORM_RELFLAGS += -fvisibility=hidden -PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds deleted file mode 100644 index 3eeb2a2..0000000 --- a/board/eNET/u-boot.lds +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) -ENTRY(_start) - -SECTIONS -{ - . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */ - __text_start = .; - .text : { *(.text*); } - - . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - . = ALIGN(4); - __u_boot_cmd_end = .; - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = ALIGN(4); - .dynsym : { *(.dynsym*) } - - . = ALIGN(4); - .hash : { *(.hash*) } - - . = ALIGN(4); - .got : { *(.got*) } - - . = ALIGN(4); - __data_end = .; - - . = ALIGN(4); - __bss_start = ABSOLUTE(.); - .bss (NOLOAD) : { *(.bss) } - . = ALIGN(4); - __bss_end = ABSOLUTE(.); - - . = ALIGN(4); - __rel_dyn_start = .; - .rel.dyn : { *(.rel.dyn) } - __rel_dyn_end = .; - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } - - /* 16bit realmode trampoline code */ - .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) } - - __realmode_start = LOADADDR(.realmode); - __realmode_size = SIZEOF(.realmode); - - /* 16bit BIOS emulation code (just enough to boot Linux) */ - .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) } - - __bios_start = LOADADDR(.bios); - __bios_size = SIZEOF(.bios); - - /* The load addresses below assumes that the flash - * will be mapped so that 0x387f0000 == 0xffff0000 - * at reset time - * - * The fe00 and ff00 offsets of the start32 and start16 - * segments are arbitrary, the just have to be mapped - * at reset and the code have to fit. - * The fff0 offset of resetvec is important, however. - */ - . = 0xfffffe00; - .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } - - . = 0xf800; - .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } - - . = 0xfff0; - .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } -}
On Fri, 4 Feb 2011 23:35:29 +1100 Graeme Russ graeme.russ@gmail.com wrote:
LDFLAGS += --cref -LDFLAGS_u-boot += --gc-sections -PLATFORM_RELFLAGS += -ffunction-sections +LDFLAGS_u-boot += --gc-sections -pie +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
The use of --cref came up recently (see http://lists.denx.de/pipermail/u-boot/2011-February/086698.html).
During what link phase is --cref supposed to be used? Currently it is being used during partial links only, and not the final link, as a result of commit 8aba9dceebb14144e07d19593111ee3a999c37fc. As the toplevel config.mk currently stands, it would have to go in PLATFORM_LDFLAGS to be used in all link phases, or LDFLAGS_u-boot to be used when linking the final image only.
BTW, is it really enabled because of something to do with i386? Or just maintainer preference (in which case it should probably be a non-arch config, or in this case just enabled unconditionally, since I don't think there's any harm to it).
-Scott
On 05/02/11 07:42, Scott Wood wrote:
On Fri, 4 Feb 2011 23:35:29 +1100 Graeme Russ graeme.russ@gmail.com wrote:
LDFLAGS += --cref -LDFLAGS_u-boot += --gc-sections -PLATFORM_RELFLAGS += -ffunction-sections +LDFLAGS_u-boot += --gc-sections -pie +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
The use of --cref came up recently (see http://lists.denx.de/pipermail/u-boot/2011-February/086698.html).
During what link phase is --cref supposed to be used? Currently it is being used during partial links only, and not the final link, as a result of commit 8aba9dceebb14144e07d19593111ee3a999c37fc. As the toplevel config.mk currently stands, it would have to go in PLATFORM_LDFLAGS to be used in all link phases, or LDFLAGS_u-boot to be used when linking the final image only.
BTW, is it really enabled because of something to do with i386? Or just maintainer preference (in which case it should probably be a non-arch config, or in this case just enabled unconditionally, since I don't think there's any harm to it).
I think --cref is historical. I have just performed a build without it and it runs fine, so I think it can be safely removed.
Maybe it might be worth starting a separate discussion thread with the goal of unifying and documenting the linker, make and config.mk files?
Regards,
Graeme
On Fri, Feb 04, 2011, Graeme Russ wrote:
diff --git a/arch/i386/config.mk b/arch/i386/config.mk index 3fb97c1..77a33dd 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -21,8 +21,6 @@ # MA 02111-1307 USA #
-CROSS_COMPILE ?= i386-linux-
STANDALONE_LOAD_ADDR = 0x40000
PLATFORM_CPPFLAGS += -fno-strict-aliasing @@ -33,8 +31,13 @@ PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding) PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time)) PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector) PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) -PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ +PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
+PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
LDFLAGS += --cref -LDFLAGS_u-boot += --gc-sections -PLATFORM_RELFLAGS += -ffunction-sections +LDFLAGS_u-boot += --gc-sections -pie +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/i386/cpu/config.mk b/arch/i386/cpu/config.mk index 16a160d..ec1d102 100644 --- a/arch/i386/cpu/config.mk +++ b/arch/i386/cpu/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA #
-PLATFORM_RELFLAGS += +CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -march=i386 -Werror +PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror diff --git a/arch/i386/cpu/u-boot.lds b/arch/i386/cpu/u-boot.lds new file mode 100644 index 0000000..3eeb2a2 --- /dev/null +++ b/arch/i386/cpu/u-boot.lds @@ -0,0 +1,104 @@ +/*
- (C) Copyright 2002
- Daniel Engstr�m, Omicron Ceti AB, daniel@omicron.se.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start)
+SECTIONS +{
- . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
- __text_start = .;
- .text : { *(.text*); }
- . = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- . = ALIGN(4);
- __u_boot_cmd_end = .;
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
- . = ALIGN(4);
- .data : { *(.data*) }
- . = ALIGN(4);
- .dynsym : { *(.dynsym*) }
- . = ALIGN(4);
- .hash : { *(.hash*) }
- . = ALIGN(4);
- .got : { *(.got*) }
- . = ALIGN(4);
- __data_end = .;
- . = ALIGN(4);
- __bss_start = ABSOLUTE(.);
- .bss (NOLOAD) : { *(.bss) }
- . = ALIGN(4);
- __bss_end = ABSOLUTE(.);
- . = ALIGN(4);
- __rel_dyn_start = .;
- .rel.dyn : { *(.rel.dyn) }
- __rel_dyn_end = .;
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
- /* 16bit realmode trampoline code */
- .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
- __realmode_start = LOADADDR(.realmode);
- __realmode_size = SIZEOF(.realmode);
- /* 16bit BIOS emulation code (just enough to boot Linux) */
- .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) }
- __bios_start = LOADADDR(.bios);
- __bios_size = SIZEOF(.bios);
- /* The load addresses below assumes that the flash
* will be mapped so that 0x387f0000 == 0xffff0000* at reset time** The fe00 and ff00 offsets of the start32 and start16* segments are arbitrary, the just have to be mapped* at reset and the code have to fit.* The fff0 offset of resetvec is important, however.*/- . = 0xfffffe00;
- .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
- . = 0xf800;
- .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
- . = 0xfff0;
- .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
+} diff --git a/board/eNET/config.mk b/board/eNET/config.mk index c4242ad..ce575ab 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -22,7 +22,3 @@ #
CONFIG_SYS_TEXT_BASE = 0x06000000 -CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing -PLATFORM_RELFLAGS += -fvisibility=hidden -PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds deleted file mode 100644 index 3eeb2a2..0000000 --- a/board/eNET/u-boot.lds +++ /dev/null @@ -1,104 +0,0 @@ -/*
- (C) Copyright 2002
- Daniel Engstr�m, Omicron Ceti AB, daniel@omicron.se.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
-OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) -ENTRY(_start)
-SECTIONS -{
- . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
- __text_start = .;
- .text : { *(.text*); }
- . = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- . = ALIGN(4);
- __u_boot_cmd_end = .;
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
- . = ALIGN(4);
- .data : { *(.data*) }
- . = ALIGN(4);
- .dynsym : { *(.dynsym*) }
- . = ALIGN(4);
- .hash : { *(.hash*) }
- . = ALIGN(4);
- .got : { *(.got*) }
- . = ALIGN(4);
- __data_end = .;
- . = ALIGN(4);
- __bss_start = ABSOLUTE(.);
- .bss (NOLOAD) : { *(.bss) }
- . = ALIGN(4);
- __bss_end = ABSOLUTE(.);
- . = ALIGN(4);
- __rel_dyn_start = .;
- .rel.dyn : { *(.rel.dyn) }
- __rel_dyn_end = .;
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
- /* 16bit realmode trampoline code */
- .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
- __realmode_start = LOADADDR(.realmode);
- __realmode_size = SIZEOF(.realmode);
- /* 16bit BIOS emulation code (just enough to boot Linux) */
- .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) }
- __bios_start = LOADADDR(.bios);
- __bios_size = SIZEOF(.bios);
- /* The load addresses below assumes that the flash
* will be mapped so that 0x387f0000 == 0xffff0000* at reset time** The fe00 and ff00 offsets of the start32 and start16* segments are arbitrary, the just have to be mapped* at reset and the code have to fit.* The fff0 offset of resetvec is important, however.*/- . = 0xfffffe00;
- .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
- . = 0xf800;
- .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
- . = 0xfff0;
- .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
-}
Acked-By: Lo�c Minier loic.minier@linaro.org
Build-tested on Debian i386 (native); fixes the build failure with tip
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/config.mk | 13 ++++-- arch/i386/cpu/config.mk | 4 +- arch/i386/cpu/u-boot.lds | 104 ++++++++++++++++++++++++++++++++++++++++++++++ board/eNET/config.mk | 4 -- board/eNET/u-boot.lds | 104 ---------------------------------------------- 5 files changed, 114 insertions(+), 115 deletions(-) create mode 100644 arch/i386/cpu/u-boot.lds delete mode 100644 board/eNET/u-boot.lds
Applied to u-boot-x86
(also added trivial removal of --cref)
Regards,
Graeme
Position independant functionality is due for removal from the x86 architecture, so create two distinct configurations - One for Flash and one for SRAM
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- board/eNET/config.mk | 1 - boards.cfg | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/eNET/config.mk b/board/eNET/config.mk index ce575ab..4257141 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -21,4 +21,3 @@ # MA 02111-1307 USA #
-CONFIG_SYS_TEXT_BASE = 0x06000000 diff --git a/boards.cfg b/boards.cfg index c3b164e..94347b1 100644 --- a/boards.cfg +++ b/boards.cfg @@ -199,7 +199,8 @@ ibf-dsp561 blackfin blackfin ip04 blackfin blackfin tcm-bf518 blackfin blackfin tcm-bf537 blackfin blackfin -eNET i386 i386 - - sc520 +eNET i386 i386 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000 +eNET_SRAM i386 i386 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000 idmr m68k mcf52x2 TASREG m68k mcf52x2 tasreg esd M5208EVBE m68k mcf52x2 m5208evbe freescale
On 04/02/11 23:35, Graeme Russ wrote:
Position independant functionality is due for removal from the x86 architecture, so create two distinct configurations - One for Flash and one for SRAM
Signed-off-by: Graeme Russ graeme.russ@gmail.com
board/eNET/config.mk | 1 - boards.cfg | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/config.mk | 1 + arch/i386/cpu/config.mk | 6 ++++++ arch/i386/cpu/u-boot.lds | 24 ++++++++---------------- arch/i386/lib/realmode.c | 8 ++++---- board/eNET/config.mk | 1 + 5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/i386/config.mk b/arch/i386/config.mk index 77a33dd..5a62a98 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -32,6 +32,7 @@ PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector) PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm +PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
diff --git a/arch/i386/cpu/config.mk b/arch/i386/cpu/config.mk index ec1d102..9b2e2c9 100644 --- a/arch/i386/cpu/config.mk +++ b/arch/i386/cpu/config.mk @@ -24,3 +24,9 @@ CROSS_COMPILE ?= i386-linux-
PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror + +# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! +LDPPFLAGS += -DRESET_SEG_START=0xffff0000 +LDPPFLAGS += -DRESET_SEG_SIZE=0x10000 +LDPPFLAGS += -DRESET_VEC_LOC=0xfff0 +LDPPFLAGS += -DSTART_16=0xf800 diff --git a/arch/i386/cpu/u-boot.lds b/arch/i386/cpu/u-boot.lds index 3eeb2a2..98a548d 100644 --- a/arch/i386/cpu/u-boot.lds +++ b/arch/i386/cpu/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS /DISCARD/ : { *(.gnu*) }
/* 16bit realmode trampoline code */ - .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) } + .realmode REALMODE_BASE : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
__realmode_start = LOADADDR(.realmode); __realmode_size = SIZEOF(.realmode); @@ -84,21 +84,13 @@ SECTIONS __bios_start = LOADADDR(.bios); __bios_size = SIZEOF(.bios);
- /* The load addresses below assumes that the flash - * will be mapped so that 0x387f0000 == 0xffff0000 - * at reset time - * - * The fe00 and ff00 offsets of the start32 and start16 - * segments are arbitrary, the just have to be mapped - * at reset and the code have to fit. - * The fff0 offset of resetvec is important, however. + /* + * The following expressions place the 16-bit Real-Mode code and + * Reset Vector at the end of the Flash ROM */ - . = 0xfffffe00; - .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } + . = START_16; + .start16 : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); }
- . = 0xf800; - .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } - - . = 0xfff0; - .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } + . = RESET_VEC_LOC; + .resetvec : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); } } diff --git a/arch/i386/lib/realmode.c b/arch/i386/lib/realmode.c index 60fe181..2dda95b 100644 --- a/arch/i386/lib/realmode.c +++ b/arch/i386/lib/realmode.c @@ -27,7 +27,6 @@ #include <asm/realmode.h>
-#define REALMODE_BASE ((char*)0x7c0) #define REALMODE_MAILBOX ((char*)0xe00)
@@ -41,13 +40,14 @@ int realmode_setup(void) ulong realmode_size = (ulong)&__realmode_size;
/* copy the realmode switch code */ - if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) { + if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) { printf("realmode switch too large (%ld bytes, max is %d)\n", - realmode_size, (REALMODE_MAILBOX-REALMODE_BASE)); + realmode_size, + (REALMODE_MAILBOX - (char *)REALMODE_BASE)); return -1; }
- memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size); + memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size); asm("wbinvd\n");
return 0; diff --git a/board/eNET/config.mk b/board/eNET/config.mk index 4257141..9d2dfa5 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -21,3 +21,4 @@ # MA 02111-1307 USA #
+LDPPFLAGS += -DFLASH_SIZE=0x40000
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/config.mk | 1 + arch/i386/cpu/config.mk | 6 ++++++ arch/i386/cpu/u-boot.lds | 24 ++++++++---------------- arch/i386/lib/realmode.c | 8 ++++---- board/eNET/config.mk | 1 + 5 files changed, 20 insertions(+), 20 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/sc520/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile index fb47c20..b962b02 100644 --- a/arch/i386/cpu/sc520/Makefile +++ b/arch/i386/cpu/sc520/Makefile @@ -32,9 +32,9 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(SOC).o
COBJS-$(CONFIG_SYS_SC520) += sc520.o +COBJS-$(CONFIG_PCI) += sc520_pci.o COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o -COBJS-$(CONFIG_PCI) += sc520_pci.o
SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
git mergetool has a nasty habit of mangling umlats - fix ones that have been missed in previous submissions
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/start.S | 2 +- arch/i386/lib/board.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 829468f..ab9338a 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -1,7 +1,7 @@ /* * U-boot - i386 Startup Code * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engstrï¿œm denaiel@omicron.se + * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström denaiel@omicron.se * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 30cb9a2..2cadce8 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engstrï¿œm, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se * * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
On 04/02/11 23:35, Graeme Russ wrote:
git mergetool has a nasty habit of mangling umlats - fix ones that have been missed in previous submissions
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/start.S | 2 +- arch/i386/lib/board.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/interrupts.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c index e4d0868..cdff3d9 100644 --- a/arch/i386/cpu/interrupts.c +++ b/arch/i386/cpu/interrupts.c @@ -29,6 +29,7 @@
#include <common.h> #include <asm/interrupt.h> +#include <asm/io.h>
#define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -108,6 +109,7 @@ void dump_regs(struct irq_regs *regs) { unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; + unsigned long sp;
printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n", (u16)regs->xcs, regs->eip, regs->eflags); @@ -139,6 +141,20 @@ void dump_regs(struct irq_regs *regs) d7 = get_debugreg(7); printf("DR6: %08lx DR7: %08lx\n", d6, d7); + + printf("Stack:\n"); + sp = regs->esp; + + sp += 64; + + while (sp > (regs->esp - 16)) { + if (sp == regs->esp) + printf("--->"); + else + printf(" "); + printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp)); + sp -= 4; + } }
struct idt_entry {
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/interrupts.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/cpu.c | 8 +------- arch/i386/include/asm/processor.h | 9 ++++++--- 2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index ae40384..1dcbb98 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -35,6 +35,7 @@
#include <common.h> #include <command.h> +#include <asm/processor.h> #include <asm/interrupt.h>
/* Constructor for a conventional segment GDT (or LDT) entry */ @@ -46,13 +47,6 @@ (((base) & 0x00ffffffULL) << 16) | \ (((limit) & 0x0000ffffULL)))
-/* Simple and small GDT entries for booting only */ - -#define GDT_ENTRY_32BIT_CS 2 -#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1) -#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1) -#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1) - /* * Set up the GDT */ diff --git a/arch/i386/include/asm/processor.h b/arch/i386/include/asm/processor.h index 5dedba8..22a1298 100644 --- a/arch/i386/include/asm/processor.h +++ b/arch/i386/include/asm/processor.h @@ -23,7 +23,10 @@
#ifndef __ASM_PROCESSOR_H_ #define __ASM_PROCESSOR_H_ 1 -/* Currently this header is unused in the i386 port - * but some generic files #include <asm/processor.h> - * so this file is a placeholder. */ + +#define GDT_ENTRY_32BIT_CS 2 +#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1) +#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1) +#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1) + #endif
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/cpu.c | 8 +------- arch/i386/include/asm/processor.h | 9 ++++++--- 2 files changed, 7 insertions(+), 10 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/cpu.c | 13 +++- arch/i386/cpu/interrupts.c | 3 +- arch/i386/cpu/sc520/sc520.c | 7 ++- arch/i386/cpu/start.S | 3 +- arch/i386/cpu/start16.S | 5 +- arch/i386/include/asm/processor-flags.h | 100 +++++++++++++++++++++++++++++++ 6 files changed, 121 insertions(+), 10 deletions(-) create mode 100644 arch/i386/include/asm/processor-flags.h
diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index 1dcbb98..e96380a 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -36,6 +36,7 @@ #include <common.h> #include <command.h> #include <asm/processor.h> +#include <asm/processor-flags.h> #include <asm/interrupt.h>
/* Constructor for a conventional segment GDT (or LDT) entry */ @@ -88,12 +89,16 @@ static void reload_gdt(void)
int cpu_init_f(void) { + const u32 em_rst = ~X86_CR0_EM; + const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; + /* initialize FPU, reset EM, set MP and NE */ asm ("fninit\n" \ - "movl %cr0, %eax\n" \ - "andl $~0x4, %eax\n" \ - "orl $0x22, %eax\n" \ - "movl %eax, %cr0\n" ); + "movl %%cr0, %%eax\n" \ + "andl %0, %%eax\n" \ + "orl %1, %%eax\n" \ + "movl %%eax, %%cr0\n" \ + : : "i" (em_rst), "i" (mp_ne_set) : "eax");
return 0; } diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c index cdff3d9..1cefe02 100644 --- a/arch/i386/cpu/interrupts.c +++ b/arch/i386/cpu/interrupts.c @@ -30,6 +30,7 @@ #include <common.h> #include <asm/interrupt.h> #include <asm/io.h> +#include <asm/processor-flags.h>
#define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -237,7 +238,7 @@ int disable_interrupts(void)
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
- return (flags&0x200); /* IE flags is bit 9 */ + return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */ }
/* IRQ Low-Level Service Routine */ diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 7acd471..21037d2 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -26,6 +26,7 @@
#include <common.h> #include <asm/io.h> +#include <asm/processor-flags.h> #include <asm/ic/sc520.h>
DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +42,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
void init_sc520(void) { + const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); + /* * Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference @@ -84,8 +87,8 @@ void init_sc520(void)
/* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); + "andl %0, %%eax\n" + "movl %%eax, %%cr0\n" : : "i" (nw_cd_rst) : "eax"); }
unsigned long init_sc520_dram(void) diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index ab9338a..460c21b 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -26,6 +26,7 @@ #include <config.h> #include <version.h> #include <asm/global_data.h> +#include <asm/processor-flags.h>
.section .text @@ -46,7 +47,7 @@ _i386boot_start:
/* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000, %eax + orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 wbinvd
diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S index 0a5823d..7dc5358 100644 --- a/arch/i386/cpu/start16.S +++ b/arch/i386/cpu/start16.S @@ -23,6 +23,7 @@ */
#include <asm/global_data.h> +#include <asm/processor-flags.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */ #define a32 .byte 0x67; @@ -45,7 +46,7 @@ board_init16_ret:
/* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000, %eax + orl $(X86_CR0_NW & X86_CR0_CD), %eax movl %eax, %cr0 wbinvd
@@ -55,7 +56,7 @@ o32 cs lgdt gdt_ptr
/* Now, we enter protected mode */ movl %cr0, %eax - orl $1, %eax + orl $X86_CR0_PE, %eax movl %eax, %cr0
/* Flush the prefetch queue */ diff --git a/arch/i386/include/asm/processor-flags.h b/arch/i386/include/asm/processor-flags.h new file mode 100644 index 0000000..7a3e836 --- /dev/null +++ b/arch/i386/include/asm/processor-flags.h @@ -0,0 +1,100 @@ +#ifndef _ASM_X86_PROCESSOR_FLAGS_H +#define _ASM_X86_PROCESSOR_FLAGS_H +/* Various flags defined: can be included from assembler. */ + +/* + * EFLAGS bits + */ +#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ +#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ +#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ +#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ +#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ +#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ +#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ +#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ +#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ +#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ +#define X86_EFLAGS_NT 0x00004000 /* Nested Task */ +#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ +#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ +#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ +#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ +#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ +#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ + +/* + * Basic CPU control in CR0 + */ +#define X86_CR0_PE 0x00000001 /* Protection Enable */ +#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ +#define X86_CR0_EM 0x00000004 /* Emulation */ +#define X86_CR0_TS 0x00000008 /* Task Switched */ +#define X86_CR0_ET 0x00000010 /* Extension Type */ +#define X86_CR0_NE 0x00000020 /* Numeric Error */ +#define X86_CR0_WP 0x00010000 /* Write Protect */ +#define X86_CR0_AM 0x00040000 /* Alignment Mask */ +#define X86_CR0_NW 0x20000000 /* Not Write-through */ +#define X86_CR0_CD 0x40000000 /* Cache Disable */ +#define X86_CR0_PG 0x80000000 /* Paging */ + +/* + * Paging options in CR3 + */ +#define X86_CR3_PWT 0x00000008 /* Page Write Through */ +#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ + +/* + * Intel CPU features in CR4 + */ +#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ +#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ +#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ +#define X86_CR4_DE 0x00000008 /* enable debugging extensions */ +#define X86_CR4_PSE 0x00000010 /* enable page size extensions */ +#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ +#define X86_CR4_MCE 0x00000040 /* Machine check enable */ +#define X86_CR4_PGE 0x00000080 /* enable global pages */ +#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ +#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ +#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ +#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ +#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ + +/* + * x86-64 Task Priority Register, CR8 + */ +#define X86_CR8_TPR 0x0000000F /* task priority register */ + +/* + * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> + */ + +/* + * NSC/Cyrix CPU configuration register indexes + */ +#define CX86_PCR0 0x20 +#define CX86_GCR 0xb8 +#define CX86_CCR0 0xc0 +#define CX86_CCR1 0xc1 +#define CX86_CCR2 0xc2 +#define CX86_CCR3 0xc3 +#define CX86_CCR4 0xe8 +#define CX86_CCR5 0xe9 +#define CX86_CCR6 0xea +#define CX86_CCR7 0xeb +#define CX86_PCR1 0xf0 +#define CX86_DIR0 0xfe +#define CX86_DIR1 0xff +#define CX86_ARR_BASE 0xc4 +#define CX86_RCR_BASE 0xdc + +#ifdef __KERNEL__ +#ifdef CONFIG_VM86 +#define X86_VM_MASK X86_EFLAGS_VM +#else +#define X86_VM_MASK 0 /* No VM86 support */ +#endif +#endif + +#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/cpu.c | 13 +++- arch/i386/cpu/interrupts.c | 3 +- arch/i386/cpu/sc520/sc520.c | 7 ++- arch/i386/cpu/start.S | 3 +- arch/i386/cpu/start16.S | 5 +- arch/i386/include/asm/processor-flags.h | 100 +++++++++++++++++++++++++++++++ 6 files changed, 121 insertions(+), 10 deletions(-) create mode 100644 arch/i386/include/asm/processor-flags.h
Applied to u-boot-x86
Regards,
Graeme
early_board_init has been skipped to avoid SDRAM corruption in the case that a fully relocatable image has been loaded into SDRAM and is being executed from SDRAM. x86 is being aligned with other architectures (ARM and PPC in particlar) and will be using Cache-As-RAM to run a C environment from Flash (or SRAM if you have some). early_board_init may be needed to assist in the setup of Cache-As-RAM and the early C environment
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/start.S | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 460c21b..97bac8f 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -67,16 +67,16 @@ _start: /* Clear the interupt vectors */ lidt blank_idt_ptr
- /* Skip low-level initialization if not starting from cold-reset */ - movl %ebx, %ecx - andl $GD_FLG_COLD_BOOT, %ecx - jz skip_mem_init - /* Early platform init (setup gpio, etc ) */ jmp early_board_init .globl early_board_init_ret early_board_init_ret:
+ /* Skip memory initialization if not starting from cold-reset */ + movl %ebx, %ecx + andl $GD_FLG_COLD_BOOT, %ecx + jz skip_mem_init + /* size memory */ jmp mem_init .globl mem_init_ret
On 04/02/11 23:35, Graeme Russ wrote:
early_board_init has been skipped to avoid SDRAM corruption in the case that a fully relocatable image has been loaded into SDRAM and is being executed from SDRAM. x86 is being aligned with other architectures (ARM and PPC in particlar) and will be using Cache-As-RAM to run a C environment from Flash (or SRAM if you have some). early_board_init may be needed to assist in the setup of Cache-As-RAM and the early C environment
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/start.S | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/cpu.c | 14 ++++++++++++-- arch/i386/cpu/sc520/sc520.c | 11 +++-------- arch/i386/include/asm/u-boot-i386.h | 2 ++ board/eNET/eNET.c | 22 ---------------------- 4 files changed, 17 insertions(+), 32 deletions(-)
diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index e96380a..2339cd4 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -87,7 +87,7 @@ static void reload_gdt(void) }
-int cpu_init_f(void) +int x86_cpu_init_f(void) { const u32 em_rst = ~X86_CR0_EM; const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; @@ -102,15 +102,25 @@ int cpu_init_f(void)
return 0; } +int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
-int cpu_init_r(void) +int x86_cpu_init_r(void) { + const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); + + /* turn on the cache and disable write through */ + asm("movl %%cr0, %%eax\n" + "andl %0, %%eax\n" + "movl %%eax, %%cr0\n" + "wbinvd\n" : : "i" (nw_cd_rst) : "eax"); + reload_gdt();
/* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts (); return 0; } +int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 21037d2..b99408c 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB daniel@omicron.se. + * Daniel Engstrï¿œm, Omicron Ceti AB daniel@omicron.se. * * See file CREDITS for list of people who contributed to this * project. @@ -40,10 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
-void init_sc520(void) +int cpu_init_f(void) { - const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); - /* * Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference @@ -85,10 +83,7 @@ void init_sc520(void) /* turn on the SDRAM write buffer */ writeb(0x11, &sc520_mmcr->dbctl);
- /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl %0, %%eax\n" - "movl %%eax, %%cr0\n" : : "i" (nw_cd_rst) : "eax"); + return x86_cpu_init_f(); }
unsigned long init_sc520_dram(void) diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h index ce097a3..80db52f 100644 --- a/arch/i386/include/asm/u-boot-i386.h +++ b/arch/i386/include/asm/u-boot-i386.h @@ -25,7 +25,9 @@ #define _U_BOOT_I386_H_ 1
/* cpu/.../cpu.c */ +int x86_cpu_init_r(void); int cpu_init_r(void); +int x86_cpu_init_f(void); int cpu_init_f(void);
/* cpu/.../timer.c */ diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 7f0e257..30d8750 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -48,33 +48,11 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; static void enet_timer_isr(void); static void enet_toggle_run_led(void);
-void init_sc520_enet (void) -{ - /* Set CPU Speed to 100MHz */ - writeb(0x01, &sc520_mmcr->cpuctl); - - /* wait at least one millisecond */ - asm("movl $0x2000,%%ecx\n" - "0: pushl %%ecx\n" - "popl %%ecx\n" - "loop 0b\n": : : "ecx"); - - /* turn on the SDRAM write buffer */ - writeb(0x11, &sc520_mmcr->dbctl); - - /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); -} - /* * Miscellaneous platform dependent initializations */ int board_early_init_f(void) { - init_sc520_enet(); - writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/cpu.c | 14 ++++++++++++-- arch/i386/cpu/sc520/sc520.c | 11 +++-------- arch/i386/include/asm/u-boot-i386.h | 2 ++ board/eNET/eNET.c | 22 ---------------------- 4 files changed, 17 insertions(+), 32 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/sc520/sc520.c | 2 +- arch/i386/cpu/sc520/sc520_asm.S | 49 ++++++++++++++++--------------------- arch/i386/include/asm/ic/sc520.h | 36 ++++++++++++++++++++++----- board/eNET/eNET_start16.S | 7 +++-- 4 files changed, 55 insertions(+), 39 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index b99408c..7caa4c8 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; * unsigned long init_sc520_dram(void) */
-volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000; +sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
int cpu_init_f(void) { diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S index 63c14b7..9f6cce3 100644 --- a/arch/i386/cpu/sc520/sc520_asm.S +++ b/arch/i386/cpu/sc520/sc520_asm.S @@ -142,16 +142,9 @@ */
#include <config.h> +#include <asm/ic/sc520.h>
.section .text -.equ DRCCTL, 0x0fffef010 /* DRAM control register */ -.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */ -.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */ -.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */ -.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */ -.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */ -.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */ - .equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */ .equ COL11_ADR, 0x0e001e00 /* 11 col addrs */ .equ COL10_ADR, 0x0e000e00 /* 10 col addrs */ @@ -179,27 +172,27 @@ mem_init:
/* initialize dram controller registers */ xorw %ax, %ax - movl $DBCTL, %edi + movl $SC520_DBCTL, %edi movb %al, (%edi) /* disable write buffer */
- movl $ECCCTL, %edi + movl $SC520_ECCCTL, %edi movb %al, (%edi) /* disable ECC */
- movl $DRCTMCTL, %edi + movl $SC520_DRCTMCTL, %edi movb $0x1e, %al /* Set SDRAM timing for slowest */ movb %al, (%edi)
/* setup loop to do 4 external banks starting with bank 3 */ movl $0xff000000, %eax /* enable last bank and setup */ - movl $DRCBENDADR, %edi /* ending address register */ + movl $SC520_DRCBENDADR, %edi /* ending address register */ movl %eax, (%edi)
- movl $DRCCFG, %edi /* setup */ + movl $SC520_DRCCFG, %edi /* setup */ movw $0xbbbb, %ax /* dram config register for */ movw %ax, (%edi)
/* issue a NOP to all DRAMs */ - movl $DRCCTL, %edi /* setup DRAM control register with */ + movl $SC520_DRCCTL, %edi /* setup DRAM control register with */ movb $0x01, %al /* Disable refresh,disable write buffer */ movb %al, (%edi) movl $CACHELINESZ, %esi /* just a dummy address to write for */ @@ -409,7 +402,7 @@ bad_reint: /* * issue all banks precharge */ - movl $DRCCTL, %esi /* setup DRAM control register with */ + movl $SC520_DRCCTL, %esi /* setup DRAM control register with */ movb $0x02, %al /* All banks precharge */ movb %al, (%esi) movl $CACHELINESZ, %esi /* address to init read buffer */ @@ -418,7 +411,7 @@ bad_reint: /* * update ENDING ADDRESS REGISTER */ - movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ movl %ecx, %ebx addl %ebx, %edi movb %dh, (%edi) @@ -435,7 +428,7 @@ bad_reint: shlw %cl, %bx notw %bx xchgw %cx, %ax - movl $DRCCFG, %edi + movl $SC520_DRCCFG, %edi movw (%edi), %ax andw %bx, %ax orw %dx, %ax @@ -444,7 +437,7 @@ bad_reint:
decw %cx movl %ecx, %ebx - movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ movb $0xff, %al addl %ebx, %edi movb %al, (%edi) @@ -452,7 +445,7 @@ bad_reint: /* * set control register to NORMAL mode */ - movl $DRCCTL, %esi /* setup DRAM control register with */ + movl $SC520_DRCCTL, %esi /* setup DRAM control register with */ movb $0x00, %al /* Normal mode value */ movb %al, (%esi) movl $CACHELINESZ, %esi /* address to init read buffer */ @@ -460,7 +453,7 @@ bad_reint: jmp nextbank
cleanup: - movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ movw $0x04, %cx xorw %ax, %ax cleanuplp: @@ -482,7 +475,7 @@ emptybank:
#if defined CONFIG_SYS_SDRAM_DRCTMCTL /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $DRCTMCTL, %edi + movl $SC520_DRCTMCTL, %edi movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al movb %al, (%edi) #else @@ -491,7 +484,7 @@ emptybank: * Set the CAS latency now since it is hard to do * when we run from the RAM */ - movl $DRCTMCTL, %edi /* DRAM timing register */ + movl $SC520_DRCTMCTL, %edi /* DRAM timing register */ movb (%edi), %al #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T andb $0xef, %al @@ -502,13 +495,13 @@ emptybank: movb %al, (%edi) #endif #endif - movl $DRCCTL, %edi /* DRAM Control register */ + movl $SC520_DRCCTL, %edi /* DRAM Control register */ movb $0x03, %al /* Load mode register cmd */ movb %al, (%edi) movw %ax, (%esi)
- movl $DRCCTL, %edi /* DRAM Control register */ + movl $SC520_DRCCTL, %edi /* DRAM Control register */ movb $0x18, %al /* Enable refresh and NORMAL mode */ movb %al, (%edi)
@@ -553,16 +546,16 @@ set_ecc:
/* enable read, write buffers */ movb $0x11, %al - movl $DBCTL, %edi + movl $SC520_DBCTL, %edi movb %al, (%edi)
/* enable NMI mapping for ECC */ - movl $ECCINT, %edi + movl $SC520_ECCINT, %edi movb $0x10, %al movb %al, (%edi)
/* Turn on ECC */ - movl $ECCCTL, %edi + movl $SC520_ECCCTL, %edi movb $0x05, %al movb %al,(%edi)
@@ -576,7 +569,7 @@ out: */ .globl get_mem_size get_mem_size: - movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */
bank0: movl (%edi), %eax movl %eax, %ecx diff --git a/arch/i386/include/asm/ic/sc520.h b/arch/i386/include/asm/ic/sc520.h index 053d9c6..5e7fb47 100644 --- a/arch/i386/include/asm/ic/sc520.h +++ b/arch/i386/include/asm/ic/sc520.h @@ -252,16 +252,38 @@ typedef struct sc520_mmcr { u8 pad_0xdc0[0x0240]; } sc520_mmcr_t;
-extern volatile sc520_mmcr_t *sc520_mmcr; +extern sc520_mmcr_t *sc520_mmcr;
#endif
-/* MMCR Offsets (required for assembler code */ -#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ -#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ -#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ -#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ -#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ +/* Memory Mapped Control Registers (MMCR) Base Address */ +#define SC520_MMCR_BASE 0xfffef000 + +/* MMCR Addresses (required for assembler code) */ +#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010) +#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012) +#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014) +#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018) +#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020) +#define SC520_DBCTL (SC520_MMCR_BASE + 0x040) +#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18) + +#define SC520_PAR0 (SC520_MMCR_BASE + 0x088) +#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1)) +#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2)) +#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3)) +#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4)) +#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5)) +#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6)) +#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7)) +#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8)) +#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9)) +#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10)) +#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11)) +#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12)) +#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13)) +#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14)) +#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
/* MMCR Register bits (not all of them :) ) */
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 06cfd55..183309c 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -30,6 +30,7 @@ /* #include <asm/ic/sc520_defs.h> */
#include "hardware.h" +#include <asm/ic/sc520.h>
.text .section .start16, "ax" @@ -46,17 +47,17 @@ board_init16: movw %ax, %ds
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */ - movl $0x00c0, %edi /* SC520_PAR14 */ + movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi movl $0x8bfff800, %eax /* TODO: Check this */ movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */ - movl $0x00c4, %edi /* SC520_PAR15 */ + movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi movl $0x38201000, %eax movl %eax, (%di)
/* Disable SDRAM write buffer */ - movw $0x0040, %di /* SC520_DBCTL */ + movw $(SC520_DBCTL - SC520_MMCR_BASE), %di xorw %ax, %ax movb %al, (%di)
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/sc520.c | 2 +- arch/i386/cpu/sc520/sc520_asm.S | 49 ++++++++++++++++--------------------- arch/i386/include/asm/ic/sc520.h | 36 ++++++++++++++++++++++----- board/eNET/eNET_start16.S | 7 +++-- 4 files changed, 55 insertions(+), 39 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/sc520/sc520.c | 19 ------------------- board/eNET/eNET.c | 9 +++++++++ 2 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 7caa4c8..19a678d 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -42,25 +42,6 @@ sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
int cpu_init_f(void) { - /* - * Set the UARTxCTL register at it's slower, - * baud clock giving us a 1.8432 MHz reference - */ - writeb(0x07, &sc520_mmcr->uart1ctl); - writeb(0x07, &sc520_mmcr->uart2ctl); - - /* first set the timer pin mapping */ - writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */ - - /* enable PCI bus arbiter (concurrent mode) */ - writeb(0x02, &sc520_mmcr->sysarbctl); - - /* enable external grants */ - writeb(0x1f, &sc520_mmcr->sysarbmenb); - - /* enable posted-writes */ - writeb(0x04, &sc520_mmcr->hbctl); - if (CONFIG_SYS_SC520_HIGH_SPEED) { /* set it to 133 MHz and write back */ writeb(0x02, &sc520_mmcr->cpuctl); diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 30d8750..b2f349f 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -94,12 +94,21 @@ int board_early_init_f(void) writew(0x0615, &sc520_mmcr->romcs1ctl); writew(0x0615, &sc520_mmcr->romcs2ctl);
+ /* + * Set the timer pin mapping + * no clock frequency selected, use 1.1892MHz + */ + writeb(0x72, &sc520_mmcr->clksel); + writeb(0x00, &sc520_mmcr->adddecctl); writeb(0x07, &sc520_mmcr->uart1ctl); writeb(0x07, &sc520_mmcr->uart2ctl); writeb(0x06, &sc520_mmcr->sysarbctl); writew(0x0003, &sc520_mmcr->sysarbmenb);
+ /* enable posted-writes */ + writeb(0x04, &sc520_mmcr->hbctl); + return 0; }
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/sc520.c | 19 ------------------- board/eNET/eNET.c | 9 +++++++++ 2 files changed, 9 insertions(+), 19 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
In later patches, cpu_init_f will be called before console has been initialised and printf will not be legitimately available
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/sc520/sc520.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 19a678d..76de6be 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -46,11 +46,9 @@ int cpu_init_f(void) /* set it to 133 MHz and write back */ writeb(0x02, &sc520_mmcr->cpuctl); gd->cpu_clk = 133000000; - printf("## CPU Speed set to 133MHz\n"); } else { /* set it to 100 MHz and write back */ writeb(0x01, &sc520_mmcr->cpuctl); - printf("## CPU Speed set to 100MHz\n"); gd->cpu_clk = 100000000; }
On 04/02/11 23:35, Graeme Russ wrote:
In later patches, cpu_init_f will be called before console has been initialised and printf will not be legitimately available
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/sc520.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Fix minor issues with the configuration of the hardware interrupts for Linux when booting the eNET board
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- board/eNET/eNET.c | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index b2f349f..3b74ce9 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -191,10 +191,18 @@ void setup_pcat_compatibility() */ writew(0x0000,&sc520_mmcr->intpinpol);
- /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ + /* + * PIT 0 -> IRQ0 + * RTC -> IRQ8 + * FP error -> IRQ13 + * UART1 -> IRQ4 + * UART2 -> IRQ3 + */ writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); + writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]); + writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
/* Disable all other interrupt sources */ writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); @@ -202,11 +210,6 @@ void setup_pcat_compatibility() writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
On 04/02/11 23:35, Graeme Russ wrote:
Fix minor issues with the configuration of the hardware interrupts for Linux when booting the eNET board
Signed-off-by: Graeme Russ graeme.russ@gmail.com
board/eNET/eNET.c | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
The SC520 has an inbuilt MC146818 - Enable it for the eNET board
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- drivers/rtc/mc146818.c | 6 ++++++ include/configs/eNET.h | 2 ++ 2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index ac4eb6a..59f6765 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -31,6 +31,12 @@ #include <command.h> #include <rtc.h>
+#ifdef __I386__ +#include <asm/io.h> +#define in8(p) inb(p) +#define out8(p, v) outb(v, p) +#endif + #if defined(CONFIG_CMD_DATE)
static uchar rtc_read (uchar reg); diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 78cab29..082f681 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -33,6 +33,7 @@ * Stuff still to be dealt with - */ #define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
/* * High Level Configuration Options @@ -91,6 +92,7 @@ #define CONFIG_CMD_BDI /* bdinfo */ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_DATE #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */
On 04/02/11 23:35, Graeme Russ wrote:
The SC520 has an inbuilt MC146818 - Enable it for the eNET board
Signed-off-by: Graeme Russ graeme.russ@gmail.com
drivers/rtc/mc146818.c | 6 ++++++ include/configs/eNET.h | 2 ++ 2 files changed, 8 insertions(+), 0 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- board/eNET/eNET.c | 104 +++++++----- board/eNET/eNET_start16.S | 5 +- include/configs/eNET.h | 382 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 445 insertions(+), 46 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 3b74ce9..546406a 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -53,36 +53,57 @@ static void enet_toggle_run_led(void); */ int board_early_init_f(void) { - writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ - writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ - writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */ - writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */ - writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */ - writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */ - writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */ - - writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */ - writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */ - writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */ - writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */ - writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */ - writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */ - writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */ - - writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ - writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ - writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ - writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ - writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */ - writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ - writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ - writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */ - writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */ - writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ - writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */ - writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */ -/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */ -/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ + u16 pio_out_cfg = 0x0000; + + /* Configure General Purpose Bus timing */ + writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt); + writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw); + writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff); + writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw); + writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff); + writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw); + writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff); + + /* Configure Programmable Input/Output Pins */ + writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0); + writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16); + writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16); + writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0); + writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs); + writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel); + + /* + * Turn off top board + * Set StrataFlash chips to 16-bit width + * Set StrataFlash chips to normal (non reset/power down) mode + */ + pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR; + pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH; + pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE; + pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE; + writew(pio_out_cfg, &sc520_mmcr->pioset15_0); + + /* Turn off auxiliary power output */ + writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0); + + /* Clear FPGA program mode */ + writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16); + + /* Configure Programmable Address Regions */ + writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]); + writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]); + writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]); + writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]); + writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]); + writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[7]); + writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[8]); + writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]); + writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]); + writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]); + writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]); + writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]); +/* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */ +/* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
/* Disable Watchdog */ writew(0x3333, &sc520_mmcr->wdtmrctl); @@ -90,24 +111,19 @@ int board_early_init_f(void) writew(0x0000, &sc520_mmcr->wdtmrctl);
/* Chip Select Configuration */ - writew(0x0033, &sc520_mmcr->bootcsctl); - writew(0x0615, &sc520_mmcr->romcs1ctl); - writew(0x0615, &sc520_mmcr->romcs2ctl); + writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl); + writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl); + writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
- /* - * Set the timer pin mapping - * no clock frequency selected, use 1.1892MHz - */ - writeb(0x72, &sc520_mmcr->clksel); + writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl); + writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl); + writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
- writeb(0x00, &sc520_mmcr->adddecctl); - writeb(0x07, &sc520_mmcr->uart1ctl); - writeb(0x07, &sc520_mmcr->uart2ctl); - writeb(0x06, &sc520_mmcr->sysarbctl); - writew(0x0003, &sc520_mmcr->sysarbmenb); + writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl); + writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
/* enable posted-writes */ - writeb(0x04, &sc520_mmcr->hbctl); + writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
return 0; } diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 183309c..4835936 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -29,6 +29,7 @@
/* #include <asm/ic/sc520_defs.h> */
+#include "config.h" #include "hardware.h" #include <asm/ic/sc520.h>
@@ -48,12 +49,12 @@ board_init16:
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */ movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi - movl $0x8bfff800, %eax /* TODO: Check this */ + movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */ movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi - movl $0x38201000, %eax + movl $CONFIG_SYS_SC520_LLIO_PAR, %eax movl %eax, (%di)
/* Disable SDRAM write buffer */ diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 082f681..efdc168 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -247,6 +247,388 @@ #define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ #define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
+/*----------------------------------------------------------------------- + * BOOTCS Control (for AM29LV040B-120JC) + * + * 000 0 00 0 000 11 0 011 }- 0x0033 + * \ / | | | \ / | | \ / + * | | | | | | | | + * | | | | | | | +---- 3 Wait States (First Access) + * | | | | | | +------- Reserved + * | | | | | +--------- 3 Wait States (Subsequent Access) + * | | | | +------------- Reserved + * | | | +---------------- Non-Paged Mode + * | | +------------------ 8 Bit Wide + * | +--------------------- GP Bus + * +------------------------ Reserved + */ +#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033 + +/*----------------------------------------------------------------------- + * ROMCS Control (for E28F128J3A-150 StrataFlash) + * + * 000 0 01 1 000 01 0 101 }- 0x0615 + * \ / | | | \ / | | \ / + * | | | | | | | | + * | | | | | | | +---- 5 Wait States (First Access) + * | | | | | | +------- Reserved + * | | | | | +--------- 1 Wait State (Subsequent Access) + * | | | | +------------- Reserved + * | | | +---------------- Paged Mode + * | | +------------------ 16 Bit Wide + * | +--------------------- GP Bus + * +------------------------ Reserved + */ +#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615 +#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615 + +/*----------------------------------------------------------------------- + * SC520 General Purpose Bus configuration + * + * Chip Select Offset 1 Clock Cycle + * Chip Select Pulse Width 8 Clock Cycles + * Chip Select Read Offset 2 Clock Cycles + * Chip Select Read Width 6 Clock Cycles + * Chip Select Write Offset 2 Clock Cycles + * Chip Select Write Width 6 Clock Cycles + * Chip Select Recovery Time 2 Clock Cycles + * + * Timing Diagram (from SC520 Register Set Manual - Order #22005B) + * + * |<-------------General Purpose Bus Cycle---------------->| + * | | + * ----------------------__________________/------------------ + * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> | + * + * ------------------------_______________/------------------- + * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->| + * + * --------------------------_______________/----------------- + * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->| + * + * ________/-----------_______________________________________ + * |<--->|<--------->| + * ^ ^ + * (GPALEOFF + 1) | + * | + * (GPALEW + 1) + */ +#define CONFIG_SYS_SC520_GPCSOFF 0x00 +#define CONFIG_SYS_SC520_GPCSPW 0x07 +#define CONFIG_SYS_SC520_GPRDOFF 0x01 +#define CONFIG_SYS_SC520_GPRDW 0x05 +#define CONFIG_SYS_SC520_GPWROFF 0x01 +#define CONFIG_SYS_SC520_GPWRW 0x05 +#define CONFIG_SYS_SC520_GPCSRT 0x01 + +/*----------------------------------------------------------------------- + * SC520 Programmable I/O configuration + * + * Pin Mode Dir. Description + * ---------------------------------------------------------------------- + * PIO0 PIO Output Unused + * PIO1 GPBHE# Output GP Bus Byte High Enable (active low) + * PIO2 PIO Output Auxiliary power output enable + * PIO3 GPAEN Output GP Bus Address Enable + * PIO4 PIO Output Top Board Enable (active low) + * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode) + * PIO6 PIO Input Data output of Power Supply ADC + * PIO7 PIO Output Clock input to Power Supply ADC + * PIO8 PIO Output Chip Select input of Power Supply ADC + * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low) + * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low) + * PIO11 PIO Input StrataFlash 1 Status + * PIO12 PIO Input StrataFlash 2 Status + * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low) + * PIO14 PIO Input Low Input Voltage Warning (active low) + * PIO15 PIO Output Watchdog (must toggle at least every 1.6s) + * PIO16 PIO Input Power Fail + * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low) + * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low) + * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low) + * PIO20 GPIRQ3 Input UART D IRQ + * PIO21 GPIRQ2 Input UART C IRQ + * PIO22 GPIRQ1 Input UART B IRQ + * PIO23 GPIRQ0 Input UART A IRQ + * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable + * PIO25 PIO Input Battery OK Indication + * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access + * PIO27 GPCS0# Output SRAM 1 Chip Select + * PIO28 PIO Input Top Board UART CTS + * PIO29 PIO Output FPGA Program Mode (active low) + * PIO30 PIO Input FPGA Initialised (active low) + * PIO31 PIO Input FPGA Done (active low) + */ +#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a +#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe +#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf +#define CONFIG_SYS_SC520_PIODIR31_16 0x2900 + +/*----------------------------------------------------------------------- + * PIO Pin defines + */ +#define CONFIG_SYS_ENET_AUX_PWR 0x0004 +#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010 +#define CONFIG_SYS_ENET_SF_WIDTH 0x0020 +#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040 +#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080 +#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100 +#define CONFIG_SYS_ENET_SF1_MODE 0x0200 +#define CONFIG_SYS_ENET_SF2_MODE 0x0400 +#define CONFIG_SYS_ENET_SF1_STATUS 0x0800 +#define CONFIG_SYS_ENET_SF2_STATUS 0x1000 +#define CONFIG_SYS_ENET_PWR_STATUS 0x4000 +#define CONFIG_SYS_ENET_WATCHDOG 0x8000 + +#define CONFIG_SYS_ENET_PWR_FAIL 0x0001 +#define CONFIG_SYS_ENET_BAT_OK 0x0200 +#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000 +#define CONFIG_SYS_ENET_FPGA_PROG 0x2000 +#define CONFIG_SYS_ENET_FPGA_INIT 0x4000 +#define CONFIG_SYS_ENET_FPGA_DONE 0x8000 + +/*----------------------------------------------------------------------- + * Chip Select Pin Function Select + * + * 1 1 1 1 1 0 0 0 }- 0xf8 + * | | | | | | | | + * | | | | | | | +--- Reserved + * | | | | | | +----- GPCS1_SEL = ROMCS1# + * | | | | | +------- GPCS2_SEL = ROMCS2# + * | | | | +--------- GPCS3_SEL = GPCS3 + * | | | +----------- GPCS4_SEL = GPCS4 + * | | +------------- GPCS5_SEL = GPCS5 + * | +--------------- GPCS6_SEL = GPCS6 + * +----------------- GPCS7_SEL = GPCS7 + */ +#define CONFIG_SYS_SC520_CSPFS 0xf8 + +/*----------------------------------------------------------------------- + * Clock Select (CLKTIMER[CLKTEST] pin) + * + * 0 111 00 1 0 }- 0x72 + * | \ / | | | + * | | | | +--- Pin Disabled + * | | | +----- Pin is an output + * | | +------- Reserved + * | +----------- Disabled (pin stays Low) + * +-------------- Reserved + */ +#define CONFIG_SYS_SC520_CLKSEL 0x72 + +/*----------------------------------------------------------------------- + * Address Decode Control + * + * 0 00 0 0 0 0 0 }- 0x00 + * | | | | | | | + * | | | | | | +--- Integrated UART 1 is enabled + * | | | | | +----- Integrated UART 2 is enabled + * | | | | +------- Integrated RTC is enabled + * | | | +--------- Reserved + * | | +----------- I/O Hole accesses are forwarded to the external GP bus + * | +------------- Reserved + * +---------------- Write-protect violations do not generate an IRQ + */ +#define CONFIG_SYS_SC520_ADDDECCTL 0x00 + +/*----------------------------------------------------------------------- + * UART Control + * + * 00000 1 1 1 }- 0x07 + * ___/ | | | + * | | | +--- Transmit TC interrupt enable + * | | +----- Receive TC interrupt enable + * | +------- 1.8432 MHz + * +----------- Reserved + */ +#define CONFIG_SYS_SC520_UART1CTL 0x07 +#define CONFIG_SYS_SC520_UART2CTL 0x07 + +/*----------------------------------------------------------------------- + * System Arbiter Control + * + * 00000 1 1 0 }- 0x06 + * ___/ | | | + * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt + * | | +----- The system arbiter operates in concurrent mode + * | +------- Park the PCI bus on the last master that acquired the bus + * +----------- Reserved + */ +#define CONFIG_SYS_SC520_SYSARBCTL 0x06 + +/*----------------------------------------------------------------------- + * System Arbiter Master Enable + * + * 00000000000 0 0 0 1 1 }- 0x06 + * _________/ | | | | | + * | | | | | +--- PCI master REQ0 enabled (Ethernet 1) + * | | | | +----- PCI master REQ1 enabled (Ethernet 2) + * | | | +------- PCI master REQ2 disabled + * | | +--------- PCI master REQ3 disabled + * | +----------- PCI master REQ4 disabled + * +------------------ Reserved + */ +#define CONFIG_SYS_SC520_SYSARBMENB 0x0003 + +/*----------------------------------------------------------------------- + * System Arbiter Master Enable + * + * 0 0000 0 00 0000 1 000 }- 0x06 + * | __/ | | __/ | _/ + * | | | | | | +---- Reserved + * | | | | | +------- Enable CPU-to-PCI bus write posting + * | | | | +---------- Reserved + * | | | +-------------- PCI bus reads to SDRAM are not automatically + * | | | retried + * | | +----------------- Target read FIFOs are not snooped during write + * | | transactions + * | +-------------------- Reserved + * +------------------------ Deassert the PCI bus reset signal + */ +#define CONFIG_SYS_SC520_HBCTL 0x08 + +/*----------------------------------------------------------------------- + * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS + * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800 + * \ / | | | | ----+----/ -----+------/ + * | | | | | | +---------- Start at 0x38000000 + * | | | | | +----------------------- 512kB Region Size + * | | | | | ((7 + 1) * 64kB) + * | | | | +------------------------------ 64kB Page Size + * | | | +-------------------------------- Writes Enabled (So it can be + * | | | reprogrammed!) + * | | +---------------------------------- Caching Disabled + * | +------------------------------------ Execution Enabled + * +--------------------------------------- BOOTCS + */ +#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800 + +/*----------------------------------------------------------------------- + * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6 + * + * 001 110 0 000100000 0001000000000000 }- 0x38201000 + * \ / \ / | ---+---/ ------+-------/ + * | | | | +----------- Start at 0x00001000 + * | | | +------------------------ 33 Bytes (0x20 + 1) + * | | +------------------------------ Ignored + * | +--------------------------------- GPCS6 + * +------------------------------------- GP Bus I/O + */ +#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000 + +/*----------------------------------------------------------------------- + * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5 + * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7 + * + * 010 101 0 0000000 100000000000000000 }- 0x54020000 + * 010 111 0 0000000 100000000000000001 }- 0x5c020001 + * \ / \ / | --+--/ -------+--------/ + * | | | | +------------ Start at 0x200000000 + * | | | | 0x200010000 + * | | | +------------------------- 4kB Region Size + * | | | ((0 + 1) * 4kB) + * | | +------------------------------ 4k Page Size + * | +--------------------------------- GPCS5 + * | GPCS7 + * +------------------------------------- GP Bus Memory + */ +#define CONFIG_SYS_SC520_CF1_PAR 0x54020000 +#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001 + +/*----------------------------------------------------------------------- + * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0 + * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3 + * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4 + * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5 + * + * 001 000 0 000000111 0001001111111000 }- 0x200713f8 + * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8 + * 001 011 0 000000111 0001001011111000 }- 0x300711f8 + * 001 011 0 000000111 0001001011111000 }- 0x340710f8 + * \ / \ / | ---+---/ ------+-------/ + * | | | | +----------- Start at 0x013f8 + * | | | | 0x012f8 + * | | | | 0x011f8 + * | | | | 0x010f8 + * | | | +------------------------ 33 Bytes (32 + 1) + * | | +------------------------------ Ignored + * | +--------------------------------- GPCS6 + * +------------------------------------- GP Bus I/O + */ +#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8 +#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8 +#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8 +#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8 + +/*----------------------------------------------------------------------- + * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1 + * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2 + * + * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000 + * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100 + * \ / | | | | ----+----/ -----+------/ + * | | | | | | +---------- Start at 0x10000000 + * | | | | | | 0x11000000 + * | | | | | +----------------------- 16MB Region Size + * | | | | | ((255 + 1) * 64kB) + * | | | | +------------------------------ 64kB Page Size + * | | | +-------------------------------- Writes Enabled + * | | +---------------------------------- Caching Disabled + * | +------------------------------------ Execution Enabled + * +--------------------------------------- ROMCS1 + * ROMCS2 + */ +#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000 +#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100 + +/*----------------------------------------------------------------------- + * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0 + * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3 + * + * 010 000 1 00000001111 01100100000000 }- 0x4203d900 + * 010 011 1 00000001111 01100100010000 }- 0x4e03d910 + * \ / \ / | ----+----/ -----+------/ + * | | | | +---------- Start at 0x19000000 + * | | | | 0x19100000 + * | | | +----------------------- 1MB Region Size + * | | | ((15 + 1) * 64kB) + * | | +------------------------------ 64kB Page Size + * | +--------------------------------- GPCS0 + * | GPCS3 + * +------------------------------------- GP Bus Memory + */ +#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900 +#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910 + +/*----------------------------------------------------------------------- + * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4 + * + * 010 100 0 00000000 11000000100000000 }- 0x50018100 + * \ / \ / | ---+--/ -------+-------/ + * | | | | +----------- Start at 0x18100000 + * | | | +------------------------ 4kB Region Size + * | | | ((0 + 1) * 4kB) + * | | +------------------------------ 4kB Page Size + * | +--------------------------------- GPCS4 + * +------------------------------------- GP Bus Memory + */ +#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100 + +/*----------------------------------------------------------------------- + * PAR for SDRAM - 128MB @ 0x00000000 + * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000 + * \ / | | | | ----+----/ -----+------/ + * | | | | | | +---------- Start at 0x00000000 + * | | | | | +----------------------- 128MB Region Size + * | | | | | ((2047 + 1) * 64kB) + * | | | | +------------------------------ 64kB Page Size + * | | | +-------------------------------- Writes Enabled + * | | +---------------------------------- Caching Enabled + * | +------------------------------------ Execution Enabled + * +--------------------------------------- SDRAM + */ +#define CONFIG_SYS_SC520_SDRAM_PAR 0xe3ffc000 + #ifndef __ASSEMBLER__ extern unsigned long ip;
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
board/eNET/eNET.c | 104 +++++++----- board/eNET/eNET_start16.S | 5 +- include/configs/eNET.h | 382 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 445 insertions(+), 46 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- board/eNET/eNET.c | 61 ++++++++++++++++++++++++++++++++++++----------- include/configs/eNET.h | 15 ----------- 2 files changed, 46 insertions(+), 30 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 546406a..8e11acf 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -47,6 +47,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
static void enet_timer_isr(void); static void enet_toggle_run_led(void); +static void enet_setup_pars(void);
/* * Miscellaneous platform dependent initializations @@ -89,21 +90,7 @@ int board_early_init_f(void) /* Clear FPGA program mode */ writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
- /* Configure Programmable Address Regions */ - writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]); - writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]); - writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]); - writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]); - writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]); - writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[7]); - writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[8]); - writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]); - writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]); - writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]); - writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]); - writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]); -/* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */ -/* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */ + enet_setup_pars();
/* Disable Watchdog */ writew(0x3333, &sc520_mmcr->wdtmrctl); @@ -128,6 +115,50 @@ int board_early_init_f(void) return 0; }
+static void enet_setup_pars(void) +{ + /* + * PARs 11 and 12 are 2MB SRAM @ 0x19000000 + * + * These are setup now because older version of U-Boot have them + * mapped to a different PAR which gets clobbered which prevents + * using SRAM for warm-booting a new image + */ + writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]); + writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]); + + /* PARs 0 and 1 are Compact Flash slots (4kB each) */ + writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]); + writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]); + + /* PAR 2 is used for Cache-As-RAM */ + + /* + * PARs 5 through 8 are additional NS16550 UARTS + * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8 + */ + writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]); + writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]); + writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]); + writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]); + + /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */ + writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]); + writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]); + + /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */ + writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]); + + /* + * PAR 14 is Low Level I/O (LEDs, Hex Switches etc) + * Already configured in board_init16 (eNET_start16.S) + * + * PAR 15 is Boot ROM + * Already configured in board_init16 (eNET_start16.S) + */ +} + + int board_early_init_r(void) { /* CPU Speed to 100MHz */ diff --git a/include/configs/eNET.h b/include/configs/eNET.h index efdc168..faeb52f 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -614,21 +614,6 @@ */ #define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
-/*----------------------------------------------------------------------- - * PAR for SDRAM - 128MB @ 0x00000000 - * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000 - * \ / | | | | ----+----/ -----+------/ - * | | | | | | +---------- Start at 0x00000000 - * | | | | | +----------------------- 128MB Region Size - * | | | | | ((2047 + 1) * 64kB) - * | | | | +------------------------------ 64kB Page Size - * | | | +-------------------------------- Writes Enabled - * | | +---------------------------------- Caching Enabled - * | +------------------------------------ Execution Enabled - * +--------------------------------------- SDRAM - */ -#define CONFIG_SYS_SC520_SDRAM_PAR 0xe3ffc000 - #ifndef __ASSEMBLER__ extern unsigned long ip;
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
board/eNET/eNET.c | 61 ++++++++++++++++++++++++++++++++++++----------- include/configs/eNET.h | 15 ----------- 2 files changed, 46 insertions(+), 30 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- board/eNET/eNET.c | 17 +-- board/eNET/eNET_start.S | 7 - include/configs/eNET.h | 290 ++++++++++++++++++++--------------------------- 3 files changed, 129 insertions(+), 185 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 8e11acf..e64a395 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -35,16 +35,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#undef SC520_CDP_DEBUG - -#ifdef SC520_CDP_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; - static void enet_timer_isr(void); static void enet_toggle_run_led(void); static void enet_setup_pars(void); @@ -199,22 +189,23 @@ int last_stage_init(void)
outb(0x00, LED_LATCH_ADDRESS);
- register_timer_isr (enet_timer_isr); + register_timer_isr(enet_timer_isr);
printf("Serck Controls eNET\n");
return 0; }
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) { if (banknum == 0) { /* non-CFI boot flash */ info->portwidth = FLASH_CFI_8BIT; info->chipwidth = FLASH_CFI_BY8; info->interface = FLASH_CFI_X8; return 1; - } else + } else { return 0; + } }
int board_eth_init(bd_t *bis) diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S index 137fe41..1b3d289 100644 --- a/board/eNET/eNET_start.S +++ b/board/eNET/eNET_start.S @@ -29,10 +29,3 @@ early_board_init: /* No 32-bit board specific initialisation */ jmp early_board_init_ret
-.globl cpu_halt_asm -cpu_halt_asm: - movb $0x0f, %al - movw $LED_LATCH_ADDRESS, %dx - outb %al, %dx - hlt - jmp cpu_halt_asm diff --git a/include/configs/eNET.h b/include/configs/eNET.h index faeb52f..b018f8b 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -30,123 +30,113 @@ #define __CONFIG_H
/* - * Stuff still to be dealt with - - */ -#define CONFIG_RTC_MC146818 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 - -/* * High Level Configuration Options * (easy to change) */ -#define DEBUG_PARSER - -#define CONFIG_X86 1 /* Intel X86 CPU */ -#define CONFIG_SYS_SC520 1 /* AMD SC520 */ +#define CONFIG_X86 +#define CONFIG_SYS_SC520 #define CONFIG_SYS_SC520_SSI -#define CONFIG_SHOW_BOOT_PROGRESS 1 -#define CONFIG_LAST_STAGE_INIT 1 +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_LAST_STAGE_INIT
-/* - * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the +/*----------------------------------------------------------------------- + * Watchdog Configuration + * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the * bottom (processor) board MUST be removed! */ #undef CONFIG_WATCHDOG #define CONFIG_HW_WATCHDOG
- /*----------------------------------------------------------------------- - * Serial Configuration - */ +/*----------------------------------------------------------------------- + * Real Time Clock Configuration + */ +#define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 + +/*----------------------------------------------------------------------- + * Serial Configuration + */ #define CONFIG_SERIAL_MULTI -#define CONFIG_CONS_INDEX 1 +#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 1843200 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) -#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 1843200 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ + 9600, 19200, 38400, 115200} +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_NS16550_COM2 UART1_BASE +#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) +#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) #define CONFIG_SYS_NS16550_PORT_MAPPED
- /*----------------------------------------------------------------------- - * Video Configuration - */ -#undef CONFIG_VIDEO /* No Video Hardware */ -#undef CONFIG_CFB_CONSOLE - -/* - * Size of malloc() pool +/*----------------------------------------------------------------------- + * Video Configuration */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE
/*----------------------------------------------------------------------- * Command line configuration. */ #include <config_cmd_default.h>
-#define CONFIG_CMD_BDI /* bdinfo */ -#define CONFIG_CMD_BOOTD /* bootd */ -#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO /* echo arguments */ -#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#define CONFIG_CMD_FPGA /* FPGA configuration Support */ -#define CONFIG_CMD_IMI /* iminfo */ -#define CONFIG_CMD_IMLS /* List all found images */ -#define CONFIG_CMD_IRQ /* IRQ Information */ -#define CONFIG_CMD_ITEST /* Integer (and string) test */ -#define CONFIG_CMD_LOADB /* loadb */ -#define CONFIG_CMD_LOADS /* loads */ -#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ -#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#undef CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_PCI /* PCI support */ -#define CONFIG_CMD_PING /* ICMP echo support */ -#define CONFIG_CMD_RUN /* run command in env variable */ -#define CONFIG_CMD_SAVEENV /* saveenv */ -#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ -#define CONFIG_CMD_SOURCE /* "source" command Support */ -#define CONFIG_CMD_XIMG /* Load part of Multi Image */ - -#define CONFIG_BOOTDELAY 15 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" -/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SETGETDCR +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_XIMG + +#define CONFIG_BOOTDELAY 15 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#define CONFIG_KGDB_BAUDRATE 115200 +#define CONFIG_KGDB_SER_INDEX 2 #endif
/* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + \ - 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "boot > " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1kHz */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01000000 +#define CONFIG_SYS_LOAD_ADDR 0x100000 +#define CONFIG_SYS_HZ 1000
/*----------------------------------------------------------------------- * SDRAM Configuration */ -#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 -#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 +#define CONFIG_NR_DRAM_BANKS 4
/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY @@ -158,96 +148,79 @@ /*----------------------------------------------------------------------- * CPU Features */ -#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#define CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */ -#define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */ -#undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */ -#undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */ -#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those - * in the SC520 on the CDP */ +#define CONFIG_SYS_SC520_HIGH_SPEED 0 +#define CONFIG_SYS_SC520_RESET +#define CONFIG_SYS_SC520_TIMER +#undef CONFIG_SYS_GENERIC_TIMER #define CONFIG_SYS_PCAT_INTERRUPTS -#define CONFIG_SYS_NUM_IRQS 16 +#define CONFIG_SYS_NUM_IRQS 16
/*----------------------------------------------------------------------- - * Memory organization + * Memory organization: + * 32kB Stack + * 256kB Monitor */ -#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */ -#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */ -#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */ -#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */ -#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_STACK_SIZE 0x8000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
- /*----------------------------------------------------------------------- - * FLASH configuration - */ -#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ +/*----------------------------------------------------------------------- + * FLASH configuration + * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000) + * 16MB StrataFlash #1 @ 0x10000000 + * 16MB StrataFlash #2 @ 0x11000000 + */ +#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_1, \ - CONFIG_SYS_FLASH_BASE_2} +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_MAX_FLASH_BANKS 3 +#define CONFIG_SYS_FLASH_BASE 0x38000000 +#define CONFIG_SYS_FLASH_BASE_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE_2 0x11000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE_1, \ + CONFIG_SYS_FLASH_BASE_2} #define CONFIG_SYS_FLASH_EMPTY_INFO #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_LEGACY_512Kx8 +#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
- /*----------------------------------------------------------------------- - * Environment configuration - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 +/*----------------------------------------------------------------------- + * Environment configuration + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 /* Redundant Copy */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE - - - /*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -#define CONFIG_SYS_FIRST_PCI_IRQ 10 -#define CONFIG_SYS_SECOND_PCI_IRQ 9 -#define CONFIG_SYS_THIRD_PCI_IRQ 11 -#define CONFIG_SYS_FORTH_PCI_IRQ 15 - - /* +#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE + +/*----------------------------------------------------------------------- + * PCI configuration + */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_SYS_FIRST_PCI_IRQ 10 +#define CONFIG_SYS_SECOND_PCI_IRQ 9 +#define CONFIG_SYS_THIRD_PCI_IRQ 11 +#define CONFIG_SYS_FORTH_PCI_IRQ 15 + +/*----------------------------------------------------------------------- * Network device (TRL8100B) support */ #define CONFIG_NET_MULTI #define CONFIG_RTL8139
/*----------------------------------------------------------------------- - * FPGA configuration - */ -#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000 -#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000 -#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000 -#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16 -#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16 -#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16 -#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16 -#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */ -#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */ -#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ -#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */ - -/*----------------------------------------------------------------------- * BOOTCS Control (for AM29LV040B-120JC) * * 000 0 00 0 000 11 0 011 }- 0x0033 @@ -614,17 +587,4 @@ */ #define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
-#ifndef __ASSEMBLER__ -extern unsigned long ip; - -#define PRINTIP asm ("call 0\n" \ - "0:\n" \ - "pop %%eax\n" \ - "movl %%eax, %0\n" \ - :"=r"(ip) \ - : /* No Input Registers */ \ - :"%eax"); \ - printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__); - -#endif #endif /* __CONFIG_H */
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
board/eNET/eNET.c | 17 +-- board/eNET/eNET_start.S | 7 - include/configs/eNET.h | 290 ++++++++++++++++++++--------------------------- 3 files changed, 129 insertions(+), 185 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/start.S | 12 +++++----- arch/i386/include/asm/global_data.h | 7 +++++- arch/i386/lib/board.c | 36 +++++++++++++++++++++++----------- include/configs/eNET.h | 3 ++ 4 files changed, 39 insertions(+), 19 deletions(-)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 97bac8f..0ce9713 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -127,13 +127,13 @@ mem_ok: /* Set the upper memory limit parameter */ subl $CONFIG_SYS_STACK_SIZE, %eax
- /* Reserve space for global data */ - subl $(GD_SIZE * 4), %eax + /* Pointer to temporary global data */ + movl $CONFIG_SYS_INIT_GD_ADDR, %edx
- /* %eax points to the global data structure */ - movl %esp, (GD_RAM_SIZE * 4)(%eax) - movl %ebx, (GD_FLAGS * 4)(%eax) - movl %ecx, (GD_LOAD_OFF * 4)(%eax) + /* %edx points to the global data structure */ + movl %esp, (GD_RAM_SIZE * 4)(%edx) + movl %ebx, (GD_FLAGS * 4)(%edx) + movl %ecx, (GD_LOAD_OFF * 4)(%edx)
call board_init_f /* Enter, U-boot! */
diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index e9000c3..cd067f5 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -87,7 +87,12 @@ extern gd_t *gd; #define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ #define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
- +#if 0 #define DECLARE_GLOBAL_DATA_PTR +#else +#define XTRN_DECLARE_GLOBAL_DATA_PTR extern +#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ +gd_t *gd +#endif
#endif /* __ASM_GBL_DATA_H */ diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 2cadce8..4227312 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -45,7 +45,15 @@ #include <miiphy.h> #endif
-DECLARE_GLOBAL_DATA_PTR; +/* + * Pointer to initial global data area + * + * Here we initialize it. + */ +#undef XTRN_DECLARE_GLOBAL_DATA_PTR +#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ +DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); +
/* Exports from the Linker Script */ extern ulong __text_start; @@ -168,7 +176,7 @@ gd_t *gd; /* * Load U-Boot into RAM, initialize BSS, perform relocation adjustments */ -void board_init_f (ulong gdp) +void board_init_f(ulong mem_top) { void *text_start = &__text_start; void *data_end = &__data_end; @@ -187,11 +195,11 @@ void board_init_f (ulong gdp) Elf32_Rel *re_end;
/* Calculate destination RAM Address and relocation offset */ - dest_addr = (void *)gdp - (bss_end - text_start); + dest_addr = (void *)mem_top - (bss_end - text_start); rel_offset = text_start - dest_addr;
/* Perform low-level initialization only when cold booted */ - if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) { + if (gd->flags & GD_FLG_COLD_BOOT) { /* First stage CPU initialization */ if (cpu_init_f() != 0) hang(); @@ -203,8 +211,8 @@ void board_init_f (ulong gdp)
/* Copy U-Boot into RAM */ dst_addr = (ulong *)dest_addr; - src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off); - end_addr = (ulong *)(data_end + ((gd_t *)gdp)->load_off); + src_addr = (ulong *)(text_start + gd->load_off); + end_addr = (ulong *)(data_end + gd->load_off);
while (src_addr < end_addr) *dst_addr++ = *src_addr++; @@ -217,8 +225,8 @@ void board_init_f (ulong gdp) *dst_addr++ = 0x00000000;
/* Perform relocation adjustments */ - re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off); - re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off); + re_src = (Elf32_Rel *)(rel_dyn_start + gd->load_off); + re_end = (Elf32_Rel *)(rel_dyn_end + gd->load_off);
do { if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) @@ -226,11 +234,11 @@ void board_init_f (ulong gdp) *(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset; } while (re_src++ < re_end);
- ((gd_t *)gdp)->reloc_off = rel_offset; - ((gd_t *)gdp)->flags |= GD_FLG_RELOC; + gd->reloc_off = rel_offset; + gd->flags |= GD_FLG_RELOC;
/* Enter the relocated U-Boot! */ - (board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr); + (board_init_r - rel_offset)(gd, (ulong)dest_addr);
/* NOTREACHED - board_init_f() does not return */ while(1); @@ -242,11 +250,15 @@ void board_init_r(gd_t *id, ulong dest_addr) int i; ulong size; static bd_t bd_data; + static gd_t gd_data; init_fnc_t **init_fnc_ptr;
show_boot_progress(0x21);
- gd = id; + /* Global data pointer is now writable */ + gd = &gd_data; + memcpy(gd, id, sizeof(gd_t)); + /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory");
diff --git a/include/configs/eNET.h b/include/configs/eNET.h index b018f8b..5249ea2 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -164,6 +164,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +/* Address of temporary Global Data */ +#define CONFIG_SYS_INIT_GD_ADDR 0x19040000 +
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/start.S | 12 +++++----- arch/i386/include/asm/global_data.h | 7 +++++- arch/i386/lib/board.c | 36 +++++++++++++++++++++++----------- include/configs/eNET.h | 3 ++ 4 files changed, 39 insertions(+), 19 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/sc520/Makefile | 1 + arch/i386/cpu/sc520/sc520_asm.S | 6 +- arch/i386/cpu/sc520/sc520_car.S | 94 +++++++++++++++++++++++++++++++++++++++ arch/i386/cpu/start.S | 35 +++++++------- include/configs/eNET.h | 20 ++++++++ 5 files changed, 135 insertions(+), 21 deletions(-) create mode 100644 arch/i386/cpu/sc520/sc520_car.S
diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile index b962b02..3c25cba 100644 --- a/arch/i386/cpu/sc520/Makefile +++ b/arch/i386/cpu/sc520/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o +SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S index 9f6cce3..901aa61 100644 --- a/arch/i386/cpu/sc520/sc520_asm.S +++ b/arch/i386/cpu/sc520/sc520_asm.S @@ -515,7 +515,7 @@ bad_ram: dram_done: /* Restore Boot Flags */ movl %ebx, %ebp - jmp mem_init_ret + ret
#if CONFIG_SYS_SDRAM_ECC_ENABLE .globl init_ecc @@ -560,7 +560,7 @@ set_ecc: movb %al,(%edi)
out: - jmp init_ecc_ret + ret #endif
/* @@ -605,4 +605,4 @@ bank3: movl (%edi), %eax
done: movl %edx, %eax - jmp get_mem_size_ret + ret diff --git a/arch/i386/cpu/sc520/sc520_car.S b/arch/i386/cpu/sc520/sc520_car.S new file mode 100644 index 0000000..22f5225 --- /dev/null +++ b/arch/i386/cpu/sc520/sc520_car.S @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2010 + * Graeme Russ graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <asm/processor-flags.h> +#include <asm/ic/sc520.h> + +.section .text + +.globl car_init +car_init: + /* + * How to enable Cache-As-RAM for the AMD Elan SC520: + * 1. Turn off the CPU Cache (may not be strictly required) + * 2. Set code execution PAR (usually the BOOTCS region) to be + * non-cachable + * 3. Create a Cachable PAR Region for an area of memory which is + * a) NOT where the code is being executed + * b) NOT SDRAM (Controller not initialised yet) + * c) WILL response to read requests + * The easiest way to do this is to create a second BOOTCS + * PAR mappnig with an address != the PAR in step 2 + * 4. Issue a wbinvd to invalidate the CPU cache + * 5. Turn on the CPU Cache + * 6. Read 16kB from the cached PAR region setup in step 3 + * 7. Turn off the CPU Cache (but DO NOT issue a wbinvd) + * + * The following code uses PAR2 as the cached PAR (PAR0 and PAR1 + * are avoided as these are the only two PARs which can be used + * as PCI BUS Memory regions which the board might require) + * + * The configuration of PAR2 must be set in the board configuration + * file as CONFIG_SYS_SC520_CAR_PAR + */ + + /* Configure Cache-As-RAM PAR */ + movl $CONFIG_SYS_SC520_CAR_PAR, %eax + movl $SC520_PAR2, %edi + movl %eax, (%edi) + + /* Trash the cache then turn it on */ + wbinvd + movl %cr0, %eax + andl $~(X86_CR0_NW | X86_CR0_CD), %eax + movl %eax, %cr0 + + /* + * The cache is now enabled and empty. Map a region of memory to + * it by reading that region. + */ + movl $CONFIG_SYS_CAR_ADDR, %esi + movl $CONFIG_SYS_CAR_SIZE, %ecx + shrl $2, %ecx /* we are reading longs */ + cld + rep lodsl + + /* Turn off the cache, but don't trash it */ + movl %cr0, %eax + orl $(X86_CR0_NW | X86_CR0_CD), %eax + movl %eax, %cr0 + + /* Clear the CAR region */ + xorl %eax, %eax + movl $CONFIG_SYS_CAR_ADDR, %edi + movl $CONFIG_SYS_CAR_SIZE, %ecx + shrl $2, %ecx /* we are writing longs */ + rep stosl + + /* + * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of + * Cache-As-RAM + */ + jmp car_init_ret diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 0ce9713..df9ca0d 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -72,41 +72,40 @@ _start: .globl early_board_init_ret early_board_init_ret:
+ /* Initialise Cache-As-RAM */ + jmp car_init +.globl car_init_ret +car_init_ret: + /* + * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, + * or fully initialised SDRAM - we really don't care which) + * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack + */ + movl $CONFIG_SYS_INIT_SP_ADDR, %esp + /* Skip memory initialization if not starting from cold-reset */ movl %ebx, %ecx andl $GD_FLG_COLD_BOOT, %ecx jz skip_mem_init
/* size memory */ - jmp mem_init -.globl mem_init_ret -mem_init_ret: + call mem_init
skip_mem_init: /* fetch memory size (into %eax) */ - jmp get_mem_size -.globl get_mem_size_ret -get_mem_size_ret: + call get_mem_size + movl %eax, %esp
#if CONFIG_SYS_SDRAM_ECC_ENABLE /* Skip ECC initialization if not starting from cold-reset */ movl %ebx, %ecx andl $GD_FLG_COLD_BOOT, %ecx - jz init_ecc_ret - jmp init_ecc + jz skip_ecc_init + call init_ecc
-.globl init_ecc_ret -init_ecc_ret: +skip_init_ecc: #endif
- /* Check we have enough memory for stack */ - movl $CONFIG_SYS_STACK_SIZE, %ecx - cmpl %ecx, %eax - jb die -mem_ok: - /* Set stack pointer to upper memory limit*/ - movl %eax, %esp - /* Test the stack */ pushl $0 popl %ecx diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 5249ea2..5c09bb5 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -161,6 +161,10 @@ * 256kB Monitor */ #define CONFIG_SYS_STACK_SIZE 0x8000 +#define CONFIG_SYS_CAR_ADDR 0x19200000 +#define CONFIG_SYS_CAR_SIZE 0x00004000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \ + CONFIG_SYS_CAR_SIZE) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) @@ -480,6 +484,22 @@ #define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
/*----------------------------------------------------------------------- + * Cache-As-RAM (Targets Boot Flash) + * + * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200 + * \ / | | | | --+--/ -------+--------/ + * | | | | | | +------------ Start at 0x19200000 + * | | | | | +------------------------- 64k Region Size + * | | | | | ((15 + 1) * 4kB) + * | | | | +------------------------------ 4kB Page Size + * | | | +-------------------------------- Writes Enabled + * | | +---------------------------------- Caching Enabled + * | +------------------------------------ Execution Prevented + * +--------------------------------------- BOOTCS + */ +#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200 + +/*----------------------------------------------------------------------- * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6 * * 001 110 0 000100000 0001000000000000 }- 0x38201000
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/Makefile | 1 + arch/i386/cpu/sc520/sc520_asm.S | 6 +- arch/i386/cpu/sc520/sc520_car.S | 94 +++++++++++++++++++++++++++++++++++++++ arch/i386/cpu/start.S | 35 +++++++------- include/configs/eNET.h | 20 ++++++++ 5 files changed, 135 insertions(+), 21 deletions(-) create mode 100644 arch/i386/cpu/sc520/sc520_car.S
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/sc520/Makefile | 2 +- arch/i386/cpu/sc520/sc520.c | 110 ------- arch/i386/cpu/sc520/sc520_asm.S | 608 ------------------------------------- arch/i386/cpu/sc520/sc520_sdram.c | 532 ++++++++++++++++++++++++++++++++ arch/i386/cpu/start.S | 48 +-- arch/i386/include/asm/ic/sc520.h | 57 ++++ arch/i386/lib/board.c | 10 +- board/eNET/eNET.c | 6 - board/eNET/eNET_start16.S | 5 - include/configs/eNET.h | 2 +- 10 files changed, 612 insertions(+), 768 deletions(-) delete mode 100644 arch/i386/cpu/sc520/sc520_asm.S create mode 100644 arch/i386/cpu/sc520/sc520_sdram.c
diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile index 3c25cba..54260b6 100644 --- a/arch/i386/cpu/sc520/Makefile +++ b/arch/i386/cpu/sc520/Makefile @@ -33,10 +33,10 @@ LIB := $(obj)lib$(SOC).o
COBJS-$(CONFIG_SYS_SC520) += sc520.o COBJS-$(CONFIG_PCI) += sc520_pci.o +COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
-SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 76de6be..d5597ca 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -31,13 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* - * utility functions for boards based on the AMD sc520 - * - * void init_sc520(void) - * unsigned long init_sc520_dram(void) - */ - sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
int cpu_init_f(void) @@ -65,109 +58,6 @@ int cpu_init_f(void) return x86_cpu_init_f(); }
-unsigned long init_sc520_dram(void) -{ - bd_t *bd = gd->bd; - - u32 dram_present=0; - u32 dram_ctrl; - -#ifdef CONFIG_SYS_SDRAM_DRCTMCTL - /* these memory control registers are set up in the assember part, - * in sc520_asm.S, during 'mem_init'. If we muck with them here, - * after we are running a stack in RAM, we have troubles. Besides, - * these refresh and delay values are better ? simply specified - * outright in the include/configs/{cfg} file since the HW designer - * simply dictates it. - */ -#else - u8 tmp; - u8 val; - - int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; - int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; - int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY; - - /* set SDRAM speed here */ - - refresh_rate /= 78; - if (refresh_rate <= 1) { - val = 0; /* 7.8us */ - } else if (refresh_rate == 2) { - val = 1; /* 15.6us */ - } else if (refresh_rate == 3 || refresh_rate == 4) { - val = 2; /* 31.2us */ - } else { - val = 3; /* 62.4us */ - } - - tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4); - writeb(tmp, &sc520_mmcr->drcctl); - - val = readb(&sc520_mmcr->drctmctl) & 0xf0; - - if (cas_precharge_delay==3) { - val |= 0x04; /* 3T */ - } else if (cas_precharge_delay==4) { - val |= 0x08; /* 4T */ - } else if (cas_precharge_delay>4) { - val |= 0x0c; - } - - if (ras_cas_delay > 3) { - val |= 2; - } else { - val |= 1; - } - writeb(val, &c520_mmcr->drctmctl); -#endif - - /* - * We read-back the configuration of the dram - * controller that the assembly code wrote - */ - dram_ctrl = readl(&sc520_mmcr->drcbendadr); - - bd->bi_dram[0].start = 0; - if (dram_ctrl & 0x80) { - /* bank 0 enabled */ - dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; - bd->bi_dram[0].size = bd->bi_dram[1].start; - } else { - bd->bi_dram[0].size = 0; - bd->bi_dram[1].start = bd->bi_dram[0].start; - } - - if (dram_ctrl & 0x8000) { - /* bank 1 enabled */ - dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; - bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start; - } else { - bd->bi_dram[1].size = 0; - bd->bi_dram[2].start = bd->bi_dram[1].start; - } - - if (dram_ctrl & 0x800000) { - /* bank 2 enabled */ - dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; - bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start; - } else { - bd->bi_dram[2].size = 0; - bd->bi_dram[3].start = bd->bi_dram[2].start; - } - - if (dram_ctrl & 0x80000000) { - /* bank 3 enabled */ - dram_present = (dram_ctrl & 0x7f000000) >> 2; - bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start; - } else { - bd->bi_dram[3].size = 0; - } - gd->ram_size = dram_present; - - return dram_present; -} - #ifdef CONFIG_SYS_SC520_RESET void reset_cpu(ulong addr) { diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S deleted file mode 100644 index 901aa61..0000000 --- a/arch/i386/cpu/sc520/sc520_asm.S +++ /dev/null @@ -1,608 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This file is largely based on code obtned from AMD. AMD's original - * copyright is included below - */ - -/* TITLE SIZER - Aspen DRAM Sizing Routine. - * ============================================================================= - * - * Copyright 1999 Advanced Micro Devices, Inc. - * You may redistribute this program and/or modify this program under the terms - * of the GNU General Public License as published by the Free Software Foundation; - * either version 2 of the License, or (at your option) any later version. - * - * This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED - * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. - * - * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY - * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF - * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. - * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS - * INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY - * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR - * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE - * LIMITATION MAY NOT APPLY TO YOU. - * - * AMD does not assume any responsibility for any errors that may appear in - * the Materials nor any responsibility to support or update the Materials. - * AMD retains the right to make changes to its test specifications at any - * time, without notice. - * ============================================================================== - */ - -/* - ****************************************************************************** - * - * FILE : sizer.asm - SDRAM DIMM Sizing Algorithm - * - * - * - * FUNCTIONS : sizemem() - jumped to, not called. To be executed after - * reset to determine the size of the SDRAM DIMMs. Initializes - * the memory subsystem. - * - * - * AUTHOR : Buddy Fey - Original. - * - * - * DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor. - * NOTE: This is a small memory model version - * - * - * INPUTS : BP contains return address offset - * CACHE is assumed to be disabled. - * The FS segment limit has already been set to big real mode - * (full 32-bit addressing capability) - * - * - * OUTPUTS : None - * - * - * REG USE : ax,bx,cx,dx,di,si,bp, fs - * - * - * REVISION : See PVCS info below - * - * - * TEST PLAN CROSS REFERENCE: - * - * - * $Workfile: $ - * $Revision: 1.2 $ - * $Date: 1999/09/22 12:49:33 $ - * $Author: chipf $ - * $Log: sizer.asm $ - * Revision 1.2 1999/09/22 12:49:33 chipf - * Add legal header - * - ******************************************************************************* - */ - - -/******************************************************************************* - * FUNCTIONAL DESCRIPTION: - * This routine is called to autodetect the geometry of the DRAM. - * - * This routine is called to determine the number of column bits for the DRAM - * devices in this external bank. This routine assumes that the external bank - * has been configured for an 11-bit column and for 4 internal banks. This gives - * us the maximum address reach in memory. By writing a test value to the max - * address and locating where it aliases to, we can determine the number of valid - * column bits. - * - * This routine is called to determine the number of internal banks each DRAM - * device has. The external bank (under test) is configured for maximum reach - * with 11-bit columns and 4 internal banks. This routine will write to a max - * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if - * that column is a "don't care". If BA1 does not affect write/read of data, - * then this device has only 2 internal banks. - * - * This routine is called to determine the ending address for this external - * bank of SDRAM. We write to a max address with a data value and then disable - * row address bits looking for "don't care" locations. Each "don't care" bit - * represents a dividing of the maximum density (128M) by 2. By dividing the - * maximum of 32 4M chunks in an external bank down by all the "don't care" bits - * determined during sizing, we set the proper density. - * - * WARNINGS. - * bp must be preserved because it is used for return linkage. - * - * EXIT - * nothing returned - but the memory subsystem is enabled - ******************************************************************************* - */ - -#include <config.h> -#include <asm/ic/sc520.h> - -.section .text -.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */ -.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */ -.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */ -.equ COL09_ADR, 0x0e000600 /* 9 col addrs */ -.equ COL08_ADR, 0x0e000200 /* 8 col addrs */ -.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */ -.equ ROW13_ADR, 0x07000000 /* 13 row addrs */ -.equ ROW12_ADR, 0x03000000 /* 12 row addrs */ -.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */ -.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */ -.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */ -.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */ -.equ COL09_DATA, 0x09090909 /* 9 col data */ -.equ COL08_DATA, 0x08080808 /* 8 col data */ -.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */ -.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */ -.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */ -.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */ -.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */ - -.globl mem_init -mem_init: - /* Preserve Boot Flags */ - movl %ebx, %ebp - - /* initialize dram controller registers */ - xorw %ax, %ax - movl $SC520_DBCTL, %edi - movb %al, (%edi) /* disable write buffer */ - - movl $SC520_ECCCTL, %edi - movb %al, (%edi) /* disable ECC */ - - movl $SC520_DRCTMCTL, %edi - movb $0x1e, %al /* Set SDRAM timing for slowest */ - movb %al, (%edi) - - /* setup loop to do 4 external banks starting with bank 3 */ - movl $0xff000000, %eax /* enable last bank and setup */ - movl $SC520_DRCBENDADR, %edi /* ending address register */ - movl %eax, (%edi) - - movl $SC520_DRCCFG, %edi /* setup */ - movw $0xbbbb, %ax /* dram config register for */ - movw %ax, (%edi) - - /* issue a NOP to all DRAMs */ - movl $SC520_DRCCTL, %edi /* setup DRAM control register with */ - movb $0x01, %al /* Disable refresh,disable write buffer */ - movb %al, (%edi) - movl $CACHELINESZ, %esi /* just a dummy address to write for */ - movw %ax, (%esi) - - /* delay for 100 usec? */ - movw $100, %cx -sizdelay: - loop sizdelay - - /* issue all banks precharge */ - movb $0x02, %al - movb %al, (%edi) - movw %ax, (%esi) - - /* issue 2 auto refreshes to all banks */ - movb $0x04, %al /* Auto refresh cmd */ - movb %al, (%edi) - movw $0x02, %cx -refresh1: - movw %ax, (%esi) - loop refresh1 - - /* issue LOAD MODE REGISTER command */ - movb $0x03, %al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) - - /* issue 8 more auto refreshes to all banks */ - movb $0x04, %al /* Auto refresh cmd */ - movb %al, (%edi) - movw $0x0008, %cx -refresh2: - movw %ax, (%esi) - loop refresh2 - - /* set control register to NORMAL mode */ - movb $0x00, %al /* Normal mode value */ - movb %al, (%edi) - - /* - * size dram starting with external bank 3 - * moving to external bank 0 - */ - movl $0x3, %ecx /* start with external bank 3 */ - -nextbank: - - /* write col 11 wrap adr */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl $COL11_DATA, %eax /* pattern for max supported columns(11) */ - movl %eax, (%esi) /* write max col pattern at max col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write col 10 wrap adr */ - movl $COL10_ADR, %esi /* set address to 10 col wrap address */ - movl $COL10_DATA, %eax /* pattern for 10 col wrap */ - movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write col 9 wrap adr */ - movl $COL09_ADR, %esi /* set address to 9 col wrap address */ - movl $COL09_DATA, %eax /* pattern for 9 col wrap */ - movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write col 8 wrap adr */ - movl $COL08_ADR, %esi /* set address to min(8) col wrap address */ - movl $COL08_DATA, %eax /* pattern for min (8) col wrap */ - movl %eax, (%esi) /* write min col pattern @ min col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write row 14 wrap adr */ - movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */ - movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */ - movl %eax, (%esi) /* write max row pattern at max row adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write row 13 wrap adr */ - movl $ROW13_ADR, %esi /* set address to 13 row wrap address */ - movl $ROW13_DATA, %eax /* pattern for 13 row wrap */ - movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write row 12 wrap adr */ - movl $ROW12_ADR, %esi /* set address to 12 row wrap address */ - movl $ROW12_DATA, %eax /* pattern for 12 row wrap */ - movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* write row 11 wrap adr */ - movl $ROW11_ADR, %edi /* set address to 11 row wrap address */ - movl $ROW11_DATA, %eax /* pattern for 11 row wrap */ - movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* - * write row 10 wrap adr --- this write is really to determine - * number of banks - */ - movl $ROW10_ADR, %edi /* set address to 10 row wrap address */ - movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */ - movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx, %eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - - /* - * read data @ row 12 wrap adr to determine * banks, - * and read data @ row 14 wrap adr to determine * rows. - * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. - * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 - * if data @ row 12 wrap == 11 or 12, we have 4 banks, - */ - xorw %di, %di /* value for 2 banks in DI */ - movl (%esi), %ebx /* read from 12 row wrap to check banks */ - /* (esi is setup from the write to row 12 wrap) */ - cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */ - jz only2 /* if pattern == AA, we only have 2 banks */ - - /* 4 banks */ - - movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */ - cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */ - jz only2 - cmpl $ROW12_DATA, %ebx /* and 12 */ - jnz bad_ram /* its bad if not 11 or 12! */ - - /* fall through */ -only2: - /* - * validate row mask - */ - movl $ROW14_ADR, %esi /* set address back to max row wrap addr */ - movl (%esi), %eax /* read actual number of rows @ row14 adr */ - - cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */ - jb bad_ram - - cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */ - ja bad_ram - - cmpb %ah, %al /* verify all 4 bytes of dword same */ - jnz bad_ram - movl %eax, %ebx - shrl $16, %ebx - cmpw %bx, %ax - jnz bad_ram - - /* - * read col 11 wrap adr for real column data value - */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl (%esi), %eax /* read real col number at max col adr */ - - /* - * validate column data - */ - cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */ - jb bad_ram - - cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */ - ja bad_ram - - subl $COL08_DATA, %eax /* normalize column data to zero */ - jc bad_ram - cmpb %ah, %al /* verify all 4 bytes of dword equal */ - jnz bad_ram - movl %eax, %edx - shrl $16, %edx - cmpw %dx, %ax - jnz bad_ram - - /* - * merge bank and col data together - */ - addw %di, %dx /* merge of bank and col info in dl */ - - /* - * fix ending addr mask based upon col info - */ - movb $0x03, %al - subb %dh, %al /* dh contains the overflow from the bank/col merge */ - movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */ - xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */ - shrb %cl, %dh - incb %dh /* ending addr is 1 greater than real end */ - xchgw %cx, %ax /* cx is bank number again */ - -bad_reint: - /* - * issue all banks precharge - */ - movl $SC520_DRCCTL, %esi /* setup DRAM control register with */ - movb $0x02, %al /* All banks precharge */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) - - /* - * update ENDING ADDRESS REGISTER - */ - movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ - movl %ecx, %ebx - addl %ebx, %edi - movb %dh, (%edi) - - /* - * update CONFIG REGISTER - */ - xorb %dh, %dh - movw $0x000f, %bx - movw %cx, %ax - shlw $2, %ax - xchgw %cx, %ax - shlw %cl, %dx - shlw %cl, %bx - notw %bx - xchgw %cx, %ax - movl $SC520_DRCCFG, %edi - movw (%edi), %ax - andw %bx, %ax - orw %dx, %ax - movw %ax, (%edi) - jcxz cleanup - - decw %cx - movl %ecx, %ebx - movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ - movb $0xff, %al - addl %ebx, %edi - movb %al, (%edi) - - /* - * set control register to NORMAL mode - */ - movl $SC520_DRCCTL, %esi /* setup DRAM control register with */ - movb $0x00, %al /* Normal mode value */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) - jmp nextbank - -cleanup: - movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ - movw $0x04, %cx - xorw %ax, %ax -cleanuplp: - movb (%edi), %al - orb %al, %al - jz emptybank - - addb %ah, %al - jns nottoomuch - - movb $0x7f, %al -nottoomuch: - movb %al, %ah - orb $0x80, %al - movb %al, (%edi) -emptybank: - incl %edi - loop cleanuplp - -#if defined CONFIG_SYS_SDRAM_DRCTMCTL - /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $SC520_DRCTMCTL, %edi - movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al - movb %al, (%edi) -#else -#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T) - /* - * Set the CAS latency now since it is hard to do - * when we run from the RAM - */ - movl $SC520_DRCTMCTL, %edi /* DRAM timing register */ - movb (%edi), %al -#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T - andb $0xef, %al -#endif -#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T - orb $0x10, %al -#endif - movb %al, (%edi) -#endif -#endif - movl $SC520_DRCCTL, %edi /* DRAM Control register */ - movb $0x03, %al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) - - - movl $SC520_DRCCTL, %edi /* DRAM Control register */ - movb $0x18, %al /* Enable refresh and NORMAL mode */ - movb %al, (%edi) - - jmp dram_done - -bad_ram: - xorl %edx, %edx - xorl %edi, %edi - jmp bad_reint - -dram_done: - /* Restore Boot Flags */ - movl %ebx, %ebp - ret - -#if CONFIG_SYS_SDRAM_ECC_ENABLE -.globl init_ecc -init_ecc: - /* A nominal memory test: just a byte at each address line */ - movl %eax, %ecx - shrl $0x1, %ecx - movl $0x1, %edi -memtest0: - movb $0xa5, (%edi) - cmpb $0xa5, (%edi) - jne out - shrl $0x1, %ecx - andl %ecx, %ecx - jz set_ecc - shll $0x1, %edi - jmp memtest0 - -set_ecc: - /* clear all ram with a memset */ - movl %eax, %ecx - xorl %esi, %esi - xorl %edi, %edi - xorl %eax, %eax - shrl $0x2, %ecx - cld - rep stosl - - /* enable read, write buffers */ - movb $0x11, %al - movl $SC520_DBCTL, %edi - movb %al, (%edi) - - /* enable NMI mapping for ECC */ - movl $SC520_ECCINT, %edi - movb $0x10, %al - movb %al, (%edi) - - /* Turn on ECC */ - movl $SC520_ECCCTL, %edi - movb $0x05, %al - movb %al,(%edi) - -out: - ret -#endif - -/* - * Read and decode the sc520 DRCBENDADR MMCR and return the number of - * available ram bytes in %eax - */ -.globl get_mem_size -get_mem_size: - movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */ - -bank0: movl (%edi), %eax - movl %eax, %ecx - andl $0x00000080, %ecx - jz bank1 - andl $0x0000007f, %eax - shll $22, %eax - movl %eax, %edx - -bank1: movl (%edi), %eax - movl %eax, %ecx - andl $0x00008000, %ecx - jz bank2 - andl $0x00007f00, %eax - shll $14, %eax - movl %eax, %edx - -bank2: movl (%edi), %eax - movl %eax, %ecx - andl $0x00800000, %ecx - jz bank3 - andl $0x007f0000, %eax - shll $6, %eax - movl %eax, %edx - -bank3: movl (%edi), %eax - movl %eax, %ecx - andl $0x80000000, %ecx - jz done - andl $0x7f000000, %eax - shrl $2, %eax - movl %eax, %edx - -done: - movl %edx, %eax - ret diff --git a/arch/i386/cpu/sc520/sc520_sdram.c b/arch/i386/cpu/sc520/sc520_sdram.c new file mode 100644 index 0000000..d5ab55d --- /dev/null +++ b/arch/i386/cpu/sc520/sc520_sdram.c @@ -0,0 +1,532 @@ +/* + * (C) Copyright 2010 + * Graeme Russ graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor-flags.h> +#include <asm/ic/sc520.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct sc520_sdram_info { + u8 banks; + u8 columns; + u8 rows; + u8 size; +}; + +static void sc520_sizemem(void); +static void sc520_set_dram_timing(void); +static void sc520_set_dram_refresh_rate(void); +static void sc520_enable_dram_refresh(void); +static void sc520_enable_sdram(void); +#if CONFIG_SYS_SDRAM_ECC_ENABLE +static void sc520_enable_ecc(void) +#endif + +int dram_init_f(void) +{ + sc520_sizemem(); + sc520_set_dram_timing(); + sc520_set_dram_refresh_rate(); + sc520_enable_dram_refresh(); + sc520_enable_sdram(); +#if CONFIG_SYS_SDRAM_ECC_ENABLE + sc520_enable_ecc(); +#endif + + return 0; +} + +static inline void sc520_dummy_write(void) +{ + writew(0x0000, CACHELINESZ); +} +static inline void sc520_issue_sdram_op_mode_select(u8 command) +{ + writeb(command, &sc520_mmcr->drcctl); + sc520_dummy_write(); +} + +static inline int check_long(u32 test_long) +{ + u8 i; + u8 tmp_byte = (u8)(test_long & 0x000000ff); + + for (i = 1; i < 4; i++) { + if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte) + return -1; + } + + return 0; +} + +static inline int write_and_test(u32 data, u32 address) +{ + writel(data, address); + if (readl(address) == data) + return 0; /* Good */ + else + return -1; /* Bad */ +} + +static void sc520_enable_sdram(void) +{ + u32 par_config; + + /* Enable Writes, Caching and Code Execution to SDRAM */ + par_config = readl(&sc520_mmcr->par[3]); + par_config &= ~(SC520_PAR_EXEC_DIS | + SC520_PAR_CACHE_DIS | + SC520_PAR_WRITE_DIS); + writel(par_config, &sc520_mmcr->par[3]); + + par_config = readl(&sc520_mmcr->par[4]); + par_config &= ~(SC520_PAR_EXEC_DIS | + SC520_PAR_CACHE_DIS | + SC520_PAR_WRITE_DIS); + writel(par_config, &sc520_mmcr->par[4]); +} + +static void sc520_set_dram_timing(void) +{ + u8 drctmctl = 0x00; + +#if defined CONFIG_SYS_SDRAM_DRCTMCTL + /* just have your hardware designer _GIVE_ you what you need here! */ + drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL; +#else + switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) { + case 2: + break; + case 3: + drctmctl |= 0x01; + break; + case 4: + default: + drctmctl |= 0x02; + break; + } + + switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) { + case 2: + break; + case 3: + drctmctl |= 0x04; + break; + case 4: + default: + drctmctl |= 0x08; + break; + + case 6: + drctmctl |= 0x0c; + break; + } + + switch (CONFIG_SYS_SDRAM_CAS_LATENCY) { + case 2: + break; + case 3: + default: + drctmctl |= 0x10; + break; + } +#endif + writeb(drctmctl, &sc520_mmcr->drctmctl); + + /* Issue load mode register command */ + sc520_issue_sdram_op_mode_select(0x03); +} + +static void sc520_set_dram_refresh_rate(void) +{ + u8 drctl; + + drctl = readb(&sc520_mmcr->drcctl); + drctl &= 0xcf; + + switch (CONFIG_SYS_SDRAM_REFRESH_RATE) { + case 78: + break; + case 156: + default: + drctl |= 0x10; + break; + case 312: + drctl |= 0x20; + break; + case 624: + drctl |= 0x30; + break; + } + + writeb(drctl, &sc520_mmcr->drcctl); +} + +static void sc520_enable_dram_refresh(void) +{ + u8 drctl; + + drctl = readb(&sc520_mmcr->drcctl); + drctl &= 0x30; /* keep refresh rate */ + drctl |= 0x08; /* enable refresh, normal mode */ + + writeb(drctl, &sc520_mmcr->drcctl); +} + +static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info) +{ + u32 col_data; + u32 row_data; + + u32 drcbendadr; + u16 drccfg; + + u8 banks = 0x00; + u8 columns = 0x00; + u8 rows = 0x00; + + bank_info->banks = 0x00; + bank_info->columns = 0x00; + bank_info->rows = 0x00; + bank_info->size = 0x00; + + if ((bank < 0) || (bank > 3)) { + printf("Bad Bank ID\n"); + return; + } + + /* Save configuration */ + drcbendadr = readl(&sc520_mmcr->drcbendadr); + drccfg = readw(&sc520_mmcr->drccfg); + + /* Setup SDRAM Bank to largest possible size */ + writew(0x000b << (bank * 4), &sc520_mmcr->drccfg); + + /* Set ending address for this bank */ + writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr); + + /* write col 11 wrap adr */ + if (write_and_test(COL11_DATA, COL11_ADR) != 0) + goto restore_and_exit; + + /* write col 10 wrap adr */ + if (write_and_test(COL10_DATA, COL10_ADR) != 0) + goto restore_and_exit; + + /* write col 9 wrap adr */ + if (write_and_test(COL09_DATA, COL09_ADR) != 0) + goto restore_and_exit; + + /* write col 8 wrap adr */ + if (write_and_test(COL08_DATA, COL08_ADR) != 0) + goto restore_and_exit; + + col_data = readl(COL11_ADR); + + /* All four bytes in the read long must be the same */ + if (check_long(col_data) < 0) + goto restore_and_exit; + + if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA)) + columns = (u8)(col_data & 0x000000ff); + else + goto restore_and_exit; + + /* write row 14 wrap adr */ + if (write_and_test(ROW14_DATA, ROW14_ADR) != 0) + goto restore_and_exit; + + /* write row 13 wrap adr */ + if (write_and_test(ROW13_DATA, ROW13_ADR) != 0) + goto restore_and_exit; + + /* write row 12 wrap adr */ + if (write_and_test(ROW12_DATA, ROW12_ADR) != 0) + goto restore_and_exit; + + /* write row 11 wrap adr */ + if (write_and_test(ROW11_DATA, ROW11_ADR) != 0) + goto restore_and_exit; + + if (write_and_test(ROW10_DATA, ROW10_ADR) != 0) + goto restore_and_exit; + + /* + * read data @ row 12 wrap adr to determine number of banks, + * and read data @ row 14 wrap adr to determine number of rows. + * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. + * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 + * if data @ row 12 wrap == 11 or 12, we have 4 banks, + */ + row_data = readl(ROW12_ADR); + + /* All four bytes in the read long must be the same */ + if (check_long(row_data) != 0) + goto restore_and_exit; + + switch (row_data) { + case ROW10_DATA: + banks = 2; + break; + + case ROW11_DATA: + case ROW12_DATA: + banks = 4; + break; + + default: + goto restore_and_exit; + } + + row_data = readl(ROW14_ADR); + + /* All four bytes in the read long must be the same */ + if (check_long(row_data) != 0) + goto restore_and_exit; + + switch (row_data) { + case ROW11_DATA: + case ROW12_DATA: + case ROW13_DATA: + case ROW14_DATA: + rows = (u8)(row_data & 0x000000ff); + break; + + default: + goto restore_and_exit; + } + + bank_info->banks = banks; + bank_info->columns = columns; + bank_info->rows = rows; + + if ((bank_info->banks != 0) && + (bank_info->columns != 0) && + (bank_info->rows != 0)) { + bank_info->size = bank_info->rows; + bank_info->size >>= (11 - bank_info->columns); + bank_info->size++; + } + +restore_and_exit: + /* Restore configuration */ + writel(drcbendadr, &sc520_mmcr->drcbendadr); + writew(drccfg, &sc520_mmcr->drccfg); +} + +static void sc520_setup_sizemem(void) +{ + u8 i; + + /* Disable write buffer */ + writeb(0x00, &sc520_mmcr->dbctl); + + /* Disable ECC */ + writeb(0x00, &sc520_mmcr->eccctl); + + /* Set slowest SDRAM timing */ + writeb(0x1e, &sc520_mmcr->drctmctl); + + /* Issue a NOP to all SDRAM banks */ + sc520_issue_sdram_op_mode_select(0x01); + + /* Delay for 100 microseconds */ + udelay(100); + + /* Issue 'All Banks Precharge' command */ + sc520_issue_sdram_op_mode_select(0x02); + + /* Issue 2 'Auto Refresh Enable' command */ + sc520_issue_sdram_op_mode_select(0x04); + sc520_dummy_write(); + + /* Issue 'Load Mode Register' command */ + sc520_issue_sdram_op_mode_select(0x03); + + /* Issue 8 more 'Auto Refresh Enable' commands */ + sc520_issue_sdram_op_mode_select(0x04); + for (i = 0; i < 7; i++) + sc520_dummy_write(); + + /* Set control register to 'Normal Mode' */ + writeb(0x00, &sc520_mmcr->drcctl); +} + +static void sc520_sizemem(void) +{ + struct sc520_sdram_info sdram_info[4]; + u8 bank_config = 0x00; + u8 end_addr = 0x00; + u16 drccfg = 0x0000; + u32 drcbendadr = 0x00000000; + u8 i; + + /* Use PARs to disable caching of maximum allowable 256MB SDRAM */ + writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]); + writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]); + + sc520_setup_sizemem(); + + gd->ram_size = 0; + + /* Size each SDRAM bank */ + for (i = 0; i <= 3; i++) { + sc520_get_bank_info(i, &sdram_info[i]); + + if (sdram_info[i].banks != 0) { + /* Update Configuration register */ + bank_config = sdram_info[i].columns - 8; + + if (sdram_info[i].banks == 4) + bank_config |= 0x08; + + drccfg |= bank_config << (i * 4); + + /* Update End Address register */ + end_addr += sdram_info[i].size; + drcbendadr |= (end_addr | 0x80) << (i * 8); + + gd->ram_size += sdram_info[i].size << 22; + } + + /* Issue 'All Banks Precharge' command */ + sc520_issue_sdram_op_mode_select(0x02); + + /* Set control register to 'Normal Mode' */ + writeb(0x00, &sc520_mmcr->drcctl); + } + + writel(drcbendadr, &sc520_mmcr->drcbendadr); + writew(drccfg, &sc520_mmcr->drccfg); + + /* Clear PARs preventing caching of SDRAM */ + writel(0x00000000, &sc520_mmcr->par[3]); + writel(0x00000000, &sc520_mmcr->par[4]); +} + +#if CONFIG_SYS_SDRAM_ECC_ENABLE +static void sc520_enable_ecc(void) + + /* A nominal memory test: just a byte at each address line */ + movl %eax, %ecx + shrl $0x1, %ecx + movl $0x1, %edi +memtest0: + movb $0xa5, (%edi) + cmpb $0xa5, (%edi) + jne out + shrl $0x1, %ecx + andl %ecx, %ecx + jz set_ecc + shll $0x1, %edi + jmp memtest0 + +set_ecc: + /* clear all ram with a memset */ + movl %eax, %ecx + xorl %esi, %esi + xorl %edi, %edi + xorl %eax, %eax + shrl $0x2, %ecx + cld + rep stosl + + /* enable read, write buffers */ + movb $0x11, %al + movl $DBCTL, %edi + movb %al, (%edi) + + /* enable NMI mapping for ECC */ + movl $ECCINT, %edi + movb $0x10, %al + movb %al, (%edi) + + /* Turn on ECC */ + movl $ECCCTL, %edi + movb $0x05, %al + movb %al,(%edi) + +out: + jmp init_ecc_ret +} +#endif + +int dram_init(void) +{ + ulong dram_ctrl; + ulong dram_present = 0x00000000; + + /* + * We read-back the configuration of the dram + * controller that the assembly code wrote + */ + dram_ctrl = readl(&sc520_mmcr->drcbendadr); + + gd->bd->bi_dram[0].start = 0; + if (dram_ctrl & 0x80) { + /* bank 0 enabled */ + gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; + dram_present = gd->bd->bi_dram[1].start; + gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start; + } else { + gd->bd->bi_dram[0].size = 0; + gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start; + } + + if (dram_ctrl & 0x8000) { + /* bank 1 enabled */ + gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; + dram_present = gd->bd->bi_dram[2].start; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start - + gd->bd->bi_dram[1].start; + } else { + gd->bd->bi_dram[1].size = 0; + gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start; + } + + if (dram_ctrl & 0x800000) { + /* bank 2 enabled */ + gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; + dram_present = gd->bd->bi_dram[3].start; + gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start - + gd->bd->bi_dram[2].start; + } else { + gd->bd->bi_dram[2].size = 0; + gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start; + } + + if (dram_ctrl & 0x80000000) { + /* bank 3 enabled */ + dram_present = (dram_ctrl & 0x7f000000) >> 2; + gd->bd->bi_dram[3].size = dram_present - + gd->bd->bi_dram[3].start; + } else { + gd->bd->bi_dram[3].size = 0; + } + + gd->ram_size = dram_present; + + return 0; +} diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index df9ca0d..95be5a2 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -82,29 +82,22 @@ car_init_ret: * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack */ movl $CONFIG_SYS_INIT_SP_ADDR, %esp + movl $CONFIG_SYS_INIT_GD_ADDR, %ebp
- /* Skip memory initialization if not starting from cold-reset */ - movl %ebx, %ecx - andl $GD_FLG_COLD_BOOT, %ecx - jz skip_mem_init + /* Set Boot Flags in Global Data */ + movl %ebx, (GD_FLAGS * 4)(%ebp)
- /* size memory */ - call mem_init - -skip_mem_init: - /* fetch memory size (into %eax) */ - call get_mem_size - movl %eax, %esp + /* Determine our load offset (and put in Global Data) */ + call 1f +1: popl %ecx + subl $1b, %ecx + movl %ecx, (GD_LOAD_OFF * 4)(%ebp)
-#if CONFIG_SYS_SDRAM_ECC_ENABLE - /* Skip ECC initialization if not starting from cold-reset */ - movl %ebx, %ecx - andl $GD_FLG_COLD_BOOT, %ecx - jz skip_ecc_init - call init_ecc + /* size memory */ + call dram_init_f
-skip_init_ecc: -#endif + /* Setup stack in SDRAM */ + movl (GD_RAM_SIZE * 4)(%ebp), %esp
/* Test the stack */ pushl $0 @@ -118,21 +111,8 @@ skip_init_ecc:
wbinvd
- /* Determine our load offset */ - call 1f -1: popl %ecx - subl $1b, %ecx - - /* Set the upper memory limit parameter */ - subl $CONFIG_SYS_STACK_SIZE, %eax - - /* Pointer to temporary global data */ - movl $CONFIG_SYS_INIT_GD_ADDR, %edx - - /* %edx points to the global data structure */ - movl %esp, (GD_RAM_SIZE * 4)(%edx) - movl %ebx, (GD_FLAGS * 4)(%edx) - movl %ecx, (GD_LOAD_OFF * 4)(%edx) + /* Set parameter to board_init_f() to boot flags */ + movl (GD_FLAGS * 4)(%ebp), %eax
call board_init_f /* Enter, U-boot! */
diff --git a/arch/i386/include/asm/ic/sc520.h b/arch/i386/include/asm/ic/sc520.h index 5e7fb47..956c1c2 100644 --- a/arch/i386/include/asm/ic/sc520.h +++ b/arch/i386/include/asm/ic/sc520.h @@ -285,6 +285,36 @@ extern sc520_mmcr_t *sc520_mmcr; #define SC520_PAR14 (SC520_PAR0 + (0x04 * 14)) #define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
+/* + * PARs for maximum allowable 256MB of SDRAM @ 0x00000000 + * Two PARs are required due to maximum PAR size of 128MB + * These are used in the SDRAM sizing code to disable caching + * + * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000 + * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800 + * \ / | | | | ----+----/ -----+------/ + * | | | | | | +---------- Start at 0x00000000 + * | | | | | | 0x08000000 + * | | | | | +----------------------- 128MB Region Size + * | | | | | ((2047 + 1) * 64kB) + * | | | | +------------------------------ 64kB Page Size + * | | | +-------------------------------- Writes Enabled + * | | +---------------------------------- Caching Enabled + * | +------------------------------------ Execution Enabled + * +--------------------------------------- SDRAM + */ +#define SC520_SDRAM1_PAR 0xe3ffc000 +#define SC520_SDRAM2_PAR 0xe3ffc800 + +#define SC520_PAR_WRITE_DIS 0x04000000 +#define SC520_PAR_CACHE_DIS 0x08000000 +#define SC520_PAR_EXEC_DIS 0x10000000 + +/* + * Programmable Address Regions to cover 256MB SDRAM (Maximum supported) + * required for DRAM sizing code + */ + /* MMCR Register bits (not all of them :) ) */
/* SSI Stuff */ @@ -315,6 +345,33 @@ extern sc520_mmcr_t *sc520_mmcr; #define UART2_DIS 0x02 /* UART2 Disable */ #define UART1_DIS 0x01 /* UART1 Disable */
+/* + * Defines used for SDRAM Sizing (number of columns and rows) + * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the + * Elan SC520 Microcontroller User's Manual (Order #22004B) + */ +#define CACHELINESZ 0x00000010 + +#define COL11_ADR 0x0e001e00 +#define COL10_ADR 0x0e000e00 +#define COL09_ADR 0x0e000600 +#define COL08_ADR 0x0e000200 +#define COL11_DATA 0x0b0b0b0b +#define COL10_DATA 0x0a0a0a0a +#define COL09_DATA 0x09090909 +#define COL08_DATA 0x08080808 + +#define ROW14_ADR 0x0f000000 +#define ROW13_ADR 0x07000000 +#define ROW12_ADR 0x03000000 +#define ROW11_ADR 0x01000000 +#define ROW10_ADR 0x00000000 +#define ROW14_DATA 0x3f3f3f3f +#define ROW13_DATA 0x1f1f1f1f +#define ROW12_DATA 0x0f0f0f0f +#define ROW11_DATA 0x07070707 +#define ROW10_DATA 0xaaaaaaaa + /* 0x28000000 - 0x3fffffff is used by the flash banks */
/* 0x40000000 - 0xffffffff is not adressable by the SC520 */ diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 4227312..09816df 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engstrï¿œm, Omicron Ceti AB, daniel@omicron.se * * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -176,7 +176,7 @@ gd_t *gd; /* * Load U-Boot into RAM, initialize BSS, perform relocation adjustments */ -void board_init_f(ulong mem_top) +void board_init_f(ulong boot_flags) { void *text_start = &__text_start; void *data_end = &__data_end; @@ -194,8 +194,12 @@ void board_init_f(ulong mem_top) Elf32_Rel *re_src; Elf32_Rel *re_end;
+ gd->flags = boot_flags; + /* Calculate destination RAM Address and relocation offset */ - dest_addr = (void *)mem_top - (bss_end - text_start); + dest_addr = (void *)gd->ram_size; + dest_addr -= CONFIG_SYS_STACK_SIZE; + dest_addr -= (bss_end - text_start); rel_offset = text_start - dest_addr;
/* Perform low-level initialization only when cold booted */ diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index e64a395..dd0ce54 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -160,12 +160,6 @@ int board_early_init_r(void) return 0; }
-int dram_init(void) -{ - init_sc520_dram(); - return 0; -} - void show_boot_progress(int val) { uchar led_mask; diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 4835936..77e5519 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -57,11 +57,6 @@ board_init16: movl $CONFIG_SYS_SC520_LLIO_PAR, %eax movl %eax, (%di)
- /* Disable SDRAM write buffer */ - movw $(SC520_DBCTL - SC520_MMCR_BASE), %di - xorw %ax, %ax - movb %al, (%di) - /* Disabe MMCR alias */ movw $0xfffc, %dx movl $0x000000cb, %eax diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 5c09bb5..50ee73e 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -136,11 +136,11 @@ * SDRAM Configuration */ #define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 +#define CONFIG_SYS_SDRAM_REFRESH_RATE 156 #define CONFIG_NR_DRAM_BANKS 4
/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY -#undef CONFIG_SYS_SDRAM_REFRESH_RATE #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/Makefile | 2 +- arch/i386/cpu/sc520/sc520.c | 110 ------- arch/i386/cpu/sc520/sc520_asm.S | 608 ------------------------------------- arch/i386/cpu/sc520/sc520_sdram.c | 532 ++++++++++++++++++++++++++++++++ arch/i386/cpu/start.S | 48 +-- arch/i386/include/asm/ic/sc520.h | 57 ++++ arch/i386/lib/board.c | 10 +- board/eNET/eNET.c | 6 - board/eNET/eNET_start16.S | 5 - include/configs/eNET.h | 2 +- 10 files changed, 612 insertions(+), 768 deletions(-) delete mode 100644 arch/i386/cpu/sc520/sc520_asm.S create mode 100644 arch/i386/cpu/sc520/sc520_sdram.c
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/start.S | 44 +++++++++++++++++++++++++++++--------------- arch/i386/lib/board.c | 6 ++++-- 2 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 95be5a2..77f0332 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -96,21 +96,6 @@ car_init_ret: /* size memory */ call dram_init_f
- /* Setup stack in SDRAM */ - movl (GD_RAM_SIZE * 4)(%ebp), %esp - - /* Test the stack */ - pushl $0 - popl %ecx - cmpl $0, %ecx - jne die - push $0x55aa55aa - popl %ecx - cmpl $0x55aa55aa, %ecx - jne die - - wbinvd - /* Set parameter to board_init_f() to boot flags */ movl (GD_FLAGS * 4)(%ebp), %eax
@@ -118,6 +103,35 @@ car_init_ret:
/* indicate (lack of) progress */ movw $0x85, %ax + jmp die + +.globl relocate_code +.type relocate_code, @function +relocate_code: + /* + * SDRAM has been initialised, U-Boot code has been copied into + * RAM, BSS has been cleared and relocation adjustments have been + * made. It is now time to jump into the in-RAM copy of U-Boot + * + * %eax = Address of top of stack + * %edx = Address of Global Data + * %ecx = Base address of in-RAM copy of U-Boot + */ + + /* Setup stack in RAM */ + movl %eax, %esp + + /* Setup call address of in-RAM copy of board_init_r() */ + movl $board_init_r, %ebp + subl (GD_RELOC_OFF * 4)(%edx), %ebp + + /* Setup parameters to board_init_r() */ + movl %edx, %eax + movl %ecx, %edx + + /* Jump to in-RAM copy of board_init_r() */ + call *%ebp + die: hlt jmp die hlt diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 09816df..e3869d6 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -189,6 +189,7 @@ void board_init_f(ulong boot_flags) ulong *src_addr; ulong *end_addr;
+ void *addr_sp; void *dest_addr; ulong rel_offset; Elf32_Rel *re_src; @@ -198,6 +199,7 @@ void board_init_f(ulong boot_flags)
/* Calculate destination RAM Address and relocation offset */ dest_addr = (void *)gd->ram_size; + addr_sp = dest_addr; dest_addr -= CONFIG_SYS_STACK_SIZE; dest_addr -= (bss_end - text_start); rel_offset = text_start - dest_addr; @@ -242,9 +244,9 @@ void board_init_f(ulong boot_flags) gd->flags |= GD_FLG_RELOC;
/* Enter the relocated U-Boot! */ - (board_init_r - rel_offset)(gd, (ulong)dest_addr); + relocate_code((ulong)addr_sp, gd, (ulong)dest_addr);
- /* NOTREACHED - board_init_f() does not return */ + /* NOTREACHED - relocate_code() does not return */ while(1); }
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/start.S | 44 +++++++++++++++++++++++++++++--------------- arch/i386/lib/board.c | 6 ++++-- 2 files changed, 33 insertions(+), 17 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/start.S | 3 --- arch/i386/include/asm/u-boot-i386.h | 1 + arch/i386/lib/board.c | 3 +++ 3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 77f0332..fd018bf 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -93,9 +93,6 @@ car_init_ret: subl $1b, %ecx movl %ecx, (GD_LOAD_OFF * 4)(%ebp)
- /* size memory */ - call dram_init_f - /* Set parameter to board_init_f() to boot flags */ movl (GD_FLAGS * 4)(%ebp), %eax
diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h index 80db52f..7b39bd2 100644 --- a/arch/i386/include/asm/u-boot-i386.h +++ b/arch/i386/include/asm/u-boot-i386.h @@ -37,6 +37,7 @@ int register_timer_isr (timer_fnc_t *isr_func);
/* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */ int timer_init(void); +int dram_init_f(void);
/* cpu/.../interrupts.c */ int cpu_init_interrupts(void); diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index e3869d6..1d47a55 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -197,6 +197,9 @@ void board_init_f(ulong boot_flags)
gd->flags = boot_flags;
+ if (dram_init_f() != 0) + hang(); + /* Calculate destination RAM Address and relocation offset */ dest_addr = (void *)gd->ram_size; addr_sp = dest_addr;
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/start.S | 3 --- arch/i386/include/asm/u-boot-i386.h | 1 + arch/i386/lib/board.c | 3 +++ 3 files changed, 4 insertions(+), 3 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/sc520/sc520.c | 7 ++++--- arch/i386/lib/board.c | 17 +++++++---------- 2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index d5597ca..e5dcac6 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -45,15 +45,16 @@ int cpu_init_f(void) gd->cpu_clk = 100000000; }
- /* wait at least one millisecond */ asm("movl $0x2000, %%ecx\n" "0: pushl %%ecx\n" "popl %%ecx\n" "loop 0b\n": : : "ecx");
- /* turn on the SDRAM write buffer */ - writeb(0x11, &sc520_mmcr->dbctl); + if (gd->flags & GD_FLG_COLD_BOOT) { + /* turn on the SDRAM write buffer */ + writeb(0x11, &sc520_mmcr->dbctl); + }
return x86_cpu_init_f(); } diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 1d47a55..73aaadc 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -207,16 +207,13 @@ void board_init_f(ulong boot_flags) dest_addr -= (bss_end - text_start); rel_offset = text_start - dest_addr;
- /* Perform low-level initialization only when cold booted */ - if (gd->flags & GD_FLG_COLD_BOOT) { - /* First stage CPU initialization */ - if (cpu_init_f() != 0) - hang(); - - /* First stage Board initialization */ - if (board_early_init_f() != 0) - hang(); - } + /* First stage CPU initialization */ + if (cpu_init_f() != 0) + hang(); + + /* First stage Board initialization */ + if (board_early_init_f() != 0) + hang();
/* Copy U-Boot into RAM */ dst_addr = (ulong *)dest_addr;
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/sc520.c | 7 ++++--- arch/i386/lib/board.c | 17 +++++++---------- 2 files changed, 11 insertions(+), 13 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/lib/board.c | 15 ++++++++++++--- 1 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 73aaadc..44441a9 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -162,9 +162,6 @@ init_fnc_t *init_sequence[] = { dram_init, /* configure available RAM banks */ interrupt_init, /* set up exceptions */ timer_init, - env_init, /* initialize environment */ - init_baudrate, /* initialze baudrate settings */ - serial_init, /* serial communications setup */ display_banner, display_dram_config,
@@ -197,6 +194,18 @@ void board_init_f(ulong boot_flags)
gd->flags = boot_flags;
+ if (env_init() != 0) + hang(); + + if (init_baudrate() != 0) + hang(); + + if (serial_init() != 0) + hang(); + + if (console_init_f() != 0) + hang(); + if (dram_init_f() != 0) hang();
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/lib/board.c | 15 ++++++++++++--- 1 files changed, 12 insertions(+), 3 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
x86 has always used relocation offset in the opposite sense to the ELF standard - Fix this
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/start.S | 2 +- arch/i386/lib/board.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index fd018bf..0031389 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -120,7 +120,7 @@ relocate_code:
/* Setup call address of in-RAM copy of board_init_r() */ movl $board_init_r, %ebp - subl (GD_RELOC_OFF * 4)(%edx), %ebp + addl (GD_RELOC_OFF * 4)(%edx), %ebp
/* Setup parameters to board_init_r() */ movl %edx, %eax diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 44441a9..02cb67d 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -214,7 +214,7 @@ void board_init_f(ulong boot_flags) addr_sp = dest_addr; dest_addr -= CONFIG_SYS_STACK_SIZE; dest_addr -= (bss_end - text_start); - rel_offset = text_start - dest_addr; + rel_offset = dest_addr - text_start;
/* First stage CPU initialization */ if (cpu_init_f() != 0) @@ -233,8 +233,8 @@ void board_init_f(ulong boot_flags) *dst_addr++ = *src_addr++;
/* Clear BSS */ - dst_addr = (ulong *)(bss_start - rel_offset); - end_addr = (ulong *)(bss_end - rel_offset); + dst_addr = (ulong *)(bss_start + rel_offset); + end_addr = (ulong *)(bss_end + rel_offset);
while (dst_addr < end_addr) *dst_addr++ = 0x00000000; @@ -245,8 +245,8 @@ void board_init_f(ulong boot_flags)
do { if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) - if (*(Elf32_Addr *)(re_src->r_offset - rel_offset) >= CONFIG_SYS_TEXT_BASE) - *(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset; + if (*(Elf32_Addr *)(re_src->r_offset + rel_offset) >= CONFIG_SYS_TEXT_BASE) + *(Elf32_Addr *)(re_src->r_offset + rel_offset) += rel_offset; } while (re_src++ < re_end);
gd->reloc_off = rel_offset;
On 04/02/11 23:35, Graeme Russ wrote:
x86 has always used relocation offset in the opposite sense to the ELF standard - Fix this
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/start.S | 2 +- arch/i386/lib/board.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/include/asm/global_data.h | 12 +++- arch/i386/lib/board.c | 111 +++++++++++++++++++++-------------- 2 files changed, 74 insertions(+), 49 deletions(-)
diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index cd067f5..f8a16d6 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -46,6 +46,8 @@ typedef struct global_data { unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; + unsigned long relocaddr; /* Start address of U-Boot in RAM */ + unsigned long start_addr_sp; /* start_addr_stackpointer */ phys_size_t ram_size; /* RAM size */ unsigned long reset_status; /* reset status register at boot */ void **jt; /* jump table */ @@ -67,11 +69,13 @@ extern gd_t *gd; #define GD_ENV_VALID 7 #define GD_CPU_CLK 8 #define GD_BUS_CLK 9 -#define GD_RAM_SIZE 10 -#define GD_RESET_STATUS 11 -#define GD_JT 12 +#define GD_RELOC_ADDR 10 +#define GD_START_ADDR_SP 11 +#define GD_RAM_SIZE 12 +#define GD_RESET_STATUS 13 +#define GD_JT 14
-#define GD_SIZE 13 +#define GD_SIZE 15
/* * Global Data Flags diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 02cb67d..44e871b 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -170,30 +170,71 @@ init_fnc_t *init_sequence[] = {
gd_t *gd;
-/* - * Load U-Boot into RAM, initialize BSS, perform relocation adjustments - */ -void board_init_f(ulong boot_flags) +static int calculate_relocation_address(void) { void *text_start = &__text_start; - void *data_end = &__data_end; - void *rel_dyn_start = &__rel_dyn_start; - void *rel_dyn_end = &__rel_dyn_end; + void *bss_end = &__bss_end; + void *dest_addr; + ulong rel_offset; + + /* Calculate destination RAM Address and relocation offset */ + dest_addr = (void *)gd->ram_size; + dest_addr -= CONFIG_SYS_STACK_SIZE; + dest_addr -= (bss_end - text_start); + rel_offset = dest_addr - text_start; + + gd->start_addr_sp = gd->ram_size; + gd->relocaddr = (ulong)dest_addr; + gd->reloc_off = rel_offset; + + return 0; +} + +static int copy_uboot_to_ram(void) +{ + ulong *dst_addr = (ulong *)gd->relocaddr; + ulong *src_addr = (ulong *)&__text_start; + ulong *end_addr = (ulong *)&__data_end; + + while (src_addr < end_addr) + *dst_addr++ = *src_addr++; + + return 0; +} + +static int clear_bss(void) +{ void *bss_start = &__bss_start; void *bss_end = &__bss_end;
- ulong *dst_addr; - ulong *src_addr; - ulong *end_addr; + ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off); + ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);;
- void *addr_sp; - void *dest_addr; - ulong rel_offset; - Elf32_Rel *re_src; - Elf32_Rel *re_end; + while (dst_addr < end_addr) + *dst_addr++ = 0x00000000; + + return 0; +}
- gd->flags = boot_flags; +static int do_elf_reloc_fixups(void) +{ + Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start); + Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end); + + do { + if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) + if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE) + *(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off; + } while (re_src++ < re_end); + + return 0; +}
+/* + * Load U-Boot into RAM, initialize BSS, perform relocation adjustments + */ +void board_init_f(ulong boot_flags) +{ if (env_init() != 0) hang();
@@ -209,12 +250,8 @@ void board_init_f(ulong boot_flags) if (dram_init_f() != 0) hang();
- /* Calculate destination RAM Address and relocation offset */ - dest_addr = (void *)gd->ram_size; - addr_sp = dest_addr; - dest_addr -= CONFIG_SYS_STACK_SIZE; - dest_addr -= (bss_end - text_start); - rel_offset = dest_addr - text_start; + if (calculate_relocation_address() != 0) + hang();
/* First stage CPU initialization */ if (cpu_init_f() != 0) @@ -225,35 +262,19 @@ void board_init_f(ulong boot_flags) hang();
/* Copy U-Boot into RAM */ - dst_addr = (ulong *)dest_addr; - src_addr = (ulong *)(text_start + gd->load_off); - end_addr = (ulong *)(data_end + gd->load_off); - - while (src_addr < end_addr) - *dst_addr++ = *src_addr++; - - /* Clear BSS */ - dst_addr = (ulong *)(bss_start + rel_offset); - end_addr = (ulong *)(bss_end + rel_offset); - - while (dst_addr < end_addr) - *dst_addr++ = 0x00000000; + if (copy_uboot_to_ram() != 0) + hang();
- /* Perform relocation adjustments */ - re_src = (Elf32_Rel *)(rel_dyn_start + gd->load_off); - re_end = (Elf32_Rel *)(rel_dyn_end + gd->load_off); + if (clear_bss() != 0) + hang();
- do { - if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) - if (*(Elf32_Addr *)(re_src->r_offset + rel_offset) >= CONFIG_SYS_TEXT_BASE) - *(Elf32_Addr *)(re_src->r_offset + rel_offset) += rel_offset; - } while (re_src++ < re_end); + if (do_elf_reloc_fixups() != 0) + hang();
- gd->reloc_off = rel_offset; gd->flags |= GD_FLG_RELOC;
/* Enter the relocated U-Boot! */ - relocate_code((ulong)addr_sp, gd, (ulong)dest_addr); + relocate_code(gd->start_addr_sp, gd, gd->relocaddr);
/* NOTREACHED - relocate_code() does not return */ while(1);
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/include/asm/global_data.h | 12 +++- arch/i386/lib/board.c | 111 +++++++++++++++++++++-------------- 2 files changed, 74 insertions(+), 49 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/lib/board.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 44e871b..4751e49 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -235,6 +235,14 @@ static int do_elf_reloc_fixups(void) */ void board_init_f(ulong boot_flags) { + /* First stage CPU initialization */ + if (cpu_init_f() != 0) + hang(); + + /* First stage Board initialization */ + if (board_early_init_f() != 0) + hang(); + if (env_init() != 0) hang();
@@ -253,14 +261,6 @@ void board_init_f(ulong boot_flags) if (calculate_relocation_address() != 0) hang();
- /* First stage CPU initialization */ - if (cpu_init_f() != 0) - hang(); - - /* First stage Board initialization */ - if (board_early_init_f() != 0) - hang(); - /* Copy U-Boot into RAM */ if (copy_uboot_to_ram() != 0) hang();
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/lib/board.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/lib/board.c | 70 ++++++++++++++++++++---------------------------- 1 files changed, 29 insertions(+), 41 deletions(-)
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 4751e49..0c37c23 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -156,7 +156,28 @@ static void display_flash_config (ulong size) */ typedef int (init_fnc_t) (void);
-init_fnc_t *init_sequence[] = { +static int calculate_relocation_address(void); +static int copy_uboot_to_ram(void); +static int clear_bss(void); +static int do_elf_reloc_fixups(void); + +init_fnc_t *init_sequence_f[] = { + cpu_init_f, + board_early_init_f, + env_init, + init_baudrate, + serial_init, + console_init_f, + dram_init_f, + calculate_relocation_address, + copy_uboot_to_ram, + clear_bss, + do_elf_reloc_fixups, + + NULL, +}; + +init_fnc_t *init_sequence_r[] = { cpu_init_r, /* basic cpu dependent setup */ board_early_init_r, /* basic board dependent setup */ dram_init, /* configure available RAM banks */ @@ -235,41 +256,12 @@ static int do_elf_reloc_fixups(void) */ void board_init_f(ulong boot_flags) { - /* First stage CPU initialization */ - if (cpu_init_f() != 0) - hang(); - - /* First stage Board initialization */ - if (board_early_init_f() != 0) - hang(); - - if (env_init() != 0) - hang(); - - if (init_baudrate() != 0) - hang(); - - if (serial_init() != 0) - hang(); - - if (console_init_f() != 0) - hang(); - - if (dram_init_f() != 0) - hang(); - - if (calculate_relocation_address() != 0) - hang(); - - /* Copy U-Boot into RAM */ - if (copy_uboot_to_ram() != 0) - hang(); - - if (clear_bss() != 0) - hang(); + init_fnc_t **init_fnc_ptr;
- if (do_elf_reloc_fixups() != 0) - hang(); + for (init_fnc_ptr = init_sequence_f; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) + hang(); + }
gd->flags |= GD_FLG_RELOC;
@@ -283,7 +275,6 @@ void board_init_f(ulong boot_flags) void board_init_r(gd_t *id, ulong dest_addr) { char *s; - int i; ulong size; static bd_t bd_data; static gd_t gd_data; @@ -307,12 +298,9 @@ void board_init_r(gd_t *id, ulong dest_addr) mem_malloc_init((((ulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3, CONFIG_SYS_MALLOC_LEN);
- for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) { - show_boot_progress(0xa130|i); - - if ((*init_fnc_ptr)() != 0) { + for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) hang (); - } } show_boot_progress(0x23);
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/lib/board.c | 70 ++++++++++++++++++++---------------------------- 1 files changed, 29 insertions(+), 41 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- arch/i386/cpu/sc520/sc520.c | 16 +++++++++++----- 1 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index e5dcac6..d0c313b 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -51,14 +51,20 @@ int cpu_init_f(void) "popl %%ecx\n" "loop 0b\n": : : "ecx");
- if (gd->flags & GD_FLG_COLD_BOOT) { - /* turn on the SDRAM write buffer */ - writeb(0x11, &sc520_mmcr->dbctl); - } - return x86_cpu_init_f(); }
+int cpu_init_r(void) +{ + /* Disable the PAR used for CAR */ + writel(0x0000000, &sc520_mmcr->par[2]); + + /* turn on the SDRAM write buffer */ + writeb(0x11, &sc520_mmcr->dbctl); + + return x86_cpu_init_r(); +} + #ifdef CONFIG_SYS_SC520_RESET void reset_cpu(ulong addr) {
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
arch/i386/cpu/sc520/sc520.c | 16 +++++++++++----- 1 files changed, 11 insertions(+), 5 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
Signed-off-by: Graeme Russ graeme.russ@gmail.com --- include/configs/eNET.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 50ee73e..0358b97 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -169,7 +169,7 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Address of temporary Global Data */ -#define CONFIG_SYS_INIT_GD_ADDR 0x19040000 +#define CONFIG_SYS_INIT_GD_ADDR CONFIG_SYS_CAR_ADDR
/* allow to overwrite serial and ethaddr */
On 04/02/11 23:35, Graeme Russ wrote:
Signed-off-by: Graeme Russ graeme.russ@gmail.com
include/configs/eNET.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
Applied to u-boot-x86
Regards,
Graeme
participants (3)
-
Graeme Russ -
Lo�c Minier -
Scott Wood