[U-Boot] [PATCH 0/8] rockchip: rk3188: fixups and armclk speedup
The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup unnecessary slow. We can easily switch to 600MHz without involving the pmic and thus do this in the SPL to also make the rc4-decoding of the U-Boot image faster.
Some smaller fixes also turned up while adding the ARMCLK-support.
It's currently based on Simon's spl-working branch and Kever's spl_early_init patch, as that includes the last missing rk3188 patches and also keeps uboot starting on rk3188.
Tested on a rk3188 radxarock.
Heiko Stuebner (8): rockchip: rk3188: sdram: Set correct sdram base rockchip: rk3188: Decode the actual amount of ram rockchip: rk3188: Cleanup some SPL/TPL rename leftovers rockchip: clk: rk3188: Allow configuration of the armclk rockchip: rk3188: Setup the armclk in spl rockchip: rk3188: Switch to new i2c IP blocks rockchip: i2c: Add compatibles for Rockchip Cortex-A9 socs rockchip: Enable pmic options and act8846 driver on rk3188 rock boards
arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 1 + arch/arm/mach-rockchip/rk3188-board-spl.c | 45 ++++++++++++++++++ arch/arm/mach-rockchip/rk3188-board-tpl.c | 6 +-- arch/arm/mach-rockchip/rk3188-board.c | 18 ++++++- arch/arm/mach-rockchip/rk3188/sdram_rk3188.c | 2 +- configs/rock_defconfig | 4 ++ drivers/clk/rockchip/clk_rk3188.c | 63 +++++++++++++++++++++++++ drivers/i2c/rk_i2c.c | 2 + 8 files changed, 135 insertions(+), 6 deletions(-)
Right now we're setting the wrong value of 0 as base in the ram_info struct, which is obviously wrong for the rk3188. So instead set the correct value we already have in CONFIG_SYS_SDRAM_BASE.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/rk3188/sdram_rk3188.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c index 461cfcdc83..fea8007265 100644 --- a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c @@ -955,7 +955,7 @@ static int rk3188_dmc_probe(struct udevice *dev) if (ret) return ret; #endif - priv->info.base = 0; + priv->info.base = CONFIG_SYS_SDRAM_BASE; priv->info.size = sdram_size_mb(priv->pmu) << 20;
return 0;
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
Right now we're setting the wrong value of 0 as base in the ram_info struct, which is obviously wrong for the rk3188. So instead set the correct value we already have in CONFIG_SYS_SDRAM_BASE.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188/sdram_rk3188.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Simon Glass sjg@chromium.org
On 23 March 2017 at 21:27, Simon Glass sjg@chromium.org wrote:
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
Right now we're setting the wrong value of 0 as base in the ram_info struct, which is obviously wrong for the rk3188. So instead set the correct value we already have in CONFIG_SYS_SDRAM_BASE.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188/sdram_rk3188.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
There was still a static ram value set in the rk3188-board from the time where we didn't have actual sdram init code. Now the sdram init leaves the ram information in SYS_REG2 and we can decode it similarly to the rk3288.
Right now we have two duplicates of that code, which is still ok and doesn't really count as common code yet, but if we get a third copy at some point from a newer soc, we should think about moving that to a more general position.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/rk3188-board.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 16f38559af..c370156e4c 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -56,8 +56,22 @@ err:
int dram_init(void) { - /* FIXME: read back ram size from sys_reg2 */ - gd->ram_size = 0x40000000; + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); + gd->ram_size = ram.size;
return 0; }
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
There was still a static ram value set in the rk3188-board from the time where we didn't have actual sdram init code. Now the sdram init leaves the ram information in SYS_REG2 and we can decode it similarly to the rk3288.
Right now we have two duplicates of that code, which is still ok and doesn't really count as common code yet, but if we get a third copy at some point from a newer soc, we should think about moving that to a more general position.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
On 23 March 2017 at 21:27, Simon Glass sjg@chromium.org wrote:
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
There was still a static ram value set in the rk3188-board from the time where we didn't have actual sdram init code. Now the sdram init leaves the ram information in SYS_REG2 and we can decode it similarly to the rk3288.
Right now we have two duplicates of that code, which is still ok and doesn't really count as common code yet, but if we get a third copy at some point from a newer soc, we should think about moving that to a more general position.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
In the beginning, we did SPL -> TPL -> U-Boot, but after clarification of the real ordering swapped SPL and TPL. It seems some renames were forgotten and may confuse future readers, so also swap these to reflect the actual ordering.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/rk3188-board-tpl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188-board-tpl.c b/arch/arm/mach-rockchip/rk3188-board-tpl.c index 442bfe7aa7..b458ef6ea8 100644 --- a/arch/arm/mach-rockchip/rk3188-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3188-board-tpl.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; static int rk3188_num_entries __attribute__ ((section(".data")));
#define PMU_BASE 0x20004000 -#define TPL_ENTRY 0x10080C00 +#define SPL_ENTRY 0x10080C00
static void jump_to_spl(void) { @@ -25,9 +25,9 @@ static void jump_to_spl(void)
struct rk3188_pmu * const pmu = (void *)PMU_BASE; image_entry_noargs_t tpl_entry = - (image_entry_noargs_t)(unsigned long)TPL_ENTRY; + (image_entry_noargs_t)(unsigned long)SPL_ENTRY;
- /* Store the SAVE_SP_ADDR in a location shared with TPL. */ + /* Store the SAVE_SP_ADDR in a location shared with SPL. */ writel(SAVE_SP_ADDR, &pmu->sys_reg[2]); tpl_entry(); }
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
In the beginning, we did SPL -> TPL -> U-Boot, but after clarification of the real ordering swapped SPL and TPL. It seems some renames were forgotten and may confuse future readers, so also swap these to reflect the actual ordering.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-tpl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
On 23 March 2017 at 21:27, Simon Glass sjg@chromium.org wrote:
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
In the beginning, we did SPL -> TPL -> U-Boot, but after clarification of the real ordering swapped SPL and TPL. It seems some renames were forgotten and may confuse future readers, so also swap these to reflect the actual ordering.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-tpl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole startup take a lot of time. We therefore want to at least move to the safe 600MHz value we can use with default pmic settings. This is also the freqency the proprietary sdram-init leaves the cpu at.
For boards that have pmic control later in u-boot, we also add the option to set the maximum frequency of 1.6GHz, if they so desire.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 1 + drivers/clk/rockchip/clk_rk3188.c | 63 +++++++++++++++++++++++++ 2 files changed, 64 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h index 74f0fedcc6..f5d6420d04 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h @@ -9,6 +9,7 @@ #define OSC_HZ (24 * 1000 * 1000)
#define APLL_HZ (1608 * 1000000) +#define APLL_SAFE_HZ (600 * 1000000) #define GPLL_HZ (594 * 1000000) #define CPLL_HZ (384 * 1000000)
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 459649f724..d36cf8f3f2 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -168,6 +168,65 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, return 0; }
+static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf, + unsigned int hz, bool has_bwadj) +{ + static const struct pll_div apll_cfg[] = { + {.nf = 50, .nr = 1, .no = 2}, + {.nf = 67, .nr = 1, .no = 1}, + }; + int div_core_peri, div_aclk_core, cfg; + + /* + * We support two possible frequencies, the safe 600MHz + * which will work with default pmic settings and will + * be set in SPL to get away from the 24MHz default and + * the maximum of 1.6Ghz, which boards can set if they + * were able to get pmic support for it. + */ + switch (hz) { + case APLL_SAFE_HZ: + cfg = 0; + div_core_peri = 1; + div_aclk_core = 3; + break; + case APLL_HZ: + cfg = 1; + div_core_peri = 2; + div_aclk_core = 3; + break; + default: + debug("Unsupported ARMCLK frequency"); + return -EINVAL; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj); + + /* waiting for pll lock */ + while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) + udelay(1); + + /* Set divider for peripherals attached to the cpu core. */ + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, + div_core_peri << CORE_PERI_DIV_SHIFT); + + /* set up dependent divisor for aclk_core */ + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT, + div_aclk_core << CORE_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, + APLL_MODE_NORMAL << APLL_MODE_SHIFT); + + return hz; +} + /* Get pll rate by id */ static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru, enum rk_clk_id clk_id) @@ -435,6 +494,10 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) ulong new_rate;
switch (clk->id) { + case PLL_APLL: + new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, + priv->has_bwadj); + break; case CLK_DDR: new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, priv->has_bwadj);
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole startup take a lot of time. We therefore want to at least move to the safe 600MHz value we can use with default pmic settings. This is also the freqency the proprietary sdram-init leaves the cpu at.
For boards that have pmic control later in u-boot, we also add the option to set the maximum frequency of 1.6GHz, if they so desire.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 1 + drivers/clk/rockchip/clk_rk3188.c | 63 +++++++++++++++++++++++++ 2 files changed, 64 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 23 March 2017 at 21:27, Simon Glass sjg@chromium.org wrote:
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole startup take a lot of time. We therefore want to at least move to the safe 600MHz value we can use with default pmic settings. This is also the freqency the proprietary sdram-init leaves the cpu at.
For boards that have pmic control later in u-boot, we also add the option to set the maximum frequency of 1.6GHz, if they so desire.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 1 + drivers/clk/rockchip/clk_rk3188.c | 63 +++++++++++++++++++++++++ 2 files changed, 64 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot startup taking a lot of time (U-Boot itself, but also the rc4 decoding done in the bootrom).
With default pmic settings we can always reach a safe frequency of 600MHz which is also the frequency the proprietary loader left the armclk at, without needing access to the systems pmic.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/rk3188-board-spl.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index af4623fdb0..affd959f86 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <clk.h> #include <common.h> #include <debug_uart.h> #include <dm.h> @@ -76,6 +77,27 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; }
+static int setup_arm_clock(void) +{ + struct udevice *dev; + struct clk clk; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ret; + + clk.id = CLK_ARM; + ret = clk_request(dev, &clk); + if (ret < 0) + return ret; + + ret = clk_set_rate(&clk, 600000000); + + clk_free(&clk); + return ret; +} + void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; @@ -144,6 +166,8 @@ void board_init_f(ulong dummy) return; }
+ setup_arm_clock(); + #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot startup taking a lot of time (U-Boot itself, but also the rc4 decoding done in the bootrom).
With default pmic settings we can always reach a safe frequency of 600MHz which is also the frequency the proprietary loader left the armclk at, without needing access to the systems pmic.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-spl.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 23 March 2017 at 21:28, Simon Glass sjg@chromium.org wrote:
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot startup taking a lot of time (U-Boot itself, but also the rc4 decoding done in the bootrom).
With default pmic settings we can always reach a safe frequency of 600MHz which is also the frequency the proprietary loader left the armclk at, without needing access to the systems pmic.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-spl.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
The rk3066/rk3188 introduced new i2c IP blocks but kept the old ones around just in case. The default also points to these old controllers.
The "new" blocks proved stable and nobody ever used the old ones anywhere, not in the kernel and not in U-Boot, so to be able to reuse the already existing driver make the rk3188 switch to the new ones in U-Boot as well.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/rk3188-board-spl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index affd959f86..14847a7b1b 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h> +#include <asm/arch/grf_rk3188.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h> @@ -102,6 +103,7 @@ void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu; + struct rk3188_grf *grf; int ret;
/* Example code showing how to enable the debug UART on RK3188 */ @@ -154,6 +156,25 @@ void board_init_f(ulong dummy) error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]);
+ /* init common grf settings */ + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(grf)) { + error("grf syscon returned %ld\n", PTR_ERR(grf)); + } else { + /* make i2c controllers use the new IP */ + rk_clrsetreg(&grf->soc_con1, + RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT | + RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT | + RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT | + RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT | + RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT, + RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT | + RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT | + RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT | + RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT | + RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT); + } + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret);
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The rk3066/rk3188 introduced new i2c IP blocks but kept the old ones around just in case. The default also points to these old controllers.
The "new" blocks proved stable and nobody ever used the old ones anywhere, not in the kernel and not in U-Boot, so to be able to reuse the already existing driver make the rk3188 switch to the new ones in U-Boot as well.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-spl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index affd959f86..14847a7b1b 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h> +#include <asm/arch/grf_rk3188.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h> @@ -102,6 +103,7 @@ void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu;
struct rk3188_grf *grf; int ret; /* Example code showing how to enable the debug UART on RK3188 */@@ -154,6 +156,25 @@ void board_init_f(ulong dummy) error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]);
/* init common grf settings */grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);if (IS_ERR(grf)) {error("grf syscon returned %ld\n", PTR_ERR(grf));} else {/* make i2c controllers use the new IP */rk_clrsetreg(&grf->soc_con1,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT);}
Can you move this to the pinctrl driver?
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret);-- 2.11.0
Regards, Simon
Am Donnerstag, 23. März 2017, 21:28:08 CET schrieb Simon Glass:
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The rk3066/rk3188 introduced new i2c IP blocks but kept the old ones around just in case. The default also points to these old controllers.
The "new" blocks proved stable and nobody ever used the old ones anywhere, not in the kernel and not in U-Boot, so to be able to reuse the already existing driver make the rk3188 switch to the new ones in U-Boot as well.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-spl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index affd959f86..14847a7b1b 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -17,6 +17,7 @@
#include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3188.h>
#include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h>
@@ -102,6 +103,7 @@ void board_init_f(ulong dummy)
{
struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu;
struct rk3188_grf *grf; int ret; /* Example code showing how to enable the debug UART on RK3188 */@@ -154,6 +156,25 @@ void board_init_f(ulong dummy)
error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]);
/* init common grf settings */grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);if (IS_ERR(grf)) {error("grf syscon returned %ld\n", PTR_ERR(grf));} else {/* make i2c controllers use the new IP */rk_clrsetreg(&grf->soc_con1,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT);}Can you move this to the pinctrl driver?
Are you sure that is the right approach?
This setting switches the i2c controller IP block used, while the i2c-pins are not affected by this at all. You could also use the i2c pins with the other i2c controller with the same pinctrl settings, so it feels a tiny bit strange to burden the pinctrl driver with this.
Heiko
Hi Heiko,
On 24 March 2017 at 01:32, Heiko Stübner heiko@sntech.de wrote:
Am Donnerstag, 23. März 2017, 21:28:08 CET schrieb Simon Glass:
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The rk3066/rk3188 introduced new i2c IP blocks but kept the old ones around just in case. The default also points to these old controllers.
The "new" blocks proved stable and nobody ever used the old ones anywhere, not in the kernel and not in U-Boot, so to be able to reuse the already existing driver make the rk3188 switch to the new ones in U-Boot as well.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-spl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index affd959f86..14847a7b1b 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -17,6 +17,7 @@
#include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3188.h>
#include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h>
@@ -102,6 +103,7 @@ void board_init_f(ulong dummy)
{
struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu;
struct rk3188_grf *grf; int ret; /* Example code showing how to enable the debug UART on RK3188 */@@ -154,6 +156,25 @@ void board_init_f(ulong dummy)
error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]);
/* init common grf settings */grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);if (IS_ERR(grf)) {error("grf syscon returned %ld\n", PTR_ERR(grf));} else {/* make i2c controllers use the new IP */rk_clrsetreg(&grf->soc_con1,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT);}Can you move this to the pinctrl driver?
Are you sure that is the right approach?
This setting switches the i2c controller IP block used, while the i2c-pins are not affected by this at all. You could also use the i2c pins with the other i2c controller with the same pinctrl settings, so it feels a tiny bit strange to burden the pinctrl driver with this.
It still seems like pinctrl to me, in that you are selecting which IP block uses those pins. If you don't want it in pinctrl, perhaps this whole thing should go in the I2C driver?
Regards, Simon
Am Samstag, 25. März 2017, 19:17:33 CEST schrieb Simon Glass:
Hi Heiko,
On 24 March 2017 at 01:32, Heiko Stübner heiko@sntech.de wrote:
Am Donnerstag, 23. März 2017, 21:28:08 CET schrieb Simon Glass:
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The rk3066/rk3188 introduced new i2c IP blocks but kept the old ones around just in case. The default also points to these old controllers.
The "new" blocks proved stable and nobody ever used the old ones anywhere, not in the kernel and not in U-Boot, so to be able to reuse the already existing driver make the rk3188 switch to the new ones in U-Boot as well.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-spl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index affd959f86..14847a7b1b 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -17,6 +17,7 @@
#include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3188.h>
#include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h>
@@ -102,6 +103,7 @@ void board_init_f(ulong dummy)
{
struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu;
struct rk3188_grf *grf; int ret; /* Example code showing how to enable the debug UART on RK3188 */@@ -154,6 +156,25 @@ void board_init_f(ulong dummy)
error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]);
/* init common grf settings */grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);if (IS_ERR(grf)) {error("grf syscon returned %ld\n", PTR_ERR(grf));} else {/* make i2c controllers use the new IP */rk_clrsetreg(&grf->soc_con1,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT);}Can you move this to the pinctrl driver?
Are you sure that is the right approach?
This setting switches the i2c controller IP block used, while the i2c-pins are not affected by this at all. You could also use the i2c pins with the other i2c controller with the same pinctrl settings, so it feels a tiny bit strange to burden the pinctrl driver with this.
It still seems like pinctrl to me, in that you are selecting which IP block uses those pins. If you don't want it in pinctrl, perhaps this whole thing should go in the I2C driver?
no pinctrl is fine, and funnily enough, when I tried moving that there, I realized that the pinctrl driver had the switch to the new controller right from the beginning and I just had forgotten about it :-S, see the
/* enable new i2c controller */ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT, 1 << RKI2C0_SEL_SHIFT);
parts in pinctrl_rk3188.c .
So it looks like we can just drop this patch altogether :-) .
Heiko
On 26 March 2017 at 07:01, Heiko Stuebner heiko@sntech.de wrote:
Am Samstag, 25. März 2017, 19:17:33 CEST schrieb Simon Glass:
Hi Heiko,
On 24 March 2017 at 01:32, Heiko Stübner heiko@sntech.de wrote:
Am Donnerstag, 23. März 2017, 21:28:08 CET schrieb Simon Glass:
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The rk3066/rk3188 introduced new i2c IP blocks but kept the old ones around just in case. The default also points to these old controllers.
The "new" blocks proved stable and nobody ever used the old ones anywhere, not in the kernel and not in U-Boot, so to be able to reuse the already existing driver make the rk3188 switch to the new ones in U-Boot as well.
Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-spl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index affd959f86..14847a7b1b 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -17,6 +17,7 @@
#include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3188.h>
#include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h>
@@ -102,6 +103,7 @@ void board_init_f(ulong dummy)
{
struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu;
struct rk3188_grf *grf; int ret; /* Example code showing how to enable the debug UART on RK3188 */@@ -154,6 +156,25 @@ void board_init_f(ulong dummy)
error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]);
/* init common grf settings */grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);if (IS_ERR(grf)) {error("grf syscon returned %ld\n", PTR_ERR(grf));} else {/* make i2c controllers use the new IP */rk_clrsetreg(&grf->soc_con1,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT,RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT);}Can you move this to the pinctrl driver?
Are you sure that is the right approach?
This setting switches the i2c controller IP block used, while the i2c-pins are not affected by this at all. You could also use the i2c pins with the other i2c controller with the same pinctrl settings, so it feels a tiny bit strange to burden the pinctrl driver with this.
It still seems like pinctrl to me, in that you are selecting which IP block uses those pins. If you don't want it in pinctrl, perhaps this whole thing should go in the I2C driver?
no pinctrl is fine, and funnily enough, when I tried moving that there, I realized that the pinctrl driver had the switch to the new controller right from the beginning and I just had forgotten about it :-S, see the
/* enable new i2c controller */ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT, 1 << RKI2C0_SEL_SHIFT);parts in pinctrl_rk3188.c .
So it looks like we can just drop this patch altogether :-) .
OK, nice, thanks!
The Cortex-A9 socs rk3066 and rk3188 share the IP but have their own compatible values, so add them to make the i2c on these platforms accessible.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- drivers/i2c/rk_i2c.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index 7c701cbed0..af925cecdb 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -380,6 +380,8 @@ static const struct dm_i2c_ops rockchip_i2c_ops = { };
static const struct udevice_id rockchip_i2c_ids[] = { + { .compatible = "rockchip,rk3066-i2c" }, + { .compatible = "rockchip,rk3188-i2c" }, { .compatible = "rockchip,rk3288-i2c" }, { } };
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The Cortex-A9 socs rk3066 and rk3188 share the IP but have their own compatible values, so add them to make the i2c on these platforms accessible.
Signed-off-by: Heiko Stuebner heiko@sntech.de
drivers/i2c/rk_i2c.c | 2 ++ 1 file changed, 2 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 23 March 2017 at 21:28, Simon Glass sjg@chromium.org wrote:
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The Cortex-A9 socs rk3066 and rk3188 share the IP but have their own compatible values, so add them to make the i2c on these platforms accessible.
Signed-off-by: Heiko Stuebner heiko@sntech.de
drivers/i2c/rk_i2c.c | 2 ++ 1 file changed, 2 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
The rock board uses the already existing act8846 as pmic, so enable the driver and needed pmic options for it.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- configs/rock_defconfig | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 86048c8fd7..153ebb5a44 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -46,6 +46,10 @@ CONFIG_SYSRESET=y CONFIG_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_ROCKCHIP_RK3188_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_ACT8846=y +CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DEBUG_UART=y
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The rock board uses the already existing act8846 as pmic, so enable the driver and needed pmic options for it.
Signed-off-by: Heiko Stuebner heiko@sntech.de
configs/rock_defconfig | 4 ++++ 1 file changed, 4 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Am Donnerstag, 23. März 2017, 21:28:15 CEST schrieb Simon Glass:
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The rock board uses the already existing act8846 as pmic, so enable the driver and needed pmic options for it.
Signed-off-by: Heiko Stuebner heiko@sntech.de
configs/rock_defconfig | 4 ++++ 1 file changed, 4 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
just as a note, I folded that into the update Rock board patch from just now, as there is no need to have that separately.
Heiko
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup unnecessary slow. We can easily switch to 600MHz without involving the pmic and thus do this in the SPL to also make the rc4-decoding of the U-Boot image faster.
Some smaller fixes also turned up while adding the ARMCLK-support.
It's currently based on Simon's spl-working branch and Kever's spl_early_init patch, as that includes the last missing rk3188 patches and also keeps uboot starting on rk3188.
This should be in mainline now so can you also please test against that?
Tested on a rk3188 radxarock.
Heiko Stuebner (8): rockchip: rk3188: sdram: Set correct sdram base rockchip: rk3188: Decode the actual amount of ram rockchip: rk3188: Cleanup some SPL/TPL rename leftovers rockchip: clk: rk3188: Allow configuration of the armclk rockchip: rk3188: Setup the armclk in spl rockchip: rk3188: Switch to new i2c IP blocks rockchip: i2c: Add compatibles for Rockchip Cortex-A9 socs rockchip: Enable pmic options and act8846 driver on rk3188 rock boards
arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 1 + arch/arm/mach-rockchip/rk3188-board-spl.c | 45 ++++++++++++++++++ arch/arm/mach-rockchip/rk3188-board-tpl.c | 6 +-- arch/arm/mach-rockchip/rk3188-board.c | 18 ++++++- arch/arm/mach-rockchip/rk3188/sdram_rk3188.c | 2 +- configs/rock_defconfig | 4 ++ drivers/clk/rockchip/clk_rk3188.c | 63 +++++++++++++++++++++++++ drivers/i2c/rk_i2c.c | 2 + 8 files changed, 135 insertions(+), 6 deletions(-)
-- 2.11.0
Regards, Simon
Am Donnerstag, 23. März 2017, 21:28:01 CET schrieb Simon Glass:
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup unnecessary slow. We can easily switch to 600MHz without involving the pmic and thus do this in the SPL to also make the rc4-decoding of the U-Boot image faster.
Some smaller fixes also turned up while adding the ARMCLK-support.
It's currently based on Simon's spl-working branch and Kever's spl_early_init patch, as that includes the last missing rk3188 patches and also keeps uboot starting on rk3188.
This should be in mainline now so can you also please test against that?
yep, all good.
As stated in my fixup series yesterday, this should of course go on top of the final radxarock addition.
Heiko
Hi Heiko,
On 24 March 2017 at 10:04, Heiko Stuebner heiko@sntech.de wrote:
Am Donnerstag, 23. März 2017, 21:28:01 CET schrieb Simon Glass:
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup unnecessary slow. We can easily switch to 600MHz without involving the pmic and thus do this in the SPL to also make the rc4-decoding of the U-Boot image faster.
Some smaller fixes also turned up while adding the ARMCLK-support.
It's currently based on Simon's spl-working branch and Kever's spl_early_init patch, as that includes the last missing rk3188 patches and also keeps uboot starting on rk3188.
This should be in mainline now so can you also please test against that?
yep, all good.
As stated in my fixup series yesterday, this should of course go on top of the final radxarock addition.
I sent a few patches which get it building for me. Please take a look and see what you think.
Regards, Simon
Am Montag, 27. März 2017, 12:36:00 CEST schrieb Simon Glass:
Hi Heiko,
On 24 March 2017 at 10:04, Heiko Stuebner heiko@sntech.de wrote:
Am Donnerstag, 23. März 2017, 21:28:01 CET schrieb Simon Glass:
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner heiko@sntech.de wrote:
The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup unnecessary slow. We can easily switch to 600MHz without involving the pmic and thus do this in the SPL to also make the rc4-decoding of the U-Boot image faster.
Some smaller fixes also turned up while adding the ARMCLK-support.
It's currently based on Simon's spl-working branch and Kever's spl_early_init patch, as that includes the last missing rk3188 patches and also keeps uboot starting on rk3188.
This should be in mainline now so can you also please test against that?
yep, all good.
As stated in my fixup series yesterday, this should of course go on top of the final radxarock addition.
I sent a few patches which get it building for me. Please take a look and see what you think.
Patches 1+2 look very nice, see replies.
I'm not sure about the third patch though, as I don't see it affecting the rock-tpl to much. When looking at the diassembly of the tpl-binary, the only driver-related functions still present there, are serial_post_probe and serial_pre_remove.
Yesterday I was playing around with serial options a bit but trying to disable the default DM_SERIAL seemed to create just more mayhem and would probably need even more header config settings when saving 26 bytes.
participants (3)
-
Heiko Stuebner -
Heiko Stübner
-
Simon Glass