Hi,

On 8/28/12, snow.jhkim@gmail.com snow.jhkim@gmail.com wrote:

From: Jeong-Hyeon Kim jhkim@insignal.co.kr

• Fixed MPLL register address It's different between Exynos4210 and Exynos4412.

• Added pinmux functions for Exynos4

• Added extended gpios for Exynos4412 Exynos4412 has more gpios than Exynos4210.

Signed-off-by: Jeong-Hyeon Kim jhkim@insignal.co.kr

arch/arm/cpu/armv7/exynos/clock.c | 11 ++ arch/arm/cpu/armv7/exynos/pinmux.c | 241 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clock.h | 27 ++++ arch/arm/include/asm/arch-exynos/cpu.h | 4 + arch/arm/include/asm/arch-exynos/gpio.h | 21 +++- 5 files changed, 303 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 680aeeb..84a6725 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -79,14 +79,25 @@ static unsigned long exynos4_get_pll_clk(int pllreg) /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / 65536) * (freq / (p * (1 << s))); } else if (pllreg == VPLL) { +#ifdef CONFIG_EXYNOS4210

we don't like the ifdefy at here. How about to check soc_is_4210 and soc_is_4412?

k = k & 0xfff;
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 1024) * (freq / (p * (1 << s)));

+#else

• k = k & 0xffff;
  

• /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
  

• fout = (m + k / 65536) * (freq / (p * (1 << s)));
  

+#endif } else { +#ifdef CONFIG_EXYNOS4210

ditto

if (s < 1)
	s = 1;
/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
fout = m * (freq / (p * (1 << (s - 1))));

+#else

• /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
  

• fout = m * (freq / (p * (1 << s)));
  

+#endif }

return fout; diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 7776add..0746878 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -26,6 +26,245 @@ #include <asm/arch/pinmux.h> #include <asm/arch/sromc.h>

+static void exynos4_uart_config(int peripheral) +{

• struct exynos4_gpio_part1 *gpio1 =

• (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
  

• struct s5p_gpio_bank *bank;
• int i, start, count;
• switch (peripheral) {
• case PERIPH_ID_UART0:

• bank = &gpio1->a0;
  

• start = 0;
  

• count = 4;
  

• break;
  

• case PERIPH_ID_UART1:

• bank = &gpio1->a0;
  

• start = 4;
  

• count = 4;
  

• break;
  

• case PERIPH_ID_UART2:

• bank = &gpio1->a1;
  

• start = 0;
  

• count = 4;
  

• break;
  

• case PERIPH_ID_UART3:

• bank = &gpio1->a1;
  

• start = 4;
  

• count = 2;
  

• break;
  

• }
• for (i = start; i < start + count; i++) {

• s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
  

• s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
  

• }

+}

+static int exynos4_mmc_config(int peripheral, int flags) +{

• struct exynos4_gpio_part2 *gpio2 =

• (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2();
  

• struct s5p_gpio_bank *bank, *bank_ext;
• int i, start = 0, gpio_func = 0;
• switch (peripheral) {
• case PERIPH_ID_SDMMC0:

• bank = &gpio2->k0;
  

• bank_ext = &gpio2->k1;
  

• start = 3;
  

• gpio_func = GPIO_FUNC(0x2);
  

• break;
  

• case PERIPH_ID_SDMMC1:

• bank = &gpio2->k1;
  

• bank_ext = NULL;
  

• break;
  

• case PERIPH_ID_SDMMC2:

• bank = &gpio2->k2;
  

• bank_ext = &gpio2->k3;
  

• start = 3;
  

• gpio_func = GPIO_FUNC(0x3);
  

• break;
  

• case PERIPH_ID_SDMMC3:

• bank = &gpio2->k3;
  

• bank_ext = NULL;
  

• break;
  

• }
• if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {

• debug("SDMMC device %d does not support 8bit mode",
  

• 		peripheral);
  

• return -1;
  

• }
• if (flags & PINMUX_FLAG_8BIT_MODE) {

• for (i = start; i <= (start + 3); i++) {
  

• 	s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
  

• 	s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
  

• 	s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
  

• }
  

• }
• for (i = 0; i < 2; i++) {

• s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
  

• s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
  

• s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
  

• }
• for (i = 3; i <= 6; i++) {

• s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
  

• s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
  

• s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
  

• }
• return 0;

+}

+static void exynos4_sromc_config(int flags) +{

• struct exynos4_gpio_part2 *gpio2 =

• (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2();
  

• int i;
• /*

• * SROM:CS1 and EBI
  

• *
  

• * GPY0[0]	SROM_CSn[0]
  

• * GPY0[1]	SROM_CSn[1](2)
  

• * GPY0[2]	SROM_CSn[2]
  

• * GPY0[3]	SROM_CSn[3]
  

• * GPY0[4]	EBI_OEn(2)
  

• * GPY0[5]	EBI_EEn(2)
  

• *
  

• * GPY1[0]	EBI_BEn[0](2)
  

• * GPY1[1]	EBI_BEn[1](2)
  

• * GPY1[2]	SROM_WAIT(2)
  

• * GPY1[3]	EBI_DATA_RDn(2)
  

• */
  

• s5p_gpio_cfg_pin(&gpio2->y0, (flags & PINMUX_FLAG_BANK),

• 		GPIO_FUNC(2));
  

• s5p_gpio_cfg_pin(&gpio2->y0, 4, GPIO_FUNC(2));
• s5p_gpio_cfg_pin(&gpio2->y0, 5, GPIO_FUNC(2));
• for (i = 0; i < 4; i++)

• s5p_gpio_cfg_pin(&gpio2->y1, i, GPIO_FUNC(2));
  

• /*

• * EBI: 8 Addrss Lines
  

• *
  

• * GPY3[0]	EBI_ADDR[0](2)
  

• * GPY3[1]	EBI_ADDR[1](2)
  

• * GPY3[2]	EBI_ADDR[2](2)
  

• * GPY3[3]	EBI_ADDR[3](2)
  

• * GPY3[4]	EBI_ADDR[4](2)
  

• * GPY3[5]	EBI_ADDR[5](2)
  

• * GPY3[6]	EBI_ADDR[6](2)
  

• * GPY3[7]	EBI_ADDR[7](2)
  

• *
  

• * EBI: 16 Data Lines
  

• *
  

• * GPY5[0]	EBI_DATA[0](2)
  

• * GPY5[1]	EBI_DATA[1](2)
  

• * GPY5[2]	EBI_DATA[2](2)
  

• * GPY5[3]	EBI_DATA[3](2)
  

• * GPY5[4]	EBI_DATA[4](2)
  

• * GPY5[5]	EBI_DATA[5](2)
  

• * GPY5[6]	EBI_DATA[6](2)
  

• * GPY5[7]	EBI_DATA[7](2)
  

• *
  

• * GPY6[0]	EBI_DATA[8](2)
  

• * GPY6[1]	EBI_DATA[9](2)
  

• * GPY6[2]	EBI_DATA[10](2)
  

• * GPY6[3]	EBI_DATA[11](2)
  

• * GPY6[4]	EBI_DATA[12](2)
  

• * GPY6[5]	EBI_DATA[13](2)
  

• * GPY6[6]	EBI_DATA[14](2)
  

• * GPY6[7]	EBI_DATA[15](2)
  

• */
  

• for (i = 0; i < 8; i++) {

• s5p_gpio_cfg_pin(&gpio2->y3, i, GPIO_FUNC(2));
  

• s5p_gpio_set_pull(&gpio2->y3, i, GPIO_PULL_UP);
  

• s5p_gpio_cfg_pin(&gpio2->y5, i, GPIO_FUNC(2));
  

• s5p_gpio_set_pull(&gpio2->y5, i, GPIO_PULL_UP);
  

• s5p_gpio_cfg_pin(&gpio2->y6, i, GPIO_FUNC(2));
  

• s5p_gpio_set_pull(&gpio2->y6, i, GPIO_PULL_UP);
  

• }

+}

+static void exynos4_i2c_config(int peripheral, int flags) +{

• struct exynos4_gpio_part1 *gpio1 =

• (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
  

• switch (peripheral) {
• case PERIPH_ID_I2C0:

• s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
  

• s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
  

• break;
  

• case PERIPH_ID_I2C1:

• s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
  

• s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
  

• break;
  

• case PERIPH_ID_I2C2:

• s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
  

• s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
  

• break;
  

• case PERIPH_ID_I2C3:

• s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
  

• s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
  

• break;
  

• case PERIPH_ID_I2C4:

• s5p_gpio_cfg_pin(&gpio1->b, 0, GPIO_FUNC(0x3));
  

• s5p_gpio_cfg_pin(&gpio1->b, 1, GPIO_FUNC(0x3));
  

• break;
  

• case PERIPH_ID_I2C5:

• s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
  

• s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
  

• break;
  

• case PERIPH_ID_I2C6:

• s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
  

• s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
  

• break;
  

• case PERIPH_ID_I2C7:

• s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
  

• s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
  

• break;
  

• }

+}

+static int exynos4_pinmux_config(int peripheral, int flags) +{

• switch (peripheral) {
• case PERIPH_ID_UART0:
• case PERIPH_ID_UART1:
• case PERIPH_ID_UART2:
• case PERIPH_ID_UART3:

• exynos4_uart_config(peripheral);
  

• break;
  

• case PERIPH_ID_SDMMC0:
• case PERIPH_ID_SDMMC1:
• case PERIPH_ID_SDMMC2:
• case PERIPH_ID_SDMMC3:

• return exynos4_mmc_config(peripheral, flags);
  

• case PERIPH_ID_SROMC:

• exynos4_sromc_config(flags);
  

• break;
  

• case PERIPH_ID_I2C0:
• case PERIPH_ID_I2C1:
• case PERIPH_ID_I2C2:
• case PERIPH_ID_I2C3:
• case PERIPH_ID_I2C4:
• case PERIPH_ID_I2C5:
• case PERIPH_ID_I2C6:
• case PERIPH_ID_I2C7:

• exynos4_i2c_config(peripheral, flags);
  

• break;
  

• default:

• debug("%s: invalid peripheral %d", __func__, peripheral);
  

• return -1;
  

• }
• return 0;

+}

static void exynos5_uart_config(int peripheral) { struct exynos5_gpio_part1 *gpio1 = @@ -269,6 +508,8 @@ int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) return exynos5_pinmux_config(peripheral, flags);

• else if (cpu_is_exynos4())

• return exynos4_pinmux_config(peripheral, flags);
  

  else { debug("pinmux functionality not supported\n"); return -1;

diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index fce38ef..e238810 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -57,10 +57,20 @@ struct exynos4_clock { unsigned char res16[0xec]; unsigned int epll_con0; unsigned int epll_con1; +#ifdef CONFIG_EXYNOS4210

like above, how about to define 4412 specific clock? e.g., exynos4412_clock?

unsigned char res17[0x8]; +#else

• unsigned int epll_con2;
• unsigned char res17[0x4];

+#endif unsigned int vpll_con0; unsigned int vpll_con1; +#ifdef CONFIG_EXYNOS4210 unsigned char res18[0xe8]; +#else

• unsigned int vpll_con2;
• unsigned char res18[0xe4];

+#endif unsigned int src_top0; unsigned int src_top1; unsigned char res19[0x8]; @@ -161,7 +171,16 @@ struct exynos4_clock { unsigned char res38[0x8c]; unsigned int clkout_cmu_top; unsigned int clkout_cmu_top_div_stat; +#ifdef CONFIG_EXYNOS4210 unsigned char res39[0x37f8]; +#else

• unsigned char res39[0x3600];
• unsigned int mpll_lock;
• unsigned char res3a[0xfc];
• unsigned int mpll_con0;
• unsigned int mpll_con1;
• unsigned char res3b[0xf0];

+#endif unsigned int src_dmc; unsigned char res40[0xfc]; unsigned int src_mask_dmc; @@ -195,14 +214,22 @@ struct exynos4_clock { unsigned int maxperf; unsigned char res51[0x2f78]; unsigned int apll_lock; +#ifdef CONFIG_EXYNOS4210 unsigned char res52[0x4]; unsigned int mpll_lock; +#else

• unsigned char res52[0x8];

+#endif unsigned char res53[0xf4]; unsigned int apll_con0; unsigned int apll_con1; +#ifdef CONFIG_EXYNOS4210 unsigned int mpll_con0; unsigned int mpll_con1; unsigned char res54[0xf0]; +#else

• unsigned char res54[0xf8];

+#endif unsigned int src_cpu; unsigned char res55[0x1fc]; unsigned int mux_stat_cpu; diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 2cd4ae1..d1117c0 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -55,7 +55,11 @@ #define EXYNOS4_MODEM_BASE 0x13A00000 #define EXYNOS4_USBPHY_CONTROL 0x10020704

+#ifdef CONFIG_EXYNOS4412 +#define EXYNOS4_GPIO_PART4_BASE 0x106E0000 +#else #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE +#endif

if it's only valid at exynos4412, then make it variable and configure it at runtime e.g.,

#define EXYNOS4412_GPIO_PART4_BASE 0x106E0000 #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE

int exynos4_get_gpio_part4_base(void) { if (cpu_is_exynos4412()) return EXYNOS4412_GPIO_PART4_BASE; return EXYNOS4_GPIO_PART4_BASE; }

Thank you, Kyungmin Park

#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE

/* EXYNOS5 */ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 97be4ea..9539aa0 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -49,6 +49,9 @@ struct exynos4_gpio_part1 { struct s5p_gpio_bank f1; struct s5p_gpio_bank f2; struct s5p_gpio_bank f3;

• struct s5p_gpio_bank res1[2];
• struct s5p_gpio_bank j0;
• struct s5p_gpio_bank j1;

};

struct exynos4_gpio_part2 { @@ -68,7 +71,13 @@ struct exynos4_gpio_part2 { struct s5p_gpio_bank y4; struct s5p_gpio_bank y5; struct s5p_gpio_bank y6;

• struct s5p_gpio_bank res1[80];

• struct s5p_gpio_bank res1[3];
• struct s5p_gpio_bank m0;
• struct s5p_gpio_bank m1;
• struct s5p_gpio_bank m2;
• struct s5p_gpio_bank m3;
• struct s5p_gpio_bank m4;
• struct s5p_gpio_bank res2[72]; struct s5p_gpio_bank x0; struct s5p_gpio_bank x1; struct s5p_gpio_bank x2;

@@ -79,6 +88,16 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; };

+struct exynos4_gpio_part4 {

• struct s5p_gpio_bank v0;
• struct s5p_gpio_bank v1;
• struct s5p_gpio_bank res1[1];
• struct s5p_gpio_bank v2;
• struct s5p_gpio_bank v3;
• struct s5p_gpio_bank res2[1];
• struct s5p_gpio_bank v4;

+};

struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; -- 1.7.1

---

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

From: Jeong-Hyeon Kim jhkim@insignal.co.kr

- Fixed MPLL register address It's different between Exynos4210 and Exynos4412.

- Added pinmux functions for Exynos4

- Added extended gpios for Exynos4412 Exynos4412 has more gpios than Exynos4210.

Signed-off-by: Jeong-Hyeon Kim jhkim@insignal.co.kr --- arch/arm/cpu/armv7/exynos/clock.c | 67 ++++++++ arch/arm/cpu/armv7/exynos/pinmux.c | 241 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clock.h | 240 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 14 ++- arch/arm/include/asm/arch-exynos/gpio.h | 21 +++- 5 files changed, 578 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 680aeeb..002a493 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -92,6 +92,70 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return fout; }

+/* exynos4: return pll clock frequency */ +static unsigned long exynos4412_get_pll_clk(int pllreg) +{ + struct exynos4412_clock *clk = + (struct exynos4412_clock *)samsung_get_base_clock(); + unsigned long r, m, p, s, k = 0, mask, fout; + unsigned int freq; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + /* + * APLL_CON: MIDV [25:16] + * MPLL_CON: MIDV [25:16] + * EPLL_CON: MIDV [24:16] + * VPLL_CON: MIDV [24:16] + */ + if (pllreg == APLL || pllreg == MPLL) + mask = 0x3ff; + else + mask = 0x1ff; + + m = (r >> 16) & mask; + + /* PDIV [13:8] */ + p = (r >> 8) & 0x3f; + /* SDIV [2:0] */ + s = r & 0x7; + + freq = CONFIG_SYS_CLK_FREQ; + + if (pllreg == EPLL) { + k = k & 0xffff; + /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ + fout = (m + k / 65536) * (freq / (p * (1 << s))); + } else if (pllreg == VPLL) { + k = k & 0xffff; + /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ + fout = (m + k / 65536) * (freq / (p * (1 << s))); + } else { + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ + fout = m * (freq / (p * (1 << s))); + } + + return fout; +} + /* exynos5: return pll clock frequency */ static unsigned long exynos5_get_pll_clk(int pllreg) { @@ -745,6 +809,9 @@ unsigned long get_pll_clk(int pllreg) if (cpu_is_exynos5()) return exynos5_get_pll_clk(pllreg); else + if (cpu_is_exynos4412()) + return exynos4412_get_pll_clk(pllreg); + else return exynos4_get_pll_clk(pllreg); }

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 7776add..0746878 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -26,6 +26,245 @@ #include <asm/arch/pinmux.h> #include <asm/arch/sromc.h>

+static void exynos4_uart_config(int peripheral) +{ + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + +static int exynos4_mmc_config(int peripheral, int flags) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2(); + struct s5p_gpio_bank *bank, *bank_ext; + int i, start = 0, gpio_func = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio2->k0; + bank_ext = &gpio2->k1; + start = 3; + gpio_func = GPIO_FUNC(0x2); + break; + case PERIPH_ID_SDMMC1: + bank = &gpio2->k1; + bank_ext = NULL; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio2->k2; + bank_ext = &gpio2->k3; + start = 3; + gpio_func = GPIO_FUNC(0x3); + break; + case PERIPH_ID_SDMMC3: + bank = &gpio2->k3; + bank_ext = NULL; + break; + } + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, gpio_func); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + return 0; +} + +static void exynos4_sromc_config(int flags) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2(); + int i; + + /* + * SROM:CS1 and EBI + * + * GPY0[0] SROM_CSn[0] + * GPY0[1] SROM_CSn[1](2) + * GPY0[2] SROM_CSn[2] + * GPY0[3] SROM_CSn[3] + * GPY0[4] EBI_OEn(2) + * GPY0[5] EBI_EEn(2) + * + * GPY1[0] EBI_BEn[0](2) + * GPY1[1] EBI_BEn[1](2) + * GPY1[2] SROM_WAIT(2) + * GPY1[3] EBI_DATA_RDn(2) + */ + s5p_gpio_cfg_pin(&gpio2->y0, (flags & PINMUX_FLAG_BANK), + GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, 4, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, 5, GPIO_FUNC(2)); + + for (i = 0; i < 4; i++) + s5p_gpio_cfg_pin(&gpio2->y1, i, GPIO_FUNC(2)); + + /* + * EBI: 8 Addrss Lines + * + * GPY3[0] EBI_ADDR[0](2) + * GPY3[1] EBI_ADDR[1](2) + * GPY3[2] EBI_ADDR[2](2) + * GPY3[3] EBI_ADDR[3](2) + * GPY3[4] EBI_ADDR[4](2) + * GPY3[5] EBI_ADDR[5](2) + * GPY3[6] EBI_ADDR[6](2) + * GPY3[7] EBI_ADDR[7](2) + * + * EBI: 16 Data Lines + * + * GPY5[0] EBI_DATA[0](2) + * GPY5[1] EBI_DATA[1](2) + * GPY5[2] EBI_DATA[2](2) + * GPY5[3] EBI_DATA[3](2) + * GPY5[4] EBI_DATA[4](2) + * GPY5[5] EBI_DATA[5](2) + * GPY5[6] EBI_DATA[6](2) + * GPY5[7] EBI_DATA[7](2) + * + * GPY6[0] EBI_DATA[8](2) + * GPY6[1] EBI_DATA[9](2) + * GPY6[2] EBI_DATA[10](2) + * GPY6[3] EBI_DATA[11](2) + * GPY6[4] EBI_DATA[12](2) + * GPY6[5] EBI_DATA[13](2) + * GPY6[6] EBI_DATA[14](2) + * GPY6[7] EBI_DATA[15](2) + */ + for (i = 0; i < 8; i++) { + s5p_gpio_cfg_pin(&gpio2->y3, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y3, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio2->y5, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y5, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio2->y6, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y6, i, GPIO_PULL_UP); + } +} + +static void exynos4_i2c_config(int peripheral, int flags) +{ + + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->b, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + break; + } +} + +static int exynos4_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos4_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos4_mmc_config(peripheral, flags); + case PERIPH_ID_SROMC: + exynos4_sromc_config(flags); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4_i2c_config(peripheral, flags); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + static void exynos5_uart_config(int peripheral) { struct exynos5_gpio_part1 *gpio1 = @@ -269,6 +508,8 @@ int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) return exynos5_pinmux_config(peripheral, flags); + else if (cpu_is_exynos4()) + return exynos4_pinmux_config(peripheral, flags); else { debug("pinmux functionality not supported\n"); return -1; diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index fce38ef..77760f2 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -251,6 +251,246 @@ struct exynos4_clock { unsigned int div_iem_l1; };

+struct exynos4412_clock { + unsigned char res1[0x4200]; + unsigned int src_leftbus; + unsigned char res2[0x1fc]; + unsigned int mux_stat_leftbus; + unsigned char res3[0xfc]; + unsigned int div_leftbus; + unsigned char res4[0xfc]; + unsigned int div_stat_leftbus; + unsigned char res5[0x1fc]; + unsigned int gate_ip_leftbus; + unsigned char res6[0x12c]; + unsigned int gate_ip_image; + unsigned char res7[0xcc]; + unsigned int clkout_cmu_leftbus; + unsigned int clkout_cmu_leftbus_div_stat; + unsigned char res8[0x37f8]; + unsigned int src_rightbus; + unsigned char res9[0x1fc]; + unsigned int mux_stat_rightbus; + unsigned char res10[0xfc]; + unsigned int div_rightbus; + unsigned char res11[0xfc]; + unsigned int div_stat_rightbus; + unsigned char res12[0x1fc]; + unsigned int gate_ip_rightbus; + unsigned char res13[0x15c]; + unsigned int gate_ip_perir; + unsigned char res14[0x9c]; + unsigned int clkout_cmu_rightbus; + unsigned int clkout_cmu_rightbus_div_stat; + unsigned char res15[0x3608]; + unsigned int epll_lock; + unsigned char res16[0xc]; + unsigned int vpll_lock; + unsigned char res17[0xec]; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int epll_con2; + unsigned char res18[0x4]; + unsigned int vpll_con0; + unsigned int vpll_con1; + unsigned int vpll_con2; + unsigned char res19[0xe4]; + unsigned int src_top0; + unsigned int src_top1; + unsigned char res20[0x8]; + unsigned int src_cam0; + unsigned int src_tv; + unsigned int src_mfc; + unsigned int src_g3d; + unsigned char res21[0x4]; + unsigned int src_lcd0; + unsigned int src_isp; + unsigned int src_maudio; + unsigned int src_fsys; + unsigned char res22[0xc]; + unsigned int src_peril0; + unsigned int src_peril1; + unsigned int src_cam1; + unsigned char res23[0xc4]; + unsigned int src_mask_cam0; + unsigned int src_mask_tv; + unsigned char res24[0xc]; + unsigned int src_mask_lcd; + unsigned int src_mask_isp; + unsigned int src_mask_maudio; + unsigned int src_mask_fsys; + unsigned char res25[0xc]; + unsigned int src_mask_peril0; + unsigned int src_mask_peril1; + unsigned char res26[0xb8]; + unsigned int mux_stat_top; + unsigned int mux_stat_top1; + unsigned char res27[0x10]; + unsigned int mux_stat_mfc; + unsigned int mux_stat_g3d; + unsigned char res28[0x28]; + unsigned int mux_stat_cam1; + unsigned char res29[0xb4]; + unsigned int div_top; + unsigned char res30[0xc]; + unsigned int div_cam0; + unsigned int div_tv; + unsigned int div_mfc; + unsigned int div_g3d; + unsigned char res31[0x4]; + unsigned int div_lcd; + unsigned int div_isp; + unsigned int div_maudio; + unsigned int div_fsys0; + unsigned int div_fsys1; + unsigned int div_fsys2; + unsigned int div_fsys3; + unsigned int div_peril0; + unsigned int div_peril1; + unsigned int div_peril2; + unsigned int div_peril3; + unsigned int div_peril4; + unsigned int div_peril5; + unsigned int div_cam1; + unsigned char res32[0x14]; + unsigned int div2_ratio; + unsigned char res33[0x8c]; + unsigned int div_stat_top; + unsigned char res34[0xc]; + unsigned int div_stat_cam0; + unsigned int div_stat_tv; + unsigned int div_stat_mfc; + unsigned int div_stat_g3d; + unsigned char res35[0x4]; + unsigned int div_stat_lcd; + unsigned int div_stat_isp; + unsigned int div_stat_maudio; + unsigned int div_stat_fsys0; + unsigned int div_stat_fsys1; + unsigned int div_stat_fsys2; + unsigned int div_stat_fsys3; + unsigned int div_stat_peril0; + unsigned int div_stat_peril1; + unsigned int div_stat_peril2; + unsigned int div_stat_peril3; + unsigned int div_stat_peril4; + unsigned int div_stat_peril5; + unsigned int div_stat_cam1; + unsigned char res36[0x14]; + unsigned int div2_stat; + unsigned char res37[0xc0]; + unsigned int gate_bus_fsys1; + unsigned char res38[0x1d8]; + unsigned int gate_ip_cam; + unsigned int gate_ip_tv; + unsigned int gate_ip_mfc; + unsigned int gate_ip_g3d; + unsigned char res39[0x4]; + unsigned int gate_ip_lcd; + unsigned int gate_ip_isp; + unsigned char res40[0x4]; + unsigned int gate_ip_fsys; + unsigned char res41[0x8]; + unsigned int gate_ip_gps; + unsigned int gate_ip_peril; + unsigned char res42[0x1c]; + unsigned int gate_block; + unsigned char res43[0x8c]; + unsigned int clkout_cmu_top; + unsigned int clkout_cmu_top_div_stat; + unsigned char res44[0x3600]; + unsigned int mpll_lock; + unsigned char res45[0xfc]; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res46[0xf0]; + unsigned int src_dmc; + unsigned char res47[0xfc]; + unsigned int src_mask_dmc; + unsigned char res48[0xfc]; + unsigned int mux_stat_dmc; + unsigned char res49[0xfc]; + unsigned int div_dmc0; + unsigned int div_dmc1; + unsigned char res50[0xf8]; + unsigned int div_stat_dmc0; + unsigned int div_stat_dmc1; + unsigned char res51[0x2f8]; + unsigned int gate_ip_dmc; + unsigned int gate_ip_dmc1; + unsigned char res52[0xf8]; + unsigned int clkout_cmu_dmc; + unsigned int clkout_cmu_dmc_div_stat; + unsigned char res53[0x5f8]; + unsigned int dcgidx_map0; + unsigned int dcgidx_map1; + unsigned int dcgidx_map2; + unsigned char res54[0x14]; + unsigned int dcgperf_map0; + unsigned int dcgperf_map1; + unsigned char res55[0x18]; + unsigned int dvcidx_map; + unsigned char res56[0x1c]; + unsigned int freq_cpu; + unsigned int freq_dpm; + unsigned char res57[0x18]; + unsigned int dvsemclk_en; + unsigned int maxperf; + unsigned char res58[0xc]; + unsigned int dmc_puause_ctrl; + unsigned int ddrphy_lock_ctrl; + unsigned int c2c_state; + unsigned char res59[0x2f60]; + unsigned int apll_lock; + unsigned char res60[0xfc]; + unsigned int apll_con0; + unsigned int apll_con1; + unsigned char res61[0xf8]; + unsigned int src_cpu; + unsigned char res62[0x1fc]; + unsigned int mux_stat_cpu; + unsigned char res63[0xfc]; + unsigned int div_cpu0; + unsigned int div_cpu1; + unsigned char res64[0xf8]; + unsigned int div_stat_cpu0; + unsigned int div_stat_cpu1; + unsigned char res65[0x2f8]; + unsigned int gate_ip_cpu; + unsigned char res66[0xfc]; + unsigned int clkout_cmu_cpu; + unsigned int clkout_cmu_cpu_div_stat; + unsigned char res67[0x5f8]; + unsigned int armclk_stopctrl; + unsigned int atclk_stopctrl; + unsigned char res68[0x18]; + unsigned int pwr_ctrl; + unsigned int pwr_ctrl2; + unsigned char res69[0x3d8]; + unsigned int l2_status; + unsigned char res70[0xc]; + unsigned int cpu_status; + unsigned char res71[0xc]; + unsigned int ptm_status; + unsigned char res72[0x2edc]; + unsigned int clk_div_isp0; + unsigned int clk_div_isp1; + unsigned char res73[0xf8]; + unsigned int clk_div_stat_isp0; + unsigned int clk_div_stat_isp1; + unsigned char res74[0x3f8]; + unsigned int gate_ip_isp0; + unsigned int gate_ip_isp1; + unsigned char res75[0x1f8]; + unsigned int clkout_cmu_isp; + unsigned int clkout_cmu_isp_stat; + unsigned char res76[0xf8]; + unsigned int clkout_cmu_spare0; + unsigned int clkout_cmu_spare1; + unsigned int clkout_cmu_spare2; + unsigned int clkout_cmu_spare3; +}; + struct exynos5_clock { unsigned int apll_lock; unsigned char res1[0xfc]; diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 2cd4ae1..58c7de6 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -58,6 +58,10 @@ #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE

+#define EXYNOS4412_DMC0_BASE 0x10600000 +#define EXYNOS4412_DMC1_BASE 0x10610000 +#define EXYNOS4412_GPIO_PART4_BASE 0x106E0000 + /* EXYNOS5 */ #define EXYNOS5_I2C_SPACING 0x10000

@@ -130,14 +134,16 @@ static inline char *s5p_get_cpu_name(void) return EXYNOS_CPU_NAME; }

-#define IS_SAMSUNG_TYPE(type, id) \ +#define IS_SAMSUNG_TYPE(type, id, shift) \ static inline int cpu_is_##type(void) \ { \ - return (s5p_cpu_id >> 12) == id; \ + return (s5p_cpu_id >> shift) == id; \ }

-IS_SAMSUNG_TYPE(exynos4, 0x4) -IS_SAMSUNG_TYPE(exynos5, 0x5) +IS_SAMSUNG_TYPE(exynos4, 0x4, 12) +IS_SAMSUNG_TYPE(exynos4210, 0x4210, 0) +IS_SAMSUNG_TYPE(exynos4412, 0x4412, 0) +IS_SAMSUNG_TYPE(exynos5, 0x5, 12)

#define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 97be4ea..9539aa0 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -49,6 +49,9 @@ struct exynos4_gpio_part1 { struct s5p_gpio_bank f1; struct s5p_gpio_bank f2; struct s5p_gpio_bank f3; + struct s5p_gpio_bank res1[2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; };

struct exynos4_gpio_part2 { @@ -68,7 +71,13 @@ struct exynos4_gpio_part2 { struct s5p_gpio_bank y4; struct s5p_gpio_bank y5; struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[80]; + struct s5p_gpio_bank res1[3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res2[72]; struct s5p_gpio_bank x0; struct s5p_gpio_bank x1; struct s5p_gpio_bank x2; @@ -79,6 +88,16 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; };

+struct exynos4_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[1]; + struct s5p_gpio_bank v4; +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1;

From: Jeong-Hyeon Kim jhkim@insignal.co.kr

Origen QUAD board is based on Samsung Exynos4412 SoC.

Signed-off-by: Jeong-Hyeon Kim jhkim@insignal.co.kr --- board/insignal/origen_quad/Makefile | 63 ++++++ board/insignal/origen_quad/boot.c | 63 ++++++ board/insignal/origen_quad/clock.c | 103 ++++++++++ board/insignal/origen_quad/dmc.c | 158 +++++++++++++++ board/insignal/origen_quad/lowlevel_init.S | 158 +++++++++++++++ board/insignal/origen_quad/origen_quad.c | 154 ++++++++++++++ board/insignal/origen_quad/pmic.c | 47 +++++ board/insignal/origen_quad/setup.h | 298 ++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/origen_quad.h | 183 +++++++++++++++++ tools/Makefile | 2 + 11 files changed, 1230 insertions(+), 0 deletions(-) create mode 100644 board/insignal/origen_quad/Makefile create mode 100644 board/insignal/origen_quad/boot.c create mode 100644 board/insignal/origen_quad/clock.c create mode 100644 board/insignal/origen_quad/dmc.c create mode 100644 board/insignal/origen_quad/lowlevel_init.S create mode 100644 board/insignal/origen_quad/origen_quad.c create mode 100644 board/insignal/origen_quad/pmic.c create mode 100644 board/insignal/origen_quad/setup.h create mode 100644 include/configs/origen_quad.h

diff --git a/board/insignal/origen_quad/Makefile b/board/insignal/origen_quad/Makefile new file mode 100644 index 0000000..04f609a --- /dev/null +++ b/board/insignal/origen_quad/Makefile @@ -0,0 +1,63 @@ +# +# Copyright (C) 2012 Samsung Electronics +# +# Copyright (C) 2012 Insignal +# +# Makefile for the Insignal OrigenQUAD board (Exynos4x12) +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +SOBJS := lowlevel_init.o + +COBJS := clock.o +COBJS += dmc.o + +ifdef CONFIG_PMIC +COBJS += pmic.o +endif + +ifndef CONFIG_SPL_BUILD +COBJS += origen_quad.o +else +COBJS += boot.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +ALL := $(obj).depend $(LIB) + +all: $(ALL) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/insignal/origen_quad/boot.c b/board/insignal/origen_quad/boot.c new file mode 100644 index 0000000..10f2289 --- /dev/null +++ b/board/insignal/origen_quad/boot.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Board initialize for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include "setup.h" + +#define IRAM_ADDRESS 0x02020000 +#define EXTERNAL_FUNC_ADDRESS (IRAM_ADDRESS + 0x0030) +#define IROM_READ_SDMMC EXTERNAL_FUNC_ADDRESS + +void inline irom_read_sdmmc(u32 start, u32 count, u32 addr) +{ + void (*read_sdmmc)(u32, u32, u32) = (void *) *(u32 *)IROM_READ_SDMMC; + read_sdmmc(start, count, addr); +} + +void board_init_f(unsigned long bootflag) +{ + __attribute__((noreturn)) void (*uboot)(void); + + irom_read_sdmmc(BL2_BLK_OFFSET, BL2_BLK_COUNT, CONFIG_SYS_TEXT_BASE); + + /* Jump to U-Boot image */ + uboot = (void *)CONFIG_SYS_TEXT_BASE; + (*uboot)(); + /* Never returns Here */ +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /* Function attribute is no-return */ + /* This Function never executes */ + while (1); +} + +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) +{ +} diff --git a/board/insignal/origen_quad/clock.c b/board/insignal/origen_quad/clock.c new file mode 100644 index 0000000..7f08e49 --- /dev/null +++ b/board/insignal/origen_quad/clock.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Clock setup for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include "setup.h" + +void clock_ctrl_init(void) +{ + struct exynos4412_clock *clk = (struct exynos4412_clock *)EXYNOS4_CLOCK_BASE; + unsigned int val; + + /* CLK_SRC_CPU */ + writel(0x00000000, &clk->src_cpu); + sdelay(0x10000); + + /* CLK_DIV_DMC */ + writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); + writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1); + + /* CLK_SRC_TOP */ + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + sdelay(0x10000); + writel(CLK_DIV_TOP_VAL, &clk->div_top); + + /* LEFTBUS */ + writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); + sdelay(0x10000); + writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); + /* RIGHTBUS */ + writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); + sdelay(0x10000); + writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); + + /* PLL locktime */ + writel(APLL_LOCK_VAL, &clk->apll_lock); + writel(MPLL_LOCK_VAL, &clk->mpll_lock); + writel(EPLL_LOCK_VAL, &clk->epll_lock); + writel(VPLL_LOCK_VAL, &clk->vpll_lock); + + /* CLK_DIV_CPU0/1 */ + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); + writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); + + /* APLL */ + writel(APLL_CON1_VAL, &clk->apll_con1); + writel(APLL_CON0_VAL, &clk->apll_con0); + /* MPLL */ + writel(MPLL_CON1_VAL, &clk->mpll_con1); + writel(MPLL_CON0_VAL, &clk->mpll_con0); + /* EPLL */ + writel(EPLL_CON2_VAL, &clk->epll_con2); + writel(EPLL_CON1_VAL, &clk->epll_con1); + writel(EPLL_CON0_VAL, &clk->epll_con0); + /* VPLL */ + writel(VPLL_CON2_VAL, &clk->vpll_con2); + writel(VPLL_CON1_VAL, &clk->vpll_con1); + writel(VPLL_CON0_VAL, &clk->vpll_con0); + sdelay(0x40000); + + writel(CLK_SRC_CPU_VAL, &clk->src_cpu); + writel(CLK_SRC_DMC_VAL, &clk->src_dmc); + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + sdelay(0x10000); + + /* UART */ + writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); + writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); + + /* for IROM */ + /* CLK_DIV_FSYS2 */ + writel(0x0000000F, &clk->div_fsys2); /* MMC2 - SDMMC */ + /* CLK_DIV_FSYS3 */ + writel(0x00000100, &clk->div_fsys3); /* MMC4 - eMMC */ +} + diff --git a/board/insignal/origen_quad/dmc.c b/board/insignal/origen_quad/dmc.c new file mode 100644 index 0000000..412f33a --- /dev/null +++ b/board/insignal/origen_quad/dmc.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Memory setup for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/dmc.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include "setup.h" + +void mem_ctrl_init(void) +{ + struct exynos4_clock *clk = (struct exynos4_clock *)EXYNOS4_CLOCK_BASE; + struct exynos4_dmc *dmc0 = (struct exynos4_dmc *)(EXYNOS4412_DMC0_BASE); + struct exynos4_dmc *dmc1 = (struct exynos4_dmc *)(EXYNOS4412_DMC1_BASE); + + /* Set DMC to 50MHz for IROM */ + writel(0x00117713, &clk->div_dmc0); + + /* + * DMC 0 + */ + writel(0xE3855403, &dmc0->phyzqcontrol); + writel(0x71101008, &dmc0->phycontrol0); + writel(0x7110100A, &dmc0->phycontrol0); + writel(0x00000084, &dmc0->phycontrol1); + writel(0x71101008, &dmc0->phycontrol0); + writel(0x0000008C, &dmc0->phycontrol1); + writel(0x00000084, &dmc0->phycontrol1); + writel(0x0000008C, &dmc0->phycontrol1); + writel(0x00000084, &dmc0->phycontrol1); + writel(0x0FFF30CA, &dmc0->concontrol); + writel(0x00202500, &dmc0->memcontrol); + writel(0x40C01323, &dmc0->memconfig0); + writel(0x80000007, &dmc0->ivcontrol); + + writel(0x64000000, &dmc0->prechconfig); + writel(0x9C4000FF, &dmc0->phycontrol0); + writel(0x0000005D, &dmc0->timingref); + +#if (CONFIG_CLK_MPLL == 330) + writel(0x2b47654e, &dmc0->timingrow); + writel(0x35330306, &dmc0->timingdata); + writel(0x442f0365, &dmc0->timingpower); +#else + writel(0x34498691, &dmc0->timingrow); + writel(0x36330306, &dmc0->timingdata); + writel(0x50380365, &dmc0->timingpower); +#endif + sdelay(0x100000); + + writel(0x07000000, &dmc0->directcmd); + sdelay(0x100000); + + writel(0x00071C00, &dmc0->directcmd); + sdelay(0x100000); + + writel(0x00010BFC, &dmc0->directcmd); + sdelay(0x100000); + + writel(0x00000608, &dmc0->directcmd); + writel(0x00000810, &dmc0->directcmd); + writel(0x00000C08, &dmc0->directcmd); + + /* + * DMC 1 + */ + writel(0xE3855403, &dmc1->phyzqcontrol); + writel(0x71101008, &dmc1->phycontrol0); + writel(0x7110100A, &dmc1->phycontrol0); + writel(0x00000084, &dmc1->phycontrol1); + writel(0x71101008, &dmc1->phycontrol0); + writel(0x0000008C, &dmc1->phycontrol1); + writel(0x00000084, &dmc1->phycontrol1); + writel(0x0000008C, &dmc1->phycontrol1); + writel(0x00000084, &dmc1->phycontrol1); + writel(0x0FFF30CA, &dmc1->concontrol); + writel(0x00202500, &dmc1->memcontrol); + writel(0x40C01323, &dmc1->memconfig0); + writel(0x80000007, &dmc1->ivcontrol); + writel(0x64000000, &dmc1->prechconfig); + writel(0x9C4000FF, &dmc1->phycontrol0); + writel(0x0000005D, &dmc1->timingref); + +#if (CONFIG_CLK_MPLL == 330) + writel(0x2b47654e, &dmc1->timingrow); + writel(0x35330306, &dmc1->timingdata); + writel(0x442f0365, &dmc1->timingpower); +#else + writel(0x34498691, &dmc1->timingrow); + writel(0x36330306, &dmc1->timingdata); + writel(0x50380365, &dmc1->timingpower); +#endif + sdelay(0x100000); + + writel(0x07000000, &dmc1->directcmd); + sdelay(0x100000); + + writel(0x00071C00, &dmc1->directcmd); + sdelay(0x100000); + + writel(0x00010BFC, &dmc1->directcmd); + sdelay(0x100000); + + writel(0x00000608, &dmc1->directcmd); + writel(0x00000810, &dmc1->directcmd); + writel(0x00000C08, &dmc1->directcmd); +} + +void mem_ctrl_init_2nd(void) +{ + struct exynos4_dmc *dmc0 = (struct exynos4_dmc *)(EXYNOS4_MIU_BASE); + struct exynos4_dmc *dmc1 = (struct exynos4_dmc *)(EXYNOS4_MIU_BASE + 0x10000); + + writel(0x7F10100A, &dmc0->phycontrol0); + writel(0xE0000084, &dmc0->phycontrol1); + writel(0x7F10100B, &dmc0->phycontrol0); + sdelay(20000); + writel(0x0000008C, &dmc0->phycontrol1); + writel(0x00000084, &dmc0->phycontrol1); + sdelay(20000); + + writel(0x7F10100A, &dmc1->phycontrol0); + writel(0xE0000084, &dmc1->phycontrol1); + writel(0x7F10100B, &dmc1->phycontrol0); + sdelay(20000); + writel(0x0000008C, &dmc1->phycontrol1); + writel(0x00000084, &dmc1->phycontrol1); + sdelay(20000); + + writel(0x0FFF30FA, &dmc0->concontrol); + writel(0x0FFF30FA, &dmc1->concontrol); + writel(0x00202533, &dmc0->memcontrol); + writel(0x00202533, &dmc1->memcontrol); +} diff --git a/board/insignal/origen_quad/lowlevel_init.S b/board/insignal/origen_quad/lowlevel_init.S new file mode 100644 index 0000000..427b5c6 --- /dev/null +++ b/board/insignal/origen_quad/lowlevel_init.S @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Lowlevel initialize for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/cpu.h> +#include "setup.h" + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + + /* use iRAM stack in bl2 */ + ldr sp, =0x02060000 + stmdb r13!, {ip,lr} + + /* check reset status */ + ldr r0, =(EXYNOS4_POWER_BASE + 0x800) /* INFORM1 */ + ldr r1, [r0] + + /* AFTR wakeup reset */ + ldr r2, =S5P_CHECK_DIDLE + cmp r1, r2 + beq exit_wakeup + + /* LPA wakeup reset */ + ldr r2, =S5P_CHECK_LPA + cmp r1, r2 + beq exit_wakeup + + /* Sleep wakeup reset */ + ldr r2, =S5P_CHECK_SLEEP + cmp r1, r2 + beq wakeup_reset + + /* + * If U-boot is already running in RAM, no need to relocate U-Boot. + * Memory controller must be configured before relocating U-Boot + * in ram. + */ + ldr r0, =0x0ffffff /* r0 <- Mask Bits*/ + bic r1, pc, r0 /* pc <- current addr of code */ + /* r1 <- unmasked bits of pc */ + ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ + bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ + cmp r1, r2 /* compare r1, r2 */ + beq 1f /* r0 == r1 then skip sdram init */ + +#ifdef CONFIG_PMIC + /* PMIC initialize */ + bl pmic_init +#endif + + /* DMC initialize */ + bl mem_ctrl_init + + /* CMU initialize */ + bl clock_ctrl_init + + /* DMC initialize */ + bl mem_ctrl_init_2nd + + /* Trust zone initialize */ + bl tzpc_init + +1: + ldmia r13!, {ip,pc} + +wakeup_reset: + bl clock_ctrl_init + bl mem_ctrl_init + bl tzpc_init + +exit_wakeup: + /* Load return address and jump to kernel */ + ldr r0, =(EXYNOS4_POWER_BASE + 0x800) /* INFORM0 */ + + /* r1 = physical address of exynos4_cpu_resume function*/ + ldr r1, [r0] + + /* Jump to kernel */ + mov pc, r1 + nop + nop + +/* + * Setting TZPC[TrustZone Protection Controller] + */ +tzpc_init: + + ldr r0, =TZPC0_BASE + mov r1, #0x0 + str r1, [r0] + mov r1, #0xff + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + mov r1, #0xbd + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + mov r1, #0xff + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC1_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC2_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC3_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC4_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC5_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + mov pc, lr + diff --git a/board/insignal/origen_quad/origen_quad.c b/board/insignal/origen_quad/origen_quad.c new file mode 100644 index 0000000..51bf5ff --- /dev/null +++ b/board/insignal/origen_quad/origen_quad.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Board initialize for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/power.h> +#include "setup.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("\nBoard: " CONFIG_BOARDNAME "\n"); + return 0; +} +#endif + + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); + +#ifdef CONFIG_RESERVED_DRAM + gd->ram_size -= CONFIG_RESERVED_DRAM; +#endif + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE); + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); + +#ifdef CONFIG_RESERVED_DRAM + gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= CONFIG_RESERVED_DRAM; +#endif +} + +#ifdef CONFIG_GENERIC_MMC +int board_emmc_init(void) +{ + int err; + err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); + if (err) { + debug("SDMMC0 not configured\n"); + return err; + } + return s5p_mmc_init(0, 8); +} + +int board_sdmmc_init(void) +{ + int err; + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) { + debug("SDMMC2 not configured\n"); + return err; + } + return s5p_mmc_init(2, 4); +} + +int board_mmc_init(bd_t *bis) +{ + int err; + + struct exynos4_power *power = (struct exynos4_power *)samsung_get_base_power(); + + if ((power->om_stat & 0x1E) == 0x8) { + err = board_emmc_init(); + err = board_sdmmc_init(); + } else { + err = board_sdmmc_init(); + err = board_emmc_init(); + } + + return 0; +} +#endif + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + if (smc9115_pre_init()) + return -1; + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return 0; +} + +static int board_uart_init(void) +{ + int err; + err = exynos_pinmux_config(PERIPH_ID_UART, PINMUX_FLAG_NONE); + if (err) + debug("UART%d not configured\n", + PERIPH_ID_UART - PERIPH_ID_UART0); + return err; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int err; + err = board_uart_init(); + if (err) + debug("UART%d init failed\n", + PERIPH_ID_UART - PERIPH_ID_UART0); + return err; +} +#endif diff --git a/board/insignal/origen_quad/pmic.c b/board/insignal/origen_quad/pmic.c new file mode 100644 index 0000000..070a3a5 --- /dev/null +++ b/board/insignal/origen_quad/pmic.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * PMIC setup for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include "setup.h" + +int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) +{ + return 0; +} + +int pmic_reg_write(struct pmic *p, u32 reg, u32 *val) +{ + return 0; +} + +void pmic_init(void) +{ + /* PS-Hold high */ + writel(0x5300, EXYNOS4_POWER_BASE + 0x330c); +} + diff --git a/board/insignal/origen_quad/setup.h b/board/insignal/origen_quad/setup.h new file mode 100644 index 0000000..98a6171 --- /dev/null +++ b/board/insignal/origen_quad/setup.h @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Configuration settings for the Insignal Origen QUAD board (Exynos4412) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SETUP_ORIGEN_QUAD_H +#define __SETUP_ORIGEN_QUAD_H + +#include <config.h> +#include <version.h> +#include <asm/arch/cpu.h> + +/* Set PLL */ +#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) + +/* APLL */ +#define set_clk_div_cpu0(core2, apll, pclk_dbg, atb, periph, corem1, corem0, core) \ + ((core2 << 28) \ + |(apll << 24) \ + |(pclk_dbg << 20) \ + |(atb << 16) \ + |(periph <<12) \ + |(corem1 << 8) \ + |(corem0 << 4) \ + |(core)) +#define set_clk_div_cpu1(cores, hpm, copy) \ + ((cores << 8) \ + |(hpm << 4) \ + |(copy)) + +#if (CONFIG_CLK_APLL == 800) +#define APLL_CON0_VAL set_pll(0x64, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 1, 1, 3, 7, 5, 2, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(3, 0, 3) +#elif (CONFIG_CLK_APLL == 1000) +#define APLL_CON0_VAL set_pll(0x7D, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 1, 1, 4, 7, 5, 2, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(3, 0, 4) +#elif (CONFIG_CLK_APLL == 1100) +#define APLL_CON0_VAL set_pll(0x113, 0x6, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 4, 7, 6, 3, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(4, 0, 4) +#elif (CONFIG_CLK_APLL == 1200) +#define APLL_CON0_VAL set_pll(0x96, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 5, 7, 7, 3, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(4, 0, 4) +#elif (CONFIG_CLK_APLL == 1300) +#define APLL_CON0_VAL set_pll(0x145, 0x6, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 5, 7, 7, 3, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 5) +#elif (CONFIG_CLK_APLL == 1400) +#define APLL_CON0_VAL set_pll(0xAF, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 6, 7, 7, 3, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 6) +#elif (CONFIG_CLK_APLL == 1500) +#define APLL_CON0_VAL set_pll(0xFA, 0x3, 0x0) +#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 6, 7, 7, 4, 0) +#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 6) +#else +#error Not supported APLL freq +#endif + +#define APLL_CON1_VAL (0x00803800) +#define APLL_LOCK_VAL (((APLL_CON0_VAL >> 8) & 0x3F) * 270) + +/* EPLL */ +#define EPLL_CON0_VAL set_pll(0x40, 0x2, 0x3) +#define EPLL_CON1_VAL (0x66010000) +#define EPLL_CON2_VAL (0x00000080) +#define EPLL_LOCK_VAL (((EPLL_CON0_VAL >> 8) & 0x3F) * 3000) + +/* MPLL */ +#if (CONFIG_CLK_MPLL == 200) +#define MPLL_CON0_VAL set_pll(0x64, 0x3, 0x1) +#elif (CONFIG_CLK_MPLL == 330) +#define MPLL_CON0_VAL set_pll(0x116, 0x5, 0x1) +#elif (CONFIG_CLK_MPLL == 400) +#define MPLL_CON0_VAL set_pll(0x64, 0x3, 0x0) +#else +#error Not supported MPLL freq +#endif +#define MPLL_CON1_VAL (0x00803800) +#define MPLL_LOCK_VAL (((MPLL_CON0_VAL >> 8) & 0x3F) * 270) + +/* VPLL */ +#define VPLL_CON0_VAL set_pll(0x48, 0x2, 0x3) +#define VPLL_CON1_VAL (0x66010000) +#define VPLL_CON2_VAL (0x00000080) +#define VPLL_LOCK_VAL (((EPLL_CON0_VAL >> 8) & 0x3F) * 3000) + +/* CLK_SRC_CPU */ +#define MUX_MPLL_USER_SEL 1 +#define MUX_HPM_SEL 0 +#define MUX_CORE_SEL 0 +#define MUX_APLL_SEL 1 +#define CLK_SRC_CPU_VAL ((MUX_MPLL_USER_SEL << 24) \ + |(MUX_HPM_SEL << 20) \ + |(MUX_CORE_SEL << 16) \ + |(MUX_APLL_SEL)) + +/* CLK_SRC_TOP0 */ +#define MUX_ONENAND_SEL 0x0 /* 0 = DOUT133, 1 = DOUT166 */ +#define MUX_ACLK_133_SEL 0x0 /* 0 = SCLKMPLL, 1 = SCLKAPLL */ +#define MUX_ACLK_160_SEL 0x0 +#define MUX_ACLK_100_SEL 0x0 +#define MUX_ACLK_200_SEL 0x0 +#define MUX_VPLL_SEL 0x1 +#define MUX_EPLL_SEL 0x1 +#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL << 28) \ + |(MUX_ACLK_133_SEL << 24) \ + |(MUX_ACLK_160_SEL << 20) \ + |(MUX_ACLK_100_SEL << 16) \ + |(MUX_ACLK_200_SEL << 12) \ + |(MUX_VPLL_SEL << 8) \ + |(MUX_EPLL_SEL << 4)) + +/* CLK_SRC_TOP1 */ +#define VPLLSRC_SEL 0x0 /* 0 = FINPLL, 1 = SCLKHDMI27M */ +#define CLK_SRC_TOP1_VAL (0x01111000) + +/* CLK_DIV_TOP */ +#define ACLK_400_MCUISP_RATIO 0x1 +#define ACLK_266_GPS_RATIO 0x2 +#define ONENAND_RATIO 0x1 +#define ACLK_133_RATIO 0x5 +#define ACLK_160_RATIO 0x4 +#define ACLK_100_RATIO 0x7 +#define ACLK_200_RATIO 0x4 +#define CLK_DIV_TOP_VAL ((ACLK_400_MCUISP_RATIO << 24) \ + |(ACLK_266_GPS_RATIO << 20) \ + |(ONENAND_RATIO << 16) \ + |(ACLK_133_RATIO << 12) \ + |(ACLK_160_RATIO << 8) \ + |(ACLK_100_RATIO << 4) \ + |(ACLK_200_RATIO)) + +/* CLK_SRC_LEFTBUS */ +#define CLK_SRC_LEFTBUS_VAL (0x10) + +/* CLK_DIV_LEFRBUS */ +#define GPL_RATIO 0x1 +#define GDL_RATIO 0x3 +#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4)|(GDL_RATIO)) + +/* CLK_SRC_RIGHTBUS */ +#define CLK_SRC_RIGHTBUS_VAL (0x10) + +/* CLK_DIV_RIGHTBUS */ +#define GPR_RATIO 0x1 +#define GDR_RATIO 0x3 +#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4)|(GDR_RATIO)) + +/* CLK_SRC_DMC */ +#define MUX_PWI_SEL 0x1 +#define MUX_CORE_TIMERS_SEL 0x1 +#define MUX_DPHY_SEL 0x0 +#define MUX_DMC_BUS_SEL 0x0 +#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL << 16) \ + |(MUX_CORE_TIMERS_SEL << 12) \ + |(MUX_DPHY_SEL << 8) \ + |(MUX_DMC_BUS_SEL << 4)) + +/* CLK_DIV_DMC0 */ +#define CORE_TIMERS_RATIO 0x0 +#define COPY2_RATIO 0x0 +#define DMCP_RATIO 0x1 +#define DMCD_RATIO 0x1 +#if (CONFIG_CLK_MPLL == 200) +#define DMC_RATIO 0x3 +#else +#define DMC_RATIO 0x1 +#endif +#define DPHY_RATIO 0x1 +#define ACP_PCLK_RATIO 0x1 +#define ACP_RATIO 0x3 + +#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ + |(COPY2_RATIO << 24) \ + |(DMCP_RATIO << 20) \ + |(DMCD_RATIO << 16) \ + |(DMC_RATIO << 12) \ + |(DPHY_RATIO << 8) \ + |(ACP_PCLK_RATIO << 4) \ + |(ACP_RATIO)) + +#define CLK_DIV_DMC1_VAL (0x07071713) + +/* CLK_SRC_PERIL0 */ +#define UART4_SEL 1 +#define UART3_SEL 1 +#define UART2_SEL 1 +#define UART1_SEL 1 +#define UART0_SEL 1 +#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \ + |(UART3_SEL << 12) \ + |(UART2_SEL<< 8) \ + |(UART1_SEL << 4) \ + |(UART0_SEL)) + +/* CLK_DIV_PERIL0 */ +#define UART4_RATIO 3 +#define UART3_RATIO 3 +#define UART2_RATIO 3 +#define UART1_RATIO 3 +#define UART0_RATIO 3 +#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \ + |(UART3_RATIO << 12) \ + |(UART2_RATIO << 8) \ + |(UART1_RATIO << 4) \ + |(UART0_RATIO)) + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* TZPC */ +#define TZPC_BASE 0x10110000 +#define TZPC_OFFSET 0x10000 +#define TZPC0_BASE (TZPC_BASE) +#define TZPC1_BASE (TZPC0_BASE + TZPC_OFFSET) +#define TZPC2_BASE (TZPC1_BASE + TZPC_OFFSET) +#define TZPC3_BASE (TZPC2_BASE + TZPC_OFFSET) +#define TZPC4_BASE (TZPC3_BASE + TZPC_OFFSET) +#define TZPC5_BASE (TZPC4_BASE + TZPC_OFFSET) +#define TZPC_DECPROT0SET_OFFSET 0x804 +#define TZPC_DECPROT1SET_OFFSET 0x810 +#define TZPC_DECPROT2SET_OFFSET 0x81C +#define TZPC_DECPROT3SET_OFFSET 0x828 + +/* IMAGE SIZE (BYTE) */ +#define MBR_BYTE_COUNT CONFIG_MBR_SIZE +#define SBL_BYTE_COUNT CONFIG_SBL_SIZE +#define BL1_BYTE_COUNT CONFIG_BL1_SIZE +#define BL2_BYTE_COUNT CONFIG_BL2_SIZE +#define ENV_BYTE_COUNT CONFIG_ENV_SIZE + +/* IMAGE OFFSET (BYTE) */ +#define MBR_BYTE_OFFSET (0) +#define SBL_BYTE_OFFSET (MBR_BYTE_OFFSET + MBR_BYTE_COUNT) +#define BL1_BYTE_OFFSET (SBL_BYTE_OFFSET + SBL_BYTE_COUNT) +#define BL2_BYTE_OFFSET (BL1_BYTE_OFFSET + BL1_BYTE_COUNT) +#define ENV_BYTE_OFFSET (Bl2_BYTE_OFFSET + BL2_BYTE_COUNT) + +#define SDMMC_BLK_SIZE (512) + +/* IMAGE SIZE (BLOCK) */ +#define SBL_BLK_COUNT (SBL_BYTE_COUNT / SDMMC_BLK_SIZE) +#define BL1_BLK_COUNT (BL1_BYTE_COUNT / SDMMC_BLK_SIZE) +#define BL2_BLK_COUNT (BL2_BYTE_COUNT / SDMMC_BLK_SIZE) +#define ENV_BLK_COUNT (ENV_BYTE_COUNT / SDMMC_BLK_SIZE) + +/* IMAGE OFFSET (BLOCK) */ +#define SBL_BLK_OFFSET (SBL_BYTE_OFFSET / SDMMC_BLK_SIZE) +#define BL1_BLK_OFFSET (BL1_BYTE_OFFSET / SDMMC_BLK_SIZE) +#define BL2_BLK_OFFSET (BL2_BYTE_OFFSET / SDMMC_BLK_SIZE) +#define ENV_BLK_OFFSET (ENV_BYTE_OFFSET / SDMMC_BLK_SIZE) + +/* UART */ +#if defined(CONFIG_SERIAL0) +#define PERIPH_ID_UART PERIPH_ID_UART0 +#elif defined(CONFIG_SERIAL1) +#define PERIPH_ID_UART PERIPH_ID_UART1 +#elif defined(CONFIG_SERIAL2) +#define PERIPH_ID_UART PERIPH_ID_UART2 +#elif defined(CONFIG_SERIAL3) +#define PERIPH_ID_UART PERIPH_ID_UART3 +#endif + +#ifndef __ASSEMBLY__ +void sdelay(unsigned long); +void clock_ctrl_init(void); +void mem_ctrl_init(void); +void tzpc_init(void); +#endif + +#endif /* __SETUP_ORIGEN_QUAD_H */ diff --git a/boards.cfg b/boards.cfg index d2ccb41..492d503 100644 --- a/boards.cfg +++ b/boards.cfg @@ -264,6 +264,7 @@ s5pc210_universal arm armv7 universal_c210 samsung smdk5250 arm armv7 smdk5250 samsung exynos smdkv310 arm armv7 smdkv310 samsung exynos trats arm armv7 trats samsung exynos +origen_quad arm armv7 origen_quad insignal exynos harmony arm armv7 harmony nvidia tegra2 seaboard arm armv7 seaboard nvidia tegra2 ventana arm armv7 ventana nvidia tegra2 diff --git a/include/configs/origen_quad.h b/include/configs/origen_quad.h new file mode 100644 index 0000000..7e39ee1 --- /dev/null +++ b/include/configs/origen_quad.h @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Copyright (C) 2012 Insignal + * + * Configuration settings for the Insignal OrigenQUAD board (Exynos4x12) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_ORIGEN_QUAD_H +#define __CONFIG_ORIGEN_QUAD_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS4 /* which is in a Exynos4 series */ +#define CONFIG_EXYNOS4412 /* which is in a Exynos4412 */ +#define CONFIG_ORIGEN_QUAD /* which is in a ORIGEN QUAD */ +#define CONFIG_BOARDNAME "Origen" +#define CONFIG_IDENT_STRING " for Insignal Origen" +#define CONFIG_MACH_TYPE 3455 + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +/* + * Clock / PLL + */ +#define CONFIG_SYS_CLK_FREQ 24000000 /* 24MHz input clock */ +#define CONFIG_CLK_APLL 1000 +#define CONFIG_CLK_MPLL 400 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_PWM + +/* + * Memory + */ +/* Default address */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 << 20UL) +/* Cache */ +#define CONFIG_SYS_DCACHE_OFF /* Keep L2 Cache Disabled */ +/* DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 /* 256 MB * 4 = 1 GB */ +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (PHYS_SDRAM_3 + PHYS_SDRAM_3_SIZE) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +/* Reserved */ +#define CONFIG_RESERVED_DRAM 0x100000 +/* Mem test */ +#define CONFIG_CMD_MEMORY +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_4 + PHYS_SDRAM_4_SIZE - (8UL << 20UL)) + +/* + * Serial + */ +#define CONFIG_SERIAL2 2 /* use SERIAL2 in 0~3 */ +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 115200 + +/* + * PMIC + */ +#define CONFIG_PMIC 1 + +/* + * SD/MMC + */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_S5P_SDHCI +#define CONFIG_CMD_MMC + +/* + * File System + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/* + * Flash + */ +#define CONFIG_SYS_NO_FLASH + +/* + * Image map on sdmmc/emmc + */ +#define CONFIG_SECURE_BL1_ONLY +#define CONFIG_SPL +#define CONFIG_MBR_SIZE (512) +#define CONFIG_SBL_SIZE (8UL << 10) /* 8KB */ +#define CONFIG_BL1_SIZE (16UL << 10) /* 16KB */ +#define CONFIG_BL2_SIZE (512UL << 10) /* 512KB */ + +/* + * Console + */ +#define CONFIG_SYS_PROMPT CONFIG_BOARDNAME " # " +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ + +/* + * Commands + */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET (CONFIG_MBR_SIZE \ + +CONFIG_SBL_SIZE \ + +CONFIG_BL1_SIZE \ + +CONFIG_BL2_SIZE) +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ +#define CONFIG_ENV_OVERWRITE +/* Default */ +#define CONFIG_BOOTCOMMAND "fatload mmc 0 40008000 uImage; bootm 40008000" + +/* + * Misc + */ +/* Initialize */ +#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 +/* display information */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +/* Delay */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK +/* TAGS */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif /* __CONFIG_ORIGEN_QUAD_H */ diff --git a/tools/Makefile b/tools/Makefile index a478179..1753a45 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -68,6 +68,7 @@ BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) BIN_FILES-y += mkenvimage$(SFX) BIN_FILES-y += mkimage$(SFX) +BIN_FILES-$(CONFIG_EXYNOS4) += mkexynosspl$(SFX) BIN_FILES-$(CONFIG_EXYNOS5) += mkexynosspl$(SFX) BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) @@ -96,6 +97,7 @@ NOPED_OBJ_FILES-y += imximage.o NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkenvimage.o NOPED_OBJ_FILES-y += mkimage.o +OBJ_FILES-$(CONFIG_EXYNOS4) += mkexynosspl.o OBJ_FILES-$(CONFIG_EXYNOS5) += mkexynosspl.o OBJ_FILES-$(CONFIG_MX28) += mxsboot.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o