The pinctrl datas of uniphier SoCs are the minimal subsets of kernel's one, and some tables has no data to save the footprint size. If the board dts tries to match a pin name on no pins defined SoC, the footprint magic code causes "Synchronous Abort".

This checks if the 'pins' data is valid, and if empty, avoids the abort with the warning as follows:

WARNING at drivers/pinctrl/uniphier/pinctrl-uniphier-core.c:36/uniphier_pinctrl_get_pins_count()! pinctrl_select_state_full: pinctrl_config_one: err=-38

Signed-off-by: Dai Okamura okamura.dai@socionext.com --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 631bb1f963..bdca3f2f71 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -33,6 +33,9 @@ static int uniphier_pinctrl_get_pins_count(struct udevice *dev) const struct uniphier_pinctrl_pin *pins = priv->socdata->pins; int pins_count = priv->socdata->pins_count;

+ if (WARN_ON(!pins_count)) + return 0; /* no table of pins */ + /* * We do not list all pins in the pin table to save memory footprint. * Report the max pin number + 1 to fake the framework.

PXs3 Ref boards need to change the strength of ethernet ports for stability, like LD20's one.

This adds the table data and fixes the boot issue on PXs3 Ref board.

Fixes: 0852033309 ("ARM: uniphier: sync with Linux 5.8-rc4") Signed-off-by: Dai Okamura okamura.dai@socionext.com --- .../pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 1fc7bdb5c8..8a8f1269bb 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Socionext Inc. + * Copyright (C) 2017-2021 Socionext Inc. * Author: Masahiro Yamada yamada.masahiro@socionext.com + * Author: Dai Okamura dai.okamura@socionext.com */

#include <common.h> @@ -10,6 +11,21 @@

#include "pinctrl-uniphier.h"

+static const struct uniphier_pinctrl_pin uniphier_pxs3_pins[] = { + UNIPHIER_PINCTRL_PIN(62, "RGMII0_TXCLK", 28, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(63, "RGMII0_TXD0", 29, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(64, "RGMII0_TXD1", 30, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(65, "RGMII0_TXD2", 31, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(66, "RGMII0_TXD3", 32, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(67, "RGMII0_TXCTL", 33, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(78, "RGMII1_TXCLK", 44, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(79, "RGMII1_TXD0", 45, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(80, "RGMII1_TXD1", 46, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(81, "RGMII1_TXD2", 47, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(82, "RGMII1_TXD3", 48, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(83, "RGMII1_TXCTL", 49, UNIPHIER_PIN_DRV_2BIT), +}; + static const unsigned emmc_pins[] = {31, 32, 33, 34, 35, 36, 37, 38}; static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_dat8_pins[] = {39, 40, 41, 42}; @@ -121,6 +137,8 @@ static const char * const uniphier_pxs3_functions[] = { };

static struct uniphier_pinctrl_socdata uniphier_pxs3_pinctrl_socdata = { + .pins = uniphier_pxs3_pins, + .pins_count = ARRAY_SIZE(uniphier_pxs3_pins), .groups = uniphier_pxs3_groups, .groups_count = ARRAY_SIZE(uniphier_pxs3_groups), .functions = uniphier_pxs3_functions,

All uniphier v7 SoCs have cortex-a9 and use cortex-a9 global timer in a simple implementation. Now DM_TIMER of it is available on 35751c7f3f ("timer: sti: convert sti-timer to arm a9 global timer"), so let's switch to it.

The old driver reads the lower 32bits of counter field and sets the prescaler as 50 with PERIPHCLK(=50MHz), so the global timer works as a 32-bit 1MHz timer.

The DM_TIMER uses the whole 64bits with no prescaler, so the global timer works as a 64-bit PERIPHCLK timer.

CONFIG_SYS_HZ_CLOCK is set as the default PERIPHCLK frequency, if there is no 'clocks' property in devicetree.

Signed-off-by: Dai Okamura okamura.dai@socionext.com --- arch/arm/dts/uniphier-v7-u-boot.dtsi | 4 +++ arch/arm/mach-uniphier/Kconfig | 1 + arch/arm/mach-uniphier/arm32/Makefile | 2 -- arch/arm/mach-uniphier/arm32/timer.c | 39 --------------------------- configs/uniphier_v7_defconfig | 2 ++ include/configs/uniphier.h | 3 +-- 6 files changed, 8 insertions(+), 43 deletions(-) delete mode 100644 arch/arm/mach-uniphier/arm32/timer.c

diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi b/arch/arm/dts/uniphier-v7-u-boot.dtsi index 9459bf0377..603b33dd2b 100644 --- a/arch/arm/dts/uniphier-v7-u-boot.dtsi +++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi @@ -2,6 +2,10 @@ soc { u-boot,dm-pre-reloc;

+ timer@60000200 { + u-boot,dm-pre-reloc; + }; + serial@54006800 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 3a8eee7b84..e489eedec6 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -12,6 +12,7 @@ config ARCH_UNIPHIER_V7_MULTI select ARMV7_NONSEC select CPU_V7A select CPU_V7_HAS_NONSEC + select ARM_GLOBAL_TIMER

config ARCH_UNIPHIER_V8_MULTI bool "UniPhier V8 SoCs" diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile index 3cd00b7e5e..b41aba7e29 100644 --- a/arch/arm/mach-uniphier/arm32/Makefile +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -8,5 +8,3 @@ obj-y += late_lowlevel_init.o obj-y += cache-uniphier.o obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o endif - -obj-y += timer.o diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c deleted file mode 100644 index a40bdf1705..0000000000 --- a/arch/arm/mach-uniphier/arm32/timer.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012-2015 Masahiro Yamada yamada.masahiro@socionext.com - */ - -#include <config.h> -#include <init.h> -#include <linux/io.h> - -#include "arm-mpcore.h" - -#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ -#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) - -static void *get_global_timer_base(void) -{ - void *val; - - asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory"); - - return val + GLOBAL_TIMER_OFFSET; -} - -unsigned long timer_read_counter(void) -{ - /* - * ARM 64bit Global Timer is too much for our purpose. - * We use only lower 32 bit of the timer counter. - */ - return readl(get_global_timer_base() + GTIMER_CNT_L); -} - -int timer_init(void) -{ - /* enable timer */ - writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL); - - return 0; -} diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index e3087a9109..591799ff35 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x85000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 CONFIG_SYS_MONITOR_LEN=2097152 +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 32b47db346..47a7408268 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -36,8 +36,7 @@ BOOT_TARGET_DEVICE_USB(func)

#if !defined(CONFIG_ARM64) -/* Time clock 1MHz */ -#define CONFIG_SYS_TIMER_RATE 1000000 +#define CONFIG_SYS_HZ_CLOCK 50000000 #endif

#define CONFIG_SYS_NAND_REGS_BASE 0x68100000