[PATCH 00/10] rockchip: px30: migrate to common bss and stack addresses + UART fixes for evb-px30
PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper pre-reloc. Something needed to be done. Jonas did migrate a few SoCs already to this common bss+stack addresses so it made sense to follow the same route for one additional SoC: PX30.
While at it, also fix a few issues related to UART on the PX30 Mini EVB I could test.
Boot (to U-Boot CLI) tested on PX30 Ringneck and PX30 Mini-EVB.
Thanks to Jonas for hinting where to look at.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- Quentin Schulz (10): rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level rockchip: Use common bss and stack addresses on PX30 rockchip: ringneck_px30: Use common bss and stack addresses rockchip: evb-px30: Use common bss and stack addresses rockchip: firefly-px30: Use common bss and stack addresses rockchip: odroid-go2: Use common bss and stack addresses rockchip: px30-core-*: Use common bss and stack addresses rockchip: px30: make UART pinmux accessible to TPL/SPL DTB rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB rockchip: evb-px30: make UART5 the debug UART
arch/arm/dts/px30-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 8 +++++++- configs/evb-px30_defconfig | 23 +++++------------------ configs/firefly-px30_defconfig | 19 +++---------------- configs/odroid-go2_defconfig | 19 +++---------------- configs/px30-core-ctouch2-of10-px30_defconfig | 19 +++---------------- configs/px30-core-ctouch2-px30_defconfig | 19 +++---------------- configs/px30-core-edimm2.2-px30_defconfig | 19 +++---------------- configs/ringneck-px30_defconfig | 19 +++---------------- 9 files changed, 46 insertions(+), 115 deletions(-) --- base-commit: a7f0154c412859323396111dd0c09dbafbc153cb change-id: 20240521-px30-2024-07-rc-7136f6241d29
Best regards,
From: Quentin Schulz quentin.schulz@cherry.de
This is the kind of setting that typically doesn't need to be changed between boards based on the same SoC, so let's make it the default in PX30 Kconfig so we don't have to care about it in the defconfig if we don't want to.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- arch/arm/mach-rockchip/px30/Kconfig | 3 +++ configs/evb-px30_defconfig | 1 - configs/firefly-px30_defconfig | 1 - configs/odroid-go2_defconfig | 1 - configs/px30-core-ctouch2-of10-px30_defconfig | 1 - configs/px30-core-ctouch2-px30_defconfig | 1 - configs/px30-core-edimm2.2-px30_defconfig | 1 - configs/ringneck-px30_defconfig | 1 - 8 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 23f8f430c4a..e39472604c3 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -83,6 +83,9 @@ config TPL_TEXT_BASE config TPL_STACK default 0xff0e4fff
+config TPL_SYS_MALLOC_F_LEN + default 0x600 + config DEBUG_UART_CHANNEL int "Mux channel to use for debug UART2/UART3" depends on DEBUG_UART_BOARD_INIT diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 07c56a45ec0..73a3c6120e0 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -16,7 +16,6 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_EVB_PX30=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index e5377dcdf3d..0a14b393667 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_EVB_PX30=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 99d7149a44c..3c1abb83ed9 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -19,7 +19,6 @@ CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index a2801ec7796..87a39e115df 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index cc33e275742..7162c117beb 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 99e1b2fc7ae..1182f60358f 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 67a44eda684..0df1b8a59ac 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_RINGNECK_PX30=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
Am Dienstag, 21. Mai 2024, 19:39:54 CEST schrieb Quentin Schulz:
From: Quentin Schulz quentin.schulz@cherry.de
This is the kind of setting that typically doesn't need to be changed between boards based on the same SoC, so let's make it the default in PX30 Kconfig so we don't have to care about it in the defconfig if we don't want to.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
the TPL part should be pretty similar for all boards, so having the malloc pool size centrally makes a lot of sense.
Reviewed-by: Heiko Stuebner heiko@sntech.de
On 2024/5/22 01:39, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
This is the kind of setting that typically doesn't need to be changed between boards based on the same SoC, so let's make it the default in PX30 Kconfig so we don't have to care about it in the defconfig if we don't want to.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/px30/Kconfig | 3 +++ configs/evb-px30_defconfig | 1 - configs/firefly-px30_defconfig | 1 - configs/odroid-go2_defconfig | 1 - configs/px30-core-ctouch2-of10-px30_defconfig | 1 - configs/px30-core-ctouch2-px30_defconfig | 1 - configs/px30-core-edimm2.2-px30_defconfig | 1 - configs/ringneck-px30_defconfig | 1 - 8 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 23f8f430c4a..e39472604c3 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -83,6 +83,9 @@ config TPL_TEXT_BASE config TPL_STACK default 0xff0e4fff
+config TPL_SYS_MALLOC_F_LEN
- default 0x600
- config DEBUG_UART_CHANNEL int "Mux channel to use for debug UART2/UART3" depends on DEBUG_UART_BOARD_INIT
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 07c56a45ec0..73a3c6120e0 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -16,7 +16,6 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_EVB_PX30=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index e5377dcdf3d..0a14b393667 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_EVB_PX30=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 99d7149a44c..3c1abb83ed9 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -19,7 +19,6 @@ CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index a2801ec7796..87a39e115df 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index cc33e275742..7162c117beb 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 99e1b2fc7ae..1182f60358f 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 67a44eda684..0df1b8a59ac 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_RINGNECK_PX30=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
From: Quentin Schulz quentin.schulz@cherry.de
See commit 008ba0d56d00 ("rockchip: Add common default bss and stack addresses") for memory layout. This migrates PX30 to use the new layout, except for TPL. Indeed, PX30 is extremely limited in SRAM, so we need to be extra careful about what goes into the TPL and how much we can allocate there, so let's keep the current value for TPL_SYS_MALLOC_F_LEN (already present in the PX30-specific Kconfig, from an earlier commit).
This will allow us to use the same memory layout on one more Rockchip SoC, which is always a nice thing. Additionally, this will make it easier to fix U-Boot proper pre-reloc running out of memory on PX30 in a subsequent commit.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- arch/arm/mach-rockchip/px30/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index e39472604c3..dcf9eb8144b 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -68,8 +68,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "px30"
+config ROCKCHIP_COMMON_STACK_ADDR + default y + config SYS_MALLOC_F_LEN - default 0x400 + default 0x400 if !SPL_SHARES_INIT_SP_ADDR
config SPL_SERIAL default y
On 2024/5/22 01:39, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
See commit 008ba0d56d00 ("rockchip: Add common default bss and stack addresses") for memory layout. This migrates PX30 to use the new layout, except for TPL. Indeed, PX30 is extremely limited in SRAM, so we need to be extra careful about what goes into the TPL and how much we can allocate there, so let's keep the current value for TPL_SYS_MALLOC_F_LEN (already present in the PX30-specific Kconfig, from an earlier commit).
This will allow us to use the same memory layout on one more Rockchip SoC, which is always a nice thing. Additionally, this will make it easier to fix U-Boot proper pre-reloc running out of memory on PX30 in a subsequent commit.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/px30/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index e39472604c3..dcf9eb8144b 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -68,8 +68,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "px30"
+config ROCKCHIP_COMMON_STACK_ADDR
- default y
- config SYS_MALLOC_F_LEN
- default 0x400
default 0x400 if !SPL_SHARES_INIT_SP_ADDR
config SPL_SERIAL default y
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory and it is thus impossible to boot into U-Boot CLI.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- configs/ringneck-px30_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 0df1b8a59ac..94179dca3ae 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_RINGNECK_PX30=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -41,11 +29,11 @@ CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set
On 2024/5/22 01:39, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory and it is thus impossible to boot into U-Boot CLI.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/ringneck-px30_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 0df1b8a59ac..94179dca3ae 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_RINGNECK_PX30=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -41,11 +29,11 @@ CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- configs/evb-px30_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 73a3c6120e0..50ce1d7a9f3 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -2,26 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-evb" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_EVB_PX30=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -39,9 +27,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
On 2024/5/22 01:39, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/evb-px30_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 73a3c6120e0..50ce1d7a9f3 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -2,26 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-evb" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_EVB_PX30=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -39,9 +27,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- configs/firefly-px30_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 0a14b393667..063e4211fb7 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-firefly" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_EVB_PX30=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
On 2024/5/22 01:39, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/firefly-px30_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 0a14b393667..063e4211fb7 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-firefly" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_EVB_PX30=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- configs/odroid-go2_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 3c1abb83ed9..f4c9b02e12f 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -2,29 +2,17 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4000 CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -44,11 +32,11 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
On 2024/5/22 01:39, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/odroid-go2_defconfig | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 3c1abb83ed9..f4c9b02e12f 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -2,29 +2,17 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4000 CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -44,11 +32,11 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- configs/px30-core-ctouch2-of10-px30_defconfig | 18 +++--------------- configs/px30-core-ctouch2-px30_defconfig | 18 +++--------------- configs/px30-core-edimm2.2-px30_defconfig | 18 +++--------------- 3 files changed, 9 insertions(+), 45 deletions(-)
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 87a39e115df..dd005f20ff8 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 7162c117beb..f6559fbae3a 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 1182f60358f..a099e9378c9 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
On 2024/5/22 01:40, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them.
Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/px30-core-ctouch2-of10-px30_defconfig | 18 +++--------------- configs/px30-core-ctouch2-px30_defconfig | 18 +++--------------- configs/px30-core-edimm2.2-px30_defconfig | 18 +++--------------- 3 files changed, 9 insertions(+), 45 deletions(-)
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 87a39e115df..dd005f20ff8 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 7162c117beb..f6559fbae3a 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 1182f60358f..a099e9378c9 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2" -CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_SPL_STACK=0x400000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
From: Quentin Schulz quentin.schulz@cherry.de
This adds the default pinmux for UART2 and UART5 to the TPL/SPL DTB (if not removed through the CONFIG_OF_SPL_REMOVE_PROPS symbol) as those two controllers are always made available to all boards.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- arch/arm/dts/px30-u-boot.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 046da022ffe..59fa9f43a97 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -33,11 +33,27 @@ bootph-all; };
+&uart2m0_xfer { + bootph-all; +}; + &uart5 { clock-frequency = <24000000>; bootph-all; };
+&uart5_cts { + bootph-all; +}; + +&uart5_rts { + bootph-all; +}; + +&uart5_xfer { + bootph-all; +}; + &sdmmc { bootph-all;
On 2024/5/22 01:40, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
This adds the default pinmux for UART2 and UART5 to the TPL/SPL DTB (if not removed through the CONFIG_OF_SPL_REMOVE_PROPS symbol) as those two controllers are always made available to all boards.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/px30-u-boot.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 046da022ffe..59fa9f43a97 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -33,11 +33,27 @@ bootph-all; };
+&uart2m0_xfer {
- bootph-all;
+};
- &uart5 { clock-frequency = <24000000>; bootph-all; };
+&uart5_cts {
- bootph-all;
+};
+&uart5_rts {
- bootph-all;
+};
+&uart5_xfer {
- bootph-all;
+};
- &sdmmc { bootph-all;
From: Quentin Schulz quentin.schulz@cherry.de
In order to be able to properly mux UART on PX30 EVB, the pinmux needs to be done at runtime, so let's not remove the pinctrl nodes from the SPL DTB.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- configs/evb-px30_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 50ce1d7a9f3..a5833ad6d09 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y
On 2024/5/22 01:40, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
In order to be able to properly mux UART on PX30 EVB, the pinmux needs to be done at runtime, so let's not remove the pinctrl nodes from the SPL DTB.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/evb-px30_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 50ce1d7a9f3..a5833ad6d09 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y
From: Quentin Schulz quentin.schulz@cherry.de
In the Device Tree, UART5 is the system UART, but in the defconfig it currently is UART2. Let's sync the two by making the defconfig use UART5 as well.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- configs/evb-px30_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index a5833ad6d09..abe545625a5 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -10,7 +10,7 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_EVB_PX30=y # CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_BASE=0xff178000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y
On 2024/5/22 01:40, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@cherry.de
In the Device Tree, UART5 is the system UART, but in the defconfig it currently is UART2. Let's sync the two by making the defconfig use UART5 as well.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/evb-px30_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index a5833ad6d09..abe545625a5 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -10,7 +10,7 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_EVB_PX30=y # CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_BASE=0xff178000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y
On Tue, May 21, 2024 at 07:39:53PM +0200, Quentin Schulz wrote:
PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper pre-reloc. Something needed to be done. Jonas did migrate a few SoCs already to this common bss+stack addresses so it made sense to follow the same route for one additional SoC: PX30.
While at it, also fix a few issues related to UART on the PX30 Mini EVB I could test.
Boot (to U-Boot CLI) tested on PX30 Ringneck and PX30 Mini-EVB.
Thanks to Jonas for hinting where to look at.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Quentin Schulz (10): rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level rockchip: Use common bss and stack addresses on PX30 rockchip: ringneck_px30: Use common bss and stack addresses rockchip: evb-px30: Use common bss and stack addresses rockchip: firefly-px30: Use common bss and stack addresses rockchip: odroid-go2: Use common bss and stack addresses rockchip: px30-core-*: Use common bss and stack addresses rockchip: px30: make UART pinmux accessible to TPL/SPL DTB rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB rockchip: evb-px30: make UART5 the debug UART
arch/arm/dts/px30-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 8 +++++++- configs/evb-px30_defconfig | 23 +++++------------------ configs/firefly-px30_defconfig | 19 +++---------------- configs/odroid-go2_defconfig | 19 +++---------------- configs/px30-core-ctouch2-of10-px30_defconfig | 19 +++---------------- configs/px30-core-ctouch2-px30_defconfig | 19 +++---------------- configs/px30-core-edimm2.2-px30_defconfig | 19 +++---------------- configs/ringneck-px30_defconfig | 19 +++---------------- 9 files changed, 46 insertions(+), 115 deletions(-)
base-commit: a7f0154c412859323396111dd0c09dbafbc153cb change-id: 20240521-px30-2024-07-rc-7136f6241d29
As I assume we want to fix the platforms for v2024.07, is this the level of config changes everyone is comfortable with on the platforms? Or should we just go with the minimum for release and the rest to -next?
Hi Tom,
On 5/21/24 8:04 PM, Tom Rini wrote:
On Tue, May 21, 2024 at 07:39:53PM +0200, Quentin Schulz wrote:
PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper pre-reloc. Something needed to be done. Jonas did migrate a few SoCs already to this common bss+stack addresses so it made sense to follow the same route for one additional SoC: PX30.
While at it, also fix a few issues related to UART on the PX30 Mini EVB I could test.
Boot (to U-Boot CLI) tested on PX30 Ringneck and PX30 Mini-EVB.
Thanks to Jonas for hinting where to look at.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Quentin Schulz (10): rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level rockchip: Use common bss and stack addresses on PX30 rockchip: ringneck_px30: Use common bss and stack addresses rockchip: evb-px30: Use common bss and stack addresses rockchip: firefly-px30: Use common bss and stack addresses rockchip: odroid-go2: Use common bss and stack addresses rockchip: px30-core-*: Use common bss and stack addresses rockchip: px30: make UART pinmux accessible to TPL/SPL DTB rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB rockchip: evb-px30: make UART5 the debug UART
arch/arm/dts/px30-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 8 +++++++- configs/evb-px30_defconfig | 23 +++++------------------ configs/firefly-px30_defconfig | 19 +++---------------- configs/odroid-go2_defconfig | 19 +++---------------- configs/px30-core-ctouch2-of10-px30_defconfig | 19 +++---------------- configs/px30-core-ctouch2-px30_defconfig | 19 +++---------------- configs/px30-core-edimm2.2-px30_defconfig | 19 +++---------------- configs/ringneck-px30_defconfig | 19 +++---------------- 9 files changed, 46 insertions(+), 115 deletions(-)
base-commit: a7f0154c412859323396111dd0c09dbafbc153cb change-id: 20240521-px30-2024-07-rc-7136f6241d29
As I assume we want to fix the platforms for v2024.07, is this the level of config changes everyone is comfortable with on the platforms? Or should we just go with the minimum for release and the rest to -next?
I can tell you that Ringneck doesn't work anymore on v2024.07-rc, but the PX30 Mini EVB was still reaching U-Boot CLI without the changes. I don't know about the other boards.
So I could split this into two series, one for master, one for next.
I could suggest: patch 1 to 3 in master, the rest in next. Patch 1 is just moving things around. Patch 2 is doing nothing if nobody uses ROCKCHIP_COMMON_STACK_ADDR and SPL_SHARES_INIT_SP_ADDR (which is the case for px30 boards). Patch 3 is for fixing Ringneck, which I know is broken.
Heiko having access to the Odroid Go2, maybe he could test without my patches and see if it reaches the CLI to know if we should pull it in for master as well.
Does this make sense?
Thanks, Quentin
Am Mittwoch, 22. Mai 2024, 10:39:25 CEST schrieb Quentin Schulz:
Hi Tom,
On 5/21/24 8:04 PM, Tom Rini wrote:
On Tue, May 21, 2024 at 07:39:53PM +0200, Quentin Schulz wrote:
PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper pre-reloc. Something needed to be done. Jonas did migrate a few SoCs already to this common bss+stack addresses so it made sense to follow the same route for one additional SoC: PX30.
While at it, also fix a few issues related to UART on the PX30 Mini EVB I could test.
Boot (to U-Boot CLI) tested on PX30 Ringneck and PX30 Mini-EVB.
Thanks to Jonas for hinting where to look at.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Quentin Schulz (10): rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level rockchip: Use common bss and stack addresses on PX30 rockchip: ringneck_px30: Use common bss and stack addresses rockchip: evb-px30: Use common bss and stack addresses rockchip: firefly-px30: Use common bss and stack addresses rockchip: odroid-go2: Use common bss and stack addresses rockchip: px30-core-*: Use common bss and stack addresses rockchip: px30: make UART pinmux accessible to TPL/SPL DTB rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB rockchip: evb-px30: make UART5 the debug UART
arch/arm/dts/px30-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 8 +++++++- configs/evb-px30_defconfig | 23 +++++------------------ configs/firefly-px30_defconfig | 19 +++---------------- configs/odroid-go2_defconfig | 19 +++---------------- configs/px30-core-ctouch2-of10-px30_defconfig | 19 +++---------------- configs/px30-core-ctouch2-px30_defconfig | 19 +++---------------- configs/px30-core-edimm2.2-px30_defconfig | 19 +++---------------- configs/ringneck-px30_defconfig | 19 +++---------------- 9 files changed, 46 insertions(+), 115 deletions(-)
base-commit: a7f0154c412859323396111dd0c09dbafbc153cb change-id: 20240521-px30-2024-07-rc-7136f6241d29
As I assume we want to fix the platforms for v2024.07, is this the level of config changes everyone is comfortable with on the platforms? Or should we just go with the minimum for release and the rest to -next?
I can tell you that Ringneck doesn't work anymore on v2024.07-rc, but the PX30 Mini EVB was still reaching U-Boot CLI without the changes. I don't know about the other boards.
So I could split this into two series, one for master, one for next.
I could suggest: patch 1 to 3 in master, the rest in next. Patch 1 is just moving things around. Patch 2 is doing nothing if nobody uses ROCKCHIP_COMMON_STACK_ADDR and SPL_SHARES_INIT_SP_ADDR (which is the case for px30 boards). Patch 3 is for fixing Ringneck, which I know is broken.
Heiko having access to the Odroid Go2, maybe he could test without my patches and see if it reaches the CLI to know if we should pull it in for master as well.
I did that yesterday evening. The Odroid Go2 also reached u-boot CLI and also booted without these changes. So I guess it's small enough or whatever.
So at least the Go2 is fine on 2024.07-rc3 either way with or without this series.
Heiko
On Wed, May 22, 2024 at 02:14:47PM +0200, Heiko Stübner wrote:
Am Mittwoch, 22. Mai 2024, 10:39:25 CEST schrieb Quentin Schulz:
Hi Tom,
On 5/21/24 8:04 PM, Tom Rini wrote:
On Tue, May 21, 2024 at 07:39:53PM +0200, Quentin Schulz wrote:
PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper pre-reloc. Something needed to be done. Jonas did migrate a few SoCs already to this common bss+stack addresses so it made sense to follow the same route for one additional SoC: PX30.
While at it, also fix a few issues related to UART on the PX30 Mini EVB I could test.
Boot (to U-Boot CLI) tested on PX30 Ringneck and PX30 Mini-EVB.
Thanks to Jonas for hinting where to look at.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de
Quentin Schulz (10): rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level rockchip: Use common bss and stack addresses on PX30 rockchip: ringneck_px30: Use common bss and stack addresses rockchip: evb-px30: Use common bss and stack addresses rockchip: firefly-px30: Use common bss and stack addresses rockchip: odroid-go2: Use common bss and stack addresses rockchip: px30-core-*: Use common bss and stack addresses rockchip: px30: make UART pinmux accessible to TPL/SPL DTB rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB rockchip: evb-px30: make UART5 the debug UART
arch/arm/dts/px30-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 8 +++++++- configs/evb-px30_defconfig | 23 +++++------------------ configs/firefly-px30_defconfig | 19 +++---------------- configs/odroid-go2_defconfig | 19 +++---------------- configs/px30-core-ctouch2-of10-px30_defconfig | 19 +++---------------- configs/px30-core-ctouch2-px30_defconfig | 19 +++---------------- configs/px30-core-edimm2.2-px30_defconfig | 19 +++---------------- configs/ringneck-px30_defconfig | 19 +++---------------- 9 files changed, 46 insertions(+), 115 deletions(-)
base-commit: a7f0154c412859323396111dd0c09dbafbc153cb change-id: 20240521-px30-2024-07-rc-7136f6241d29
As I assume we want to fix the platforms for v2024.07, is this the level of config changes everyone is comfortable with on the platforms? Or should we just go with the minimum for release and the rest to -next?
I can tell you that Ringneck doesn't work anymore on v2024.07-rc, but the PX30 Mini EVB was still reaching U-Boot CLI without the changes. I don't know about the other boards.
So I could split this into two series, one for master, one for next.
I could suggest: patch 1 to 3 in master, the rest in next. Patch 1 is just moving things around. Patch 2 is doing nothing if nobody uses ROCKCHIP_COMMON_STACK_ADDR and SPL_SHARES_INIT_SP_ADDR (which is the case for px30 boards). Patch 3 is for fixing Ringneck, which I know is broken.
Heiko having access to the Odroid Go2, maybe he could test without my patches and see if it reaches the CLI to know if we should pull it in for master as well.
I did that yesterday evening. The Odroid Go2 also reached u-boot CLI and also booted without these changes. So I guess it's small enough or whatever.
So at least the Go2 is fine on 2024.07-rc3 either way with or without this series.
OK, thanks. I'll grab 1-3 for master shortly then.
Am Dienstag, 21. Mai 2024, 19:39:53 CEST schrieb Quentin Schulz:
PX30 Ringneck ran out of memory in the allocation pool of U-Boot proper pre-reloc. Something needed to be done. Jonas did migrate a few SoCs already to this common bss+stack addresses so it made sense to follow the same route for one additional SoC: PX30.
While at it, also fix a few issues related to UART on the PX30 Mini EVB I could test.
Boot (to U-Boot CLI) tested on PX30 Ringneck and PX30 Mini-EVB.
Thanks to Jonas for hinting where to look at.
u-boot 2024.07-rc3 with this series on an Odroid Go2
Tested-by: Heiko Stuebner heiko@sntech.de
Device boots and boots into a Debian image sucessfully.
Heiko
participants (5)
-
Heiko Stübner -
Kever Yang -
Quentin Schulz -
Quentin Schulz -
Tom Rini