Pepperl+Fuchs GmbH, Mannheim Geschaeftsfuehrer/Managing Directors: Dr.-Ing. Gunther Kegel (Vors./CEO), Werner Guthier, Mehmet Hatiboglu Vorsitzender des Aufsichtsrats/Chairman of the supervisory board: Claus Michael Registergericht/Register Court: AG Mannheim HRB 4713 On 2017-12-07 12:01, Siegmund, Jan wrote:

Hi all, does anybody have an idea for the following problem?

• FPGA is programmed using an overlay
• FPGA writes to SDRAM via the FPGA2SDRAM-bridge
• Linux hangs and the watchdog resets the board (the FPGA stays programmed)
• After the reset and boot, the FPGA is reprogrammed using the same overlay
• Now, the FPGA can write to the SDRAM without a problem

[..]

I haven't tried this method of programming the fpga yet (only programmed from U-Boot for now). But reading the SPL source code, it seems as the bridges are taken out of reset if the fpga is programmed when the SPL runs. That's a difference. And it would mean using your way of programming the fpga, the bridges might still be in reset.

Regards, Simon

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On Thu, Dec 7, 2017 at 5:00 AM, Siegmund, Jan jan.siegmund0@hm.edu wrote:

Hi SIegmund,

Hi all, does anybody have an idea for the following problem?

• FPGA is programmed using an overlay
• FPGA writes to SDRAM via the FPGA2SDRAM-bridge
• Linux hangs and the watchdog resets the board (the FPGA stays programmed)
• After the reset and boot, the FPGA is reprogrammed using the same overlay
• Now, the FPGA can write to the SDRAM without a problem

The environment:

*Board: DE0-NANO-SoC *U-Boot: 2017.11 *Kernel: 4.14.0-rc7 (review-v4.14-rc7-non-dt-support-v5.1 branch)

The overlay:

/dts-v1/; /plugin/;

/ { fragment@0 { target-path = "/soc/base_fpga_region"; #address-cells = <1>; #size-cells = <1>; __overlay__ { #address-cells = <1>; #size-cells = <1>; fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; firmware-name = "foo_base.rbf";

                    fpga-bridge@ffc25080 {
                            compatible = "altr,socfpga-fpga2sdram-bridge";
                            reg = <0xffc25080 0x4>;
                            bridge-enable = <1>;
                    };

It's been a while since I've touched that bridge, but here's what I can think of, hope it helps.

This overlay will add the bridge after programming. It looks like it should enable it since you have bridge-enable = <1>, so I'm not sure why that's not working.

Would it make sense to add the f2s bridge before doing the fpga programming? You could add the f2s bridge in the base device tree and add it to your fpga-bridges list so that that bridge is enabled after the fpga is programmed.

Alan

                    foo@ff200000 {
                            compatible= "altr,bar";
                            interrupt-parent = <&intc>;
                            interrupts = <0 40 4>;
                    };

            };
    };

};

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