[U-Boot] [PATCH v2] armv8/ls2080ardb: Update DDR timing to support more UDIMMs
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM.
Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H
Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com --- v2: verified lower rate, for 1333MT/s no changes are necessary.
board/freescale/ls2080ardb/ddr.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index bda9d4a..b3c6306 100644 --- a/board/freescale/ls2080ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h @@ -29,9 +29,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,}, - {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,}, - {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,}, + {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,}, + {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,}, + {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,}, {} };
On 04/06/2016 11:50 PM, Shengzhou Liu wrote:
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM.
Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB.
- Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
- Apacer UDIMM: 78.C1GM4.AF10B
- Transcend UDIMM: TS1GLH72V1H
Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com
v2: verified lower rate, for 1333MT/s no changes are necessary.
board/freescale/ls2080ardb/ddr.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index bda9d4a..b3c6306 100644 --- a/board/freescale/ls2080ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h @@ -29,9 +29,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
- {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
- {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
- {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
- {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
- {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,}, {}
};
Shengzhou,
I see a problem with this patch on one LS2085ARDB board, at 1866MT/s with MT18ASF1G72AZ-2G1A1. Please try it yourself on ls2085rdb-3 (ATX boardfarm). My order of patches are
http://patchwork.ozlabs.org/patch/607290/ http://patchwork.ozlabs.org/patch/598135/ http://patchwork.ozlabs.org/patch/598136/ http://patchwork.ozlabs.org/patch/607274/
My test code base is master branch bbca7108db79076d3a9a9c112792d7c4608a665c.
York
On 05/05/2016 12:29 PM, York Sun wrote:
On 04/06/2016 11:50 PM, Shengzhou Liu wrote:
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM.
Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB.
- Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
- Apacer UDIMM: 78.C1GM4.AF10B
- Transcend UDIMM: TS1GLH72V1H
Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com
v2: verified lower rate, for 1333MT/s no changes are necessary.
board/freescale/ls2080ardb/ddr.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index bda9d4a..b3c6306 100644 --- a/board/freescale/ls2080ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h @@ -29,9 +29,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
- {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
- {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
- {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
- {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
- {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,}, {}
};
Shengzhou,
I see a problem with this patch on one LS2085ARDB board, at 1866MT/s with MT18ASF1G72AZ-2G1A1. Please try it yourself on ls2085rdb-3 (ATX boardfarm). My order of patches are
http://patchwork.ozlabs.org/patch/607290/ http://patchwork.ozlabs.org/patch/598135/ http://patchwork.ozlabs.org/patch/598136/ http://patchwork.ozlabs.org/patch/607274/
My test code base is master branch bbca7108db79076d3a9a9c112792d7c4608a665c.
Shengzhou,
I rebased the code and repeated the tests on the same board but seeing no issue now.
York
On 05/17/2016 09:25 AM, York Sun wrote:
On 05/05/2016 12:29 PM, York Sun wrote:
On 04/06/2016 11:50 PM, Shengzhou Liu wrote:
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM.
Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB.
- Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
- Apacer UDIMM: 78.C1GM4.AF10B
- Transcend UDIMM: TS1GLH72V1H
Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com
v2: verified lower rate, for 1333MT/s no changes are necessary.
board/freescale/ls2080ardb/ddr.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index bda9d4a..b3c6306 100644 --- a/board/freescale/ls2080ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h @@ -29,9 +29,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
- {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
- {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
- {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
- {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
- {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,}, {}
};
Shengzhou,
I see a problem with this patch on one LS2085ARDB board, at 1866MT/s with MT18ASF1G72AZ-2G1A1. Please try it yourself on ls2085rdb-3 (ATX boardfarm). My order of patches are
http://patchwork.ozlabs.org/patch/607290/ http://patchwork.ozlabs.org/patch/598135/ http://patchwork.ozlabs.org/patch/598136/ http://patchwork.ozlabs.org/patch/607274/
My test code base is master branch bbca7108db79076d3a9a9c112792d7c4608a665c.
Shengzhou,
I rebased the code and repeated the tests on the same board but seeing no issue now.
Shengzhou,
I am still seeing it unstable on ls2085rdb-5 (ATX boardfarm) at 1866MT/s. It can boot if I change clk_adjust to 5. Please work with hardware team to confirm.
York
-----Original Message----- From: York Sun [mailto:york.sun@nxp.com] Sent: Thursday, May 19, 2016 4:28 AM To: Shengzhou Liu shengzhou.liu@nxp.com; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH v2] armv8/ls2080ardb: Update DDR timing to support more UDIMMs
Shengzhou,
I am still seeing it unstable on ls2085rdb-5 (ATX boardfarm) at 1866MT/s. It can boot if I change clk_adjust to 5. Please work with hardware team to confirm.
York
York
On LS1046RDB, the clk_adj is 9, an odd instead of even data, so we have to update it, and there will be more new boards in future.
Shengzhou
On 04/06/2016 11:50 PM, Shengzhou Liu wrote:
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM.
Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB.
- Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
- Apacer UDIMM: 78.C1GM4.AF10B
- Transcend UDIMM: TS1GLH72V1H
Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com
v2: verified lower rate, for 1333MT/s no changes are necessary.
board/freescale/ls2080ardb/ddr.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Applied to u-boot-fsl-qoriq master, awaiting upstream.
Thanks.
York
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Shengzhou Liu
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York Sun