[U-Boot] [PATCH 1/5] sh: sh7757lcr: Fix copy-paste error in README
Update the README to use the correct defconfig.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Vladimir Zapolskiy vz@mleia.com Cc: Yoshihiro Shimoda shimoda.yoshihiro@renesas.com --- board/renesas/sh7757lcr/README.sh7757lcr | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/renesas/sh7757lcr/README.sh7757lcr b/board/renesas/sh7757lcr/README.sh7757lcr index 3e9c1c1a1e..9453839d2c 100644 --- a/board/renesas/sh7757lcr/README.sh7757lcr +++ b/board/renesas/sh7757lcr/README.sh7757lcr @@ -20,7 +20,7 @@ configuration for This board:
You can select the configuration as follows:
- - make sh7785lcr_config + - make sh7757lcr_config
This board specific command:
Last change to this board was done in 2016, it uses non-DM USB with no prospects of ever being converted to DM USB, drop it.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Vladimir Zapolskiy vz@mleia.com Cc: Yoshihiro Shimoda shimoda.yoshihiro@renesas.com --- arch/sh/Kconfig | 5 - board/renesas/ecovec/Kconfig | 12 -- board/renesas/ecovec/MAINTAINERS | 7 - board/renesas/ecovec/Makefile | 8 -- board/renesas/ecovec/ecovec.c | 98 -------------- board/renesas/ecovec/lowlevel_init.S | 196 --------------------------- configs/ecovec_defconfig | 40 ------ include/configs/ecovec.h | 133 ------------------ scripts/config_whitelist.txt | 1 - 9 files changed, 500 deletions(-) delete mode 100644 board/renesas/ecovec/Kconfig delete mode 100644 board/renesas/ecovec/MAINTAINERS delete mode 100644 board/renesas/ecovec/Makefile delete mode 100644 board/renesas/ecovec/ecovec.c delete mode 100644 board/renesas/ecovec/lowlevel_init.S delete mode 100644 configs/ecovec_defconfig delete mode 100644 include/configs/ecovec.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index d20761e66c..ff7932bacb 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -75,10 +75,6 @@ config TARGET_AP325RXA bool "Renesas AP-325RXA" select CPU_SH4
-config TARGET_ECOVEC - bool "EcoVec" - select CPU_SH4A - config TARGET_MIGOR bool "Migo-R" select CPU_SH4 @@ -135,7 +131,6 @@ source "board/ms7722se/Kconfig" source "board/ms7750se/Kconfig" source "board/renesas/MigoR/Kconfig" source "board/renesas/ap325rxa/Kconfig" -source "board/renesas/ecovec/Kconfig" source "board/renesas/r0p7734/Kconfig" source "board/renesas/r2dplus/Kconfig" source "board/renesas/r7780mp/Kconfig" diff --git a/board/renesas/ecovec/Kconfig b/board/renesas/ecovec/Kconfig deleted file mode 100644 index 08cde83356..0000000000 --- a/board/renesas/ecovec/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ECOVEC - -config SYS_BOARD - default "ecovec" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "ecovec" - -endif diff --git a/board/renesas/ecovec/MAINTAINERS b/board/renesas/ecovec/MAINTAINERS deleted file mode 100644 index 439b528de9..0000000000 --- a/board/renesas/ecovec/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -ECOVEC BOARD -M: Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com -M: Nobuhiro Iwamatsu iwamatsu@nigauri.org -S: Maintained -F: board/renesas/ecovec/ -F: include/configs/ecovec.h -F: configs/ecovec_defconfig diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile deleted file mode 100644 index aae3f70813..0000000000 --- a/board/renesas/ecovec/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Nobuhiro Iwamatsu iwamatsu@nigauri.org -# Copyright (C) 2011 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com -# - -obj-y := ecovec.o -extra-y += lowlevel_init.o diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c deleted file mode 100644 index 6b6c5dc559..0000000000 --- a/board/renesas/ecovec/ecovec.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009, 2011 Renesas Solutions Corp. - * Copyright (C) 2009 Kuninori Morimoto morimoto.kuninori@renesas.com - * Copyright (C) 2011 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - */ - -#include <common.h> -#include <command.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <i2c.h> -#include <netdev.h> - -/* USB power management register */ -#define UPONCR0 0xA40501D4 - -int checkboard(void) -{ - puts("BOARD: ecovec\n"); - return 0; -} - -static void debug_led(u8 led) -{ - /* PDGR[0-4] is debug LED */ - outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR); -} - -int board_late_init(void) -{ - u8 mac[6]; - char env_mac[18]; - - udelay(1000); - - /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/ - outw(inw(PLCR) & ~0xFFF0, PLCR); - outw(inw(PNCR) & ~0x000F, PNCR); - outw(inw(PXCR) & ~0x0FC0, PXCR); - outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB); - outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC); - outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE); - - debug_led(1 << 3); - - outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); - - i2c_set_bus_num(1); /* Use I2C 1 */ - - /* Read MAC address */ - i2c_read(0x50, 0x10, 0, mac, 6); - - /* Set MAC address */ - sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - env_set("ethaddr", env_mac); - - debug_led(0x0F); - - return 0; -} - -int board_init(void) -{ - - /* LED (PTG) */ - outw((inw(PGCR) & ~0xFF) | 0x55, PGCR); - outw((inw(HIZCRA) & ~0x02), HIZCRA); - - debug_led(1 << 0); - - /* SCIF0 (PTF, PTM) */ - outw(inw(PFCR) & ~0x30, PFCR); - outw(inw(PMCR) & ~0x0C, PMCR); - outw((inw(PSELA) & ~0x40) | 0x40, PSELA); - - debug_led(1 << 1); - - /* RMII (PTA) */ - outw((inw(PACR) & ~0x0C) | 0x04, PACR); - outb((inb(PADR) & ~0x02) | 0x02, PADR); - - debug_led(1 << 2); - - /* USB host */ - outw((inw(PBCR) & ~0x300) | 0x100, PBCR); - outb((inb(PBDR) & ~0x10) | 0x10, PBDR); - outl(inl(MSTPCR2) & ~0x100000, MSTPCR2); - outw(0x0600, UPONCR0); - - debug_led(1 << 3); - - /* debug switch */ - outw((inw(PVCR) & ~0x03) | 0x02 , PVCR); - - return 0; -} diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S deleted file mode 100644 index adad932316..0000000000 --- a/board/renesas/ecovec/lowlevel_init.S +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Nobuhiro Iwamatsu nobuhiro.Iwamatsu.yj@renesas.com - * - * board/renesas/ecovec/lowlevel_init.S - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> -#include <configs/ecovec.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */ - mov.l PVDR_A, r1 - mov.l PVDR_D, r2 - mov.b @r1, r0 - tst r0, r2 - bt 1f - mov.l JUMP_A, r1 - jmp @r1 - nop - -1: - /* Disable watchdog */ - write16 RWTCSR_A, RWTCSR_D - - /* MMU Disable */ - write32 MMUCR_A, MMUCR_D - - /* Setup clocks */ - write32 PLLCR_A, PLLCR_D - write32 FRQCRA_A, FRQCRA_D - write32 FRQCRB_A, FRQCRB_D - - wait_timer TIMER_D - - write32 MMSELR_A, MMSELR_D - - /* Srtup BSC */ - write32 CMNCR_A, CMNCR_D - write32 CS0BCR_A, CS0BCR_D - write32 CS0WCR_A, CS0WCR_D - - wait_timer TIMER_D - - /* Setup SDRAM */ - write32 DBPDCNT0_A, DBPDCNT0_D0 - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBKIND_A, DBKIND_D - write32 DBCKECNT_A, DBCKECNT_D - - wait_timer TIMER_D - - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBMRCNT_A, DBMRCNT_D0 - write32 DBMRCNT_A, DBMRCNT_D1 - write32 DBMRCNT_A, DBMRCNT_D2 - write32 DBMRCNT_A, DBMRCNT_D3 - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBMRCNT_A, DBMRCNT_D4 - write32 DBMRCNT_A, DBMRCNT_D5 - write32 DBMRCNT_A, DBMRCNT_D6 - - wait_timer TIMER_D - - write32 DBEN_A, DBEN_D - write32 DBRFPDN1_A, DBRFPDN1_D - write32 DBRFPDN2_A, DBRFPDN2_D - write32 DBCMDCNT_A, DBCMDCNT_D0 - - - /* Dummy read */ - mov.l DUMMY_A ,r1 - synco - mov.l @r1, r0 - synco - - mov.l SDRAM_A ,r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBPDCNT0_A, DBPDCNT0_D1 - write32 DBRFPDN0_A, DBRFPDN0_D - - wait_timer TIMER_D - - write32 CCR_A, CCR_D - - stc sr, r0 - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - - .align 2 - -PVDR_A: .long PVDR -PVDR_D: .long 0x00000001 -JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR -TIMER_D: .long 64 -RWTCSR_A: .long RWTCSR -RWTCSR_D: .long 0x0000A507 -MMUCR_A: .long MMUCR -MMUCR_D: .long 0x00000004 -PLLCR_A: .long PLLCR -PLLCR_D: .long 0x00004000 -FRQCRA_A: .long FRQCRA -FRQCRA_D: .long 0x8E003508 -FRQCRB_A: .long FRQCRB -FRQCRB_D: .long 0x0 -MMSELR_A: .long MMSELR -MMSELR_D: .long 0xA5A50000 -CMNCR_A: .long CMNCR -CMNCR_D: .long 0x00000013 -CS0BCR_A: .long CS0BCR -CS0BCR_D: .long 0x11110400 -CS0WCR_A: .long CS0WCR -CS0WCR_D: .long 0x00000440 -DBPDCNT0_A: .long DBPDCNT0 -DBPDCNT0_D0: .long 0x00000181 -DBPDCNT0_D1: .long 0x00000080 -DBCONF_A: .long DBCONF -DBCONF_D: .long 0x015B0002 -DBTR0_A: .long DBTR0 -DBTR0_D: .long 0x03061502 -DBTR1_A: .long DBTR1 -DBTR1_D: .long 0x02020102 -DBTR2_A: .long DBTR2 -DBTR2_D: .long 0x01090305 -DBTR3_A: .long DBTR3 -DBTR3_D: .long 0x00000002 -DBKIND_A: .long DBKIND -DBKIND_D: .long 0x00000005 -DBCKECNT_A: .long DBCKECNT -DBCKECNT_D: .long 0x00000001 -DBCMDCNT_A: .long DBCMDCNT -DBCMDCNT_D0:.long 0x2 -DBCMDCNT_D1:.long 0x4 -DBMRCNT_A: .long DBMRCNT -DBMRCNT_D0: .long 0x00020000 -DBMRCNT_D1: .long 0x00030000 -DBMRCNT_D2: .long 0x00010040 -DBMRCNT_D3: .long 0x00000532 -DBMRCNT_D4: .long 0x00000432 -DBMRCNT_D5: .long 0x000103C0 -DBMRCNT_D6: .long 0x00010040 -DBEN_A: .long DBEN -DBEN_D: .long 0x01 -DBRFPDN0_A: .long DBRFPDN0 -DBRFPDN1_A: .long DBRFPDN1 -DBRFPDN2_A: .long DBRFPDN2 -DBRFPDN0_D: .long 0x00010000 -DBRFPDN1_D: .long 0x00000613 -DBRFPDN2_D: .long 0x238C003A -SDRAM_A: .long 0xa8000000 -DUMMY_A: .long 0x0c400000 -CCR_A: .long CCR -CCR_D: .long 0x0000090B -SR_MASK_D: .long 0xEFFFFF0F diff --git a/configs/ecovec_defconfig b/configs/ecovec_defconfig deleted file mode 100644 index e6d19446eb..0000000000 --- a/configs/ecovec_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x8FFC0000 -CONFIG_TARGET_ECOVEC=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200" -CONFIG_VERSION_VARIABLE=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SH_ETHER=y -CONFIG_SCIF_CONSOLE=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h deleted file mode 100644 index be03bf1627..0000000000 --- a/include/configs/ecovec.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas Solutions ECOVEC board - * - * Copyright (C) 2009 - 2011 Renesas Solutions Corp. - * Copyright (C) 2009 Kuninori Morimoto morimoto.kuninori@renesas.com - * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - */ - -#ifndef __ECOVEC_H -#define __ECOVEC_H - -/* - * Address Interface BusWidth - *----------------------------------------- - * 0x0000_0000 U-Boot 16bit - * 0x0004_0000 Linux romImage 16bit - * 0x0014_0000 MTD for Linux 16bit - * 0x0400_0000 Internal I/O 16/32bit - * 0x0800_0000 DRAM 32bit - * 0x1800_0000 MFI 16bit - */ - -#define CONFIG_CPU_SH7724 1 - -#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000 - -#define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2 -#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000 -#define CONFIG_SYS_I2C_SH_SPEED0 100000 -#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000 -#define CONFIG_SYS_I2C_SH_SPEED1 100000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 41666666 - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT (0) -#define CONFIG_SH_ETHER_PHY_ADDR (0x1f) -#define CONFIG_PHY_SMSC 1 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - -/* USB / R8A66597 */ -#define CONFIG_USB_R8A66597_HCD -#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000 -#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ -#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ -#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ -#define CONFIG_SUPERH_ON_CHIP_R8A66597 - -/* undef to save memory */ -/* Monitor Command Prompt */ -/* Buffer size for Console output */ -#define CONFIG_SYS_PBSIZE 256 -/* List of legal baudrate settings for this board */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_SCIF 1 -#define CONFIG_CONS_SCIF0 1 - -/* Suppress display of console information at boot */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE (0x88000000) -#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024) -/* Enable alternate, more extensive, memory test */ -/* Scratch address used by the alternate memory test */ -#undef CONFIG_SYS_MEMTEST_SCRATCH - -/* Enable temporary baudrate change while serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -/* FLASH */ -#undef CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* if you use all NOR Flash , you change dip-switch. Please see Manual. */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* Timeout for Flash erase operations (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -/* Timeout for Flash write operations (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -/* Timeout for Flash set sector lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -/* Timeout for Flash clear lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) - -/* - * Use hardware flash sectors protection instead - * of U-Boot software protection - */ -#undef CONFIG_SYS_DIRECT_FLASH_TFTP - -/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) -/* Monitor size */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* ENV setting */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 41666666 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#endif /* __ECOVEC_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 48ef03149e..f64ef85159 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -434,7 +434,6 @@ CONFIG_ECC_MODE_SHIFT CONFIG_ECC_SRAM_ADDR_MASK CONFIG_ECC_SRAM_ADDR_SHIFT CONFIG_ECC_SRAM_REQ_BIT -CONFIG_ECOVEC_ROMIMAGE_ADDR CONFIG_EDB9301 CONFIG_EDB9302 CONFIG_EDB9302A
There are no more boards using this CPU and there is no prospect of any boards showing up soon, remove it.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Vladimir Zapolskiy vz@mleia.com Cc: Yoshihiro Shimoda shimoda.yoshihiro@renesas.com --- arch/sh/include/asm/cpu_sh4.h | 2 - arch/sh/include/asm/cpu_sh7724.h | 209 ------------------------------- drivers/net/sh_eth.c | 2 +- drivers/net/sh_eth.h | 3 - drivers/serial/serial_sh.h | 15 +-- scripts/config_whitelist.txt | 1 - 6 files changed, 4 insertions(+), 228 deletions(-) delete mode 100644 arch/sh/include/asm/cpu_sh7724.h
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index b558d6935c..977b648dd4 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -30,8 +30,6 @@ # include <asm/cpu_sh7722.h> #elif defined (CONFIG_CPU_SH7723) # include <asm/cpu_sh7723.h> -#elif defined (CONFIG_CPU_SH7724) -# include <asm/cpu_sh7724.h> #elif defined (CONFIG_CPU_SH7734) # include <asm/cpu_sh7734.h> #elif defined (CONFIG_CPU_SH7752) diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h deleted file mode 100644 index 7b217959ed..0000000000 --- a/arch/sh/include/asm/cpu_sh7724.h +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008, 2011 Renesas Solutions Corp. - * - * SH7724 Internal I/O register - */ - -#ifndef _ASM_CPU_SH7724_H_ -#define _ASM_CPU_SH7724_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000090d - -/* EXP */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* MMU */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 - -/* CACHE */ -#define CCR 0xFF00001C -#define RAMCR 0xFF000074 - -/* INTC */ - -/* BSC */ -#define MMSELR 0xFF800020 -#define CMNCR 0xFEC10000 -#define CS0BCR 0xFEC10004 -#define CS2BCR 0xFEC10008 -#define CS4BCR 0xFEC10010 -#define CS5ABCR 0xFEC10014 -#define CS5BBCR 0xFEC10018 -#define CS6ABCR 0xFEC1001C -#define CS6BBCR 0xFEC10020 -#define CS0WCR 0xFEC10024 -#define CS2WCR 0xFEC10028 -#define CS4WCR 0xFEC10030 -#define CS5AWCR 0xFEC10034 -#define CS5BWCR 0xFEC10038 -#define CS6AWCR 0xFEC1003C -#define CS6BWCR 0xFEC10040 -#define RBWTCNT 0xFEC10054 - -/* SBSC */ -#define SBSC_SDCR 0xFE400008 -#define SBSC_SDWCR 0xFE40000C -#define SBSC_SDPCR 0xFE400010 -#define SBSC_RTCSR 0xFE400014 -#define SBSC_RTCNT 0xFE400018 -#define SBSC_RTCOR 0xFE40001C -#define SBSC_RFCR 0xFE400020 - -/* DSBC */ -#define DBKIND 0xFD000008 -#define DBSTATE 0xFD00000C -#define DBEN 0xFD000010 -#define DBCMDCNT 0xFD000014 -#define DBCKECNT 0xFD000018 -#define DBCONF 0xFD000020 -#define DBTR0 0xFD000030 -#define DBTR1 0xFD000034 -#define DBTR2 0xFD000038 -#define DBTR3 0xFD00003C -#define DBRFPDN0 0xFD000040 -#define DBRFPDN1 0xFD000044 -#define DBRFPDN2 0xFD000048 -#define DBRFSTS 0xFD00004C -#define DBMRCNT 0xFD000060 -#define DBPDCNT0 0xFD000108 - -/* DMAC */ - -/* CPG */ -#define FRQCRA 0xA4150000 -#define FRQCRB 0xA4150004 -#define FRQCR FRQCRA -#define VCLKCR 0xA4150004 -#define SCLKACR 0xA4150008 -#define SCLKBCR 0xA415000C -#define IRDACLKCR 0xA4150018 -#define PLLCR 0xA4150024 -#define DLLFRQ 0xA4150050 - -/* LOW POWER MODE */ -#define STBCR 0xA4150020 -#define MSTPCR0 0xA4150030 -#define MSTPCR1 0xA4150034 -#define MSTPCR2 0xA4150038 - -/* RWDT */ -#define RWTCNT 0xA4520000 -#define RWTCSR 0xA4520004 -#define WTCNT RWTCNT - -/* TMU */ -#define TMU_BASE 0xFFD80000 - -/* TPU */ - -/* CMT */ -#define CMSTR 0xA44A0000 -#define CMCSR 0xA44A0060 -#define CMCNT 0xA44A0064 -#define CMCOR 0xA44A0068 - -/* MSIOF */ - -/* SCIF */ -#define SCIF0_BASE 0xFFE00000 -#define SCIF1_BASE 0xFFE10000 -#define SCIF2_BASE 0xFFE20000 -#define SCIF3_BASE 0xa4e30000 -#define SCIF4_BASE 0xa4e40000 -#define SCIF5_BASE 0xa4e50000 - -/* RTC */ -/* IrDA */ -/* KEYSC */ -/* USB */ -/* IIC */ -/* FLCTL */ -/* VPU */ -/* VIO(CEU) */ -/* VIO(VEU) */ -/* VIO(BEU) */ -/* 2DG */ -/* LCDC */ -/* VOU */ -/* TSIF */ -/* SIU */ -/* ATAPI */ - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PDCR 0xA4050106 -#define PECR 0xA4050108 -#define PFCR 0xA405010A -#define PGCR 0xA405010C -#define PHCR 0xA405010E -#define PJCR 0xA4050110 -#define PKCR 0xA4050112 -#define PLCR 0xA4050114 -#define PMCR 0xA4050116 -#define PNCR 0xA4050118 -#define PQCR 0xA405011A -#define PRCR 0xA405011C -#define PSCR 0xA405011E -#define PTCR 0xA4050140 -#define PUCR 0xA4050142 -#define PVCR 0xA4050144 -#define PWCR 0xA4050146 -#define PXCR 0xA4050148 -#define PYCR 0xA405014A -#define PZCR 0xA405014C -#define PSELA 0xA405014E -#define PSELB 0xA4050150 -#define PSELC 0xA4050152 -#define PSELD 0xA4050154 -#define PSELE 0xA4050156 -#define HIZCRA 0xA4050158 -#define HIZCRB 0xA405015A -#define HIZCRC 0xA405015C -#define HIZCRD 0xA405015E -#define MSELCRA 0xA4050180 -#define MSELCRB 0xA4050182 -#define PULCR 0xA4050184 -#define DRVCRA 0xA405018A -#define DRVCRB 0xA405018C - -/* I/O Port */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 -#define PDDR 0xA4050126 -#define PEDR 0xA4050128 -#define PFDR 0xA405012A -#define PGDR 0xA405012C -#define PHDR 0xA405012E -#define PJDR 0xA4050130 -#define PKDR 0xA4050132 -#define PLDR 0xA4050134 -#define PMDR 0xA4050136 -#define PNDR 0xA4050138 -#define PQDR 0xA405013A -#define PRDR 0xA405013C -#define PSDR 0xA405013E -#define PTDR 0xA4050160 -#define PUDR 0xA4050162 -#define PVDR 0xA4050164 -#define PWDR 0xA4050166 -#define PXDR 0xA4050168 -#define PYDR 0xA405016A -#define PZDR 0xA405016C - -/* UBC */ -/* H-UDI */ - -#endif /* _ASM_CPU_SH7724_H_ */ diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 4646f2ba4e..a2577e1e8f 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -425,7 +425,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) sh_eth_write(port_info, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) sh_eth_write(port_info, 1, RTRATE); -#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2) +#elif defined(CONFIG_RCAR_GEN2) val = ECMR_RTM; #endif } else if (phy->speed == 10) { diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index cd8190062a..d8b4bda3ef 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -295,9 +295,6 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xfef00000 #endif -#elif defined(CONFIG_CPU_SH7724) -#define SH_ETH_TYPE_ETHER -#define BASE_IO_ADDR 0xA4600000 #elif defined(CONFIG_R8A7740) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xE9A00000 diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index deb4b647c6..c6f4778628 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -107,11 +107,6 @@ struct uart_port { # define SCSPTR5 0xa4050128 # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -#elif defined(CONFIG_CPU_SH7724) -# define SCIF_ORER 0x0001 /* overrun error bit */ -# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ - 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ - 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) #elif defined(CONFIG_CPU_SH7734) # define SCSPTR0 0xFFE40020 # define SCSPTR1 0xFFE41020 @@ -256,8 +251,6 @@ struct uart_port { defined(CONFIG_CPU_SH7786) || \ defined(CONFIG_CPU_SHX3) #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ -#elif defined(CONFIG_CPU_SH7724) -#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) #else #define SCI_CTRL_FLAGS_REIE 0 #endif @@ -494,7 +487,7 @@ static inline void sci_##name##_out(struct uart_port *port,\ #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ sh4_scif_offset, sh4_scif_size) \ CPU_SCIF_FNS(name) -#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) +#elif defined(CONFIG_CPU_SH7723) #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ sh4_scif_offset, sh4_scif_size) \ CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ @@ -549,8 +542,7 @@ SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) SCIF_FNS(SCLSR, 0x00, 0) SCIF_FNS(DL, 0x00, 0) /* dummy */ -#elif defined(CONFIG_CPU_SH7723) ||\ - defined(CONFIG_CPU_SH7724) +#elif defined(CONFIG_CPU_SH7723) SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) @@ -747,8 +739,7 @@ static inline int sci_rxd_in(struct uart_port *port) defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) -#elif defined(CONFIG_CPU_SH7723) ||\ - defined(CONFIG_CPU_SH7724) +#elif defined(CONFIG_CPU_SH7723) static inline int scbrr_calc(struct uart_port *port, int bps, int clk) { if (port->type == PORT_SCIF) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f64ef85159..efa55a1890 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -277,7 +277,6 @@ CONFIG_CPU_SH7706 CONFIG_CPU_SH7720 CONFIG_CPU_SH7722 CONFIG_CPU_SH7723 -CONFIG_CPU_SH7724 CONFIG_CPU_SH7734 CONFIG_CPU_SH7750 CONFIG_CPU_SH7751
Last change to this board was done in 2016, it uses non-DM USB with no prospects of ever being converted to DM USB, drop it.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Vladimir Zapolskiy vz@mleia.com Cc: Yoshihiro Shimoda shimoda.yoshihiro@renesas.com --- arch/sh/Kconfig | 5 - board/renesas/sh7785lcr/Kconfig | 12 - board/renesas/sh7785lcr/MAINTAINERS | 7 - board/renesas/sh7785lcr/Makefile | 7 - board/renesas/sh7785lcr/README.sh7785lcr | 123 -------- board/renesas/sh7785lcr/lowlevel_init.S | 361 ----------------------- board/renesas/sh7785lcr/rtl8169.h | 43 --- board/renesas/sh7785lcr/rtl8169_mac.c | 330 --------------------- board/renesas/sh7785lcr/selfcheck.c | 150 ---------- board/renesas/sh7785lcr/sh7785lcr.c | 63 ---- configs/sh7785lcr_32bit_defconfig | 40 --- configs/sh7785lcr_defconfig | 39 --- include/configs/sh7785lcr.h | 128 -------- 13 files changed, 1308 deletions(-) delete mode 100644 board/renesas/sh7785lcr/Kconfig delete mode 100644 board/renesas/sh7785lcr/MAINTAINERS delete mode 100644 board/renesas/sh7785lcr/Makefile delete mode 100644 board/renesas/sh7785lcr/README.sh7785lcr delete mode 100644 board/renesas/sh7785lcr/lowlevel_init.S delete mode 100644 board/renesas/sh7785lcr/rtl8169.h delete mode 100644 board/renesas/sh7785lcr/rtl8169_mac.c delete mode 100644 board/renesas/sh7785lcr/selfcheck.c delete mode 100644 board/renesas/sh7785lcr/sh7785lcr.c delete mode 100644 configs/sh7785lcr_32bit_defconfig delete mode 100644 configs/sh7785lcr_defconfig delete mode 100644 include/configs/sh7785lcr.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index ff7932bacb..a5772da87a 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -107,10 +107,6 @@ config TARGET_SH7763RDP bool "SH7763RDP" select CPU_SH4
-config TARGET_SH7785LCR - bool "SH7785LCR" - select CPU_SH4A - endchoice
config SYS_ARCH @@ -141,7 +137,6 @@ source "board/renesas/sh7752evb/Kconfig" source "board/renesas/sh7753evb/Kconfig" source "board/renesas/sh7757lcr/Kconfig" source "board/renesas/sh7763rdp/Kconfig" -source "board/renesas/sh7785lcr/Kconfig" source "board/shmin/Kconfig"
endmenu diff --git a/board/renesas/sh7785lcr/Kconfig b/board/renesas/sh7785lcr/Kconfig deleted file mode 100644 index e204c76ef5..0000000000 --- a/board/renesas/sh7785lcr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7785LCR - -config SYS_BOARD - default "sh7785lcr" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7785lcr" - -endif diff --git a/board/renesas/sh7785lcr/MAINTAINERS b/board/renesas/sh7785lcr/MAINTAINERS deleted file mode 100644 index 17578e036a..0000000000 --- a/board/renesas/sh7785lcr/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SH7785LCR BOARD -#M: - -S: Maintained -F: board/renesas/sh7785lcr/ -F: include/configs/sh7785lcr.h -F: configs/sh7785lcr_defconfig -F: configs/sh7785lcr_32bit_defconfig diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile deleted file mode 100644 index ba00657d7e..0000000000 --- a/board/renesas/sh7785lcr/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com -# - -obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7785lcr/README.sh7785lcr b/board/renesas/sh7785lcr/README.sh7785lcr deleted file mode 100644 index 56455fc162..0000000000 --- a/board/renesas/sh7785lcr/README.sh7785lcr +++ /dev/null @@ -1,123 +0,0 @@ -======================================== -Renesas Technology R0P7785LC0011RL board -======================================== - -This board specification: -========================= - -The R0P7785LC0011RL(board config name:sh7785lcr) has the following device: - - - SH7785 (SH-4A) - - DDR2-SDRAM 512MB - - NOR Flash 64MB - - 2D Graphic controller - - SATA controller - - Ethernet controller - - USB host/peripheral controller - - SD controller - - I2C controller - - RTC - -This board has 2 physical memory maps. It can be changed with DIP switch(S2-5). - - phys address | S2-5 = OFF | S2-5 = ON - -------------------------------+---------------+--------------- - 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash - 0x04000000 - 0x05ffffff(CS1) | PLD | PLD - 0x06000000 - 0x07ffffff(CS1) | reserved | I2C - 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM - 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM - 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 - 0x14000000 - 0x17ffffff(CS5) | I2C | USB - 0x18000000 - 0x1bffffff(CS6) | reserved | SD - 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) - - -configuration for This board: -============================= - -You can choose configuration as follows: - - - make sh7785lcr_config - - make sh7785lcr_32bit_config - -When you use "make sh7785lcr_config", there is build U-Boot for 29-bit -address mode. This mode can use 128MB DDR-SDRAM. - -When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit -extended address mode. This mode can use 384MB DDR-SDRAM. And if you run -"pmb" command, this mode can use 512MB DDR-SDRAM. - - * 32-bit extended address mode PMB mapping * - a) on start-up - virt | phys | size | device - -------------+---------------+---------------+--------------- - 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable) - 0xa0000000 | 0x00000000 | 64MB | NOR Flash - 0xa4000000 | 0x04000000 | 16MB | PLD - 0xa6000000 | 0x08000000 | 16MB | USB - 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable) - - b) after "pmb" command - virt | phys | size | device - -------------+---------------+---------------+--------------- - 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable) - 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable) - - -This board specific command: -============================ - -This board has the following its specific command: - - - hwtest - - printmac - - setmac - - pmb (sh7785lcr_32bit_config only) - - -1. hwtest - -This is self-check command. This command has the following options: - - - all : test all hardware - - pld : output PLD version - - led : turn on LEDs - - dipsw : test DIP switch - - sm107 : output SM107 version - - net : check RTL8110 ID - - sata : check SiI3512 ID - - net : output PCI slot device ID - -i.e) -=> hwtest led -turn on LEDs 3, 5, 7, 9 -turn on LEDs 4, 6, 8, 10 - -=> hwtest net -Ethernet OK - - -2. printmac - -This command outputs MAC address of this board. - -i.e) -=> printmac -MAC = 00:00:87:**:**:** - - -3. setmac - -This command writes MAC address of this board. - -i.e) -=> setmac 00:00:87:**:**:** - - -4. pmb - -This command change PMB for DDR-SDRAM all mapping. However you cannot use -NOR Flash and USB Host on U-Boot when you run this command. -i.e) -=> pmb diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S deleted file mode 100644 index 658ebbaaeb..0000000000 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ /dev/null @@ -1,361 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com - */ -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -#include <asm/processor.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - wait_timer WAIT_200US - wait_timer WAIT_200US - - /*------- LBSC -------*/ - write32 MMSELR_A, MMSELR_D - - /*------- DBSC2 -------*/ - write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D - write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D - write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D - write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D - write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1 - write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2 - wait_timer WAIT_200US - - write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H - wait_timer WAIT_200US - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1 - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2 - wait_timer WAIT_200US - - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 - - write32 DBSC2_DBEN_A, DBSC2_DBEN_D - write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D - write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D - write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D - wait_timer WAIT_200US - - /*------- GPIO -------*/ - write16 PACR_A, PXCR_D - write16 PBCR_A, PXCR_D - write16 PCCR_A, PXCR_D - write16 PDCR_A, PXCR_D - write16 PECR_A, PXCR_D - write16 PFCR_A, PXCR_D - write16 PGCR_A, PXCR_D - write16 PHCR_A, PHCR_D - write16 PJCR_A, PJCR_D - write16 PKCR_A, PKCR_D - write16 PLCR_A, PXCR_D - write16 PMCR_A, PMCR_D - write16 PNCR_A, PNCR_D - write16 PPCR_A, PXCR_D - write16 PQCR_A, PXCR_D - write16 PRCR_A, PXCR_D - - write8 PEPUPR_A, PEPUPR_D - write8 PHPUPR_A, PHPUPR_D - write8 PJPUPR_A, PJPUPR_D - write8 PKPUPR_A, PKPUPR_D - write8 PLPUPR_A, PLPUPR_D - write8 PMPUPR_A, PMPUPR_D - write8 PNPUPR_A, PNPUPR_D - write16 PPUPR1_A, PPUPR1_D - write16 PPUPR2_A, PPUPR2_D - write16 P1MSELR_A, P1MSELR_D - write16 P2MSELR_A, P2MSELR_D - - /*------- LBSC -------*/ - write32 BCR_A, BCR_D - write32 CS0BCR_A, CS0BCR_D - write32 CS0WCR_A, CS0WCR_D - write32 CS1BCR_A, CS1BCR_D - write32 CS1WCR_A, CS1WCR_D - write32 CS4BCR_A, CS4BCR_D - write32 CS4WCR_A, CS4WCR_D - - mov.l PASCR_A, r0 - mov.l @r0, r2 - mov.l PASCR_32BIT_MODE, r1 - tst r1, r2 - bt lbsc_29bit - - write32 CS2BCR_A, CS_USB_BCR_D - write32 CS2WCR_A, CS_USB_WCR_D - write32 CS3BCR_A, CS_SD_BCR_D - write32 CS3WCR_A, CS_SD_WCR_D - write32 CS5BCR_A, CS_I2C_BCR_D - write32 CS5WCR_A, CS_I2C_WCR_D - write32 CS6BCR_A, CS0BCR_D - write32 CS6WCR_A, CS0WCR_D - bra lbsc_end - nop - -lbsc_29bit: - write32 CS5BCR_A, CS_USB_BCR_D - write32 CS5WCR_A, CS_USB_WCR_D - write32 CS6BCR_A, CS_SD_BCR_D - write32 CS6WCR_A, CS_SD_WCR_D - -lbsc_end: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 64M 0 0 - * 1 0xa4000000 0x04000000 1 16M 0 0 - * 2 0xa6000000 0x08000000 1 16M 0 0 - * 9 0x88000000 0x48000000 1 128M 1 1 - * 10 0x90000000 0x50000000 1 128M 1 1 - * 11 0x98000000 0x58000000 1 128M 1 1 - * 13 0xa8000000 0x48000000 1 128M 0 0 - * 14 0xb0000000 0x50000000 1 128M 0 0 - * 15 0xb8000000 0x58000000 1 128M 0 0 - */ - write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D - write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D - write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D - write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D - write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D - write32 PMB_DATA_USB_A, PMB_DATA_USB_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D - write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D - write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D - write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D - write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D - write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D - write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif - - write32 CCR_A, CCR_D - - rts - nop - - .align 4 - -/*------- GPIO -------*/ -/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ -PXCR_D: .word 0x0000 - -PHCR_D: .word 0x00c0 -PJCR_D: .word 0xc3fc -PKCR_D: .word 0x03ff -PMCR_D: .word 0xffff -PNCR_D: .word 0xf0c3 - -PEPUPR_D: .long 0xff -PHPUPR_D: .long 0x00 -PJPUPR_D: .long 0x00 -PKPUPR_D: .long 0x00 -PLPUPR_D: .long 0x00 -PMPUPR_D: .long 0xfc -PNPUPR_D: .long 0x00 -PPUPR1_D: .word 0xffbf -PPUPR2_D: .word 0xff00 -P1MSELR_D: .word 0x3780 -P2MSELR_D: .word 0x0000 - -#define GPIO_BASE 0xffe70000 -PACR_A: .long GPIO_BASE + 0x00 -PBCR_A: .long GPIO_BASE + 0x02 -PCCR_A: .long GPIO_BASE + 0x04 -PDCR_A: .long GPIO_BASE + 0x06 -PECR_A: .long GPIO_BASE + 0x08 -PFCR_A: .long GPIO_BASE + 0x0a -PGCR_A: .long GPIO_BASE + 0x0c -PHCR_A: .long GPIO_BASE + 0x0e -PJCR_A: .long GPIO_BASE + 0x10 -PKCR_A: .long GPIO_BASE + 0x12 -PLCR_A: .long GPIO_BASE + 0x14 -PMCR_A: .long GPIO_BASE + 0x16 -PNCR_A: .long GPIO_BASE + 0x18 -PPCR_A: .long GPIO_BASE + 0x1a -PQCR_A: .long GPIO_BASE + 0x1c -PRCR_A: .long GPIO_BASE + 0x1e -PEPUPR_A: .long GPIO_BASE + 0x48 -PHPUPR_A: .long GPIO_BASE + 0x4e -PJPUPR_A: .long GPIO_BASE + 0x50 -PKPUPR_A: .long GPIO_BASE + 0x52 -PLPUPR_A: .long GPIO_BASE + 0x54 -PMPUPR_A: .long GPIO_BASE + 0x56 -PNPUPR_A: .long GPIO_BASE + 0x58 -PPUPR1_A: .long GPIO_BASE + 0x60 -PPUPR2_A: .long GPIO_BASE + 0x62 -P1MSELR_A: .long GPIO_BASE + 0x80 -P2MSELR_A: .long GPIO_BASE + 0x82 - -MMSELR_A: .long 0xfc400020 -#if defined(CONFIG_SH_32BIT) -MMSELR_D: .long 0xa5a50005 -#else -MMSELR_D: .long 0xa5a50002 -#endif - -/*------- DBSC2 -------*/ -#define DBSC2_BASE 0xfe800000 -DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c -DBSC2_DBEN_A: .long DBSC2_BASE + 0x10 -DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14 -DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20 -DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30 -DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34 -DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38 -DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40 -DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44 -DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48 -DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c -DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50 -DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54 -DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60 -DDR_DUMMY_ACCESS_A: .long 0x40000000 - -DBSC2_DBCONF_D: .long 0x00630002 -DBSC2_DBTR0_D: .long 0x050b1f04 -DBSC2_DBTR1_D: .long 0x00040204 -DBSC2_DBTR2_D: .long 0x02100308 -DBSC2_DBFREQ_D1: .long 0x00000000 -DBSC2_DBFREQ_D2: .long 0x00000100 -DBSC2_DBDICODTOCD_D:.long 0x000f0907 - -DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003 -DBSC2_DBCMDCNT_D_PALL: .long 0x00000002 -DBSC2_DBCMDCNT_D_REF: .long 0x00000004 - -DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000 -DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000 -DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006 -DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386 -DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952 -DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852 - -DBSC2_DBEN_D: .long 0x00000001 - -DBSC2_DBPDCNT0_D3: .long 0x00000080 -DBSC2_DBRFCNT1_D: .long 0x00000926 -DBSC2_DBRFCNT2_D: .long 0x00fe00fe -DBSC2_DBRFCNT0_D: .long 0x00010000 - -WAIT_200US: .long 33333 - -/*------- LBSC -------*/ -PASCR_A: .long 0xff000070 -PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */ - -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS0WCR_A: .long CS0WCR -CS1BCR_A: .long CS1BCR -CS1WCR_A: .long CS1WCR -CS2BCR_A: .long CS2BCR -CS2WCR_A: .long CS2WCR -CS3BCR_A: .long CS3BCR -CS3WCR_A: .long CS3WCR -CS4BCR_A: .long CS4BCR -CS4WCR_A: .long CS4WCR -CS5BCR_A: .long CS5BCR -CS5WCR_A: .long CS5WCR -CS6BCR_A: .long CS6BCR -CS6WCR_A: .long CS6WCR - -BCR_D: .long 0x80000003 -CS0BCR_D: .long 0x22222340 -CS0WCR_D: .long 0x00111118 -CS1BCR_D: .long 0x11111100 -CS1WCR_D: .long 0x33333303 -CS4BCR_D: .long 0x11111300 -CS4WCR_D: .long 0x00101012 - -/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */ -CS_USB_BCR_D: .long 0x11111200 -CS_USB_WCR_D: .long 0x00020005 - -/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ -CS_SD_BCR_D: .long 0x00000300 -CS_SD_WCR_D: .long 0x00030108 - -/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */ -CS_I2C_BCR_D: .long 0x11111100 -CS_I2C_WCR_D: .long 0x00000003 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9) -PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10) -PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13) -PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14) -PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15) - -PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4) -PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90) -PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0) -PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8) - -PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0) -PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1) -PMB_DATA_USB_A: .long PMB_DATA_BASE(2) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9) -PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10) -PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13) -PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14) -PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1) -PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1) -PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) -PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1) -PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1) - -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 /* check booting mode */ -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long 0xff00001c -CCR_D: .long 0x0000090b diff --git a/board/renesas/sh7785lcr/rtl8169.h b/board/renesas/sh7785lcr/rtl8169.h deleted file mode 100644 index 51240e6d62..0000000000 --- a/board/renesas/sh7785lcr/rtl8169.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com - */ - -#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr)) -#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr)) -#define PCI_PAR PCIREG_32(0xfe0401c0) -#define PCI_PDR PCIREG_32(0xfe040220) -#define PCI_CR PCIREG_32(0xfe040100) -#define PCI_CONF1 PCIREG_32(0xfe040004) - -#define HIGH 1 -#define LOW 0 - -#define PCI_PROG 0x80 -#define PCI_EEP_ADDRESS (unsigned short)0x0007 -#define PCI_MAC_ADDRESS_SIZE 3 - -#define TIME1 100 -#define TIME2 20000 - -#define BIT_DUMMY 0 -#define MAC_EEP_READ 1 -#define MAC_EEP_WRITE 2 -#define MAC_EEP_ERACE 3 -#define MAC_EEP_EWEN 4 -#define MAC_EEP_EWDS 5 - -/* RTL8169 */ -const unsigned short EEPROM_W_Data_8169_A[] = { - 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b, - 0x4020, 0xa101 -}; -const unsigned short EEPROM_W_Data_8169_B[] = { - 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 -}; diff --git a/board/renesas/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c deleted file mode 100644 index 68c324113f..0000000000 --- a/board/renesas/sh7785lcr/rtl8169_mac.c +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com - */ - -#include <common.h> -#include "rtl8169.h" - -static unsigned char *PCI_MEMR; - -static void mac_delay(unsigned int cnt) -{ - udelay(cnt); -} - -static void mac_pci_setup(void) -{ - unsigned long pci_data; - - PCI_PAR = 0x00000010; - PCI_PDR = 0x00001000; - PCI_PAR = 0x00000004; - pci_data = PCI_PDR; - PCI_PDR = pci_data | 0x00000007; - PCI_PAR = 0x00000010; - - PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0); -} - -static void EECS(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x08; - else - *PCI_MEMR = data & 0xf7; -} - -static void EECLK(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x04; - else - *PCI_MEMR = data & 0xfb; -} - -static void EEDI(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x02; - else - *PCI_MEMR = data & 0xfd; -} - -static inline void sh7785lcr_bitset(unsigned short bit) -{ - if (bit) - EEDI(HIGH); - else - EEDI(LOW); - - EECLK(LOW); - mac_delay(TIME1); - EECLK(HIGH); - mac_delay(TIME1); - EEDI(LOW); -} - -static inline unsigned char sh7785lcr_bitget(void) -{ - unsigned char bit; - - EECLK(LOW); - mac_delay(TIME1); - bit = *PCI_MEMR & 0x01; - EECLK(HIGH); - mac_delay(TIME1); - - return bit; -} - -static inline void sh7785lcr_setcmd(unsigned char command) -{ - sh7785lcr_bitset(BIT_DUMMY); - switch (command) { - case MAC_EEP_READ: - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - break; - case MAC_EEP_WRITE: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(1); - break; - case MAC_EEP_ERACE: - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - break; - case MAC_EEP_EWEN: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(0); - break; - case MAC_EEP_EWDS: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(0); - break; - default: - break; - } -} - -static inline unsigned short sh7785lcr_getdt(void) -{ - unsigned short data = 0; - int i; - - sh7785lcr_bitget(); /* DUMMY */ - for (i = 0 ; i < 16 ; i++) { - data <<= 1; - data |= sh7785lcr_bitget(); - } - return data; -} - -static inline void sh7785lcr_setadd(unsigned short address) -{ - sh7785lcr_bitset(address & 0x0020); /* A5 */ - sh7785lcr_bitset(address & 0x0010); /* A4 */ - sh7785lcr_bitset(address & 0x0008); /* A3 */ - sh7785lcr_bitset(address & 0x0004); /* A2 */ - sh7785lcr_bitset(address & 0x0002); /* A1 */ - sh7785lcr_bitset(address & 0x0001); /* A0 */ -} - -static inline void sh7785lcr_setdata(unsigned short data) -{ - sh7785lcr_bitset(data & 0x8000); - sh7785lcr_bitset(data & 0x4000); - sh7785lcr_bitset(data & 0x2000); - sh7785lcr_bitset(data & 0x1000); - sh7785lcr_bitset(data & 0x0800); - sh7785lcr_bitset(data & 0x0400); - sh7785lcr_bitset(data & 0x0200); - sh7785lcr_bitset(data & 0x0100); - sh7785lcr_bitset(data & 0x0080); - sh7785lcr_bitset(data & 0x0040); - sh7785lcr_bitset(data & 0x0020); - sh7785lcr_bitset(data & 0x0010); - sh7785lcr_bitset(data & 0x0008); - sh7785lcr_bitset(data & 0x0004); - sh7785lcr_bitset(data & 0x0002); - sh7785lcr_bitset(data & 0x0001); -} - -static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address, - unsigned int count) -{ - unsigned int i; - - for (i = 0; i < count; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - - sh7785lcr_setcmd(MAC_EEP_WRITE); - sh7785lcr_setadd(address++); - sh7785lcr_setdata(*(data + i)); - - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - mac_delay(TIME2); - } -} - -static void sh7785lcr_macerase(void) -{ - unsigned int i; - unsigned short pci_address = 7; - - for (i = 0; i < 3; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - sh7785lcr_setcmd(MAC_EEP_ERACE); - sh7785lcr_setadd(pci_address++); - mac_delay(TIME1); - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - } - - mac_delay(TIME2); - - printf("\n\nErace End\n"); - for (i = 0; i < 10; i++) - mac_delay(TIME2); -} - -static void sh7785lcr_macwrite(unsigned short *data) -{ - sh7785lcr_macerase(); - - sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7); - sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); - sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54); -} - -void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count) -{ - unsigned int i; - unsigned short wk; - - for (i = 0 ; i < count; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - sh7785lcr_setcmd(MAC_EEP_READ); - sh7785lcr_setadd(address++); - wk = sh7785lcr_getdt(); - - *buf++ = (unsigned char)(wk & 0xff); - *buf++ = (unsigned char)((wk >> 8) & 0xff); - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - } -} - -static void sh7785lcr_macadrd(unsigned char *buf) -{ - *PCI_MEMR = PCI_PROG; - - sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); -} - -static void sh7785lcr_eepewen(void) -{ - *PCI_MEMR = PCI_PROG; - mac_delay(TIME1); - EECS(LOW); - EECLK(LOW); - EEDI(LOW); - EECS(HIGH); - mac_delay(TIME1); - - sh7785lcr_setcmd(MAC_EEP_EWEN); - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - mac_delay(TIME1); -} - -void mac_write(unsigned short *data) -{ - mac_pci_setup(); - sh7785lcr_eepewen(); - sh7785lcr_macwrite(data); -} - -void mac_read(void) -{ - unsigned char data[6]; - - mac_pci_setup(); - sh7785lcr_macadrd(data); - printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n", - data[0], data[1], data[2], data[3], data[4], data[5]); -} - -int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - unsigned char mac[6]; - char *s, *e; - - if (argc != 2) - return cmd_usage(cmdtp); - - s = argv[1]; - - for (i = 0; i < 6; i++) { - mac[i] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - mac_write((unsigned short *)mac); - - return 0; -} - -U_BOOT_CMD( - setmac, 2, 1, do_set_mac, - "write MAC address for RTL8110SCL", - "\n" - "setmac <mac address> - write MAC address for RTL8110SCL" -); - -int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 1) - return cmd_usage(cmdtp); - - mac_read(); - - return 0; -} - -U_BOOT_CMD( - printmac, 1, 1, do_print_mac, - "print MAC address for RTL8110", - "\n" - " - print MAC address for RTL8110" -); diff --git a/board/renesas/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c deleted file mode 100644 index c5f469342d..0000000000 --- a/board/renesas/sh7785lcr/selfcheck.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com - */ - -#include <common.h> -#include <console.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/pci.h> - -#if defined(CONFIG_CPU_32BIT) -#define NOCACHE_OFFSET 0x00000000 -#else -#define NOCACHE_OFFSET 0xa0000000 -#endif -#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET) -#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET) -#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET) - -#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET) - -static void test_pld(void) -{ - printf("PLD version = %04x\n", readb(PLD_VERSR)); -} - -static void test_sm107(void) -{ - printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID)); -} - -static void test_led(void) -{ - printf("turn on LEDs 3, 5, 7, 9\n"); - writeb(0x55, PLD_LEDCR); - mdelay(2000); - printf("turn on LEDs 4, 6, 8, 10\n"); - writeb(0xaa, PLD_LEDCR); - mdelay(2000); - writeb(0x00, PLD_LEDCR); -} - -static void test_dipsw(void) -{ - printf("Please DIPSW set = B'0101\n"); - while (readb(PLD_SWSR) != 0x05) { - if (ctrlc()) - return; - } - printf("Please DIPSW set = B'1010\n"); - while (readb(PLD_SWSR) != 0x0A) { - if (ctrlc()) - return; - } - printf("DIPSW OK\n"); -} - -static void test_net(void) -{ - unsigned long data; - - writel(0x80000000, 0xfe0401c0); - data = readl(0xfe040220); - if (data == 0x816910ec) - printf("Ethernet OK\n"); - else - printf("Ethernet NG, data = %08x\n", (unsigned int)data); -} - -static void test_sata(void) -{ - unsigned long data; - - writel(0x80000800, 0xfe0401c0); - data = readl(0xfe040220); - if (data == 0x35121095) - printf("SATA OK\n"); - else - printf("SATA NG, data = %08x\n", (unsigned int)data); -} - -static void test_pci(void) -{ - writel(0x80001800, 0xfe0401c0); - printf("PCI CN1 ID = %08x\n", readl(0xfe040220)); - - writel(0x80001000, 0xfe0401c0); - printf("PCI CN2 ID = %08x\n", readl(0xfe040220)); -} - -int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *cmd; - - if (argc != 2) - return cmd_usage(cmdtp); - - cmd = argv[1]; - switch (cmd[0]) { - case 'a': /* all */ - test_pld(); - test_led(); - test_dipsw(); - test_sm107(); - test_net(); - test_sata(); - test_pci(); - break; - case 'p': /* pld or pci */ - if (cmd[1] == 'l') - test_pld(); - else - test_pci(); - break; - case 'l': /* led */ - test_led(); - break; - case 'd': /* dipsw */ - test_dipsw(); - break; - case 's': /* sm107 or sata */ - if (cmd[1] == 'm') - test_sm107(); - else - test_sata(); - break; - case 'n': /* net */ - test_net(); - break; - default: - return cmd_usage(cmdtp); - } - - return 0; -} - -U_BOOT_CMD( - hwtest, 2, 1, do_hw_test, - "hardware test for R0P7785LC0011RL board", - "\n" - "hwtest all - test all hardware\n" - "hwtest pld - output PLD version\n" - "hwtest led - turn on LEDs\n" - "hwtest dipsw - test DIP switch\n" - "hwtest sm107 - output SM107 version\n" - "hwtest net - check RTL8110 ID\n" - "hwtest sata - check SiI3512 ID\n" - "hwtest pci - output PCI slot device ID" -); diff --git a/board/renesas/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c deleted file mode 100644 index 1874334814..0000000000 --- a/board/renesas/sh7785lcr/sh7785lcr.c +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/pci.h> -#include <netdev.h> - -int checkboard(void) -{ - puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7780_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -#if defined(CONFIG_SH_32BIT) -int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - /* clear ITLB */ - writel(0x00000004, 0xff000010); - - /* delete PMB for peripheral */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - writel(0, PMB_ADDR_BASE(1)); - writel(0, PMB_DATA_BASE(1)); - writel(0, PMB_ADDR_BASE(2)); - writel(0, PMB_DATA_BASE(2)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8)); - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12)); - - return 0; -} - -U_BOOT_CMD( - pmb, 1, 1, do_pmb, - "pmb - PMB setting\n", - "\n" - " - PMB setting for all SDRAM mapping" -); -#endif diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig deleted file mode 100644 index b520be5c37..0000000000 --- a/configs/sh7785lcr_32bit_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x8FF80000 -CONFIG_SH_32BIT=y -CONFIG_TARGET_SH7785LCR=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC1,115200 root=/dev/nfs ip=dhcp" -CONFIG_VERSION_VARIABLE=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_PCI=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PCI=y -CONFIG_SCIF_CONSOLE=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig deleted file mode 100644 index d48ba73346..0000000000 --- a/configs/sh7785lcr_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x0FF80000 -CONFIG_TARGET_SH7785LCR=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC1,115200 root=/dev/nfs ip=dhcp" -CONFIG_VERSION_VARIABLE=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_PCI=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PCI=y -CONFIG_SCIF_CONSOLE=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h deleted file mode 100644 index f27f665fb6..0000000000 --- a/include/configs/sh7785lcr.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas Technology R0P7785LC0011RL board - * - * Copyright (C) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com - */ - -#ifndef __SH7785LCR_H -#define __SH7785LCR_H - -#define CONFIG_CPU_SH7785 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootdevice=0:1\0" \ - "usbload=usb reset;usbboot;usb stop;bootm\0" - -#define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS - -/* MEMORY */ -#if defined(CONFIG_SH_32BIT) -/* 0x40000000 - 0x47FFFFFF does not use */ -#define CONFIG_SH_SDRAM_OFFSET (0x8000000) -#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) -#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) -#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) -#define SH7785LCR_FLASH_BASE_1 (0xa0000000) -#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) -#define SH7785LCR_USB_BASE (0xa6000000) -#else -#define SH7785LCR_SDRAM_BASE (0x08000000) -#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) -#define SH7785LCR_FLASH_BASE_1 (0xa0000000) -#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) -#define SH7785LCR_USB_BASE (0xb4000000) -#endif - -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF1 1 -#define CONFIG_SCIF_EXT_CLOCK 1 - -#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - (SH7785LCR_SDRAM_SIZE) - \ - 4 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* FLASH */ -#undef CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ - (0 * SH7785LCR_FLASH_BANK_SIZE) } - -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) - -#undef CONFIG_SYS_DIRECT_FLASH_TFTP - -/* R8A66597 */ -#define CONFIG_USB_R8A66597_HCD -#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE -#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ -#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ -#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ - -/* PCI Controller */ -#define CONFIG_SH4_PCI -#define CONFIG_SH7780_PCI -#if defined(CONFIG_SH_32BIT) -#define CONFIG_SH7780_PCI_LSR 0x1ff00001 -#define CONFIG_SH7780_PCI_LAR 0x5f000000 -#define CONFIG_SH7780_PCI_BAR 0x5f000000 -#else -#define CONFIG_SH7780_PCI_LSR 0x07f00001 -#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE -#endif -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ - -#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ - -#if defined(CONFIG_SH_32BIT) -#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE -#else -#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE -#endif -#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE - -/* ENV setting */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) - -/* Board Clock */ -/* The SCIF used external clock. system clock only used timer. */ -#define CONFIG_SYS_CLK_FREQ 50000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#endif /* __SH7785LCR_H */
There are no more boards using this CPU and there is no prospect of any boards showing up soon, remove it.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Chris Brandt chris.brandt@renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Vladimir Zapolskiy vz@mleia.com Cc: Yoshihiro Shimoda shimoda.yoshihiro@renesas.com --- arch/sh/include/asm/cpu_sh4.h | 2 - arch/sh/include/asm/cpu_sh7785.h | 119 ------------------------------- doc/README.sh | 1 - drivers/serial/serial_sh.c | 1 - drivers/serial/serial_sh.h | 6 +- scripts/config_whitelist.txt | 1 - 6 files changed, 1 insertion(+), 129 deletions(-) delete mode 100644 arch/sh/include/asm/cpu_sh7785.h
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index 977b648dd4..5fc9c962d8 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -42,8 +42,6 @@ # include <asm/cpu_sh7763.h> #elif defined (CONFIG_CPU_SH7780) # include <asm/cpu_sh7780.h> -#elif defined (CONFIG_CPU_SH7785) -# include <asm/cpu_sh7785.h> #else # error "Unknown SH4 variant" #endif diff --git a/arch/sh/include/asm/cpu_sh7785.h b/arch/sh/include/asm/cpu_sh7785.h deleted file mode 100644 index b0388957f9..0000000000 --- a/arch/sh/include/asm/cpu_sh7785.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _ASM_CPU_SH7785_H_ -#define _ASM_CPU_SH7785_H_ - -/* - * Copyright (c) 2007,2008 Nobuhiro Iwamatsu iwamatsu@nigauri.org - * Copyright (c) 2008 Yusuke Goda goda.yusuke@renesas.com - * Copyright (c) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com - */ - -#define CACHE_OC_NUM_WAYS 1 -#define CCR_CACHE_INIT 0x0000090b - -/* Exceptions */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* Cache Controller */ -#define CCR 0xFF00001C -#define QACR0 0xFF000038 -#define QACR1 0xFF00003C -#define RAMCR 0xFF000074 - -/* Watchdog Timer and Reset */ -#define WTCNT WDTCNT -#define WDTST 0xFFCC0000 -#define WDTCSR 0xFFCC0004 -#define WDTBST 0xFFCC0008 -#define WDTCNT 0xFFCC0010 -#define WDTBCNT 0xFFCC0018 - -/* Timer Unit */ -#define TMU_BASE 0xFFD80000 - -/* Serial Communication Interface with FIFO */ -#define SCIF1_BASE 0xffeb0000 - -/* LBSC */ -#define MMSELR 0xfc400020 -#define LBSC_BASE 0xff800000 -#define BCR (LBSC_BASE + 0x1000) -#define CS0BCR (LBSC_BASE + 0x2000) -#define CS1BCR (LBSC_BASE + 0x2010) -#define CS2BCR (LBSC_BASE + 0x2020) -#define CS3BCR (LBSC_BASE + 0x2030) -#define CS4BCR (LBSC_BASE + 0x2040) -#define CS5BCR (LBSC_BASE + 0x2050) -#define CS6BCR (LBSC_BASE + 0x2060) -#define CS0WCR (LBSC_BASE + 0x2008) -#define CS1WCR (LBSC_BASE + 0x2018) -#define CS2WCR (LBSC_BASE + 0x2028) -#define CS3WCR (LBSC_BASE + 0x2038) -#define CS4WCR (LBSC_BASE + 0x2048) -#define CS5WCR (LBSC_BASE + 0x2058) -#define CS6WCR (LBSC_BASE + 0x2068) -#define CS5PCR (LBSC_BASE + 0x2070) -#define CS6PCR (LBSC_BASE + 0x2080) - -/* PCI Controller */ -#define SH7780_PCIECR 0xFE000008 -#define SH7780_PCIVID 0xFE040000 -#define SH7780_PCIDID 0xFE040002 -#define SH7780_PCICMD 0xFE040004 -#define SH7780_PCISTATUS 0xFE040006 -#define SH7780_PCIRID 0xFE040008 -#define SH7780_PCIPIF 0xFE040009 -#define SH7780_PCISUB 0xFE04000A -#define SH7780_PCIBCC 0xFE04000B -#define SH7780_PCICLS 0xFE04000C -#define SH7780_PCILTM 0xFE04000D -#define SH7780_PCIHDR 0xFE04000E -#define SH7780_PCIBIST 0xFE04000F -#define SH7780_PCIIBAR 0xFE040010 -#define SH7780_PCIMBAR0 0xFE040014 -#define SH7780_PCIMBAR1 0xFE040018 -#define SH7780_PCISVID 0xFE04002C -#define SH7780_PCISID 0xFE04002E -#define SH7780_PCICP 0xFE040034 -#define SH7780_PCIINTLINE 0xFE04003C -#define SH7780_PCIINTPIN 0xFE04003D -#define SH7780_PCIMINGNT 0xFE04003E -#define SH7780_PCIMAXLAT 0xFE04003F -#define SH7780_PCICID 0xFE040040 -#define SH7780_PCINIP 0xFE040041 -#define SH7780_PCIPMC 0xFE040042 -#define SH7780_PCIPMCSR 0xFE040044 -#define SH7780_PCIPMCSRBSE 0xFE040046 -#define SH7780_PCI_CDD 0xFE040047 -#define SH7780_PCICR 0xFE040100 -#define SH7780_PCILSR0 0xFE040104 -#define SH7780_PCILSR1 0xFE040108 -#define SH7780_PCILAR0 0xFE04010C -#define SH7780_PCILAR1 0xFE040110 -#define SH7780_PCIIR 0xFE040114 -#define SH7780_PCIIMR 0xFE040118 -#define SH7780_PCIAIR 0xFE04011C -#define SH7780_PCICIR 0xFE040120 -#define SH7780_PCIAINT 0xFE040130 -#define SH7780_PCIAINTM 0xFE040134 -#define SH7780_PCIBMIR 0xFE040138 -#define SH7780_PCIPAR 0xFE0401C0 -#define SH7780_PCIPINT 0xFE0401CC -#define SH7780_PCIPINTM 0xFE0401D0 -#define SH7780_PCIMBR0 0xFE0401E0 -#define SH7780_PCIMBMR0 0xFE0401E4 -#define SH7780_PCIMBR1 0xFE0401E8 -#define SH7780_PCIMBMR1 0xFE0401EC -#define SH7780_PCIMBR2 0xFE0401F0 -#define SH7780_PCIMBMR2 0xFE0401F4 -#define SH7780_PCIIOBR 0xFE0401F8 -#define SH7780_PCIIOBMR 0xFE0401FC -#define SH7780_PCICSCR0 0xFE040210 -#define SH7780_PCICSCR1 0xFE040214 -#define SH7780_PCICSAR0 0xFE040218 -#define SH7780_PCICSAR1 0xFE04021C -#define SH7780_PCIPDR 0xFE040220 - -#endif /* _ASM_CPU_SH7780_H_ */ diff --git a/doc/README.sh b/doc/README.sh index 6baee089e3..667c7974e5 100644 --- a/doc/README.sh +++ b/doc/README.sh @@ -94,7 +94,6 @@ U-Boot for Renesas SuperH I plan to support the following CPUs and boards. 5.1. CPUs - SH7751R(SH4) - - SH7785(SH4)
5.2. Boards - Many boards ;-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index c934d5f25a..e6fe5c7c67 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -21,7 +21,6 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CPU_SH7760) || \ defined(CONFIG_CPU_SH7780) || \ - defined(CONFIG_CPU_SH7785) || \ defined(CONFIG_CPU_SH7786) static int scif_rxfill(struct uart_port *port) { diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index c6f4778628..887dd19ff5 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -170,8 +170,7 @@ struct uart_port { # define SCSCR_INIT(port) 0x3a #endif
-#elif defined(CONFIG_CPU_SH7785) || \ - defined(CONFIG_CPU_SH7786) +#elif defined(CONFIG_CPU_SH7786) # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ @@ -247,7 +246,6 @@ struct uart_port { defined(CONFIG_CPU_SH7751R) || \ defined(CONFIG_CPU_SH7763) || \ defined(CONFIG_CPU_SH7780) || \ - defined(CONFIG_CPU_SH7785) || \ defined(CONFIG_CPU_SH7786) || \ defined(CONFIG_CPU_SHX3) #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ @@ -586,7 +584,6 @@ SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) #if defined(CONFIG_CPU_SH7760) || \ defined(CONFIG_CPU_SH7780) || \ - defined(CONFIG_CPU_SH7785) || \ defined(CONFIG_CPU_SH7786) SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) @@ -726,7 +723,6 @@ static inline int sci_rxd_in(struct uart_port *port) */
#if (defined(CONFIG_CPU_SH7780) || \ - defined(CONFIG_CPU_SH7785) || \ defined(CONFIG_CPU_SH7786)) && \ !defined(CONFIG_SH_SH2007) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index efa55a1890..e48c40d34b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -285,7 +285,6 @@ CONFIG_CPU_SH7753 CONFIG_CPU_SH7757 CONFIG_CPU_SH7763 CONFIG_CPU_SH7780 -CONFIG_CPU_SH7785 CONFIG_CPU_TYPE_R CONFIG_CPU_VR41XX CONFIG_CQSPI_REF_CLK
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Marek Vasut