Implement minimum required functions for the basic support to queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

---

Changes in v4: None Changes in v3: - Update to use u-boot coding convention for fsp codes - Use jnz to jump to the car_init error code at the end of tnc_car.S file instead of being in the normal path flow - Add a TODO comment block to document the fsp_init() call - Change label xxx_stack to xxx_romstack - Add a comment block to explain the ROM stack

Changes in v2: - Replace 0xcf9 with macro PORT_RESET from processor.h - Move FspInit call from start.S to car_init - Add UART0_BASE and UART1_BASE to ibmpc.h

arch/x86/cpu/queensbay/Makefile | 9 +++ arch/x86/cpu/queensbay/tnc.c | 48 ++++++++++++++ arch/x86/cpu/queensbay/tnc_car.S | 127 ++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/queensbay/tnc_dram.c | 78 +++++++++++++++++++++++ arch/x86/cpu/queensbay/tnc_pci.c | 61 ++++++++++++++++++ arch/x86/include/asm/ibmpc.h | 3 + board/intel/crownbay/MAINTAINERS | 6 ++ board/intel/crownbay/Makefile | 7 +++ board/intel/crownbay/crownbay.c | 21 +++++++ board/intel/crownbay/start.S | 9 +++ 10 files changed, 369 insertions(+) create mode 100644 arch/x86/cpu/queensbay/Makefile create mode 100644 arch/x86/cpu/queensbay/tnc.c create mode 100644 arch/x86/cpu/queensbay/tnc_car.S create mode 100644 arch/x86/cpu/queensbay/tnc_dram.c create mode 100644 arch/x86/cpu/queensbay/tnc_pci.c create mode 100644 board/intel/crownbay/MAINTAINERS create mode 100644 board/intel/crownbay/Makefile create mode 100644 board/intel/crownbay/crownbay.c create mode 100644 board/intel/crownbay/start.S

diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile new file mode 100644 index 0000000..ace04ca --- /dev/null +++ b/arch/x86/cpu/queensbay/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += tnc_car.o tnc_dram.o tnc.o +obj-y += fsp_configs.o fsp_support.o +obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c new file mode 100644 index 0000000..8b9815f --- /dev/null +++ b/arch/x86/cpu/queensbay/tnc.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/post.h> +#include <asm/arch/fsp/fsp_support.h> +#include <asm/processor.h> + +int arch_cpu_init(void) +{ + post_code(POST_CPU_INIT); +#ifdef CONFIG_SYS_X86_TSC_TIMER + timer_set_base(rdtsc()); +#endif + + return x86_cpu_init_f(); +} + +int print_cpuinfo(void) +{ + post_code(POST_CPU_INFO); + return default_print_cpuinfo(); +} + +void reset_cpu(ulong addr) +{ + /* cold reset */ + outb(0x06, PORT_RESET); +} + +void board_final_cleanup(void) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); + status = fsp_notify(NULL, INIT_PHASE_BOOT); + if (status != FSP_SUCCESS) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return; +} diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S new file mode 100644 index 0000000..6834a64 --- /dev/null +++ b/arch/x86/cpu/queensbay/tnc_car.S @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/post.h> + +.globl car_init +car_init: + /* + * Note: ebp holds the BIST value (built-in self test) so far, but ebp + * will be destroyed through the FSP call, thus we have to test the + * BIST value here before we call into FSP. + */ + test %ebp, %ebp + jz car_init_start + post_code(POST_BIST_FAILURE) + jmp die + +car_init_start: + post_code(POST_CAR_START) + lea find_fsp_header_romstack, %esp + jmp find_fsp_header + +find_fsp_header_ret: + /* EAX points to FSP_INFO_HEADER */ + mov %eax, %ebp + + /* sanity test */ + cmp $CONFIG_FSP_LOCATION, %eax + jb die + + /* calculate TempRamInitEntry address */ + mov 0x30(%ebp), %eax + add 0x1c(%ebp), %eax + + /* call FSP TempRamInitEntry to setup temporary stack */ + lea temp_ram_init_romstack, %esp + jmp *%eax + +temp_ram_init_ret: + addl $4, %esp + cmp $0, %eax + jnz car_init_fail + + post_code(POST_CAR_CPU_CACHE) + + /* + * The FSP TempRamInit initializes the ecx and edx registers to + * point to a temporary but writable memory range (Cache-As-RAM). + * ecx: the start of this temporary memory range, + * edx: the end of this range. + */ + + /* stack grows down from top of CAR */ + movl %edx, %esp + + /* + * TODO: + * + * According to FSP architecture spec, the fsp_init() will not return + * to its caller, instead it requires the bootloader to provide a + * so-called continuation function to pass into the FSP as a parameter + * of fsp_init, and fsp_init() will call that continuation function + * directly. + * + * The call to fsp_init() may need to be moved out of the car_init() + * to cpu_init_f() with the help of some inline assembly codes. + * Note there is another issue that fsp_init() will setup another stack + * using the fsp_init parameter stack_top after DRAM is initialized, + * which means any data on the previous stack (on the CAR) gets lost + * (ie: U-Boot global_data). FSP is supposed to support such scenario, + * however it does not work. This should be revisited in the future. + */ + movl $CONFIG_FSP_TEMP_RAM_ADDR, %eax + xorl %edx, %edx + xorl %ecx, %ecx + call fsp_init + +.global fsp_init_done +fsp_init_done: + /* + * We come here from FspInit with eax pointing to the HOB list. + * Save eax to esi temporarily. + */ + movl %eax, %esi + /* + * Re-initialize the ebp (BIST) to zero, as we already reach here + * which means we passed BIST testing before. + */ + xorl %ebp, %ebp + jmp car_init_ret + +car_init_fail: + post_code(POST_CAR_FAILURE) + +die: + hlt + jmp die + hlt + + /* + * The function call before CAR initialization is tricky. It cannot + * be called using the 'call' instruction but only the 'jmp' with + * the help of a handcrafted stack in the ROM. The stack needs to + * contain the function return address as well as the parameters. + */ + .balign 4 +find_fsp_header_romstack: + .long find_fsp_header_ret + + .balign 4 +temp_ram_init_romstack: + .long temp_ram_init_ret + .long temp_ram_init_params +temp_ram_init_params: + .long ucode_start /* microcode base */ + .long ucode_size /* microcode size */ + .long CONFIG_SYS_MONITOR_BASE /* code region base */ + .long CONFIG_SYS_MONITOR_LEN /* code region size */ + + .balign 4 +ucode_start: + .include "arch/x86/cpu/queensbay/M0220661105.inc" +ucode_size = ( . - ucode_start) diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c new file mode 100644 index 0000000..dbc1710 --- /dev/null +++ b/arch/x86/cpu/queensbay/tnc_dram.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/fsp/fsp_support.h> +#include <asm/e820.h> +#include <asm/post.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + phys_size_t ram_size = 0; + union hob_pointers_t hob; + + hob.raw = gd->arch.hob_list; + while (!END_OF_HOB(hob)) { + if (hob.hdr->type == HOB_TYPE_RES_DESC) { + if (hob.res_desc->type == RES_SYS_MEM || + hob.res_desc->type == RES_MEM_RESERVED) { + ram_size += hob.res_desc->len; + } + } + hob.raw = GET_NEXT_HOB(hob); + } + + gd->ram_size = ram_size; + post_code(POST_DRAM); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. + * It overrides the default implementation found elsewhere which simply + * picks the end of ram, wherever that may be. The location of the stack, + * the relocation address, and how far U-Boot is moved by relocation are + * set in the global data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + return get_usable_lowmem_top(gd->arch.hob_list); +} + +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + unsigned num_entries = 0; + + union hob_pointers_t hob; + + hob.raw = gd->arch.hob_list; + + while (!END_OF_HOB(hob)) { + if (hob.hdr->type == HOB_TYPE_RES_DESC) { + entries[num_entries].addr = hob.res_desc->phys_start; + entries[num_entries].size = hob.res_desc->len; + + if (hob.res_desc->type == RES_SYS_MEM) + entries[num_entries].type = E820_RAM; + else if (hob.res_desc->type == RES_MEM_RESERVED) + entries[num_entries].type = E820_RESERVED; + } + hob.raw = GET_NEXT_HOB(hob); + num_entries++; + } + + return num_entries; +} diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c new file mode 100644 index 0000000..39bff49 --- /dev/null +++ b/arch/x86/cpu/queensbay/tnc_pci.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pci.h> +#include <asm/pci.h> +#include <asm/arch/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + pci_set_region(hose->regions + 3, + 0, + 0, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; +} + +int board_pci_post_scan(struct pci_controller *hose) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); + status = fsp_notify(NULL, INIT_PHASE_PCI); + if (status != FSP_SUCCESS) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return 0; +} diff --git a/arch/x86/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h index e6d183b..c3b5187 100644 --- a/arch/x86/include/asm/ibmpc.h +++ b/arch/x86/include/asm/ibmpc.h @@ -18,4 +18,7 @@ #define SYSCTLA 0x92 #define SLAVE_PIC 0xa0

+#define UART0_BASE 0x3f8 +#define UART1_BASE 0x2f8 + #endif diff --git a/board/intel/crownbay/MAINTAINERS b/board/intel/crownbay/MAINTAINERS new file mode 100644 index 0000000..1eb6869 --- /dev/null +++ b/board/intel/crownbay/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL CROWNBAY BOARD +M: Bin Meng bmeng.cn@gmail.com +S: Maintained +F: board/intel/crownbay/ +F: include/configs/crownbay.h +F: configs/crownbay_defconfig diff --git a/board/intel/crownbay/Makefile b/board/intel/crownbay/Makefile new file mode 100644 index 0000000..aeb219b --- /dev/null +++ b/board/intel/crownbay/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += crownbay.o start.o diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c new file mode 100644 index 0000000..8c6df98 --- /dev/null +++ b/board/intel/crownbay/crownbay.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> +#include <smsc_lpc47m.h> + +#define SERIAL_DEV PNP_DEV(0x2e, 4) + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + + return 0; +} diff --git a/board/intel/crownbay/start.S b/board/intel/crownbay/start.S new file mode 100644 index 0000000..cf92b4c --- /dev/null +++ b/board/intel/crownbay/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret

Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - Add a comment to explain we don't need check bit0 in GPIO base address register - Add setup_pch_gpios() in crownbay.c

arch/x86/include/asm/arch-queensbay/gpio.h | 13 +++++++++++++ arch/x86/include/asm/gpio.h | 4 ++-- board/coreboot/coreboot/coreboot.c | 2 +- board/google/chromebook_link/link.c | 2 +- board/intel/crownbay/crownbay.c | 5 +++++ drivers/gpio/intel_ich6_gpio.c | 20 ++++++++++++-------- 6 files changed, 34 insertions(+), 12 deletions(-) create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h

diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h new file mode 100644 index 0000000..ab4e059 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/gpio.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x44 + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 1787e52..1099427 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -11,7 +11,7 @@ #include <asm-generic/gpio.h>

struct ich6_bank_platdata { - uint32_t base_addr; + uint16_t base_addr; const char *bank_name; };

@@ -147,7 +147,7 @@ struct pch_gpio_map { } set3; };

-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio); +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio); void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);

#endif /* _X86_GPIO_H_ */ diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index b260f9a..154faf6 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -16,7 +16,7 @@ int arch_early_init_r(void) return 0; }

-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 4d95c1c..9978e92 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -125,7 +125,7 @@ int board_early_init_f(void) return 0; }

-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { /* GPIO Set 1 */ if (gpio->set1.level) diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 8c6df98..54670d3 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -19,3 +19,8 @@ int board_early_init_f(void)

return 0; } + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 3433216..7720cc3 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -39,9 +39,9 @@

struct ich6_bank_priv { /* These are I/O addresses */ - uint32_t use_sel; - uint32_t io_sel; - uint32_t lvl; + uint16_t use_sel; + uint16_t io_sel; + uint16_t lvl; };

/* TODO: Move this to device tree, or platform data */ @@ -57,7 +57,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) u8 tmpbyte; u16 tmpword; u32 tmplong; - u32 gpiobase; + u16 gpiobase; int offset;

/* Where should it be? */ @@ -116,11 +116,15 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) /* * GPIOBASE moved to its current offset with ICH6, but prior to * that it was unused (or undocumented). Check that it looks - * okay: not all ones or zeros, and mapped to I/O space (bit 0). + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. */ tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); - if (tmplong == 0x00000000 || tmplong == 0xffffffff || - !(tmplong & 0x00000001)) { + if (tmplong == 0x00000000 || tmplong == 0xffffffff) { debug("%s: unexpected GPIOBASE value\n", __func__); return -ENODEV; } @@ -131,7 +135,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ - gpiobase = tmplong & 0xfffffffe; + gpiobase = tmplong & 0xfffe; offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); if (offset == -1) { debug("%s: Invalid register offset %d\n", __func__, offset);

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/x86/cpu/Makefile | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 7f09db5..5033d2b 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -15,6 +15,7 @@ obj-y += interrupts.o cpu.o call64.o obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ +obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-y += lapic.o obj-$(CONFIG_PCI) += pci.o obj-y += turbo.o

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - Fix several typos in queensbay/Kconfig - Change FSP_FILE and CMC_FILE description to indicate the file is in the board directory - Add help for FSP_TEMP_RAM_ADDR - Add more help for CMC_FILE

arch/x86/Kconfig | 13 +++++++ arch/x86/cpu/queensbay/Kconfig | 79 ++++++++++++++++++++++++++++++++++++++++++ board/intel/crownbay/Kconfig | 20 +++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/x86/cpu/queensbay/Kconfig create mode 100644 board/intel/crownbay/Kconfig

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fdfb618..ebf72b3 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.

+config TARGET_CROWNBAY + bool "Support Intel Crown Bay CRB" + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + endchoice

config RAMBASE @@ -310,8 +319,12 @@ endmenu

source "arch/x86/cpu/ivybridge/Kconfig"

+source "arch/x86/cpu/queensbay/Kconfig" + source "board/coreboot/coreboot/Kconfig"

source "board/google/chromebook_link/Kconfig"

+source "board/intel/crownbay/Kconfig" + endmenu diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig new file mode 100644 index 0000000..56fe85c --- /dev/null +++ b/arch/x86/cpu/queensbay/Kconfig @@ -0,0 +1,79 @@ +# +# Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_QUEENSBAY + bool + select HAVE_FSP + select HAVE_CMC + +if INTEL_QUEENSBAY + +config HAVE_FSP + bool "Add an Firmware Support Package binary" + help + Select this option to add an Firmware Support Package binary to + the resulting U-Boot image. It is a binary blob which U-Boot uses + to set up SDRAM and other chipset specific initialization. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config FSP_FILE + string "Firmware Support Package binary filename" + depends on HAVE_FSP + default "fsp.bin" + help + The filename of the file to use as Firmware Support Package binary + in the board directory. + +config FSP_LOCATION + hex "Firmware Support Package binary location" + depends on HAVE_FSP + default 0xfffc0000 + help + FSP is not Position Independent Code (PIC) and the whole FSP has to + be rebased if it is placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + + The default base address of 0xfffc0000 indicates that the binary must + be located at offset 0xc0000 from the beginning of a 1MB flash device. + +config FSP_TEMP_RAM_ADDR + hex + default 0x2000000 + help + Stack top address which is used in FspInit after DRAM is ready and + CAR is disabled. + +config HAVE_CMC + bool "Add a Chipset Micro Code state machine binary" + help + Select this option to add a Chipset Micro Code state machine binary + to the resulting U-Boot image. It is a 64K data block of machine + specific code which must be put in the flash for the processor to + access when powered up before system BIOS is executed. + +config CMC_FILE + string "Chipset Micro Code state machine filename" + depends on HAVE_CMC + default "cmc.bin" + help + The filename of the file to use as Chipset Micro Code state machine + binary in the board directory. + +config CMC_LOCATION + hex "Chipset Micro Code state machine binary location" + depends on HAVE_CMC + default 0xfffb0000 + help + The location of the CMC binary is determined by a strap. It must be + put in flash at a location matching the strap-determined base address. + + The default base address of 0xfffb0000 indicates that the binary must + be located at offset 0xb0000 from the beginning of a 1MB flash device. + +endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig new file mode 100644 index 0000000..4709f9b --- /dev/null +++ b/board/intel/crownbay/Kconfig @@ -0,0 +1,20 @@ +if TARGET_CROWNBAY + +config SYS_BOARD + default "crownbay" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "queensbay" + +config SYS_CONFIG_NAME + default "crownbay" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select INTEL_QUEENSBAY + select BOARD_ROMSIZE_KB_1024 + +endif

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

configs/crownbay_defconfig | 6 ++++++ include/configs/crownbay.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 configs/crownbay_defconfig create mode 100644 include/configs/crownbay.h

diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig new file mode 100644 index 0000000..ce90553 --- /dev/null +++ b/configs/crownbay_defconfig @@ -0,0 +1,6 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CROWNBAY=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="crownbay" diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h new file mode 100644 index 0000000..2314e62 --- /dev/null +++ b/include/configs/crownbay.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_SYS_X86_START16 0xfffff800 +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_X86_RESET_VECTOR +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_COREBOOT_SERIAL +#define CONFIG_SMSC_LPC47M + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x80000000 + +#define CONFIG_PCI_PREF_BUS 0xc0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x20000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA} + +/* Video is not supported */ +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE + +#endif /* __CONFIG_H */

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - New patch to use consistent name XXX_ADDR for binary blobs

Makefile | 2 +- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/cpu/queensbay/Kconfig | 4 ++-- arch/x86/cpu/queensbay/fsp_support.c | 2 +- arch/x86/cpu/queensbay/tnc_car.S | 2 +- include/configs/chromebook_link.h | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/Makefile b/Makefile index d4e60e8..41137a5 100644 --- a/Makefile +++ b/Makefile @@ -958,7 +958,7 @@ IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin endif

ifneq ($(CONFIG_HAVE_MRC),) -IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin +IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin endif

ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index df2b990..b95e781 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -177,7 +177,7 @@ int sdram_initialise(struct pei_data *pei_data)

debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));

- data = (char *)CONFIG_X86_MRC_START; + data = (char *)CONFIG_X86_MRC_ADDR; if (data) { int rv; int (*func)(struct pei_data *); diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index 56fe85c..f6b5201 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -29,7 +29,7 @@ config FSP_FILE The filename of the file to use as Firmware Support Package binary in the board directory.

-config FSP_LOCATION +config FSP_ADDR hex "Firmware Support Package binary location" depends on HAVE_FSP default 0xfffc0000 @@ -65,7 +65,7 @@ config CMC_FILE The filename of the file to use as Chipset Micro Code state machine binary in the board directory.

-config CMC_LOCATION +config CMC_ADDR hex "Chipset Micro Code state machine binary location" depends on HAVE_CMC default 0xfffb0000 diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c index df3bbd0..f830eeb 100644 --- a/arch/x86/cpu/queensbay/fsp_support.c +++ b/arch/x86/cpu/queensbay/fsp_support.c @@ -64,7 +64,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void) volatile register u8 *fsp asm("eax");

/* Initalize the FSP base */ - fsp = (u8 *)CONFIG_FSP_LOCATION; + fsp = (u8 *)CONFIG_FSP_ADDR;

/* Check the FV signature, _FVH */ if (((struct fv_header_t *)fsp)->sign == 0x4856465F) { diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S index 2e9139e..5e09568 100644 --- a/arch/x86/cpu/queensbay/tnc_car.S +++ b/arch/x86/cpu/queensbay/tnc_car.S @@ -29,7 +29,7 @@ find_fsp_header_ret: mov %eax, %ebp

/* sanity test */ - cmp $CONFIG_FSP_LOCATION, %eax + cmp $CONFIG_FSP_ADDR, %eax jb die

/* calculate TempRamInitEntry address */ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 645b31c..c9d84e4 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -25,7 +25,7 @@

#define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 8 -#define CONFIG_X86_MRC_START 0xfffa0000 +#define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_CACHE_MRC_SIZE_KB 512

#define CONFIG_COREBOOT_SERIAL

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - Update ifdtool flags to indicate FSP and CMC files are in the board directory - Use consistent XXX_FILE name for binary blob file

Makefile | 10 +++++++++- include/configs/chromebook_link.h | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile index 41137a5..49c4a89 100644 --- a/Makefile +++ b/Makefile @@ -961,8 +961,16 @@ ifneq ($(CONFIG_HAVE_MRC),) IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin endif

+ifneq ($(CONFIG_HAVE_FSP),) +IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE) +endif + +ifneq ($(CONFIG_HAVE_CMC),) +IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE) +endif + ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) -IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) +IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE) endif

quiet_cmd_ifdtool = IFDTOOL $@ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index c9d84e4..b311f4c 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -39,7 +39,7 @@ {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}

-#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 #define CONFIG_VIDEO_X86

The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: - Add a commit message for the SPI support

Changes in v2: - Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h - Check return value of x86_cpu_init_f()

arch/x86/cpu/queensbay/tnc.c | 26 +++++++++++++++++++++++++- arch/x86/include/asm/arch-queensbay/tnc.h | 15 +++++++++++++++ include/configs/crownbay.h | 2 ++ 3 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 8b9815f..8637cdc 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -6,18 +6,42 @@

#include <common.h> #include <asm/io.h> +#include <asm/pci.h> #include <asm/post.h> +#include <asm/arch/tnc.h> #include <asm/arch/fsp/fsp_support.h> #include <asm/processor.h>

+static void unprotect_spi_flash(void) +{ + u32 bc; + + bc = pci_read_config32(PCH_LPC_DEV, 0xd8); + bc |= 0x1; /* unprotect the flash */ + pci_write_config32(PCH_LPC_DEV, 0xd8, bc); +} + int arch_cpu_init(void) { + struct pci_controller *hose; + int ret; + post_code(POST_CPU_INIT); #ifdef CONFIG_SYS_X86_TSC_TIMER timer_set_base(rdtsc()); #endif

- return x86_cpu_init_f(); + ret = x86_cpu_init_f(); + if (ret) + return ret; + + ret = pci_early_init_hose(&hose); + if (ret) + return ret; + + unprotect_spi_flash(); + + return 0; }

int print_cpuinfo(void) diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h new file mode 100644 index 0000000..67c5e05 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_TNC_H_ +#define _X86_ARCH_TNC_H_ + +#include <pci.h> + +/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) + +#endif /* _X86_ARCH_TNC_H_ */ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 2314e62..a051b11 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -45,6 +45,8 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}

+#define CONFIG_SPI_FLASH_SST + /* Video is not supported */ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE

We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

board/intel/crownbay/crownbay.c | 6 ++++++ include/configs/crownbay.h | 1 + 2 files changed, 7 insertions(+)

diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 54670d3..2a254ef 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/ibmpc.h> #include <asm/pnp_def.h> +#include <netdev.h> #include <smsc_lpc47m.h>

#define SERIAL_DEV PNP_DEV(0x2e, 4) @@ -24,3 +25,8 @@ void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index a051b11..09a52ab 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -37,6 +37,7 @@

#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP +#define CONFIG_E1000

#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \

There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - Use ARRAY_SIZE(mmc_supported) instead of 2 - Check return value of add_sdhci()

arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/topcliff.c | 47 +++++++++++++++++++++++++++++++++++++++ include/configs/crownbay.h | 6 +++++ 3 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/queensbay/topcliff.c

diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index ace04ca..2c2ec01 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y += tnc_car.o tnc_dram.o tnc.o +obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o obj-y += fsp_configs.o fsp_support.o obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c new file mode 100644 index 0000000..b01422a --- /dev/null +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <pci.h> +#include <pci_ids.h> +#include <sdhci.h> + +static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, + { } +}; + +int cpu_mmc_init(bd_t *bis) +{ + struct sdhci_host *mmc_host; + pci_dev_t devbusfn; + u32 iobase; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) { + devbusfn = pci_find_devices(mmc_supported, i); + if (devbusfn == -1) + return -ENODEV; + + mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + if (!mmc_host) + return -ENOMEM; + + mmc_host->name = "Topcliff SDHCI"; + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + mmc_host->ioaddr = (void *)iobase; + mmc_host->quirks = 0; + ret = add_sdhci(mmc_host, 0, 0); + if (ret) + return ret; + } + + return 0; +} diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 09a52ab..b9db6b7 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -48,6 +48,12 @@

#define CONFIG_SPI_FLASH_SST

+#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + /* Video is not supported */ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - New patch to rename coreboot-serial to x86-serial

arch/x86/dts/coreboot.dtsi | 2 +- drivers/serial/Makefile | 2 +- drivers/serial/{serial_coreboot.c => serial_x86.c} | 12 ++++++------ include/configs/chromebook_link.h | 2 +- include/configs/coreboot.h | 2 +- include/configs/crownbay.h | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) rename drivers/serial/{serial_coreboot.c => serial_x86.c} (67%)

diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi index c8dc4ce..65a93ac 100644 --- a/arch/x86/dts/coreboot.dtsi +++ b/arch/x86/dts/coreboot.dtsi @@ -6,7 +6,7 @@ };

serial { - compatible = "coreboot-uart"; + compatible = "x86-uart"; reg = <0x3f8 0x10>; reg-shift = <0>; io-mapped = <1>; diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 8c84942..4cc00cd 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o -obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o +obj-$(CONFIG_X86_SERIAL) += serial_x86.o

ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_x86.c similarity index 67% rename from drivers/serial/serial_coreboot.c rename to drivers/serial/serial_x86.c index 5c6a76c..e81e035 100644 --- a/drivers/serial/serial_coreboot.c +++ b/drivers/serial/serial_x86.c @@ -9,12 +9,12 @@ #include <ns16550.h> #include <serial.h>

-static const struct udevice_id coreboot_serial_ids[] = { - { .compatible = "coreboot-uart" }, +static const struct udevice_id x86_serial_ids[] = { + { .compatible = "x86-uart" }, { } };

-static int coreboot_serial_ofdata_to_platdata(struct udevice *dev) +static int x86_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev_get_platdata(dev); int ret; @@ -27,10 +27,10 @@ static int coreboot_serial_ofdata_to_platdata(struct udevice *dev) return 0; } U_BOOT_DRIVER(serial_ns16550) = { - .name = "serial_coreboot", + .name = "serial_x86", .id = UCLASS_SERIAL, - .of_match = coreboot_serial_ids, - .ofdata_to_platdata = coreboot_serial_ofdata_to_platdata, + .of_match = x86_serial_ids, + .ofdata_to_platdata = x86_serial_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), .priv_auto_alloc_size = sizeof(struct NS16550), .probe = ns16550_serial_probe, diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index b311f4c..8930210 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -28,7 +28,7 @@ #define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_CACHE_MRC_SIZE_KB 512

-#define CONFIG_COREBOOT_SERIAL +#define CONFIG_X86_SERIAL

#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 2581380..990a2d1 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -49,7 +49,7 @@ {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}

-#define CONFIG_COREBOOT_SERIAL +#define CONFIG_X86_SERIAL

#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial,cbmem\0" \ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index b9db6b7..eadb339 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -20,7 +20,7 @@ #define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 1

-#define CONFIG_COREBOOT_SERIAL +#define CONFIG_X86_SERIAL #define CONFIG_SMSC_LPC47M

#define CONFIG_PCI_MEM_BUS 0x40000000

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v4: - Minor update per review comments from Pavel Machek

Changes in v3: None Changes in v2: - Remove the 'make menuconfig' in the crownbay build instructions - Indicate all the binary blobs should be put in the board directory

doc/README.x86 | 126 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 doc/README.x86

diff --git a/doc/README.x86 b/doc/README.x86 new file mode 100644 index 0000000..c12dfe5 --- /dev/null +++ b/doc/README.x86 @@ -0,0 +1,126 @@ +# +# Copyright (C) 2014, Simon Glass sjg@chromium.org +# Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +============= + +This document describes the information about U-Boot running on x86 targets, +including supported boards, build instructions, todo list, etc. + +Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimal adjustments +on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and Intel +Crown Bay board support running U-Boot 'bare metal'. + +As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux +kernel as part of a FIT image. It also supports a compressed zImage. + +Build Instructions +------------------ +Building U-Boot as a coreboot payload is just like building U-Boot for targets +on other architectures, like below: + +$ make coreboot-x86_defconfig +$ make all + +Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a +little bit tricky, as generally it requires several binary blobs which are not +shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is +not turned on by default in the U-Boot source tree. Firstly, you need turn it +on by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions: + +First, you need the following binary blobs: + +* descriptor.bin - Intel flash descriptor +* me.bin - Intel Management Engine +* mrc.bin - Memory Reference Code, which sets up SDRAM +* video ROM - sets up the display + +You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin. +As for the video ROM, you can get it here [2]. +Make sure all these binary blobs are put in the board directory. + +Now you can build U-Boot and obtain u-boot.rom: + +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide, including initialization of the CPU, +memory controller, chipset and certain bus interfaces. + +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Rename the first one to fsp.bin and second one to cmc.bin and put them in the +board directory. + +Now you can build U-Boot and obtaim u-boot.rom + +$ make crownbay_defconfig +$ make all + +CPU Microcode +------------- +Modern CPU usually requires a special bit stream called microcode [5] to be +loaded on the processor after power up in order to function properly. U-Boot +has already integrated these as hex dumps in the source tree. + +Driver Model +------------ +x86 has been converted to use driver model for serial and GPIO. + +Device Tree +----------- +x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to +be turned on. Not every device on the board is configured via devie tree, but +more and more devices will be added as time goes by. Check out the directory +arch/x86/dts/ for these device tree source files. + +TODO List +--------- +- MTRR support (for performance) +- Audio +- Chrome OS verified boot +- SMI and ACPI support, to provide platform info and facilities to Linux + +References +---------- +[1] http://www.coreboot.org +[2] http://www.coreboot.org/~stepan/pci8086,0166.rom +[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-plat... +[4] http://www.intel.com/fsp +[5] http://en.wikipedia.org/wiki/Microcode

This is the follow-on patch to clean up the FSP support codes:

- Remove the _t suffix on the structures defines - Use __packed for structure defines - Use U-Boot's assert() - Use standard bool true/false - Remove read_unaligned64() - Use memcmp() in the compare_guid() - Remove the cast in the memset() call - Replace some magic numbers with macros - Use panic() when no valid FSP image header is found - Change some FSP utility routines to use an fsp_ prefix - Add comment blocks for asm_continuation and fsp_init_done - Remove some casts in find_fsp_header() - Change HOB access macros to static inline routines - Add comments to mention find_fsp_header() may be called in a stackless environment - Add comments to mention init(&params) in fsp_init() cannot be removed

Signed-off-by: Bin Meng bmeng.cn@gmail.com

---

Changes in v4: - Use __packed for structure defines - Fix some typos and print FSP full name in cmd_hob.c

Changes in v3: None Changes in v2: - Remove some casts in find_fsp_header() - Change HOB access macros to static inline routines

arch/x86/cpu/queensbay/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/fsp_support.c | 253 ++++++++++----------- arch/x86/cpu/queensbay/tnc_dram.c | 18 +- arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h | 18 +- arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h | 28 +-- arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h | 14 +- arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h | 112 +++++---- .../asm/arch-queensbay/fsp/fsp_infoheader.h | 6 +- .../include/asm/arch-queensbay/fsp/fsp_platform.h | 8 +- .../include/asm/arch-queensbay/fsp/fsp_support.h | 63 ++--- .../x86/include/asm/arch-queensbay/fsp/fsp_types.h | 17 +- arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 8 +- arch/x86/lib/cmd_hob.c | 22 +- 13 files changed, 279 insertions(+), 290 deletions(-)

diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index aef18fc..af28e45 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -8,7 +8,7 @@ #include <common.h> #include <asm/arch/fsp/fsp_support.h>

-void update_fsp_upd(struct upd_region_t *fsp_upd) +void update_fsp_upd(struct upd_region *fsp_upd) { /* Override any UPD setting if required */

diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c index f830eeb..ef1916b 100644 --- a/arch/x86/cpu/queensbay/fsp_support.c +++ b/arch/x86/cpu/queensbay/fsp_support.c @@ -10,67 +10,48 @@ #include <asm/post.h>

/** - * Reads a 64-bit value from memory that may be unaligned. - * - * This function returns the 64-bit value pointed to by buf. The function - * guarantees that the read operation does not produce an alignment fault. - * - * If the buf is NULL, then ASSERT(). - * - * @buf: Pointer to a 64-bit value that may be unaligned. - * - * @return: The 64-bit value read from buf. - */ -static u64 read_unaligned64(const u64 *buf) -{ - ASSERT(buf != NULL); - - return *buf; -} - -/** * Compares two GUIDs * - * If the GUIDs are identical then TRUE is returned. - * If there are any bit differences in the two GUIDs, then FALSE is returned. - * - * If guid1 is NULL, then ASSERT(). - * If guid2 is NULL, then ASSERT(). + * If the GUIDs are identical then true is returned. + * If there are any bit differences in the two GUIDs, then false is returned. * * @guid1: A pointer to a 128 bit GUID. * @guid2: A pointer to a 128 bit GUID. * - * @retval TRUE: guid1 and guid2 are identical. - * @retval FALSE: guid1 and guid2 are not identical. + * @retval true: guid1 and guid2 are identical. + * @retval false: guid1 and guid2 are not identical. */ -static unsigned char compare_guid(const struct efi_guid_t *guid1, - const struct efi_guid_t *guid2) +static bool compare_guid(const struct efi_guid *guid1, + const struct efi_guid *guid2) { - u64 guid1_low; - u64 guid2_low; - u64 guid1_high; - u64 guid2_high; - - guid1_low = read_unaligned64((const u64 *)guid1); - guid2_low = read_unaligned64((const u64 *)guid2); - guid1_high = read_unaligned64((const u64 *)guid1 + 1); - guid2_high = read_unaligned64((const u64 *)guid2 + 1); - - return (unsigned char)(guid1_low == guid2_low && guid1_high == guid2_high); + if (memcmp(guid1, guid2, sizeof(struct efi_guid)) == 0) + return true; + else + return false; }

u32 __attribute__((optimize("O0"))) find_fsp_header(void) { + /* + * This function may be called before the a stack is established, + * so special care must be taken. First, it cannot declare any local + * variable using stack. Only register variable can be used here. + * Secondly, some compiler version will add prolog or epilog code + * for the C function. If so the function call may not work before + * stack is ready. + * + * GCC 4.8.1 has been verified to be working for the following codes. + */ volatile register u8 *fsp asm("eax");

/* Initalize the FSP base */ fsp = (u8 *)CONFIG_FSP_ADDR;

/* Check the FV signature, _FVH */ - if (((struct fv_header_t *)fsp)->sign == 0x4856465F) { + if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) { /* Go to the end of the FV header and align the address */ - fsp += ((struct fv_header_t *)fsp)->ext_hdr_off; - fsp += ((struct fv_ext_header_t *)fsp)->ext_hdr_size; + fsp += ((struct fv_header *)fsp)->ext_hdr_off; + fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size; fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8); } else { fsp = 0; @@ -78,20 +59,27 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)

/* Check the FFS GUID */ if (fsp && - (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[0] == 0x912740BE) && - (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[1] == 0x47342284) && - (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[2] == 0xB08471B9) && - (((u32 *)&(((struct ffs_file_header_t *)fsp)->name))[3] == 0x0C3F3527)) { + ((struct ffs_file_header *)fsp)->name.data1 == FSP_GUID_DATA1 && + ((struct ffs_file_header *)fsp)->name.data2 == FSP_GUID_DATA2 && + ((struct ffs_file_header *)fsp)->name.data3 == FSP_GUID_DATA3 && + ((struct ffs_file_header *)fsp)->name.data4[0] == FSP_GUID_DATA4_0 && + ((struct ffs_file_header *)fsp)->name.data4[1] == FSP_GUID_DATA4_1 && + ((struct ffs_file_header *)fsp)->name.data4[2] == FSP_GUID_DATA4_2 && + ((struct ffs_file_header *)fsp)->name.data4[3] == FSP_GUID_DATA4_3 && + ((struct ffs_file_header *)fsp)->name.data4[4] == FSP_GUID_DATA4_4 && + ((struct ffs_file_header *)fsp)->name.data4[5] == FSP_GUID_DATA4_5 && + ((struct ffs_file_header *)fsp)->name.data4[6] == FSP_GUID_DATA4_6 && + ((struct ffs_file_header *)fsp)->name.data4[7] == FSP_GUID_DATA4_7) { /* Add the FFS header size to find the raw section header */ - fsp += sizeof(struct ffs_file_header_t); + fsp += sizeof(struct ffs_file_header); } else { fsp = 0; }

if (fsp && - ((struct raw_section_t *)fsp)->type == EFI_SECTION_RAW) { + ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) { /* Add the raw section header size to find the FSP header */ - fsp += sizeof(struct raw_section_t); + fsp += sizeof(struct raw_section); } else { fsp = 0; } @@ -99,7 +87,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void) return (u32)fsp; }

-void fsp_continue(struct shared_data_t *shared_data, u32 status, void *hob_list) +void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list) { u32 stack_len; u32 stack_base; @@ -107,18 +95,18 @@ void fsp_continue(struct shared_data_t *shared_data, u32 status, void *hob_list)

post_code(POST_MRC);

- ASSERT(status == 0); + assert(status == 0);

/* Get the migrated stack in normal memory */ - stack_base = (u32)get_bootloader_tmp_mem(hob_list, &stack_len); - ASSERT(stack_base != 0); + stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len); + assert(stack_base != 0); stack_top = stack_base + stack_len - sizeof(u32);

/* * Old stack base is stored at the very end of the stack top, * use it to calculate the migrated shared data base */ - shared_data = (struct shared_data_t *)(stack_base + + shared_data = (struct shared_data *)(stack_base + ((u32)shared_data - *(u32 *)stack_top));

/* The boot loader main function entry */ @@ -127,50 +115,50 @@ void fsp_continue(struct shared_data_t *shared_data, u32 status, void *hob_list)

void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) { - struct shared_data_t shared_data; + struct shared_data shared_data; fsp_init_f init; - struct fsp_init_params_t params; - struct fspinit_rtbuf_t rt_buf; - struct vpd_region_t *fsp_vpd; - struct fsp_header_t *fsp_hdr; - struct fsp_init_params_t *params_ptr; - struct upd_region_t *fsp_upd; - - fsp_hdr = (struct fsp_header_t *)find_fsp_header(); + struct fsp_init_params params; + struct fspinit_rtbuf rt_buf; + struct vpd_region *fsp_vpd; + struct fsp_header *fsp_hdr; + struct fsp_init_params *params_ptr; + struct upd_region *fsp_upd; + + fsp_hdr = (struct fsp_header *)find_fsp_header(); if (fsp_hdr == NULL) { /* No valid FSP info header was found */ - ASSERT(FALSE); + panic("Invalid FSP header"); }

- fsp_upd = (struct upd_region_t *)&shared_data.fsp_upd; - memset((void *)&rt_buf, 0, sizeof(struct fspinit_rtbuf_t)); + fsp_upd = (struct upd_region *)&shared_data.fsp_upd; + memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));

/* Reserve a gap in stack top */ rt_buf.common.stack_top = (u32 *)stack_top - 32; rt_buf.common.boot_mode = boot_mode; - rt_buf.common.upd_data = (struct upd_region_t *)fsp_upd; + rt_buf.common.upd_data = (struct upd_region *)fsp_upd;

/* Get VPD region start */ - fsp_vpd = (struct vpd_region_t *)(fsp_hdr->img_base + + fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base + fsp_hdr->cfg_region_off);

/* Verifify the VPD data region is valid */ - ASSERT((fsp_vpd->img_rev == VPD_IMAGE_REV) && + assert((fsp_vpd->img_rev == VPD_IMAGE_REV) && (fsp_vpd->sign == VPD_IMAGE_ID));

/* Copy default data from Flash */ memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset), - sizeof(struct upd_region_t)); + sizeof(struct upd_region));

/* Verifify the UPD data region is valid */ - ASSERT(fsp_upd->terminator == 0x55AA); + assert(fsp_upd->terminator == UPD_TERMINATOR);

/* Override any UPD setting if required */ update_fsp_upd(fsp_upd);

- memset((void *)&params, 0, sizeof(struct fsp_init_params_t)); + memset(&params, 0, sizeof(struct fsp_init_params)); params.nvs_buf = nvs_buf; - params.rt_buf = (struct fspinit_rtbuf_t *)&rt_buf; + params.rt_buf = (struct fspinit_rtbuf *)&rt_buf; params.continuation = (fsp_continuation_f)asm_continuation;

init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); @@ -199,32 +187,28 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)

/* * Should never get here. - * Control will continue from romstage_main_continue_asm. + * Control will continue from fsp_continue. * This line below is to prevent the compiler from optimizing * structure intialization. + * + * DO NOT REMOVE! */ init(&params); - - /* - * Should never return. - * Control will continue from ContinuationFunc - */ - ASSERT(FALSE); }

-u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase) +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) { fsp_notify_f notify; - struct fsp_notify_params_t params; - struct fsp_notify_params_t *params_ptr; + struct fsp_notify_params params; + struct fsp_notify_params *params_ptr; u32 status;

if (!fsp_hdr) - fsp_hdr = (struct fsp_header_t *)find_fsp_header(); + fsp_hdr = (struct fsp_header *)find_fsp_header();

if (fsp_hdr == NULL) { /* No valid FSP info header */ - ASSERT(FALSE); + panic("Invalid FSP header"); }

notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify); @@ -245,9 +229,9 @@ u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase) return status; }

-u32 get_usable_lowmem_top(const void *hob_list) +u32 fsp_get_usable_lowmem_top(const void *hob_list) { - union hob_pointers_t hob; + union hob_pointers hob; phys_addr_t phys_start; u32 top;

@@ -255,26 +239,26 @@ u32 get_usable_lowmem_top(const void *hob_list) hob.raw = (void *)hob_list;

/* * Collect memory ranges */ - top = 0x100000; - while (!END_OF_HOB(hob)) { - if (hob.hdr->type == HOB_TYPE_RES_DESC) { + top = FSP_LOWMEM_BASE; + while (!end_of_hob(hob)) { + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) { if (hob.res_desc->type == RES_SYS_MEM) { phys_start = hob.res_desc->phys_start; /* Need memory above 1MB to be collected here */ - if (phys_start >= 0x100000 && - phys_start < (phys_addr_t)0x100000000) + if (phys_start >= FSP_LOWMEM_BASE && + phys_start < (phys_addr_t)FSP_HIGHMEM_BASE) top += (u32)(hob.res_desc->len); } } - hob.raw = GET_NEXT_HOB(hob); + hob.raw = get_next_hob(hob); }

return top; }

-u64 get_usable_highmem_top(const void *hob_list) +u64 fsp_get_usable_highmem_top(const void *hob_list) { - union hob_pointers_t hob; + union hob_pointers hob; phys_addr_t phys_start; u64 top;

@@ -282,33 +266,33 @@ u64 get_usable_highmem_top(const void *hob_list) hob.raw = (void *)hob_list;

/* Collect memory ranges */ - top = 0x100000000; - while (!END_OF_HOB(hob)) { - if (hob.hdr->type == HOB_TYPE_RES_DESC) { + top = FSP_HIGHMEM_BASE; + while (!end_of_hob(hob)) { + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) { if (hob.res_desc->type == RES_SYS_MEM) { phys_start = hob.res_desc->phys_start; /* Need memory above 1MB to be collected here */ - if (phys_start >= (phys_addr_t)0x100000000) + if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE) top += (u32)(hob.res_desc->len); } } - hob.raw = GET_NEXT_HOB(hob); + hob.raw = get_next_hob(hob); }

return top; }

-u64 get_fsp_reserved_mem_from_guid(const void *hob_list, u64 *len, - struct efi_guid_t *guid) +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len, + struct efi_guid *guid) { - union hob_pointers_t hob; + union hob_pointers hob;

/* Get the HOB list for processing */ hob.raw = (void *)hob_list;

/* Collect memory ranges */ - while (!END_OF_HOB(hob)) { - if (hob.hdr->type == HOB_TYPE_RES_DESC) { + while (!end_of_hob(hob)) { + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) { if (hob.res_desc->type == RES_MEM_RESERVED) { if (compare_guid(&hob.res_desc->owner, guid)) { if (len) @@ -318,99 +302,100 @@ u64 get_fsp_reserved_mem_from_guid(const void *hob_list, u64 *len, } } } - hob.raw = GET_NEXT_HOB(hob); + hob.raw = get_next_hob(hob); }

return 0; }

-u32 get_fsp_reserved_mem(const void *hob_list, u32 *len) +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len) { - const struct efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; u64 length; u32 base;

- base = (u32)get_fsp_reserved_mem_from_guid(hob_list, - &length, (struct efi_guid_t *)&guid); + base = (u32)fsp_get_reserved_mem_from_guid(hob_list, + &length, (struct efi_guid *)&guid); if ((len != 0) && (base != 0)) *len = (u32)length;

return base; }

-u32 get_tseg_reserved_mem(const void *hob_list, u32 *len) +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len) { - const struct efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; + const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; u64 length; u32 base;

- base = (u32)get_fsp_reserved_mem_from_guid(hob_list, - &length, (struct efi_guid_t *)&guid); + base = (u32)fsp_get_reserved_mem_from_guid(hob_list, + &length, (struct efi_guid *)&guid); if ((len != 0) && (base != 0)) *len = (u32)length;

return base; }

-void *get_next_hob(u16 type, const void *hob_list) +void *fsp_get_next_hob(u16 type, const void *hob_list) { - union hob_pointers_t hob; + union hob_pointers hob;

- ASSERT(hob_list != NULL); + assert(hob_list != NULL);

hob.raw = (u8 *)hob_list;

/* Parse the HOB list until end of list or matching type is found */ - while (!END_OF_HOB(hob)) { - if (hob.hdr->type == type) + while (!end_of_hob(hob)) { + if (get_hob_type(hob) == type) return hob.raw;

- hob.raw = GET_NEXT_HOB(hob); + hob.raw = get_next_hob(hob); }

return NULL; }

-void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list) +void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list) { - union hob_pointers_t hob; + union hob_pointers hob;

hob.raw = (u8 *)hob_list; - while ((hob.raw = get_next_hob(HOB_TYPE_GUID_EXT, + while ((hob.raw = fsp_get_next_hob(HOB_TYPE_GUID_EXT, hob.raw)) != NULL) { if (compare_guid(guid, &hob.guid->name)) break; - hob.raw = GET_NEXT_HOB(hob); + hob.raw = get_next_hob(hob); }

return hob.raw; }

-void *get_guid_hob_data(const void *hob_list, u32 *len, struct efi_guid_t *guid) +void *fsp_get_guid_hob_data(const void *hob_list, u32 *len, + struct efi_guid *guid) { u8 *guid_hob;

- guid_hob = get_next_guid_hob(guid, hob_list); + guid_hob = fsp_get_next_guid_hob(guid, hob_list); if (guid_hob == NULL) { return NULL; } else { if (len) - *len = GET_GUID_HOB_DATA_SIZE(guid_hob); + *len = get_guid_hob_data_size(guid_hob);

- return GET_GUID_HOB_DATA(guid_hob); + return get_guid_hob_data(guid_hob); } }

-void *get_fsp_nvs_data(const void *hob_list, u32 *len) +void *fsp_get_nvs_data(const void *hob_list, u32 *len) { - const struct efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + const struct efi_guid guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;

- return get_guid_hob_data(hob_list, len, (struct efi_guid_t *)&guid); + return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid); }

-void *get_bootloader_tmp_mem(const void *hob_list, u32 *len) +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) { - const struct efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID; + const struct efi_guid guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;

- return get_guid_hob_data(hob_list, len, (struct efi_guid_t *)&guid); + return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid); } diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c index dbc1710..8e97c9b 100644 --- a/arch/x86/cpu/queensbay/tnc_dram.c +++ b/arch/x86/cpu/queensbay/tnc_dram.c @@ -14,17 +14,17 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { phys_size_t ram_size = 0; - union hob_pointers_t hob; + union hob_pointers hob;

hob.raw = gd->arch.hob_list; - while (!END_OF_HOB(hob)) { - if (hob.hdr->type == HOB_TYPE_RES_DESC) { + while (!end_of_hob(hob)) { + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) { if (hob.res_desc->type == RES_SYS_MEM || hob.res_desc->type == RES_MEM_RESERVED) { ram_size += hob.res_desc->len; } } - hob.raw = GET_NEXT_HOB(hob); + hob.raw = get_next_hob(hob); }

gd->ram_size = ram_size; @@ -49,19 +49,19 @@ void dram_init_banksize(void) */ ulong board_get_usable_ram_top(ulong total_size) { - return get_usable_lowmem_top(gd->arch.hob_list); + return fsp_get_usable_lowmem_top(gd->arch.hob_list); }

unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) { unsigned num_entries = 0;

- union hob_pointers_t hob; + union hob_pointers hob;

hob.raw = gd->arch.hob_list;

- while (!END_OF_HOB(hob)) { - if (hob.hdr->type == HOB_TYPE_RES_DESC) { + while (!end_of_hob(hob)) { + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) { entries[num_entries].addr = hob.res_desc->phys_start; entries[num_entries].size = hob.res_desc->len;

@@ -70,7 +70,7 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) else if (hob.res_desc->type == RES_MEM_RESERVED) entries[num_entries].type = E820_RESERVED; } - hob.raw = GET_NEXT_HOB(hob); + hob.raw = get_next_hob(hob); num_entries++; }

diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h index 25b938f..a9d7156 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h @@ -14,9 +14,7 @@ */ typedef void (*fsp_continuation_f)(u32 status, void *hob_list);

-#pragma pack(1) - -struct fsp_init_params_t { +struct fsp_init_params { /* Non-volatile storage buffer pointer */ void *nvs_buf; /* Runtime buffer pointer */ @@ -25,7 +23,7 @@ struct fsp_init_params_t { fsp_continuation_f continuation; };

-struct common_buf_t { +struct common_buf { /* * Stack top pointer used by the bootloader. The new stack frame will be * set up at this location after FspInit API call. @@ -36,24 +34,22 @@ struct common_buf_t { u32 reserved[7]; /* Reserved */ };

-enum fsp_phase_t { +enum fsp_phase { /* Notification code for post PCI enuermation */ INIT_PHASE_PCI = 0x20, /* Notification code before transfering control to the payload */ INIT_PHASE_BOOT = 0x40 };

-struct fsp_notify_params_t { +struct fsp_notify_params { /* Notification phase used for NotifyPhase API */ - enum fsp_phase_t phase; + enum fsp_phase phase; };

-#pragma pack() - /* FspInit API function prototype */ -typedef u32 (*fsp_init_f)(struct fsp_init_params_t *param); +typedef u32 (*fsp_init_f)(struct fsp_init_params *params);

/* FspNotify API function prototype */ -typedef u32 (*fsp_notify_f)(struct fsp_notify_params_t *param); +typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);

#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h index 1f73680..eaec2b4 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h @@ -8,10 +8,8 @@ #ifndef __FSP_FFS_H__ #define __FSP_FFS_H__

-#pragma pack(1) - /* Used to verify the integrity of the file */ -union ffs_integrity_t { +union __packed ffs_integrity { struct { /* * The IntegrityCheck.checksum.header field is an 8-bit @@ -43,14 +41,14 @@ union ffs_integrity_t { * Each file begins with the header that describe the * contents and state of the files. */ -struct ffs_file_header_t { +struct __packed ffs_file_header { /* * This GUID is the file name. * It is used to uniquely identify the file. */ - struct efi_guid_t name; + struct efi_guid name; /* Used to verify the integrity of the file */ - union ffs_integrity_t integrity; + union ffs_integrity integrity; /* Identifies the type of file */ u8 type; /* Declares various file attribute bits */ @@ -64,16 +62,16 @@ struct ffs_file_header_t { u8 state; };

-struct ffs_file_header2_t { +struct __packed ffs_file_header2 { /* * This GUID is the file name. It is used to uniquely identify the file. * There may be only one instance of a file with the file name GUID of * Name in any given firmware volume, except if the file type is * EFI_FV_FILE_TYPE_FFS_PAD. */ - struct efi_guid_t name; + struct efi_guid name; /* Used to verify the integrity of the file */ - union ffs_integrity_t integrity; + union ffs_integrity integrity; /* Identifies the type of file */ u8 type; /* Declares various file attribute bits */ @@ -81,9 +79,9 @@ struct ffs_file_header2_t { /* * The length of the file in bytes, including the FFS header. * The length of the file data is either - * (size - sizeof(struct ffs_file_header_t)). This calculation means a + * (size - sizeof(struct ffs_file_header)). This calculation means a * zero-length file has a size of 24 bytes, which is - * sizeof(struct ffs_file_header_t). Size is not required to be a + * sizeof(struct ffs_file_header). Size is not required to be a * multiple of 8 bytes. Given a file F, the next file header is located * at the next 8-byte aligned firmware volume offset following the last * byte of the file F. @@ -98,7 +96,7 @@ struct ffs_file_header2_t { * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists * and size must be set to zero. * If FFS_ATTRIB_LARGE_FILE is not set then - * struct ffs_file_header_t is used. + * struct ffs_file_header is used. */ u32 ext_size; }; @@ -129,7 +127,7 @@ struct ffs_file_header2_t { #define EFI_SECTION_SMM_DEPEX 0x1C

/* Common section header */ -struct raw_section_t { +struct __packed raw_section { /* * A 24-bit unsigned integer that contains the total size of * the section in bytes, including the EFI_COMMON_SECTION_HEADER. @@ -138,7 +136,7 @@ struct raw_section_t { u8 type; };

-struct raw_section2_t { +struct __packed raw_section2 { /* * A 24-bit unsigned integer that contains the total size of * the section in bytes, including the EFI_COMMON_SECTION_HEADER. @@ -153,6 +151,4 @@ struct raw_section2_t { u32 ext_size; };

-#pragma pack() - #endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h index 01300db..a024451 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h @@ -63,7 +63,7 @@ #define EFI_FVB2_ALIGNMENT_1G 0x001E0000 #define EFI_FVB2_ALIGNMENT_2G 0x001F0000

-struct fv_blkmap_entry_t { +struct fv_blkmap_entry { /* The number of sequential blocks which are of the same size */ u32 num_blocks; /* The size of the blocks */ @@ -71,7 +71,7 @@ struct fv_blkmap_entry_t { };

/* Describes the features and layout of the firmware volume */ -struct fv_header_t { +struct fv_header { /* * The first 16 bytes are reserved to allow for the reset vector of * processors whose reset vector is at address 0. @@ -81,7 +81,7 @@ struct fv_header_t { * Declares the file system with which the firmware volume * is formatted. */ - struct efi_guid_t fs_guid; + struct efi_guid fs_guid; /* * Length in bytes of the complete firmware volume, including * the header. @@ -118,18 +118,18 @@ struct fv_header_t { * An array of run-length encoded FvBlockMapEntry structures. * The array is terminated with an entry of {0,0}. */ - struct fv_blkmap_entry_t block_map[1]; + struct fv_blkmap_entry block_map[1]; };

-#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H') +#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')

/* Firmware Volume Header Revision definition */ #define EFI_FVH_REVISION 0x02

/* Extension header pointed by ExtHeaderOffset of volume header */ -struct fv_ext_header_t { +struct fv_ext_header { /* firmware volume name */ - struct efi_guid_t fv_name; + struct efi_guid fv_name; /* Size of the rest of the extension header including this structure */ u32 ext_hdr_size; }; diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h index 44c0f90..380b64e 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h @@ -19,14 +19,14 @@ * Describes the format and size of the data inside the HOB. * All HOBs must contain this generic HOB header. */ -struct hob_header_t { +struct hob_header { u16 type; /* HOB type */ u16 len; /* HOB length */ u32 reserved; /* always zero */ };

/* Enumeration of memory types introduced in UEFI */ -enum efi_mem_type_t { +enum efi_mem_type { EFI_RESERVED_MEMORY_TYPE, /* * The code portions of a loaded application. @@ -87,16 +87,16 @@ enum efi_mem_type_t { * exist outside the HOB list. This HOB type describes how memory is used, * not the physical attributes of memory. */ -struct hob_mem_alloc_t { - struct hob_header_t hdr; +struct hob_mem_alloc { + struct hob_header hdr; /* * A GUID that defines the memory allocation region's type and purpose, * as well as other fields within the memory allocation HOB. This GUID * is used to define the additional data within the HOB that may be - * present for the memory allocation HOB. Type efi_guid_t is defined in + * present for the memory allocation HOB. Type efi_guid is defined in * InstallProtocolInterface() in the UEFI 2.0 specification. */ - struct efi_guid_t name; + struct efi_guid name; /* * The base address of memory allocated by this HOB. * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0 @@ -111,7 +111,7 @@ struct hob_mem_alloc_t { * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0 * specification. */ - enum efi_mem_type_t mem_type; + enum efi_mem_type mem_type; /* padding */ u8 reserved[4]; }; @@ -155,14 +155,14 @@ struct hob_mem_alloc_t { * Describes the resource properties of all fixed, nonrelocatable resource * ranges found on the processor host bus during the HOB producer phase. */ -struct hob_res_desc_t { - struct hob_header_t hdr; +struct hob_res_desc { + struct hob_header hdr; /* * A GUID representing the owner of the resource. This GUID is * used by HOB consumer phase components to correlate device * ownership of a resource. */ - struct efi_guid_t owner; + struct efi_guid owner; u32 type; u32 attr; /* The physical start address of the resource region */ @@ -175,24 +175,24 @@ struct hob_res_desc_t { * Allows writers of executable content in the HOB producer phase to * maintain and manage HOBs with specific GUID. */ -struct hob_guid_t { - struct hob_header_t hdr; +struct hob_guid { + struct hob_header hdr; /* A GUID that defines the contents of this HOB */ - struct efi_guid_t name; + struct efi_guid name; /* GUID specific data goes here */ };

/* Union of all the possible HOB Types */ -union hob_pointers_t { - struct hob_header_t *hdr; - struct hob_mem_alloc_t *mem_alloc; - struct hob_res_desc_t *res_desc; - struct hob_guid_t *guid; +union hob_pointers { + struct hob_header *hdr; + struct hob_mem_alloc *mem_alloc; + struct hob_res_desc *res_desc; + struct hob_guid *guid; u8 *raw; };

/** - * Returns the type of a HOB. + * get_hob_type() - return the type of a HOB * * This macro returns the type field from the HOB header for the * HOB specified by hob. @@ -201,11 +201,13 @@ union hob_pointers_t { * * @return: HOB type. */ -#define GET_HOB_TYPE(hob) \ - ((*(struct hob_header_t **)&(hob))->type) +static inline u16 get_hob_type(union hob_pointers hob) +{ + return hob.hdr->type; +}

/** - * Returns the length, in bytes, of a HOB. + * get_hob_length() - return the length, in bytes, of a HOB * * This macro returns the len field from the HOB header for the * HOB specified by hob. @@ -214,11 +216,13 @@ union hob_pointers_t { * * @return: HOB length. */ -#define GET_HOB_LENGTH(hob) \ - ((*(struct hob_header_t **)&(hob))->len) +static inline u16 get_hob_length(union hob_pointers hob) +{ + return hob.hdr->len; +}

/** - * Returns a pointer to the next HOB in the HOB list. + * get_next_hob() - return a pointer to the next HOB in the HOB list * * This macro returns a pointer to HOB that follows the HOB specified by hob * in the HOB List. @@ -227,25 +231,31 @@ union hob_pointers_t { * * @return: A pointer to the next HOB in the HOB list. */ -#define GET_NEXT_HOB(hob) \ - (void *)(*(u8 **)&(hob) + GET_HOB_LENGTH(hob)) +static inline void *get_next_hob(union hob_pointers hob) +{ + return (void *)(*(u8 **)&(hob) + get_hob_length(hob)); +}

/** - * Determines if a HOB is the last HOB in the HOB list. + * end_of_hob() - determine if a HOB is the last HOB in the HOB list * * This macro determine if the HOB specified by hob is the last HOB in the - * HOB list. If hob is last HOB in the HOB list, then TRUE is returned. - * Otherwise, FALSE is returned. + * HOB list. If hob is last HOB in the HOB list, then true is returned. + * Otherwise, false is returned. * * @hob: A pointer to a HOB. * - * @retval TRUE: The HOB specified by hob is the last HOB in the HOB list. - * @retval FALSE: The HOB specified by hob is not the last HOB in the HOB list. + * @retval true: The HOB specified by hob is the last HOB in the HOB list. + * @retval false: The HOB specified by hob is not the last HOB in the HOB list. */ -#define END_OF_HOB(hob) (GET_HOB_TYPE(hob) == (u16)HOB_TYPE_EOH) +static inline bool end_of_hob(union hob_pointers hob) +{ + return get_hob_type(hob) == HOB_TYPE_EOH; +}

/** - * Returns a pointer to data buffer from a HOB of type HOB_TYPE_GUID_EXT. + * get_guid_hob_data() - return a pointer to data buffer from a HOB of + * type HOB_TYPE_GUID_EXT * * This macro returns a pointer to the data buffer in a HOB specified by hob. * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT. @@ -254,11 +264,14 @@ union hob_pointers_t { * * @return: A pointer to the data buffer in a HOB. */ -#define GET_GUID_HOB_DATA(hob) \ - (void *)(*(u8 **)&(hob) + sizeof(struct hob_guid_t)) +static inline void *get_guid_hob_data(u8 *hob) +{ + return (void *)(hob + sizeof(struct hob_guid)); +}

/** - * Returns the size of the data buffer from a HOB of type HOB_TYPE_GUID_EXT. + * get_guid_hob_data_size() - return the size of the data buffer from a HOB + * of type HOB_TYPE_GUID_EXT * * This macro returns the size, in bytes, of the data buffer in a HOB * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT. @@ -267,14 +280,31 @@ union hob_pointers_t { * * @return: The size of the data buffer. */ -#define GET_GUID_HOB_DATA_SIZE(hob) \ - (u16)(GET_HOB_LENGTH(hob) - sizeof(struct hob_guid_t)) +static inline u16 get_guid_hob_data_size(u8 *hob) +{ + union hob_pointers hob_p = *(union hob_pointers *)hob; + return get_hob_length(hob_p) - sizeof(struct hob_guid); +}

/* FSP specific GUID HOB definitions */ +#define FSP_GUID_DATA1 0x912740be +#define FSP_GUID_DATA2 0x2284 +#define FSP_GUID_DATA3 0x4734 +#define FSP_GUID_DATA4_0 0xb9 +#define FSP_GUID_DATA4_1 0x71 +#define FSP_GUID_DATA4_2 0x84 +#define FSP_GUID_DATA4_3 0xb0 +#define FSP_GUID_DATA4_4 0x27 +#define FSP_GUID_DATA4_5 0x35 +#define FSP_GUID_DATA4_6 0x3f +#define FSP_GUID_DATA4_7 0x0c + #define FSP_HEADER_GUID \ { \ - 0x912740be, 0x2284, 0x4734, \ - {0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c} \ + FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \ + { FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \ + FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \ + FSP_GUID_DATA4_6, FSP_GUID_DATA4_7 } \ }

#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h index ad78bcd..4a4d627 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h @@ -10,9 +10,7 @@

#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */

-#pragma pack(1) - -struct fsp_header_t { +struct __packed fsp_header { u32 sign; /* 'FSPH' */ u32 hdr_len; /* header length */ u8 reserved1[3]; @@ -31,6 +29,4 @@ struct fsp_header_t { u32 reserved2; };

-#pragma pack() - #endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h index a7b6e6b..61286ce 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h @@ -8,12 +8,8 @@ #ifndef __FSP_PLATFORM_H__ #define __FSP_PLATFORM_H__

-#pragma pack(1) - -struct fspinit_rtbuf_t { - struct common_buf_t common; /* FSP common runtime data structure */ +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ };

-#pragma pack() - #endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h index 3296a2b..3ae1b66 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h @@ -18,14 +18,30 @@ #include "fsp_bootmode.h" #include "fsp_vpd.h"

-struct shared_data_t { - struct fsp_header_t *fsp_hdr; +struct shared_data { + struct fsp_header *fsp_hdr; u32 *stack_top; - struct upd_region_t fsp_upd; + struct upd_region fsp_upd; };

+#define FSP_LOWMEM_BASE 0x100000UL +#define FSP_HIGHMEM_BASE 0x100000000ULL + +/** + * FSP Continuation assembly helper routine + * + * This routine jumps to the C version of FSP continuation function + */ void asm_continuation(void);

+/** + * FSP initialization complete + * + * This is the function that indicates FSP initialization is complete and jumps + * back to the bootloader with HOB list pointer as the parameter. + * + * @hob_list: HOB list pointer + */ void fsp_init_done(void *hob_list);

/** @@ -37,19 +53,12 @@ void fsp_init_done(void *hob_list); * * @retval: Never returns */ -void fsp_continue(struct shared_data_t *shared_data, u32 status, +void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list);

/** * Find FSP header offset in FSP image * - * If this function is called before the a stack is established, special care - * must be taken. First, it cannot declare any local variable using stack. - * Only register variable can be used here. Secondly, some compiler version - * will add prolog or epilog code for the C function. If so the function call - * may not work before stack is ready. GCC 4.8.1 has been verified to be - * working for the following code. - * * @retval: the offset of FSP header. If signature is invalid, returns 0. */ u32 find_fsp_header(void); @@ -67,11 +76,11 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf); * FSP notification wrapper function * * @fsp_hdr: Pointer to FSP information header - * @phase: FSP initialization phase defined in enum fsp_phase_t + * @phase: FSP initialization phase defined in enum fsp_phase * * @retval: compatible status code with EFI_STATUS defined in PI spec */ -u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase); +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);

/** * This function retrieves the top of usable low memory. @@ -80,7 +89,7 @@ u32 fsp_notify(struct fsp_header_t *fsp_hdr, u32 phase); * * @retval: Usable low memory top. */ -u32 get_usable_lowmem_top(const void *hob_list); +u32 fsp_get_usable_lowmem_top(const void *hob_list);

/** * This function retrieves the top of usable high memory. @@ -89,7 +98,7 @@ u32 get_usable_lowmem_top(const void *hob_list); * * @retval: Usable high memory top. */ -u64 get_usable_highmem_top(const void *hob_list); +u64 fsp_get_usable_highmem_top(const void *hob_list);

/** * This function retrieves a special reserved memory region. @@ -102,8 +111,8 @@ u64 get_usable_highmem_top(const void *hob_list); * @retval: Reserved region start address. * 0 if this region does not exist. */ -u64 get_fsp_reserved_mem_from_guid(const void *hob_list, - u64 *len, struct efi_guid_t *guid); +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, + u64 *len, struct efi_guid *guid);

/** * This function retrieves the FSP reserved normal memory. @@ -114,7 +123,7 @@ u64 get_fsp_reserved_mem_from_guid(const void *hob_list, * @retval: FSP reserved memory base * 0 if this region does not exist. */ -u32 get_fsp_reserved_mem(const void *hob_list, u32 *len); +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len);

/** * This function retrieves the TSEG reserved normal memory. @@ -126,7 +135,7 @@ u32 get_fsp_reserved_mem(const void *hob_list, u32 *len); * @retval NULL: Failed to find the TSEG reserved memory. * @retval others: TSEG reserved memory base. */ -u32 get_tseg_reserved_mem(const void *hob_list, u32 *len); +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);

/** * Returns the next instance of a HOB type from the starting HOB. @@ -136,7 +145,7 @@ u32 get_tseg_reserved_mem(const void *hob_list, u32 *len); * * @retval: A HOB object with matching type; Otherwise NULL. */ -void *get_next_hob(u16 type, const void *hob_list); +void *fsp_get_next_hob(u16 type, const void *hob_list);

/** * Returns the next instance of the matched GUID HOB from the starting HOB. @@ -146,7 +155,7 @@ void *get_next_hob(u16 type, const void *hob_list); * * @retval: A HOB object with matching GUID; Otherwise NULL. */ -void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list); +void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list);

/** * This function retrieves a GUID HOB data buffer and size. @@ -159,8 +168,8 @@ void *get_next_guid_hob(const struct efi_guid_t *guid, const void *hob_list); * @retval NULL: Failed to find the GUID HOB. * @retval others: GUID HOB data buffer pointer. */ -void *get_guid_hob_data(const void *hob_list, u32 *len, - struct efi_guid_t *guid); +void *fsp_get_guid_hob_data(const void *hob_list, u32 *len, + struct efi_guid *guid);

/** * This function retrieves FSP Non-volatile Storage HOB buffer and size. @@ -172,7 +181,7 @@ void *get_guid_hob_data(const void *hob_list, u32 *len, * @retval NULL: Failed to find the NVS HOB. * @retval others: FSP NVS data buffer pointer. */ -void *get_fsp_nvs_data(const void *hob_list, u32 *len); +void *fsp_get_nvs_data(const void *hob_list, u32 *len);

/** * This function retrieves Bootloader temporary stack buffer and size. @@ -184,15 +193,15 @@ void *get_fsp_nvs_data(const void *hob_list, u32 *len); * @retval NULL: Failed to find the bootloader temporary stack HOB. * @retval others: Bootloader temporary stackbuffer pointer. */ -void *get_bootloader_tmp_mem(const void *hob_list, u32 *len); +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);

/** * This function overrides the default configurations in the UPD data region. * - * @fsp_upd: A pointer to the upd_region_t data strcture + * @fsp_upd: A pointer to the upd_region data strcture * * @return: None */ -void update_fsp_upd(struct upd_region_t *fsp_upd); +void update_fsp_upd(struct upd_region *fsp_upd);

#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h index 12ebbfd..f32d827 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h @@ -8,20 +8,8 @@ #ifndef __FSP_TYPES_H__ #define __FSP_TYPES_H__

-/* - * Boolean true value. UEFI Specification defines this value to be 1, - * but this form is more portable. - */ -#define TRUE ((unsigned char)(1 == 1)) - -/* - * Boolean false value. UEFI Specification defines this value to be 0, - * but this form is more portable. - */ -#define FALSE ((unsigned char)(0 == 1)) - /* 128 bit buffer containing a unique identifier value */ -struct efi_guid_t { +struct efi_guid { u32 data1; u16 data2; u16 data3; @@ -80,9 +68,6 @@ struct efi_guid_t { #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))

-/* Assertion for debug */ -#define ASSERT(exp) do { if (!(exp)) for (;;); } while (FALSE) - /* * Define FSP API return status code. * Compatiable with EFI_STATUS defined in PI Spec. diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h index 11cc32f..bce58b1 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h @@ -10,9 +10,9 @@ #ifndef __VPDHEADER_H__ #define __VPDHEADER_H__

-#pragma pack(1) +#define UPD_TERMINATOR 0x55AA

-struct upd_region_t { +struct __packed upd_region { u64 sign; /* Offset 0x0000 */ u64 reserved; /* Offset 0x0008 */ u8 dummy[240]; /* Offset 0x0010 */ @@ -39,7 +39,7 @@ struct upd_region_t { #define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */ #define VPD_IMAGE_REV 0x00000301

-struct vpd_region_t { +struct __packed vpd_region { u64 sign; /* Offset 0x0000 */ u32 img_rev; /* Offset 0x0008 */ u32 upd_offset; /* Offset 0x000C */ @@ -53,6 +53,4 @@ struct vpd_region_t { u8 pcie_port_ioh; /* Offset 0x0029 */ };

-#pragma pack() - #endif diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c index 2fdff2b..b552fe6 100644 --- a/arch/x86/lib/cmd_hob.c +++ b/arch/x86/lib/cmd_hob.c @@ -17,18 +17,18 @@ static char *hob_type[] = { "Memory Allocation", "Resource Descriptor", "GUID Extension", - "Firmware Volumn", + "Firmware Volume", "CPU", "Memory Pool", "reserved", - "Firmware Volumn 2", + "Firmware Volume 2", "Load PEIM Unused", "UEFI Capsule", };

int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - union hob_pointers_t hob; + union hob_pointers hob; u16 type; char *desc; int i = 0; @@ -39,29 +39,27 @@ int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

printf("No. | Address | Type | Length in Bytes\n"); printf("----|----------|---------------------|----------------\n"); - while (!END_OF_HOB(hob)) { + while (!end_of_hob(hob)) { printf("%-3d | %08x | ", i, (unsigned int)hob.raw); - type = hob.hdr->type; + type = get_hob_type(hob); if (type == HOB_TYPE_UNUSED) desc = "*Unused*"; else if (type == HOB_TYPE_EOH) - desc = "**END OF HOB**"; + desc = "*END OF HOB*"; else if (type >= 0 && type <= ARRAY_SIZE(hob_type)) desc = hob_type[type]; else - desc = "!!!Invalid Type!!!"; - printf("%-19s | %-15d\n", desc, hob.hdr->len); - hob.raw = GET_NEXT_HOB(hob); + desc = "*Invalid Type*"; + printf("%-19s | %-15d\n", desc, get_hob_length(hob)); + hob.raw = get_next_hob(hob); i++; }

return 0; }

-/* -------------------------------------------------------------------- */ - U_BOOT_CMD( hob, 1, 1, do_hob, - "print FSP Hand-Off Block information", + "print Firmware Support Package (FSP) Hand-Off Block information", "" );